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Update ChangeLog
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@@ -60,16 +60,16 @@
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* We will use its default, POR frequency of 4MHz to avoid an additional clock
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* switch.
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*
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* OSC16M Output = 4MHz
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* `- GCLK1 Input = 4MHz Prescaler = 1 output = 4MHz
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* `- DFLL Input = 4MHz Multiplier = 12 output = 48MHz
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* `- GCLK0 Input = 48MHz Prescaler = 1 output = 48MHz
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* `- PM Input = 48Mhz CPU divider = 1 CPU frequency = 48MHz
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* APBA divider = 1 APBA frequency = 48MHz
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* APBB divider = 1 APBB frequency = 48MHz
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* APBC divider = 1 APBC frequency = 48MHz
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* APBD divider = 1 APBD frequency = 48MHz
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* APBE divider = 1 APBE frequency = 48MHz
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* OSC16M Output = 4MHz
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* `- GCLK1 Input = 4MHz Prescaler = 1 output = 4MHz
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* `- DFLL Input = 4MHz Multiplier = 12 output = 48MHz
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* `- GCLK0 Input = 48MHz Prescaler = 1 output = 48MHz
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* `- MCLK Input = 48Mhz CPU divider = 1 CPU frequency = 48MHz
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* APBA divider = 1 APBA frequency = 48MHz
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* APBB divider = 1 APBB frequency = 48MHz
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* APBC divider = 1 APBC frequency = 48MHz
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* APBD divider = 1 APBD frequency = 48MHz
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* APBE divider = 1 APBE frequency = 48MHz
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*
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* The SAML21 Xplained Pro has one on-board crystal:
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*
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@@ -412,8 +412,8 @@
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* 1 48 MHz
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*/
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#if 0 /* REVISIT -- Sample code is running with zero wait states */
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# define BOARD_FLASH_WAITSTATES 0
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#if 0
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# define BOARD_FLASH_WAITSTATES 3
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#else
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# define BOARD_FLASH_WAITSTATES 1
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#endif
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