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Add STM3210E-EVAL LCD driver.

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3745 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2011-07-05 20:15:48 +00:00
parent ba9d75a05a
commit 84b779ea6f
9 changed files with 1283 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files
configs/stm3210e-eval/src/Makefile
+4 -3
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@@ -40,9 +40,10 @@ CFLAGS += -I$(TOPDIR)/sched
ASRCS =
AOBJS = $(ASRCS:.S=$(OBJEXT))
CSRCS = up_boot.c up_leds.c up_buttons.c up_spi.c up_usbdev.c \
up_extcontext.c up_selectnor.c up_deselectnor.c \
up_selectsram.c up_deselectsram.c
CSRCS = up_boot.c up_lcd.c up_leds.c up_buttons.c up_spi.c \
up_usbdev.c up_extcontext.c up_selectnor.c up_deselectnor.c \
up_selectsram.c up_deselectsram.c up_selectlcd.c \
up_deselectlcd.c
ifeq ($(CONFIG_NSH_ARCHINIT),y)
CSRCS += up_nsh.c
configs/stm3210e-eval/src/stm3210e-internal.h
+21
View File
@@ -245,6 +245,27 @@ extern void stm32_selectsram(void);
*
************************************************************************************/
extern void stm32_deselectsram(void);
/************************************************************************************
* Name: stm32_selectlcd
*
* Description:
* Initialize to the LCD
*
************************************************************************************/
extern void stm32_selectlcd(void);
/************************************************************************************
* Name: stm32_deselectlcd
*
* Description:
* Disable the LCD
*
************************************************************************************/
extern void stm32_deselectlcd(void);
#endif /* CONFIG_STM32_FSMC */
configs/stm3210e-eval/src/up_deselectlcd.c
+97
View File
@@ -0,0 +1,97 @@
/************************************************************************************
* configs/stm3210e-eval/src/up_deselectlcd.c
* arch/arm/src/board/up_deselectlcd.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include "up_arch.h"
#include "stm32_fsmc.h"
#include "stm3210e-internal.h"
#ifdef CONFIG_STM32_FSMC
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Private Data
************************************************************************************/
/************************************************************************************
* Private Functions
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: stm32_deselectlcd
*
* Description:
* Disable the LCD
*
************************************************************************************/
void stm32_deselectlcd(void)
{
/* Restore registers to their power up settings */
putreg32(0xffffffff, STM32_FSMC_BCR4);
/* Bank1 NOR/SRAM timing register configuration */
putreg32(0x0fffffff, STM32_FSMC_BTR4);
/* Disable AHB clocking to the FSMC */
stm32_disablefsmc();
}
#endif /* CONFIG_STM32_FSMC */
configs/stm3210e-eval/src/up_extmem.c
+14 -22
View File
@@ -75,17 +75,19 @@
* respectively.
*
* Pin Usage (per schematic)
* FLASH SRAM NAND
* D[0..15] [0..15] [0..15] [0..7]
* A[0..23] [0..22] [0..18] [16,17]
* PSMC_NE3 PG10 OUT ~CE --- ---
* PSMC_NBL0 PE0 OUT ~BLE --- ---
* PSMC_NBL1 PE1 OUT ~BHE --- ---
* PSMC_NE2 PG9 OUT --- ~E ---
* PSMC_NWE PD5 OUT ~WE ~W ~W
* PSMC_NOE PD4 OUT ~OE ~G ~R
* PSMC_NWAIT PD6 IN --- R~B ---
* PSMC_INT2 PG6* IN --- --- R~B
*
* FLASH SRAM NAND LCD
* D[0..15] [0..15] [0..15] [0..7] [0..15]
* A[0..23] [0..22] [0..18] [16,17] [0]
* FSMC_NBL0 PE0 OUT ~BLE --- --- ---
* FSMC_NBL1 PE1 OUT ~BHE --- --- ---
* FSMC_NE2 PG9 OUT --- ~E --- ---
* FSMC_NE3 PG10 OUT ~CE --- --- ---
* FSMC_NE4 PG12 OUT --- --- --- ~CS
* FSMC_NWE PD5 OUT ~WE ~W ~W ~WR/SCL
* FSMC_NOE PD4 OUT ~OE ~G ~R ~RD
* FSMC_NWAIT PD6 IN --- R~B --- ---
* FSMC_INT2 PG6* IN --- --- R~B ---
*
* *JP7 will switch to PD6
*/
@@ -113,7 +115,7 @@ const uint16_t g_commonconfig[NCOMMON_CONFIG] =
GPIO_NPS_D8, GPIO_NPS_D9, GPIO_NPS_D10, GPIO_NPS_D11,
GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, GPIO_NPS_D15,
/* NOE, NWE, NE3 */
/* NOE, NWE */
GPIO_NPS_NOE, GPIO_NPS_NWE
};
@@ -122,16 +124,6 @@ const uint16_t g_commonconfig[NCOMMON_CONFIG] =
* Private Data
************************************************************************************/
/* GPIO configurations unique to SRAM */
static const uint16_t g_sramconfig[] =
{
/* NE3, NBL0, NBL1, */
GPIO_NPS_NE3, GPIO_NPS_NBL0, GPIO_NPS_NBL1
};
#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint16_t))
/************************************************************************************
* Private Functions
************************************************************************************/
configs/stm3210e-eval/src/up_lcd.c
Executable
+962
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File diff suppressed because it is too large Load Diff
configs/stm3210e-eval/src/up_selectlcd.c
+146
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@@ -0,0 +1,146 @@
/************************************************************************************
* configs/stm3210e-eval/src/up_selectlcd.c
* arch/arm/src/board/up_selectlcd.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <debug.h>
#include "chip.h"
#include "up_arch.h"
#include "stm32.h"
#include "stm3210e-internal.h"
#ifdef CONFIG_STM32_FSMC
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#if STM32_NGPIO_PORTS < 6
# error "Required GPIO ports not enabled"
#endif
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Private Data
************************************************************************************/
/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and 16-bit
* accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of SRAM,
* respectively.
*
* Pin Usage (per schematic)
* FLASH SRAM NAND LCD
* D[0..15] [0..15] [0..15] [0..7] [0..15]
* A[0..23] [0..22] [0..18] [16,17] [0]
* FSMC_NBL0 PE0 OUT ~BLE --- --- ---
* FSMC_NBL1 PE1 OUT ~BHE --- --- ---
* FSMC_NE2 PG9 OUT --- ~E --- ---
* FSMC_NE3 PG10 OUT ~CE --- --- ---
* FSMC_NE4 PG12 OUT --- --- --- ~CS
* FSMC_NWE PD5 OUT ~WE ~W ~W ~WR/SCL
* FSMC_NOE PD4 OUT ~OE ~G ~R ~RD
* FSMC_NWAIT PD6 IN --- R~B --- ---
* FSMC_INT2 PG6* IN --- --- R~B ---
*
* *JP7 will switch to PD6
*/
/* GPIO configurations unique to SRAM */
static const uint16_t g_lcdconfig[] =
{
/* NE4 */
GPIO_NPS_NE4
};
#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint16_t))
/************************************************************************************
* Private Functions
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: stm32_selectlcd
*
* Description:
* Initialize to the LCD
*
************************************************************************************/
void stm32_selectlcd(void)
{
/* Configure new GPIO state */
stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG);
stm32_extmemgpios(g_lcdconfig, NLCD_CONFIG);
/* Enable AHB clocking to the FSMC */
stm32_enablefsmc();
/* Bank4 NOR/SRAM control register configuration */
putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR4);
/* Bank4 NOR/SRAM timing register configuration */
putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTRUN(0)|
FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA, STM32_FSMC_BTR4);
putreg32(0xffffffff, STM32_FSMC_BWTR4);
/* Enable the bank by setting the MBKEN bit */
putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR4);
}
#endif /* CONFIG_STM32_FSMC */
configs/stm3210e-eval/src/up_selectnor.c
+14 -12
View File
@@ -64,17 +64,19 @@
************************************************************************************/
/* Pin Usage (per schematic)
* FLASH SRAM NAND
* D[0..15] [0..15] [0..15] [0..7]
* A[0..23] [0..22] [0..18] [16,17]
* PSMC_NE3 PG10 OUT ~CE --- ---
* PSMC_NBL0 PE0 OUT ~BLE --- ---
* PSMC_NBL1 PE1 OUT ~BHE --- ---
* PSMC_NE2 PG9 OUT --- ~E ---
* PSMC_NWE PD5 OUT ~WE ~W ~W
* PSMC_NOE PD4 OUT ~OE ~G ~R
* PSMC_NWAIT PD6 IN --- R~B ---
* PSMC_INT2 PG6* IN --- --- R~B
*
* FLASH SRAM NAND LCD
* D[0..15] [0..15] [0..15] [0..7] [0..15]
* A[0..23] [0..22] [0..18] [16,17] [0]
* FSMC_NBL0 PE0 OUT ~BLE --- --- ---
* FSMC_NBL1 PE1 OUT ~BHE --- --- ---
* FSMC_NE2 PG9 OUT --- ~E --- ---
* FSMC_NE3 PG10 OUT ~CE --- --- ---
* FSMC_NE4 PG12 OUT --- --- --- ~CS
* FSMC_NWE PD5 OUT ~WE ~W ~W ~WR/SCL
* FSMC_NOE PD4 OUT ~OE ~G ~R ~RD
* FSMC_NWAIT PD6 IN --- R~B --- ---
* FSMC_INT2 PG6* IN --- --- R~B ---
*
* *JP7 will switch to PD6
*/
@@ -129,7 +131,7 @@ void stm32_selectnor(void)
putreg32(FSMC_BTR_ADDSET(3)|FSMC_BTR_ADDHLD(1)|FSMC_BTR_DATAST(6)|FSMC_BTR_BUSTRUN(1)|
FSMC_BTR_CLKDIV(1)|FSMC_BTR_DATLAT(2)|FSMC_BTR_ACCMODB, STM32_FSMC_BTR2);
putreg32(0x0fffffff, STM32_FSMC_BCR3);
putreg32(0x0fffffff, STM32_FSMC_BWTR2);
/* Enable the bank */
configs/stm3210e-eval/src/up_selectsram.c
+13 -12
View File
@@ -72,17 +72,18 @@
* respectively.
*
* Pin Usage (per schematic)
* FLASH SRAM NAND
* D[0..15] [0..15] [0..15] [0..7]
* A[0..23] [0..22] [0..18] [16,17]
* PSMC_NE3 PG10 OUT ~CE --- ---
* PSMC_NBL0 PE0 OUT ~BLE --- ---
* PSMC_NBL1 PE1 OUT ~BHE --- ---
* PSMC_NE2 PG9 OUT --- ~E ---
* PSMC_NWE PD5 OUT ~WE ~W ~W
* PSMC_NOE PD4 OUT ~OE ~G ~R
* PSMC_NWAIT PD6 IN --- R~B ---
* PSMC_INT2 PG6* IN --- --- R~B
* FLASH SRAM NAND LCD
* D[0..15] [0..15] [0..15] [0..7] [0..15]
* A[0..23] [0..22] [0..18] [16,17] [0]
* FSMC_NBL0 PE0 OUT ~BLE --- --- ---
* FSMC_NBL1 PE1 OUT ~BHE --- --- ---
* FSMC_NE2 PG9 OUT --- ~E --- ---
* FSMC_NE3 PG10 OUT ~CE --- --- ---
* FSMC_NE4 PG12 OUT --- --- --- ~CS
* FSMC_NWE PD5 OUT ~WE ~W ~W ~WR/SCL
* FSMC_NOE PD4 OUT ~OE ~G ~R ~RD
* FSMC_NWAIT PD6 IN --- R~B --- ---
* FSMC_INT2 PG6* IN --- --- R~B ---
*
* *JP7 will switch to PD6
*/
@@ -133,7 +134,7 @@ void stm32_selectsram(void)
putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(1)|FSMC_BTR_DATAST(3)|FSMC_BTR_BUSTRUN(1)|
FSMC_BTR_CLKDIV(1)|FSMC_BTR_DATLAT(2)|FSMC_BTR_ACCMODA, STM32_FSMC_BTR3);
putreg32(0xffffffff, STM32_FSMC_BCR3);
putreg32(0xffffffff, STM32_FSMC_BWTR3);
/* Enable the bank */
drivers/lcd/skeleton.c
+12 -7
View File
@@ -59,6 +59,7 @@
/* Configuration **********************************************************************/
/* Verify that all configuration requirements have been met */
/* Debug ******************************************************************************/
/* Define the following to enable register-level debug output */
#undef CONFIG_LCD_SKELDEBUG
@@ -261,10 +262,7 @@ static int skel_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer,
gvdbg("row: %d col: %d npixels: %d\n", row, col, npixels);
DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0);
/* When the SPI interfacee is used, the SD1329 controller does not support reading
* from GDDRAM.
*/
#warning "Missing logic"
return -ENOSYS;
}
@@ -316,6 +314,7 @@ static int skel_getpower(struct lcd_dev_s *dev)
{
struct skel_dev_s *priv = (struct skel_dev_s *)dev;
gvdbg("power: %d\n", 0);
#warning "Missing logic"
return 0;
}
@@ -336,6 +335,7 @@ static int skel_setpower(struct lcd_dev_s *dev, int power)
DEBUGASSERT(power <= CONFIG_LCD_MAXPOWER);
/* Set new power level */
#warning "Missing logic"
return OK;
}
@@ -351,6 +351,7 @@ static int skel_setpower(struct lcd_dev_s *dev, int power)
static int skel_getcontrast(struct lcd_dev_s *dev)
{
gvdbg("Not implemented\n");
#warning "Missing logic"
return -ENOSYS;
}
@@ -365,6 +366,7 @@ static int skel_getcontrast(struct lcd_dev_s *dev)
static int skel_setcontrast(struct lcd_dev_s *dev, unsigned int contrast)
{
gvdbg("contrast: %d\n", contrast);
#warning "Missing logic"
return -ENOSYS;
}
@@ -388,9 +390,12 @@ FAR struct lcd_dev_s *up_oledinitialize(FAR struct spi_dev_s *spi)
/* Configure GPIO pins */
#warning "Missing logic"
/* Enable clocking /
/* Enable clocking */
#warning "Missing logic"
/* Configure and enable LCD */
return lcddev == 0 ? &g_lcddev.dev : NULL;
#warning "Missing logic"
return &g_lcddev.dev;
}