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TMS570: Add SCI header file
This commit is contained in:
Gregory Nutt
@@ -0,0 +1,233 @@
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/****************************************************************************************************
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* arch/arm/src/tms570/chip/tms570_sci.h
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* Secondary System Control Register Definitions
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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*
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* TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, Technical Reference Manual, Texas
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* Instruments, Literature Number: SPNU517A, September 2013
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_SCI_H
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#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_SCI_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/tms570_memorymap.h"
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* Register Offsets *********************************************************************************/
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#define TMS570_SCI_GCR0_OFFSET 0x0000 /* SCI Global Control Register 0 */
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#define TMS570_SCI_GCR1_OFFSET 0x0004 /* SCI Global Control Register 1 */
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#define TMS570_SCI_GCR2_OFFSET 0x0008 /* SCI Global Control Register 2 */
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#define TMS570_SCI_SETINT_OFFSET 0x000c /* SCI Set Interrupt Register */
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#define TMS570_SCI_CLEARINT_OFFSET 0x0010 /* SCI Clear Interrupt Register */
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#define TMS570_SCI_SETINTLVL_OFFSET 0x0014 /* SCI Set Interrupt Level Register */
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#define TMS570_SCI_CLEARINTLVL_OFFSET 0x0018 /* SCI Clear Interrupt Level Register */
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#define TMS570_SCI_FLR_OFFSET 0x001c /* SCI Flags Register */
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#define TMS570_SCI_INTVECT0_OFFSET 0x0020 /* SCI Interrupt Vector Offset 0 */
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#define TMS570_SCI_INTVECT1_OFFSET 0x0024 /* SCI Interrupt Vector Offset 1 */
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#define TMS570_SCI_FORMAT_OFFSET 0x0028 /* SCI Format Control Register */
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#define TMS570_SCI_BRS_OFFSET 0x002c /* Baud Rate Selection Register */
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#define TMS570_SCI_ED_OFFSET 0x0030 /* Receiver Emulation Data Buffer */
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#define TMS570_SCI_RD_OFFSET 0x0034 /* Receiver Data Buffer */
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#define TMS570_SCI_TD_OFFSET 0x0038 /* Transmit Data Buffer */
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#define TMS570_SCI_PIO0_OFFSET 0x003c /* SCI Pin I/O Control Register 0 */
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#define TMS570_SCI_PIO1_OFFSET 0x0040 /* SCI Pin I/O Control Register 1 */
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#define TMS570_SCI_PIO2_OFFSET 0x0044 /* SCI Pin I/O Control Register 2 */
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#define TMS570_SCI_PIO3_OFFSET 0x0048 /* SCI Pin I/O Control Register 3 */
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#define TMS570_SCI_PIO4_OFFSET 0x004c /* SCI Pin I/O Control Register 4 */
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#define TMS570_SCI_PIO5_OFFSET 0x0050 /* SCI Pin I/O Control Register 5 */
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#define TMS570_SCI_PIO6_OFFSET 0x0054 /* SCI Pin I/O Control Register 6 */
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#define TMS570_SCI_PIO7_OFFSET 0x0058 /* SCI Pin I/O Control Register 7 */
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#define TMS570_SCI_PIO8_OFFSET 0x005c /* SCI Pin I/O Control Register 8 */
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#define TMS570_LIN_COMPARE_OFFSET 0x0060 /* LIN Compare Register */
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#define TMS570_LIN_RD0_OFFSET 0x0064 /* LIN Receive Buffer 0 Register */
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#define TMS570_LIN_RD1_OFFSET 0x0068 /* LIN Receive Buffer 1 Register */
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#define TMS570_LIN_MASK_OFFSET 0x006c /* LIN Mask Register */
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#define TMS570_LIN_ID_OFFSET 0x0070 /* LIN Identification Register */
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#define TMS570_LIN_TD0_OFFSET 0x0074 /* LIN Transmit Buffer 0 */
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#define TMS570_LIN_TD1_OFFSET 0x0078 /* LIN Transmit Buffer 1 */
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#define TMS570_SCI_MBRS_OFFSET 0x007c /* Maximum Baud Rate Selection Register */
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#define TMS570_SCI_IODFTCTRL_OFFSET 0x0090 /* Input/Output Error Enable Register */
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/* Register Addresses *******************************************************************************/
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#define TMS570_SCI1_GCR0 (TMS570_SCI1_BASE+TMS570_SCI_GCR0_OFFSET)
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#define TMS570_SCI1_GCR1 (TMS570_SCI1_BASE+TMS570_SCI_GCR1_OFFSET)
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#define TMS570_SCI1_GCR2 (TMS570_SCI1_BASE+TMS570_SCI_GCR2_OFFSET)
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#define TMS570_SCI1_SETINT (TMS570_SCI1_BASE+TMS570_SCI_SETINT_OFFSET)
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#define TMS570_SCI1_CLEARINT (TMS570_SCI1_BASE+TMS570_SCI_CLEARINT_OFFSET)
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#define TMS570_SCI1_SETINTLVL (TMS570_SCI1_BASE+TMS570_SCI_SETINTLVL_OFFSET)
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#define TMS570_SCI1_CLEARINTLVL (TMS570_SCI1_BASE+TMS570_SCI_CLEARINTLVL_OFFSET)
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#define TMS570_SCI1_FLR (TMS570_SCI1_BASE+TMS570_SCI_FLR_OFFSET)
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#define TMS570_SCI1_INTVECT0 (TMS570_SCI1_BASE+TMS570_SCI_INTVECT0_OFFSET)
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#define TMS570_SCI1_INTVECT1 (TMS570_SCI1_BASE+TMS570_SCI_INTVECT1_OFFSET)
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#define TMS570_SCI1_FORMAT (TMS570_SCI1_BASE+TMS570_SCI_FORMAT_OFFSET)
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#define TMS570_SCI1_BRS (TMS570_SCI1_BASE+TMS570_SCI_BRS_OFFSET)
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#define TMS570_SCI1_ED (TMS570_SCI1_BASE+TMS570_SCI_ED_OFFSET)
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#define TMS570_SCI1_RD (TMS570_SCI1_BASE+TMS570_SCI_RD_OFFSET)
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#define TMS570_SCI1_TD (TMS570_SCI1_BASE+TMS570_SCI_TD_OFFSET)
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#define TMS570_SCI1_PIO0 (TMS570_SCI1_BASE+TMS570_SCI_PIO0_OFFSET)
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#define TMS570_SCI1_PIO1 (TMS570_SCI1_BASE+TMS570_SCI_PIO1_OFFSET)
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#define TMS570_SCI1_PIO2 (TMS570_SCI1_BASE+TMS570_SCI_PIO2_OFFSET)
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#define TMS570_SCI1_PIO3 (TMS570_SCI1_BASE+TMS570_SCI_PIO3_OFFSET)
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#define TMS570_SCI1_PIO4 (TMS570_SCI1_BASE+TMS570_SCI_PIO4_OFFSET)
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#define TMS570_SCI1_PIO5 (TMS570_SCI1_BASE+TMS570_SCI_PIO5_OFFSET)
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#define TMS570_SCI1_PIO6 (TMS570_SCI1_BASE+TMS570_SCI_PIO6_OFFSET)
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#define TMS570_SCI1_PIO7 (TMS570_SCI1_BASE+TMS570_SCI_PIO7_OFFSET)
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#define TMS570_SCI1_PIO8 (TMS570_SCI1_BASE+TMS570_SCI_PIO8_OFFSET)
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#define TMS570_LIN1_COMPARE (TMS570_SCI1_BASE+TMS570_LIN_COMPARE_OFFSET)
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#define TMS570_LIN1_RD0 (TMS570_SCI1_BASE+TMS570_LIN_RD0_OFFSET)
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#define TMS570_LIN1_RD1 (TMS570_SCI1_BASE+TMS570_LIN_RD1_OFFSET)
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#define TMS570_LIN1_MASK (TMS570_SCI1_BASE+TMS570_LIN_MASK_OFFSET)
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#define TMS570_LIN1_ID (TMS570_SCI1_BASE+TMS570_LIN_ID_OFFSET)
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#define TMS570_LIN1_TD0 (TMS570_SCI1_BASE+TMS570_LIN_TD0_OFFSET)
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#define TMS570_LIN1_TD1 (TMS570_SCI1_BASE+TMS570_LIN_TD1_OFFSET)
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#define TMS570_SCI1_MBRS (TMS570_SCI1_BASE+TMS570_SCI_MBRS_OFFSET)
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#define TMS570_SCI1_IODFTCTRL (TMS570_SCI1_BASE+TMS570_SCI_IODFTCTRL_OFFSET)
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#if TMS570_NSCI > 1
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# define TMS570_SCI2_GCR0 (TMS570_SCI2_BASE+TMS570_SCI_GCR0_OFFSET)
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# define TMS570_SCI2_GCR1 (TMS570_SCI2_BASE+TMS570_SCI_GCR1_OFFSET)
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# define TMS570_SCI2_GCR2 (TMS570_SCI2_BASE+TMS570_SCI_GCR2_OFFSET)
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# define TMS570_SCI2_SETINT (TMS570_SCI2_BASE+TMS570_SCI_SETINT_OFFSET)
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# define TMS570_SCI2_CLEARINT (TMS570_SCI2_BASE+TMS570_SCI_CLEARINT_OFFSET)
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# define TMS570_SCI2_SETINTLVL (TMS570_SCI2_BASE+TMS570_SCI_SETINTLVL_OFFSET)
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# define TMS570_SCI2_CLEARINTLVL (TMS570_SCI2_BASE+TMS570_SCI_CLEARINTLVL_OFFSET)
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# define TMS570_SCI2_FLR (TMS570_SCI2_BASE+TMS570_SCI_FLR_OFFSET)
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# define TMS570_SCI2_INTVECT0 (TMS570_SCI2_BASE+TMS570_SCI_INTVECT0_OFFSET)
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# define TMS570_SCI2_INTVECT1 (TMS570_SCI2_BASE+TMS570_SCI_INTVECT1_OFFSET)
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# define TMS570_SCI2_FORMAT (TMS570_SCI2_BASE+TMS570_SCI_FORMAT_OFFSET)
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# define TMS570_SCI2_BRS (TMS570_SCI2_BASE+TMS570_SCI_BRS_OFFSET)
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# define TMS570_SCI2_ED (TMS570_SCI2_BASE+TMS570_SCI_ED_OFFSET)
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# define TMS570_SCI2_RD (TMS570_SCI2_BASE+TMS570_SCI_RD_OFFSET)
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# define TMS570_SCI2_TD (TMS570_SCI2_BASE+TMS570_SCI_TD_OFFSET)
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# define TMS570_SCI2_PIO0 (TMS570_SCI2_BASE+TMS570_SCI_PIO0_OFFSET)
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# define TMS570_SCI2_PIO1 (TMS570_SCI2_BASE+TMS570_SCI_PIO1_OFFSET)
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# define TMS570_SCI2_PIO2 (TMS570_SCI2_BASE+TMS570_SCI_PIO2_OFFSET)
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# define TMS570_SCI2_PIO3 (TMS570_SCI2_BASE+TMS570_SCI_PIO3_OFFSET)
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# define TMS570_SCI2_PIO4 (TMS570_SCI2_BASE+TMS570_SCI_PIO4_OFFSET)
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# define TMS570_SCI2_PIO5 (TMS570_SCI2_BASE+TMS570_SCI_PIO5_OFFSET)
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# define TMS570_SCI2_PIO6 (TMS570_SCI2_BASE+TMS570_SCI_PIO6_OFFSET)
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# define TMS570_SCI2_PIO7 (TMS570_SCI2_BASE+TMS570_SCI_PIO7_OFFSET)
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# define TMS570_SCI2_PIO8 (TMS570_SCI2_BASE+TMS570_SCI_PIO8_OFFSET)
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# define TMS570_LIN2_COMPARE (TMS570_SCI2_BASE+TMS570_LIN_COMPARE_OFFSET)
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# define TMS570_LIN2_RD0 (TMS570_SCI2_BASE+TMS570_LIN_RD0_OFFSET)
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# define TMS570_LIN2_RD1 (TMS570_SCI2_BASE+TMS570_LIN_RD1_OFFSET)
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# define TMS570_LIN2_MASK (TMS570_SCI2_BASE+TMS570_LIN_MASK_OFFSET)
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# define TMS570_LIN2_ID (TMS570_SCI2_BASE+TMS570_LIN_ID_OFFSET)
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# define TMS570_LIN2_TD0 (TMS570_SCI2_BASE+TMS570_LIN_TD0_OFFSET)
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# define TMS570_LIN2_TD1 (TMS570_SCI2_BASE+TMS570_LIN_TD1_OFFSET)
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# define TMS570_SCI2_MBRS (TMS570_SCI2_BASE+TMS570_SCI_MBRS_OFFSET)
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# define TMS570_SCI2_IODFTCTRL (TMS570_SCI2_BASE+TMS570_SCI_IODFTCTRL_OFFSET)
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#endif
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/* Register Bit-Field Definitions *******************************************************************/
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/* SCI Global Control Register 0 */
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#define SCI_GCR0_
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/* SCI Global Control Register 1 */
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#define SCI_GCR1_
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/* SCI Global Control Register 2 */
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#define SCI_GCR2_
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/* SCI Set Interrupt Register */
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#define SCI_SETINT_
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/* SCI Clear Interrupt Register */
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#define SCI_CLEARINT_
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/* SCI Set Interrupt Level Register */
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#define SCI_SETINTLVL_
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/* SCI Clear Interrupt Level Register */
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#define SCI_CLEARINTLVL_
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/* SCI Flags Register */
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#define SCI_FLR_
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/* SCI Interrupt Vector Offset 0 */
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#define SCI_INTVECT0_
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/* SCI Interrupt Vector Offset 1 */
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#define SCI_INTVECT1_
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/* SCI Format Control Register */
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#define SCI_FORMAT_
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/* Baud Rate Selection Register */
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#define SCI_BRS_
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/* Receiver Emulation Data Buffer */
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#define SCI_ED_
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/* Receiver Data Buffer */
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#define SCI_RD_
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/* Transmit Data Buffer */
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#define SCI_TD_
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/* SCI Pin I/O Control Register 0 */
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#define SCI_PIO0_
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/* SCI Pin I/O Control Register 1 */
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#define SCI_PIO1_
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/* SCI Pin I/O Control Register 2 */
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#define SCI_PIO2_
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/* SCI Pin I/O Control Register 3 */
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#define SCI_PIO3_
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/* SCI Pin I/O Control Register 4 */
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#define SCI_PIO4_
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/* SCI Pin I/O Control Register 5 */
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#define SCI_PIO5_
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/* SCI Pin I/O Control Register 6 */
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#define SCI_PIO6_
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/* SCI Pin I/O Control Register 7 */
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#define SCI_PIO7_
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/* SCI Pin I/O Control Register 8 */
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#define SCI_PIO8_
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/* LIN Compare Register */
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#define LIN_COMPARE_
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/* LIN Receive Buffer 0 Register */
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#define LIN_RD0_
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/* LIN Receive Buffer 1 Register */
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#define LIN_RD1_
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/* LIN Mask Register */
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#define LIN_MASK_
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/* LIN Identification Register */
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#define LIN_ID_
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/* LIN Transmit Buffer 0 */
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#define LIN_TD0_
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/* LIN Transmit Buffer 1 */
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#define LIN_TD1_
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/* Maximum Baud Rate Selection Register */
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#define SCI_MBRS_
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/* Input/Output Error Enable Register */
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#define SCI_IODFTCTRL_
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#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_SCI_H */
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@@ -101,7 +101,7 @@
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#define TMS570_MIBADC_BASE 0xfff7bc00 /* 0xfff7c000-0xfff7c1ff: MIBADC */
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#define TMS570_DCAN1_BASE 0xfff7dc00 /* 0xfff7dc00-0xfff7ddff: DCAN1 */
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#define TMS570_DCAN2_BASE 0xfff7de00 /* 0xfff7de00-0xfff7dfff: DCAN2 */
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#define TMS570_SCI_BASE 0xfff7e400 /* 0xfff7e400-0xfff7e4ff: SCI/LIN */
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#define TMS570_SCI1_BASE 0xfff7e400 /* 0xfff7e400-0xfff7e4ff: SCI1/LIN1 */
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#define TMS570_MIBSPI1_BASE 0xfff7f400 /* 0xfff7f400-0xfff7f5ff: MibSPI1 */
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#define TMS570_SPI2_BASE 0xfff7f600 /* 0xfff7f600-0xfff7f7ff: SPI2 */
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#define TMS570_SPI3_BASE 0xfff7f800 /* 0xfff7f800-0xfff7f9ff: SPI3 */
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@@ -268,9 +268,20 @@ void arm_boot(void)
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* is still in local reset.
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*/
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tms570_memory_initialize(SYS_MSIENA_VIM_RAM | SYS_MSIENA_N2HET_RAM |
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SYS_MSIENA_HTU_RAM | SYS_MSIENA_DCAN1_RAM |
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SYS_MSIENA_DCAN2_RAM | SYS_MSIENA_MIBADC_RAM);
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tms570_memory_initialize(SYS_MSIENA_VIM_RAM
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#ifdef CONFIG_TMS570_N2HET
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| SYS_MSIENA_N2HET_RAM | SYS_MSIENA_HTU_RAM
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#endif
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#ifdef CONFIG_TMS570_DCAN1
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| SYS_MSIENA_DCAN1_RAM
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#endif
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#ifdef CONFIG_TMS570_DCAN2
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| SYS_MSIENA_DCAN2_RAM
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#endif
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#ifdef CONFIG_TMS570_MIBASPI1
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| SYS_MSIENA_MIBADC_RAM
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#endif
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);
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#ifdef CONFIG_ARCH_FPU
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/* Initialize the FPU */
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