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arch/arm/src/imxrt/chip: Add SNVS/RTC register definition header file.
This commit is contained in:
Gregory Nutt
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/********************************************************************************************
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* arch/arm/src/imxrt/imxrt_snvs.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SNVS_H
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#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SNVS_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/imxrt_memorymap.h"
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* Register offsets *************************************************************************/
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#define IMXRT_SNVS_HPLR_OFFSET 0x0000 /* SNVS_HP Lock Register */
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#define IMXRT_SNVS_HPCOMR_OFFSET 0x0004 /* SNVS_HP Command Register */
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#define IMXRT_SNVS_HPCR_OFFSET 0x0008 /* SNVS_HP Control Register */
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#define IMXRT_SNVS_HPSR_OFFSET 0x0014 /* SNVS_HP Status Register */
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#define IMXRT_SNVS_HPRTCMR_OFFSET 0x0024 /* SNVS_HP Real Time Counter MSB Register */
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#define IMXRT_SNVS_HPRTCLR_OFFSET 0x0028 /* SNVS_HP Real Time Counter LSB Register */
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#define IMXRT_SNVS_HPTAMR_OFFSET 0x002c /* SNVS_HP Time Alarm MSB Register */
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#define IMXRT_SNVS_HPTALR_OFFSET 0x0030 /* SNVS_HP Time Alarm LSB Register */
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#define IMXRT_SNVS_LPLR_OFFSET 0x0034 /* SNVS_LP Lock Register */
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#define IMXRT_SNVS_LPCR_OFFSET 0x0038 /* SNVS_LP Control Register */
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#define IMXRT_SNVS_LPSR_OFFSET 0x004c /* SNVS_LP Status Register */
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#define IMXRT_SNVS_LPSMCMR_OFFSET 0x005c /* SNVS_LP Secure Monotonic Counter MSB Register */
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#define IMXRT_SNVS_LPSMCLR_OFFSET 0x0060 /* SNVS_LP Secure Monotonic Counter LSB Register */
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#define IMXRT_SNVS_LPGPR0L_OFFSET 0x0068 /* SNVS_LP General Purpose Register 0 (legacy alias) */
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#define IMXRT_SNVS_LPGPRA_OFFSET(n) (0x0090 + ((n) << 2))
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#define IMXRT_SNVS_LPGPR0A_OFFSET 0x0090 /* NVS_LP General Purpose Registers 0 LPGPR0_alias */
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#define IMXRT_SNVS_LPGPR1A_OFFSET 0x0094 /* NVS_LP General Purpose Registers 1 LPGPR1_alias */
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#define IMXRT_SNVS_LPGPR2A_OFFSET 0x0098 /* NVS_LP General Purpose Registers 2 LPGPR2_alias */
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#define IMXRT_SNVS_LPGPR3A_OFFSET 0x009c /* NVS_LP General Purpose Registers 3 LPGPR3_alias */
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#define IMXRT_SNVS_LPGPR_OFFSET(n) (0x0100 + ((n) << 2))
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#define IMXRT_SNVS_LPGPR0_OFFSET 0x0100 /* SNVS_LP General Purpose Registers 0 */
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#define IMXRT_SNVS_LPGPR1_OFFSET 0x0104 /* SNVS_LP General Purpose Registers 1 */
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#define IMXRT_SNVS_LPGPR2_OFFSET 0x0108 /* SNVS_LP General Purpose Registers 2 */
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#define IMXRT_SNVS_LPGPR3_OFFSET 0x010c /* SNVS_LP General Purpose Registers 3 */
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#define IMXRT_SNVS_HPVIDR1_OFFSET 0x0bf8 /* SNVS_HP Version ID Register 1 */
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#define IMXRT_SNVS_HPVIDR2_OFFSET 0x0bfc /* SNVS_HP Version ID Register 2 */
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/* Register addresses ***********************************************************************/
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#define IMXRT_SNVS_HPLR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPLR_OFFSET)
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#define IMXRT_SNVS_HPCOMR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPCOMR_OFFSET)
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#define IMXRT_SNVS_HPCR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPCR_OFFSET)
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#define IMXRT_SNVS_HPSR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPSR_OFFSET)
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#define IMXRT_SNVS_HPRTCMR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPRTCMR_OFFSET)
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#define IMXRT_SNVS_HPRTCLR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPRTCLR_OFFSET)
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#define IMXRT_SNVS_HPTAMR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPTAMR_OFFSET)
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#define IMXRT_SNVS_HPTALR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPTALR_OFFSET)
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#define IMXRT_SNVS_LPLR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPLR_OFFSET)
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#define IMXRT_SNVS_LPCR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPCR_OFFSET)
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#define IMXRT_SNVS_LPSR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPSR_OFFSET)
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#define IMXRT_SNVS_LPSMCMR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPSMCMR_OFFSET)
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#define IMXRT_SNVS_LPSMCLR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPSMCLR_OFFSET)
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#define IMXRT_SNVS_LPGPR0L (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR0L_OFFSET)
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#define IMXRT_SNVS_LPGPRA(n) (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPRA_OFFSET(n))
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#define IMXRT_SNVS_LPGPR0A (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR0A_OFFSET)
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#define IMXRT_SNVS_LPGPR1A (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR1A_OFFSET)
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#define IMXRT_SNVS_LPGPR2A (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR2A_OFFSET)
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#define IMXRT_SNVS_LPGPR3A (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR3A_OFFSET)
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#define IMXRT_SNVS_LPGPR(n) (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR_OFFSET(n))
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#define IMXRT_SNVS_LPGPR0 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR0_OFFSET)
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#define IMXRT_SNVS_LPGPR1 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR1_OFFSET)
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#define IMXRT_SNVS_LPGPR2 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR2_OFFSET)
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#define IMXRT_SNVS_LPGPR3 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR3_OFFSET)
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#define IMXRT_SNVS_HPVIDR1 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPVIDR1_OFFSET)
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#define IMXRT_SNVS_HPVIDR2 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPVIDR2_OFFSET)
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/* Register bit definitions *****************************************************************/
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/* SNVS_HP Lock Register */
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/* Bits 0-3: Reserved */
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#define SNVS_HPLR_MCSL (1 << 4) /* Bit 4: Monotonic Counter Soft Lock */
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#define SNVS_HPLR_GPRSL (1 << 5) /* Bit 5: General Purpose Register Soft Lock */
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/* Bits 6-31: Reserved */
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/* SNVS_HP Command Register */
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/* Bits 0-3: Reserved */
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#define SNVS_HPCOMR_LPSWR (1 << 4) /* Bit 4: LP Software Reset */
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#define SNVS_HPCOMR_LPSWRDIS (1 << 5) /* Bit 5: LP Software Reset Disable */
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/* Bits 6-30: Reserved */
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#define SNVS_HPCOMR_NPSWAEN (1 << 31) /* Bit 31: Non-Privileged Software Access Enable */
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/* SNVS_HP Control Register */
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#define SNVS_HPCR_RTCEN (1 << 0) /* Bit 0: HP Real Time Counter Enable */
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#define SNVS_HPCR_HPTAEN (1 << 1) /* Bit 1: HP Time Alarm Enable */
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/* Bit 2: Reserved */
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#define SNVS_HPCR_PIEN (1 << 3) /* Bit 3: HP Periodic Interrupt Enable */
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#define SNVS_HPCR_PIFREQ_SHIFT (4) /* Bits 4-7: Periodic Interrupt Frequency */
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#define SNVS_HPCR_PIFREQ_MASK (15 << SNVS_HPCR_PIFREQ_SHIFT)
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# define SNVS_HPCR_PIFREQ(n) ((uint32_t)(n) << SNVS_HPCR_PIFREQ_SHIFT)
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#define SNVS_HPCR_HPCALBEN (1 << 8) /* Bit 8: HP Real Time Counter Calibration Enabled */
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/* Bit 9: Reserved */
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#define SNVS_HPCR_HPCALBVAL_SHIFT (10) /* Bits 10-14: HP Calibration Value */
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#define SNVS_HPCR_HPCALBVAL_MASK (31 << SNVS_HPCR_HPCALBVAL_SHIFT)
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# define SNVS_HPCR_HPCALBVAL_ZERO (0 << SNVS_HPCR_HPCALBVAL_SHIFT) /* +0 counts per 32768 ticks */
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# define SNVS_HPCR_HPCALBVAL_P1 (1 << SNVS_HPCR_HPCALBVAL_SHIFT) /* +1 counts per 32768 ticks */
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# define SNVS_HPCR_HPCALBVAL_P2 (2 << SNVS_HPCR_HPCALBVAL_SHIFT) /* +2 counts per 32768 ticks */
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# define SNVS_HPCR_HPCALBVAL_P15 (15 << SNVS_HPCR_HPCALBVAL_SHIFT) /* +15 counts per 32768 ticks */
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# define SNVS_HPCR_HPCALBVAL_M16 (16 << SNVS_HPCR_HPCALBVAL_SHIFT) /* -16 counts per 32768 ticks */
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# define SNVS_HPCR_HPCALBVAL_M15 (17 << SNVS_HPCR_HPCALBVAL_SHIFT) /* -15 counts per 32768 ticks */
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# define SNVS_HPCR_HPCALBVAL_M2 (30 << SNVS_HPCR_HPCALBVAL_SHIFT) /* -2 counts per 32768 ticks */
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# define SNVS_HPCR_HPCALBVAL_M1 (31 << SNVS_HPCR_HPCALBVAL_SHIFT) /* -1 counts per 32768 ticks */
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/* Bits 15-23: Reserved */
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#define SNVS_HPCR_BTNCONFIG_SHIFT (24) /* Bits 24-26: Button Configuration */
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#define SNVS_HPCR_BTNCONFIG_MASK (7 << SNVS_HPCR_BTNCONFIG_SHIFT)
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# define SNVS_HPCR_BTNCONFIG_ LOW (0 << SNVS_HPCR_BTNCONFIG_SHIFT) /* Button signal active low */
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# define SNVS_HPCR_BTNCONFIG_HIGH (1 << SNVS_HPCR_BTNCONFIG_SHIFT) /* Button signal active high */
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# define SNVS_HPCR_BTNCONFIG_RISING (2 << SNVS_HPCR_BTNCONFIG_SHIFT) /* Button signal active on rising edge */
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# define SNVS_HPCR_BTNCONFIG_FALLING (3 << SNVS_HPCR_BTNCONFIG_SHIFT) /* Button signal active on falling edge */
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# define SNVS_HPCR_BTNCONFIG_BOTH (4 << SNVS_HPCR_BTNCONFIG_SHIFT) /* Button signal active on any edge */
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#define SNVS_HPCR_BTNMASK (1 << 27) /* Bit 27: Button interrupt mask */
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/* Bits 28-31: Reserved */
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/* SNVS_HP Status Register */
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#define SNVS_HPSR_HPTA (1 << 0) /* Bit 0: HP Time Alarm */
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#define SNVS_HPSR_PI (1 << 1) /* Bit 1: Periodic Interrupt */
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/* Bits 2-3: Reserved */
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#define SNVS_HPSR_LPDIS (1 << 4) /* Bit 4: Low Power Disable */
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/* Bit 95 Reserved */
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#define SNVS_HPSR_BTN (1 << 6) /* Bit 6: Button */
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#define SNVS_HPSR_BI (1 << 7) /* Bit 7: Button Interrupt */
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/* Bits 8-31: Reserved */
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/* SNVS_HP Real Time Counter MSB Register (15-bit MSB of counter) */
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/* SNVS_HP Real Time Counter LSB Register (32-bit LSB of counter) */
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#define SNVS_HPRTCMR_MASK 0x00007fff /* Bits 0-14: HP Real Time Counter */
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/* SNVS_HP Time Alarm MSB Register (15-bit MSB of counter) */
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/* SNVS_HP Time Alarm LSB Register (32-bit LSB of counter) */
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#define SNVS_HPTAMR_MASK 0x00007fff /* Bits 0-14: HP Time Alarm, most-significant 15 bits */
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#define SNVS_HPTALR_
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/* SNVS_LP Lock Register */
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/* Bits 0-3: Reserved */
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#define SNVS_LPLR_MCHL (1 << 4) /* Bit 4: Monotonic Counter Hard Lock */
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#define SNVS_LPLR_GPRHL (1 << 5) /* Bit 5: General Purpose Register Hard Lock */
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/* Bits 6-31: Reserved */
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/* SNVS_LP Control Register */
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/* Bits 0-1: Reserved */
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#define SNVS_LPCR_MCENV (1 << 2) /* Bit 2: Monotonic Counter Enabled and Valid */
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#define SNVS_LPCR_LPWUIEN (1 << 3) /* Bit 3: LP Wake-Up Interrupt Enable */
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/* Bit 4: Reserved */
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#define SNVS_LPCR_DPEN (1 << 5) /* Bit 5: Dumb PMIC Enabled */
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#define SNVS_LPCR_TOP (1 << 6) /* Bit 6: Turn off System Power */
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#define SNVS_LPCR_PWRGLITCHEN (1 << 7) /* Bit 7: Power Glitch Enable */
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/* Bits 8-15: Reserved */
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#define SNVS_LPCR_BTNPRESSTIME_SHIFT (16) /* Bits 16-17: PMIC button press time out values */
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#define SNVS_LPCR_BTNPRESSTIME_MASK (3 << SNVS_LPCR_BTNPRESSTIME_SHIFT)
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# define SNVS_LPCR_BTNPRESSTIME_5SEC (0 << SNVS_LPCR_BTNPRESSTIME_SHIFT) /* 5 secs */
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# define SNVS_LPCR_BTNPRESSTIME_10SEC (1 << SNVS_LPCR_BTNPRESSTIME_SHIFT) /* 10 secs */
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# define SNVS_LPCR_BTNPRESSTIME_15SEC (2 << SNVS_LPCR_BTNPRESSTIME_SHIFT) /* 15 secs */
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# define SNVS_LPCR_BTNPRESSTIME_DESAB (3 << SNVS_LPCR_BTNPRESSTIME_SHIFT) /* Long press disabled */
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#define SNVS_LPCR_DEBOUNCE_SHIFT (18) /* Bits 18-19: Debounce time for BTN input signal */
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#define SNVS_LPCR_DEBOUNCE_MASK (3 << SNVS_LPCR_DEBOUNCE_SHIFT)
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# define SNVS_LPCR_DEBOUNCE_50MS (0 << SNVS_LPCR_DEBOUNCE_SHIFT) /* 50msec debounce */
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# define SNVS_LPCR_DEBOUNCE_100MS (1 << SNVS_LPCR_DEBOUNCE_SHIFT) /* 100msec debounce */
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# define SNVS_LPCR_DEBOUNCE_500MS (2 << SNVS_LPCR_DEBOUNCE_SHIFT) /* 500msec debounce */
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# define SNVS_LPCR_DEBOUNCE_NONE (3 << SNVS_LPCR_DEBOUNCE_SHIFT) /* 0msec debounce */
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#define SNVS_LPCR_ONTIME_SHIFT (20) /* Bits 20-21: ON time configuration */
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#define SNVS_LPCR_ONTIME_MASK (3 << SNVS_LPCR_ONTIME_SHIFT)
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# define SNVS_LPCR_ONTIME_500MS (0 << SNVS_LPCR_ONTIME_SHIFT) /* 500msec off->on transition time */
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# define SNVS_LPCR_ONTIME_50MS (1 << SNVS_LPCR_ONTIME_SHIFT) /* 50msec off->on transition time */
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# define SNVS_LPCR_ONTIME_100MS (2 << SNVS_LPCR_ONTIME_SHIFT) /* 100msec off->on transition time */
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# define SNVS_LPCR_ONTIME_NONE (3 << SNVS_LPCR_ONTIME_SHIFT) /* 0msec off->on transition time */
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#define SNVS_LPCR_PKEN (1 << 22) /* Bit 22: PMIC On Request Enable */
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#define SNVS_LPCR_PKOVERRIDE (1 << 23) /* Bit 23: PMIC On Request Override */
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/* Bits 24-31: Reserved */
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/* SNVS_LP Status Register */
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/* Bits 0-1: Reserved */
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#define SNVS_LPSR_MCR (1 << 2) /* Bit 2: Monotonic Counter Rollover */
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/* Bits 3-16: Reserved */ */
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#define SNVS_LPSR_EO (1 << 17) /* Bit 17: Emergency Off */
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#define SNVS_LPSR_SPO (1 << 18) /* Bit 18: Set Power Off */
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/* Bits 19-31: Reserved */
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/* SNVS_LP Secure Monotonic Counter MSB Register */
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/* SNVS_LP Secure Monotonic Counter LSB Register (32-bit LSB counter value) */
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#define SNVS_LPSMCMR_MONCOUNTER_SHIFT (0) /* Bits 0-15: Monotonic Counter most-significant 16 Bits */
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#define SNVS_LPSMCMR_MONCOUNTER_MASK (0xffff << SNVS_LPSMCMR_MONCOUNTER_SHIFT)
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# define SNVS_LPSMCMR_MONCOUNTER(n) ((uint32_t)(n) << SNVS_LPSMCMR_MONCOUNTER_SHIFT)
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#define SNVS_LPSMCMR_MCERABITS_SHIFT (16) /* Bits 16-31: Monotonic Counter Era Bits */
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#define SNVS_LPSMCMR_MCERABITS_MASK (0xffff << SNVS_LPSMCMR_MCERABITS_SHIFT)
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# define SNVS_LPSMCMR_MCERABITS(n) ((uint32_t)(n) << SNVS_LPSMCMR_MCERABITS_SHIFT)
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/* SNVS_LP General Purpose Register 0 (legacy alias) (32-bit value) */
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/* NVS_LP General Purpose Registers 0 LPGPR0_alias (32-bit value) */
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/* NVS_LP General Purpose Registers 1 LPGPR1_alias (32-bit value) */
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/* NVS_LP General Purpose Registers 2 LPGPR2_alias (32-bit value) */
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/* NVS_LP General Purpose Registers 3 LPGPR3_alias (32-bit value) */
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/* SNVS_LP General Purpose Registers 0 (32-bit value) */
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/* SNVS_LP General Purpose Registers 1 (32-bit value) */
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/* SNVS_LP General Purpose Registers 2 (32-bit value) */
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/* SNVS_LP General Purpose Registers 3 (32-bit value) */
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/* SNVS_HP Version ID Register 1 */
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#define SNVS_HPVIDR1_MINORREV_SHIFT (0) /* Bits 0-7: SNVS block minor version number */
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#define SNVS_HPVIDR1_MINORREV_MASK (0xff << SNVS_HPVIDR1_MINORREV_SHIFT)
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#define SNVS_HPVIDR1_MAJORREV_SHIFT (8) /* Bits 8-15: SNVS block major version number */
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#define SNVS_HPVIDR1_MAJORREV_MASK (0xff << SNVS_HPVIDR1_MAJORREV_SHIFT)
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#define SNVS_HPVIDR1_IPID_SHIFT (16) /* Bits 16-31: SNVS block ID */
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#define SNVS_HPVIDR1_IPID_MASK (0xffff << SNVS_HPVIDR1_IPID_SHIFT)
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/* SNVS_HP Version ID Register 2 */
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#define SNVS_HPVIDR2_CONFIGOPT_SHIFT (0) /* Bits 0-7: SNVS Configuration Options */
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#define SNVS_HPVIDR2_CONFIGOPT_MASK (0xff << SNVS_HPVIDR2_CONFIGOPT_SHIFT)
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#define SNVS_HPVIDR2_ECOREV_SHIFT (8) /* Bits 8-15: SNVS ECO Revision */
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#define SNVS_HPVIDR2_ECOREV_MASK (0xff << SNVS_HPVIDR2_ECOREV_SHIFT)
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#define SNVS_HPVIDR2_INTGOPT_SHIFT (16) /* Bits 16-23: SNVS Integration Options */
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#define SNVS_HPVIDR2_INTGOPT_MASK (0xff << SNVS_HPVIDR2_INTGOPT_SHIFT)
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#define SNVS_HPVIDR2_IPERA_SHIFT (24) /* Bits 24-31: IP Era */
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#define SNVS_HPVIDR2_IPERA_MASK (0xff << SNVS_HPVIDR2_IPERA_SHIFT)
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#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SNVS_H */
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||||
Reference in New Issue
Block a user