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Mostly cosmetic clean-up of comments

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This commit is contained in:
Gregory Nutt
2014-02-17 19:22:53 -06:00
parent 26db6a7609
commit 828dd726d9
7 changed files with 10 additions and 20 deletions
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arch/arm/src/kl/kl_idle.c
+1 -1
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/kl_idle.c
* arch/arm/src/kl/kl_idle.c
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/kl/kl_irq.c
+1 -1
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/kl_irq.c
* arch/arm/src/kl/kl_irq.c
*
* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/kl/kl_irqprio.c
+1 -2
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@@ -1,6 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/kl_irqprio.c
* arch/arm/src/chip/kl_irqprio.c
* arch/arm/src/kl/kl_irqprio.c
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/kl/kl_pwm.c
+2 -4
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@@ -693,12 +693,10 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg
* Initialize one timer for use with the upper_level PWM driver.
*
* Input Parameters:
* timer - A number identifying the timer use. The number of valid timer
* IDs varies with the STM32 MCU and MCU family but is somewhere in
* the range of {1,..,14}.
* timer - A number identifying the timer use.
*
* Returned Value:
* On success, a pointer to the STM32 lower half PWM driver is returned.
* On success, a pointer to the KL lower half PWM driver is returned.
* NULL is returned on any failure.
*
****************************************************************************/
arch/arm/src/kl/kl_pwm.h
+3 -9
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@@ -77,13 +77,9 @@
* configuration settings:
*
* CONFIG_KL_TPMx_CHANNEL - Specifies the timer output channel {1,..,4}
* PWM_TPMx_CHn - One of the values defined in chip/stm32*_pinmap.h. In the case
* PWM_TPMx_CHn - One of the values defined in chip/kl*_pinmap.h. In the case
* where there are multiple pin selections, the correct setting must be provided
* in the arch/board/board.h file.
*
* NOTE: The STM32 timers are each capable of generating different signals on
* each of the four channels with different duty cycles. That capability is
* not supported by this driver: Only one output channel per timer.
*/
#ifdef CONFIG_KL_TPM0_PWM
@@ -175,12 +171,10 @@ extern "C" {
* Initialize one timer for use with the upper_level PWM driver.
*
* Input Parameters:
* timer - A number identifying the timer use. The number of valid timer
* IDs varies with the STM32 MCU and MCU family but is somewhere in
* the range of {1,..,14}.
* timer - A number identifying the timer use.
*
* Returned Value:
* On success, a pointer to the STM32 lower half PWM driver is returned.
* On success, a pointer to the KL lower half PWM driver is returned.
* NULL is returned on any failure.
*
************************************************************************************/
arch/arm/src/samd/Make.defs
+1 -1
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@@ -75,6 +75,6 @@ ifeq ($(CONFIG_NUTTX_KERNEL),y)
CHIP_CSRCS += sam_userspace.c
endif
ifeq ($(CONFIG_NUTTX_KERNEL),y)
ifeq ($(CONFIG_ARCH_IRQPRIO),y)
CHIP_CSRCS += sam_irqprio.c
endif
arch/arm/src/samd/sam_irqprio.c
+1 -2
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@@ -1,6 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32/kl_irqprio.c
* arch/arm/src/chip/kl_irqprio.c
* arch/arm/src/samd/sam_irqprio.c
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>