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Merged in david_s5/nuttx/master_h7 (pull request #900)
stm32 h7 Add ADC and a few fixes for timer and Serial * stm32h7:Fix error when SINGLEWIRE or CONFIG_STM32H7_SERIALBRK_BSDCOMPAT defined * stm32h7:time fixed compile errors with TIM13,TIM14, TIM7 * stm32h7:Added ADC Driver * stmh7x3:Added ADC pins to pin map * stm32h7:Added ADC clocking * nucleo-h743zi:Add ADC Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
David Sidrane
committed by
Gregory Nutt
Gregory Nutt
parent
9e622bd9a4
commit
81e17306d1
@@ -143,6 +143,20 @@ config STM32H7_USART
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default n
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# These are the peripheral selections proper
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config STM32H7_ADC1
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bool "ADC1"
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default n
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select STM32H7_ADC
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config STM32H7_ADC2
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bool "ADC2"
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default n
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select STM32H7_ADC
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config STM32H7_ADC3
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bool "ADC3"
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default n
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select STM32H7_ADC
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config STM32H7_DMA1
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bool "DMA1"
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@@ -2841,6 +2855,354 @@ config STM32H7_PWM_MULTICHAN
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Specifies that the PWM driver supports multiple output
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channels per timer.
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config STM32H7_TIM1_ADC
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bool "TIM1 ADC"
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default n
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depends on STM32H7_TIM1 && STM32H7_ADC
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---help---
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Reserve timer 1 for use by an ADC
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Timer devices may be used for different purposes. If STM32H7_TIM1 is
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defined then the following may also be defined to indicate that the
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timer is intended to be used for ADC conversion. Note that ADC usage
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requires two definition: Not only do you have to assign the timer
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for used by the ADC, but then you also have to configure which ADC
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channel it is assigned to.
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choice
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prompt "Select ADC for use with TIM1"
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default STM32H7_TIM1_ADC1
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depends on STM32H7_TIM1_ADC
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config STM32H7_TIM1_ADC1
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bool "Use TIM1 for ADC1"
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depends on STM32H7_ADC1
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select STM32H7_HAVE_ADC1_TIMER
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---help---
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Reserve TIM1 to trigger ADC1
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config STM32H7_TIM1_ADC2
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bool "Use TIM1 for ADC2"
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depends on STM32H7_ADC2
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select STM32H7_HAVE_ADC2_TIMER
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---help---
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Reserve TIM1 to trigger ADC2
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config STM32H7_TIM1_ADC3
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bool "Use TIM1 for ADC3"
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depends on STM32H7_ADC3
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select STM32H7_HAVE_ADC3_TIMER
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---help---
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Reserve TIM1 to trigger ADC3
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endchoice
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config STM32H7_TIM2_ADC
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bool "TIM2 ADC"
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default n
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depends on STM32H7_TIM2 && STM32H7_ADC
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---help---
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Reserve timer 2 for use by an ADC
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Timer devices may be used for different purposes. If STM32H7_TIM2 is
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defined then the following may also be defined to indicate that the
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timer is intended to be used for ADC conversion. Note that ADC usage
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requires two definition: Not only do you have to assign the timer
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for used by the ADC, but then you also have to configure which ADC
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channel it is assigned to.
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choice
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prompt "Select ADC for use with TIM2"
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default STM32H7_TIM2_ADC1
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depends on STM32H7_TIM2_ADC
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config STM32H7_TIM2_ADC1
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bool "Use TIM2 for ADC1"
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depends on STM32H7_ADC1
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select STM32H7_HAVE_ADC1_TIMER
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---help---
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Reserve TIM2 to trigger ADC1
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config STM32H7_TIM2_ADC2
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bool "Use TIM2 for ADC2"
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depends on STM32H7_ADC2
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select STM32H7_HAVE_ADC2_TIMER
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---help---
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Reserve TIM2 to trigger ADC2
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config STM32H7_TIM2_ADC3
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bool "Use TIM2 for ADC3"
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depends on STM32H7_ADC3
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select STM32H7_HAVE_ADC3_TIMER
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---help---
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Reserve TIM2 to trigger ADC3
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endchoice
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config STM32H7_TIM3_ADC
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bool "TIM3 ADC"
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default n
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depends on STM32H7_TIM3 && STM32H7_ADC
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---help---
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Reserve timer 3 for use by an ADC
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Timer devices may be used for different purposes. If STM32H7_TIM3 is
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defined then the following may also be defined to indicate that the
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timer is intended to be used for ADC conversion. Note that ADC usage
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requires two definition: Not only do you have to assign the timer
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for used by the ADC, but then you also have to configure which ADC
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channel it is assigned to.
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choice
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prompt "Select ADC for use with TIM3"
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default STM32H7_TIM3_ADC1
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depends on STM32H7_TIM3_ADC
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config STM32H7_TIM3_ADC1
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bool "Use TIM3 for ADC1"
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depends on STM32H7_ADC1
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select STM32H7_HAVE_ADC1_TIMER
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---help---
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Reserve TIM3 to trigger ADC1
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config STM32H7_TIM3_ADC2
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bool "Use TIM3 for ADC2"
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depends on STM32H7_ADC2
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select STM32H7_HAVE_ADC2_TIMER
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---help---
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Reserve TIM3 to trigger ADC2
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config STM32H7_TIM3_ADC3
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bool "Use TIM3 for ADC3"
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depends on STM32H7_ADC3
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select STM32H7_HAVE_ADC3_TIMER
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---help---
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Reserve TIM3 to trigger ADC3
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endchoice
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config STM32H7_TIM4_ADC
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bool "TIM4 ADC"
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default n
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depends on STM32H7_TIM4 && STM32H7_ADC
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---help---
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Reserve timer 4 for use by ADC
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Timer devices may be used for different purposes. If STM32H7_TIM4 is
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defined then the following may also be defined to indicate that the
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timer is intended to be used for ADC conversion. Note that ADC usage
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requires two definition: Not only do you have to assign the timer
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for used by the ADC, but then you also have to configure which ADC
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channel it is assigned to.
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choice
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prompt "Select ADC for use with TIM4"
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default STM32H7_TIM4_ADC1
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depends on STM32H7_TIM4_ADC
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config STM32H7_TIM4_ADC1
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bool "Use TIM4 for ADC1"
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depends on STM32H7_ADC1
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select STM32H7_HAVE_ADC1_TIMER
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---help---
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Reserve TIM4 to trigger ADC1
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config STM32H7_TIM4_ADC2
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bool "Use TIM4 for ADC2"
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depends on STM32H7_ADC2
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select STM32H7_HAVE_ADC2_TIMER
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---help---
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Reserve TIM4 to trigger ADC2
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config STM32H7_TIM4_ADC3
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bool "Use TIM4 for ADC3"
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depends on STM32H7_ADC3
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select STM32H7_HAVE_ADC3_TIMER
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---help---
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Reserve TIM4 to trigger ADC3
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endchoice
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config STM32H7_TIM6_ADC
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bool "TIM6 ADC"
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default n
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depends on STM32H7_TIM6 && STM32H7_ADC
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---help---
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Reserve timer 6 for use by ADC
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Timer devices may be used for different purposes. If STM32H7_TIM6 is
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defined then the following may also be defined to indicate that the
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timer is intended to be used for ADC conversion. Note that ADC usage
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requires two definition: Not only do you have to assign the timer
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for used by the ADC, but then you also have to configure which ADC
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channel it is assigned to.
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choice
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prompt "Select ADC for use with TIM6"
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default STM32H7_TIM6_ADC1
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depends on STM32H7_TIM6_ADC
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config STM32H7_TIM6_ADC1
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bool "Use TIM6 for ADC1"
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depends on STM32H7_ADC1
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select STM32H7_HAVE_ADC1_TIMER
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---help---
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Reserve TIM6 to trigger ADC1
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config STM32H7_TIM6_ADC2
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bool "Use TIM6 for ADC2"
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depends on STM32H7_ADC2
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select STM32H7_HAVE_ADC2_TIMER
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---help---
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Reserve TIM6 to trigger ADC2
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config STM32H7_TIM6_ADC3
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bool "Use TIM6 for ADC3"
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depends on STM32H7_ADC3
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select STM32H7_HAVE_ADC3_TIMER
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---help---
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Reserve TIM6 to trigger ADC3
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endchoice
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config STM32H7_TIM8_ADC
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bool "TIM8 ADC"
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default n
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depends on STM32H7_TIM8 && STM32H7_ADC
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---help---
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Reserve timer 8 for use by ADC
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Timer devices may be used for different purposes. If STM32H7_TIM8 is
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defined then the following may also be defined to indicate that the
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timer is intended to be used for ADC conversion. Note that ADC usage
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requires two definition: Not only do you have to assign the timer
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for used by the ADC, but then you also have to configure which ADC
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channel it is assigned to.
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choice
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prompt "Select ADC for use with TIM8"
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default STM32H7_TIM8_ADC1
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depends on STM32H7_TIM8_ADC
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config STM32H7_TIM8_ADC1
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bool "Use TIM8 for ADC1"
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depends on STM32H7_ADC1
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select STM32H7_HAVE_ADC1_TIMER
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---help---
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Reserve TIM8 to trigger ADC1
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config STM32H7_TIM8_ADC2
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bool "Use TIM8 for ADC2"
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depends on STM32H7_ADC2
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select STM32H7_HAVE_ADC2_TIMER
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---help---
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Reserve TIM8 to trigger ADC2
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config STM32H7_TIM8_ADC3
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bool "Use TIM8 for ADC3"
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depends on STM32H7_ADC3
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select STM32H7_HAVE_ADC3_TIMER
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---help---
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Reserve TIM8 to trigger ADC3
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endchoice
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config STM32H7_TIM15_ADC
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bool "TIM15 ADC"
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default n
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depends on STM32H7_TIM15 && STM32H7_ADC
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---help---
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Reserve timer 15 for use by ADC
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Timer devices may be used for different purposes. If STM32H7_TIM15 is
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defined then the following may also be defined to indicate that the
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timer is intended to be used for ADC conversion. Note that ADC usage
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requires two definition: Not only do you have to assign the timer
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for used by the ADC, but then you also have to configure which ADC
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channel it is assigned to.
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choice
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prompt "Select ADC for use with TIM15"
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default STM32H7_TIM15_ADC1
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depends on STM32H7_TIM15_ADC
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config STM32H7_TIM15_ADC1
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bool "Use TIM15 for ADC1"
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depends on STM32H7_ADC1
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select STM32H7_HAVE_ADC1_TIMER
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---help---
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Reserve TIM15 to trigger ADC1
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config STM32H7_TIM15_ADC2
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bool "Use TIM15 for ADC2"
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depends on STM32H7_ADC2
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select STM32H7_HAVE_ADC2_TIMER
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---help---
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Reserve TIM15 to trigger ADC2
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config STM32H7_TIM15_ADC3
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bool "Use TIM15 for ADC3"
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depends on STM32H7_ADC3
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select STM32H7_HAVE_ADC3_TIMER
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---help---
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Reserve TIM15 to trigger ADC3
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endchoice
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config STM32H7_HAVE_ADC1_TIMER
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bool
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config STM32H7_HAVE_ADC2_TIMER
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bool
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config STM32H7_HAVE_ADC3_TIMER
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bool
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config STM32H7_ADC1_SAMPLE_FREQUENCY
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int "ADC1 Sampling Frequency"
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default 100
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depends on STM32H7_HAVE_ADC1_TIMER
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---help---
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ADC1 sampling frequency. Default: 100Hz
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config STM32H7_ADC1_TIMTRIG
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int "ADC1 Timer Trigger"
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default 0
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range 0 4
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depends on STM32H7_HAVE_ADC1_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
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config STM32H7_ADC2_SAMPLE_FREQUENCY
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int "ADC2 Sampling Frequency"
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default 100
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depends on STM32H7_HAVE_ADC2_TIMER
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---help---
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ADC2 sampling frequency. Default: 100Hz
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config STM32H7_ADC2_TIMTRIG
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int "ADC2 Timer Trigger"
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default 0
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range 0 4
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depends on STM32H7_HAVE_ADC2_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
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config STM32H7_ADC3_SAMPLE_FREQUENCY
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int "ADC3 Sampling Frequency"
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default 100
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depends on STM32H7_HAVE_ADC3_TIMER
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---help---
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ADC3 sampling frequency. Default: 100Hz
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config STM32H7_ADC3_TIMTRIG
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int "ADC3 Timer Trigger"
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default 0
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range 0 4
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depends on STM32H7_HAVE_ADC3_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
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config STM32H7_TIM1_CAP
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bool "TIM1 Capture"
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default n
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@@ -102,6 +102,10 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
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CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c
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endif
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ifeq ($(CONFIG_STM32H7_ADC),y)
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CHIP_CSRCS += stm32_adc.c
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endif
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ifeq ($(CONFIG_STM32H7_DMA),y)
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CHIP_CSRCS += stm32_dma.c
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endif
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File diff suppressed because it is too large
Load Diff
@@ -70,6 +70,68 @@
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* pins in this file.
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*/
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/* ADC */
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#define GPIO_ADC1_INP2 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN11)
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#define GPIO_ADC1_INN2 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN12)
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#define GPIO_ADC1_INP6 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN12)
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#define GPIO_ADC1_INP16 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
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#define GPIO_ADC1_INN16 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
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#define GPIO_ADC1_INP17 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
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#define GPIO_ADC12_INP0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0_C)
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#define GPIO_ADC12_INP1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1_C)
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#define GPIO_ADC12_INN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0_C)
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#define GPIO_ADC12_INP3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
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#define GPIO_ADC12_INN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
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#define GPIO_ADC12_INP4 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4)
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#define GPIO_ADC12_INN4 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
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#define GPIO_ADC12_INP5 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
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#define GPIO_ADC12_INN5 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
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#define GPIO_ADC12_INP7 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
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#define GPIO_ADC12_INP8 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
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#define GPIO_ADC12_INP9 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
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#define GPIO_ADC12_INN12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
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#define GPIO_ADC12_INP13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
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#define GPIO_ADC12_INP14 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
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#define GPIO_ADC12_INP15 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
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#define GPIO_ADC12_INP18 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
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#define GPIO_ADC12_INN18 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
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#define GPIO_ADC12_INP19 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
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#define GPIO_ADC123_INP10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
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#define GPIO_ADC123_INN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
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#define GPIO_ADC123_INP11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
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#define GPIO_ADC123_INN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
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#define GPIO_ADC123_INP12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
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#define GPIO_ADC2_INN2 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN14)
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#define GPIO_ADC2_INP2 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN13)
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#define GPIO_ADC2_INP6 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN14)
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#define GPIO_ADC3_INP0 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2_C)
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#define GPIO_ADC3_INP1 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3_C)
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#define GPIO_ADC3_INN1 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2_C)
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#define GPIO_ADC3_INP2 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN9)
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#define GPIO_ADC3_INN2 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN10)
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#define GPIO_ADC3_INP3 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN7)
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#define GPIO_ADC3_INN3 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN8)
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#define GPIO_ADC3_INP4 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN5)
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#define GPIO_ADC3_INN4 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN6)
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#define GPIO_ADC3_INP5 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN3)
|
||||
#define GPIO_ADC3_INN5 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN4)
|
||||
#define GPIO_ADC3_INP6 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN10)
|
||||
#define GPIO_ADC3_INP7 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_ADC3_INP8 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_ADC3_INP9 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN4)
|
||||
#define GPIO_ADC3_INP13 (GPIO_ANALOG|GPIO_PORTH|GPIO_PIN2)
|
||||
#define GPIO_ADC3_INN13 (GPIO_ANALOG|GPIO_PORTH|GPIO_PIN3)
|
||||
#define GPIO_ADC3_INP14 (GPIO_ANALOG|GPIO_PORTH|GPIO_PIN3)
|
||||
#define GPIO_ADC3_INN14 (GPIO_ANALOG|GPIO_PORTH|GPIO_PIN4)
|
||||
#define GPIO_ADC3_INP15 (GPIO_ANALOG|GPIO_PORTH|GPIO_PIN4)
|
||||
#define GPIO_ADC3_INN15 (GPIO_ANALOG|GPIO_PORTH|GPIO_PIN5)
|
||||
#define GPIO_ADC3_INP16 (GPIO_ANALOG|GPIO_PORTH|GPIO_PIN5)
|
||||
|
||||
/* CAN */
|
||||
|
||||
#define GPIO_CAN1_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1482,11 +1482,14 @@ static int up_interrupt(int irq, void *context, FAR void *arg)
|
||||
static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
|
||||
{
|
||||
#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \
|
||||
|| defined(CONFIG_STM32H7_USART_SINGLEWIRE) \
|
||||
|| defined(CONFIG_STM32H7_SERIALBRK_BSDCOMPAT)
|
||||
struct inode *inode = filep->f_inode;
|
||||
struct uart_dev_s *dev = inode->i_private;
|
||||
#endif
|
||||
#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32H7_SERIALBRK_BSDCOMPAT)
|
||||
#if defined(CONFIG_SERIAL_TERMIOS) \
|
||||
|| defined(CONFIG_STM32H7_USART_SINGLEWIRE) \
|
||||
|| defined(CONFIG_STM32H7_SERIALBRK_BSDCOMPAT)
|
||||
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
|
||||
#endif
|
||||
int ret = OK;
|
||||
@@ -1701,21 +1704,12 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
|
||||
|
||||
flags = enter_critical_section();
|
||||
cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET);
|
||||
up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK);
|
||||
up_serialout(priv, STM32_USART_RQR_OFFSET, cr1 | USART_RQR_SBKRQ);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
break;
|
||||
|
||||
case TIOCCBRK: /* No BSD compatibility: May turn off break too soon */
|
||||
{
|
||||
uint32_t cr1;
|
||||
irqstate_t flags;
|
||||
|
||||
flags = enter_critical_section();
|
||||
cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET);
|
||||
up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
case TIOCCBRK: /* No BSD compatibility: HW does not support stopping a break */
|
||||
break;
|
||||
# endif
|
||||
#endif
|
||||
|
||||
@@ -389,7 +389,7 @@ struct stm32_tim_priv_s stm32_tim12_priv =
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_TIM13
|
||||
struct stm32_tim_priv_s stm32_tim12_priv =
|
||||
struct stm32_tim_priv_s stm32_tim13_priv =
|
||||
{
|
||||
.ops = &stm32_tim_ops,
|
||||
.mode = STM32_TIM_MODE_UNUSED,
|
||||
@@ -398,7 +398,7 @@ struct stm32_tim_priv_s stm32_tim12_priv =
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_TIM14
|
||||
struct stm32_tim_priv_s stm32_tim12_priv =
|
||||
struct stm32_tim_priv_s stm32_tim14_priv =
|
||||
{
|
||||
.ops = &stm32_tim_ops,
|
||||
.mode = STM32_TIM_MODE_UNUSED,
|
||||
@@ -1430,7 +1430,7 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
|
||||
#endif
|
||||
#ifdef CONFIG_STM32H7_TIM7
|
||||
case STM32_TIM7_BASE:
|
||||
modifyreg32(STM32_RCC_APB1LENR, RCC_APB1ENR_TIM7EN, 0);
|
||||
modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM7EN, 0);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32H7_TIM8
|
||||
@@ -1444,7 +1444,7 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32H7_TIM13
|
||||
case STM32_TIM12_BASE:
|
||||
case STM32_TIM13_BASE:
|
||||
modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM13EN, 0);
|
||||
break;
|
||||
#endif
|
||||
|
||||
@@ -145,6 +145,11 @@ static inline void rcc_enableahb1(void)
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_AHB1ENR);
|
||||
#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2)
|
||||
/* ADC1 & 2 clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_ADC12EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_DMA1
|
||||
/* DMA 1 clock enable */
|
||||
@@ -262,6 +267,12 @@ static inline void rcc_enableahb4(void)
|
||||
|
||||
regval = getreg32(STM32_RCC_AHB4ENR);
|
||||
|
||||
#ifdef CONFIG_STM32H7_ADC3
|
||||
/* ADC3 clock enable */
|
||||
|
||||
regval |= RCC_AHB4ENR_ADC3EN;
|
||||
#endif
|
||||
|
||||
/* Enable GPIO, GPIOB, ... GPIOK */
|
||||
|
||||
#if STM32H7_NGPIO > 0
|
||||
@@ -673,16 +684,26 @@ static void stm32_stdclockconfig(void)
|
||||
regval |= RCC_CR_PLL1ON;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* TODO: Enable the PLL2 */
|
||||
/* Enable the PLL2 */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLL2ON;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* TODO: Enable the PLL3 */
|
||||
|
||||
/* Wait until the PLL is ready */
|
||||
/* Wait until the PLL1 is ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL1RDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Wait until the PLL2 is ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Configure FLASH wait states */
|
||||
|
||||
regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES);
|
||||
@@ -760,6 +781,16 @@ static void stm32_stdclockconfig(void)
|
||||
putreg32(regval, STM32_RCC_D2CCIP2R);
|
||||
#endif
|
||||
|
||||
/* Configure ADC source clock */
|
||||
|
||||
#if defined(STM32_RCC_D3CCIPR_ADCSEL)
|
||||
regval = getreg32(STM32_RCC_D3CCIPR);
|
||||
regval &= ~RCC_D3CCIPR_ADCSEL_MASK;
|
||||
regval |= STM32_RCC_D3CCIPR_ADCSEL;
|
||||
putreg32(regval, STM32_RCC_D3CCIPR);
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK)
|
||||
/* Low speed internal clock source LSI */
|
||||
|
||||
|
||||
@@ -134,15 +134,17 @@
|
||||
|
||||
/* PLL2 */
|
||||
|
||||
#define STM32_PLLCFG_PLL2CFG 0
|
||||
#define STM32_PLLCFG_PLL2M 0
|
||||
#define STM32_PLLCFG_PLL2N 0
|
||||
#define STM32_PLLCFG_PLL2P 0
|
||||
#define STM32_PLLCFG_PLL2Q 0
|
||||
#define STM32_PLLCFG_PLL2R 0
|
||||
#define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE | \
|
||||
RCC_PLLCFGR_PLL2RGE_4_8_MHZ | \
|
||||
RCC_PLLCFGR_DIVP2EN)
|
||||
#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(2)
|
||||
#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(200)
|
||||
#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(40)
|
||||
#define STM32_PLLCFG_PLL2Q 0
|
||||
#define STM32_PLLCFG_PLL2R 0
|
||||
|
||||
#define STM32_VCO2_FREQUENCY
|
||||
#define STM32_PLL2P_FREQUENCY
|
||||
#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 200)
|
||||
#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 2)
|
||||
#define STM32_PLL2Q_FREQUENCY
|
||||
#define STM32_PLL2R_FREQUENCY
|
||||
|
||||
@@ -248,7 +250,11 @@
|
||||
|
||||
/* USB 1 and 2 clock source - HSI48 */
|
||||
|
||||
#define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_HSI48
|
||||
#define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_HSI48
|
||||
|
||||
/* ADC 1 2 3 clock source - pll2_pclk */
|
||||
|
||||
#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2
|
||||
|
||||
/* FLASH wait states
|
||||
*
|
||||
|
||||
@@ -38,6 +38,10 @@
|
||||
ASRCS =
|
||||
CSRCS = stm32_boot.c stm32_bringup.c
|
||||
|
||||
ifeq ($(CONFIG_ADC),y)
|
||||
CSRCS += stm32_adc.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_LEDS),y)
|
||||
CSRCS += stm32_autoleds.c
|
||||
else
|
||||
|
||||
@@ -186,8 +186,6 @@ void stm32_spidev_initialize(void);
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
// TODO: implement ADC or delete this
|
||||
|
||||
#ifdef CONFIG_ADC
|
||||
int stm32_adc_setup(void);
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,218 @@
|
||||
/************************************************************************************
|
||||
* configs/nucleo-h743zi/src/stm32_adc.c
|
||||
*
|
||||
* Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david.sidrane@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/analog/adc.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32_adc.h"
|
||||
#include "nucleo-h743zi.h"
|
||||
|
||||
#ifdef CONFIG_ADC
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Configuration ********************************************************************/
|
||||
/* Up to 3 ADC interfaces are supported */
|
||||
|
||||
#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || defined(CONFIG_STM32H7_ADC3)
|
||||
#ifndef CONFIG_STM32H7_ADC1
|
||||
# warning "Channel information only available for ADC1"
|
||||
#endif
|
||||
|
||||
/* The number of ADC channels in the conversion list */
|
||||
|
||||
#define ADC1_NCHANNELS 5
|
||||
#define ADC3_NCHANNELS 1
|
||||
|
||||
/************************************************************************************
|
||||
* Private Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32H7_ADC1
|
||||
/* Identifying number of each ADC channel: Variable Resistor.
|
||||
*
|
||||
* ADC1: {5, 10, 12, 13, 15};
|
||||
*/
|
||||
|
||||
static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = {5, 10, 12, 13, 15};
|
||||
|
||||
/* Configurations of pins used by each ADC channels
|
||||
*
|
||||
* ADC1: {GPIO_ADC12_INP5, GPIO_ADC123_INP10, GPIO_ADC123_INP12, GPIO_ADC12_INP13,
|
||||
* GPIO_ADC12_INP15};
|
||||
*/
|
||||
|
||||
static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = {GPIO_ADC12_INP5, \
|
||||
GPIO_ADC123_INP10, \
|
||||
GPIO_ADC123_INP12, \
|
||||
GPIO_ADC12_INP13, \
|
||||
GPIO_ADC12_INP15};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_ADC3
|
||||
/* Identifying number of each ADC channel: Variable Resistor.
|
||||
*
|
||||
* ADC3: {6,};
|
||||
*/
|
||||
|
||||
static const uint8_t g_adc3_chanlist[ADC1_NCHANNELS] = {6};
|
||||
|
||||
/* Configurations of pins used by each ADC channels
|
||||
*
|
||||
*
|
||||
* ADC3: {GPIO_ADC3_INP6}
|
||||
*/
|
||||
|
||||
static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = {GPIO_ADC3_INP6};
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Private Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_adc_setup
|
||||
*
|
||||
* Description:
|
||||
* Initialize ADC and register the ADC driver.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int stm32_adc_setup(void)
|
||||
{
|
||||
#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3)
|
||||
static bool initialized = false;
|
||||
struct adc_dev_s *adc;
|
||||
int ret;
|
||||
int i;
|
||||
char devname[] = "/dev/adc0";
|
||||
|
||||
/* Check if we have already initialized */
|
||||
|
||||
if (!initialized)
|
||||
{
|
||||
#endif
|
||||
#if defined(CONFIG_STM32H7_ADC1)
|
||||
/* Configure the pins as analog inputs for the selected channels */
|
||||
|
||||
for (i = 0; i < ADC1_NCHANNELS; i++)
|
||||
{
|
||||
if (g_adc1_pinlist[i] != 0)
|
||||
{
|
||||
stm32_configgpio(g_adc1_pinlist[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC1 interface\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Register the ADC driver at "/dev/adc0" */
|
||||
|
||||
ret = adc_register(devname, adc);
|
||||
if (ret < 0)
|
||||
{
|
||||
aerr("ERROR: adc_register(%s) failed: %d\n", devname, ret);
|
||||
return ret;
|
||||
}
|
||||
devname[8]++;
|
||||
#endif
|
||||
#if defined(CONFIG_STM32H7_ADC3)
|
||||
/* Configure the pins as analog inputs for the selected channels */
|
||||
|
||||
for (i = 0; i < ADC3_NCHANNELS; i++)
|
||||
{
|
||||
if (g_adc3_pinlist[i] != 0)
|
||||
{
|
||||
stm32_configgpio(g_adc3_pinlist[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC3 interface\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Register the ADC driver at "/dev/adc0 or 1" */
|
||||
|
||||
ret = adc_register(devname, adc);
|
||||
if (ret < 0)
|
||||
{
|
||||
aerr("ERROR: adc_register(%s) failed: %d\n", devname, ret);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3)
|
||||
/* Now we are initialized */
|
||||
|
||||
initialized = true;
|
||||
}
|
||||
|
||||
return OK;
|
||||
#else
|
||||
return -ENOSYS;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */
|
||||
#endif /* CONFIG_ADC */
|
||||
Reference in New Issue
Block a user