mirror of
https://github.com/apache/nuttx.git
synced 2026-05-13 02:18:38 +08:00
boards/stm32l1: migrate to new pinmap
migrate stm32l1 to new pinmap Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl
committed by
Alan C. Assis
Alan C. Assis
parent
fe5c65649a
commit
801bf3e9a4
@@ -8,6 +8,7 @@
|
||||
# CONFIG_LIBC_LONG_LONG is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
# CONFIG_NX_DISABLE_16BPP is not set
|
||||
# CONFIG_STM32_USE_LEGACY_PINMAP is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="nucleo-l152re"
|
||||
CONFIG_ARCH_BOARD_NUCLEO_L152RE=y
|
||||
|
||||
@@ -7,6 +7,7 @@
|
||||
#
|
||||
# CONFIG_LIBC_LONG_LONG is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
# CONFIG_STM32_USE_LEGACY_PINMAP is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="nucleo-l152re"
|
||||
CONFIG_ARCH_BOARD_NUCLEO_L152RE=y
|
||||
|
||||
@@ -210,8 +210,8 @@
|
||||
* USART2_TX - PA2
|
||||
*/
|
||||
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */
|
||||
#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_40MHz) /* PA3 */
|
||||
#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_40MHz) /* PA2 */
|
||||
|
||||
/* SPI1 */
|
||||
|
||||
@@ -221,7 +221,7 @@
|
||||
|
||||
/* I2C1 */
|
||||
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 /* PB8 CN5 pin 10, D15 */
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 /* PB9 CN5 pin 9, D14 */
|
||||
#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_40MHz) /* PB8 CN5 pin 10, D15 */
|
||||
#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_40MHz) /* PB9 CN5 pin 9, D14 */
|
||||
|
||||
#endif /* __BOARDS_ARM_STM32_NUCLEO_L152RE_INCLUDE_BOARD_H */
|
||||
|
||||
@@ -12,6 +12,7 @@
|
||||
# CONFIG_NSH_DISABLE_PS is not set
|
||||
# CONFIG_NSH_DISABLE_XD is not set
|
||||
# CONFIG_SERIAL is not set
|
||||
# CONFIG_STM32_USE_LEGACY_PINMAP is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="stm32ldiscovery"
|
||||
CONFIG_ARCH_BOARD_STM32L_DISCOVERY=y
|
||||
|
||||
@@ -11,6 +11,7 @@
|
||||
# CONFIG_NSH_DISABLE_HEXDUMP is not set
|
||||
# CONFIG_NSH_DISABLE_PS is not set
|
||||
# CONFIG_NSH_DISABLE_XD is not set
|
||||
# CONFIG_STM32_USE_LEGACY_PINMAP is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="stm32ldiscovery"
|
||||
CONFIG_ARCH_BOARD_STM32L_DISCOVERY=y
|
||||
|
||||
@@ -248,25 +248,25 @@
|
||||
#if !defined(CONFIG_STM32_LCD)
|
||||
/* Select PA9 and PA10 if the LCD is not enabled */
|
||||
|
||||
# define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */
|
||||
# define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */
|
||||
# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_40MHz) /* PA10 */
|
||||
# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_40MHz) /* PA9 */
|
||||
|
||||
/* This there are no other options for USART1 on this part */
|
||||
|
||||
# define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */
|
||||
# define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */
|
||||
# define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_40MHz) /* PA3 */
|
||||
# define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_40MHz) /* PA2 */
|
||||
|
||||
/* Arbitrarily select PB10 and PB11 */
|
||||
|
||||
# define GPIO_USART3_RX GPIO_USART3_RX_1 /* PB11 */
|
||||
# define GPIO_USART3_TX GPIO_USART3_TX_1 /* PB10 */
|
||||
# define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_40MHz) /* PB11 */
|
||||
# define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_40MHz) /* PB10 */
|
||||
|
||||
#elif !defined(CONFIG_ARCH_LEDS)
|
||||
|
||||
/* Select PB6 and PB7 if the LEDs are not enabled */
|
||||
|
||||
# define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */
|
||||
# define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */
|
||||
# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_40MHz) /* PB7 */
|
||||
# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_40MHz) /* PB6 */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -184,34 +184,34 @@
|
||||
* PC11 LCD_SEG41 LCD SEG23
|
||||
*/
|
||||
|
||||
#define BOARD_SLCD_COM0 GPIO_LCD_COM0 /* PA8 */
|
||||
#define BOARD_SLCD_COM1 GPIO_LCD_COM1 /* PA9 */
|
||||
#define BOARD_SLCD_COM2 GPIO_LCD_COM2 /* PA10 */
|
||||
#define BOARD_SLCD_COM3 GPIO_LCD_COM3 /* PB9 */
|
||||
#define BOARD_SLCD_SEG0 GPIO_LCD_SEG0 /* PA1 */
|
||||
#define BOARD_SLCD_SEG1 GPIO_LCD_SEG1 /* PA2 */
|
||||
#define BOARD_SLCD_SEG2 GPIO_LCD_SEG2 /* PA3 */
|
||||
#define BOARD_SLCD_SEG3 GPIO_LCD_SEG7 /* PB3 */
|
||||
#define BOARD_SLCD_SEG4 GPIO_LCD_SEG8 /* PB4 */
|
||||
#define BOARD_SLCD_SEG5 GPIO_LCD_SEG9 /* PB5 */
|
||||
#define BOARD_SLCD_SEG6 GPIO_LCD_SEG10 /* PB10 */
|
||||
#define BOARD_SLCD_SEG7 GPIO_LCD_SEG11 /* PB11 */
|
||||
#define BOARD_SLCD_SEG8 GPIO_LCD_SEG12 /* PB12 */
|
||||
#define BOARD_SLCD_SEG9 GPIO_LCD_SEG13 /* PB13 */
|
||||
#define BOARD_SLCD_SEG10 GPIO_LCD_SEG14 /* PB14 */
|
||||
#define BOARD_SLCD_SEG11 GPIO_LCD_SEG15 /* PB15 */
|
||||
#define BOARD_SLCD_SEG12 GPIO_LCD_SEG17 /* PA15 */
|
||||
#define BOARD_SLCD_SEG13 GPIO_LCD_SEG16 /* PB8 */
|
||||
#define BOARD_SLCD_SEG14 GPIO_LCD_SEG18 /* PC0 */
|
||||
#define BOARD_SLCD_SEG15 GPIO_LCD_SEG19 /* PC1 */
|
||||
#define BOARD_SLCD_SEG16 GPIO_LCD_SEG20 /* PC2 */
|
||||
#define BOARD_SLCD_SEG17 GPIO_LCD_SEG21 /* PC3 */
|
||||
#define BOARD_SLCD_SEG18 GPIO_LCD_SEG24 /* PC6 */
|
||||
#define BOARD_SLCD_SEG19 GPIO_LCD_SEG25 /* PC7 */
|
||||
#define BOARD_SLCD_SEG20 GPIO_LCD_SEG26 /* PC8 */
|
||||
#define BOARD_SLCD_SEG21 GPIO_LCD_SEG27 /* PC9 */
|
||||
#define BOARD_SLCD_SEG22 GPIO_LCD_SEG40 /* PC10 */
|
||||
#define BOARD_SLCD_SEG23 GPIO_LCD_SEG41 /* PC11 */
|
||||
#define BOARD_SLCD_COM0 GPIO_LCD_COM0_0 /* PA8 */
|
||||
#define BOARD_SLCD_COM1 GPIO_LCD_COM1_0 /* PA9 */
|
||||
#define BOARD_SLCD_COM2 GPIO_LCD_COM2_0 /* PA10 */
|
||||
#define BOARD_SLCD_COM3 GPIO_LCD_COM3_0 /* PB9 */
|
||||
#define BOARD_SLCD_SEG0 GPIO_LCD_SEG0_0 /* PA1 */
|
||||
#define BOARD_SLCD_SEG1 GPIO_LCD_SEG1_0 /* PA2 */
|
||||
#define BOARD_SLCD_SEG2 GPIO_LCD_SEG2_0 /* PA3 */
|
||||
#define BOARD_SLCD_SEG3 GPIO_LCD_SEG7_0 /* PB3 */
|
||||
#define BOARD_SLCD_SEG4 GPIO_LCD_SEG8_0 /* PB4 */
|
||||
#define BOARD_SLCD_SEG5 GPIO_LCD_SEG9_0 /* PB5 */
|
||||
#define BOARD_SLCD_SEG6 GPIO_LCD_SEG10_0 /* PB10 */
|
||||
#define BOARD_SLCD_SEG7 GPIO_LCD_SEG11_0 /* PB11 */
|
||||
#define BOARD_SLCD_SEG8 GPIO_LCD_SEG12_0 /* PB12 */
|
||||
#define BOARD_SLCD_SEG9 GPIO_LCD_SEG13_0 /* PB13 */
|
||||
#define BOARD_SLCD_SEG10 GPIO_LCD_SEG14_0 /* PB14 */
|
||||
#define BOARD_SLCD_SEG11 GPIO_LCD_SEG15_0 /* PB15 */
|
||||
#define BOARD_SLCD_SEG12 GPIO_LCD_SEG17_0 /* PA15 */
|
||||
#define BOARD_SLCD_SEG13 GPIO_LCD_SEG16_0 /* PB8 */
|
||||
#define BOARD_SLCD_SEG14 GPIO_LCD_SEG18_0 /* PC0 */
|
||||
#define BOARD_SLCD_SEG15 GPIO_LCD_SEG19_0 /* PC1 */
|
||||
#define BOARD_SLCD_SEG16 GPIO_LCD_SEG20_0 /* PC2 */
|
||||
#define BOARD_SLCD_SEG17 GPIO_LCD_SEG21_0 /* PC3 */
|
||||
#define BOARD_SLCD_SEG18 GPIO_LCD_SEG24_0 /* PC6 */
|
||||
#define BOARD_SLCD_SEG19 GPIO_LCD_SEG25_0 /* PC7 */
|
||||
#define BOARD_SLCD_SEG20 GPIO_LCD_SEG26_0 /* PC8 */
|
||||
#define BOARD_SLCD_SEG21 GPIO_LCD_SEG27_0 /* PC9 */
|
||||
#define BOARD_SLCD_SEG22 GPIO_LCD_SEG40_0 /* PC10 */
|
||||
#define BOARD_SLCD_SEG23 GPIO_LCD_SEG41_0 /* PC11 */
|
||||
|
||||
#define BOARD_SLCD_NCOM 4
|
||||
#define BOARD_SLCD_NSEG 24
|
||||
|
||||
Reference in New Issue
Block a user