mirror of
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Initial support for the Kinetis L family and the Freedom KL25Z board from Alan Carvalho de Assis
This commit is contained in:
Gregory Nutt
@@ -4548,4 +4548,11 @@
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kconfig-config frontends tools (2013-4-12).
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* configs/nucleus2g/usbserial: Converted to use the
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kconfig-config frontends tools (2013-4-12).
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* arch/arm/src/kl and arch/arm/include/kl: Add support for the
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Kinetis L family of Cortex-M0+ MCUs. Contributed by Alan
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Carvalho de Assis. NOTE: This is still very much a work in
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progress as of this initial commit (2013-04-16).
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* configs/freedom-kl25z: Support for the Freedom KL25Z board
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contributed by Alan Carvalho de Assis. NOTE: This is still
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very much a work inprogress as of this initial commit
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(2013-04-16).
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@@ -51,6 +51,13 @@ config ARCH_CHIP_KINETIS
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---help---
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Freescale Kinetis Architectures (ARM Cortex-M4)
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config ARCH_CHIP_KL
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bool "Freescale Kinetis L"
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select ARCH_CORTEXM0
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select ARCH_HAVE_CMNVECTOR
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---help---
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Freescale Kinetis L Architectures (ARM Cortex-M0+)
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config ARCH_CHIP_LM
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bool "TI Stellaris"
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select ARCH_HAVE_MPU
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@@ -0,0 +1,120 @@
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/************************************************************************************
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* arch/arm/include/kinetis/chip.h
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*
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* Copyright (C) 2013, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
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||||
************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_KL_CHIP_H
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#define __ARCH_ARM_INCLUDE_KL_CHIP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Get customizations for each supported chip */
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#if defined(CONFIG_ARCH_CHIP_MKL25Z128)
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# define KL_Z128 1 /* Kinetics KL25Z128 family */
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# define KL_FLASH_SIZE (128*1024) /* 64Kb */
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# define KL_SRAM_SIZE (16*1024) /* 16Kb */
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# undef KL_MPU /* No memory protection unit */
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# undef KL_EXTBUS /* No external bus interface */
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# define KL_NDMACH 4 /* Up to 4 DMA channels */
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# undef KL_NENET /* No Ethernet controller */
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# define KL_NUSBHOST 1 /* One USB host controller */
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# define KL_NUSBOTG 1 /* With USB OTG controller */
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# define KL_NUSBDEV 1 /* One USB device controller */
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# undef KL_NSDHC /* No SD host controller */
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# define KL_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
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# define KL_NI2C 2 /* Two I2C modules */
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# undef KL_NISO7816 /* No UART with ISO-786 */
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# define KL_NUART 3 /* Three UARTs */
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# define KL_NSPI 2 /* Two SPI modules */
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# undef KL_NCAN /* No CAN in 64-pin chips */
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# define KL_NI2S 1 /* One I2S module */
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# undef KL_NSLCD /* One segment LCD interface (up to 25x8/29x4) */
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# define KL_NADC16 1 /* One 16-bit ADC */
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# undef KL_NADC12 /* No 12-channel ADC */
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# undef KL_NADC13 /* No 13-channel ADC */
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# undef KL_NADC15 /* No 15-channel ADC */
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# undef KL_NADC18 /* No 18-channel ADC */
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# undef KL_NPGA /* No Programmable Gain Amplifiers */
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# define KL_NCMP 1 /* One analog comparator */
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# define KL_NDAC6 1 /* Three 6-bit DAC */
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# define KL_NDAC12 1 /* Two 12-bit DAC */
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# define KL_NVREF 1 /* Voltage reference */
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# define KL_NTIMERS8 1 /* One 8 channel timers */
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# undef KL_NTIMERS12 /* No 12 channel timers */
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# undef KL_NTIMERS20 /* No 20 channel timers */
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# undef KL_NRNG /* No random number generator */
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# define KL_NRTC 1 /* Real time clock */
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# undef KL_NMMCAU /* No hardware encryption */
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# undef KL_NTAMPER /* No tamper detect */
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# undef KL_NCRC /* No CRC */
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#else
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# error "Unsupported Kinetis chip"
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#endif
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/* NVIC priority levels *************************************************************/
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/* Each priority field holds a priority value, 0-15. The lower the value, the greater
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* the priority of the corresponding interrupt. The processor implements only
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* bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Steps between supported priority values */
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#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
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#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_KL_CHIP_H */
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@@ -0,0 +1,166 @@
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/************************************************************************************
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* arch/arm/include/kinetis/irq.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
|
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
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/* This file should never be included directed but, rather, only indirectly through
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* nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_KL_IRQ_H
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#define __ARCH_ARM_INCLUDE_KL_IRQ_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* IRQ numbers **********************************************************************/
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/* The IRQ numbers corresponds directly to vector numbers and hence map directly to
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* bits in the NVIC. This does, however, waste several words of memory in the IRQ
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* to handle mapping tables.
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*/
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/* Processor Exceptions (vectors 0-15) */
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#define KL_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define KL_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define KL_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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/* Vectors 4-10: Reserved */
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#define KL_IRQ_SVCALL (11) /* Vector 11: SVC call */
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/* Vector 12-13: Reserved */
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#define KL_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define KL_IRQ_SYSTICK (15) /* Vector 15: System tick */
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/* External interrupts (vectors >= 16) */
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#define KL_IRQ_EXTINT (16)
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/* K40 Family ***********************************************************************
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*
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* The interrupt vectors for the following parts is defined in Freescale document
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* K40P144M100SF2RM
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*/
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#if defined(CONFIG_ARCH_CHIP_MKL25Z128)
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# define KL_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */
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# define KL_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */
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# define KL_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */
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# define KL_IRQ_DMACH3 (19) /* Vector 19: DMA channel 3 transfer complete */
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/* Vector 20: Reserved */
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# define KL_IRQ_FTFA (21) /* Vector 21: FTFA */
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# define KL_IRQ_LVDLVW (22) /* Vector 22: LVD_LVW */
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# define KL_IRQ_LLW (23) /* Vector 23: LLW */
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# define KL_IRQ_I2C0 (24) /* Vector 24: I2C0 */
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# define KL_IRQ_I2C1 (25) /* Vector 25: I2C1 */
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# define KL_IRQ_SPI0 (26) /* Vector 26: SPI0 */
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# define KL_IRQ_SPI1 (27) /* Vector 27: SPI1 */
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# define KL_IRQ_UART0 (28) /* Vector 28: UART0 */
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# define KL_IRQ_UART1 (29) /* Vector 29: UART1 */
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# define KL_IRQ_UART2 (30) /* Vector 30: UART2 */
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# define KL_IRQ_ADC0 (31) /* Vector 31: Analog Device Converter 0 */
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# define KL_IRQ_CMP0 (32) /* Vector 32: Comparator 0 */
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# define KL_IRQ_TPM0 (33) /* Vector 33: Timer/PWM Module 0 */
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# define KL_IRQ_TPM1 (34) /* Vector 34: Timer/PWM Module 1 */
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# define KL_IRQ_TPM2 (35) /* Vector 35: Timer/PWM Module 2 */
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# define KL_IRQ_RTC (36) /* Vector 36: Realtime Clock */
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# define KL_IRQ_RTCSEC (37) /* Vector 37: Realtime Clock, seconds interrupt */
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# define KL_IRQ_PIT (38) /* Vector 38: Programmable Interrupt Timer */
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/* Vector 39: Reserved */
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# define KL_IRQ_USB0 (40) /* Vector 40: USB0 */
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# define KL_IRQ_DAC0 (41) /* Vector 41: Digital Analog Converter 0 */
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# define KL_IRQ_TSI0 (42) /* Vector 42: TSI0 */
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# define KL_IRQ_MCG (43) /* Vector 43: MCG */
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# define KL_IRQ_LPTIMER (44) /* Vector 44: Low Power Timer */
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/* Vector 45: Reserved */
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# define KL_IRQ_PORTA (46) /* Vector 46: GPIO Port A */
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# define KL_IRQ_PORTD (47) /* Vector 47: GPIO Port D */
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/* Note that the total number of IRQ numbers supported is equal to the number of
|
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* valid interrupt vectors. This is wasteful in that certain tables are sized by
|
||||
* this value. There are only 94 valid interrupts so, potentially the numver of
|
||||
* IRQs to could be reduced to 94. However, equating IRQ numbers with vector numbers
|
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* also simplifies operations on NVIC registers and (at least in my state of mind
|
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* now) seems to justify the waste.
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*/
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# define NR_VECTORS (64) /* 64 vectors */
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# define NR_IRQS (64) /* 64 interrupts but 48 IRQ numbers */
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# define KL_IRQ_INTERRUPT (64)
|
||||
|
||||
#else
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||||
/* The interrupt vectors for other parts are defined in other documents and may or
|
||||
* may not be the same as above (the family members are all very similar) This
|
||||
* error just means that you have to look at the document and determine for yourself
|
||||
* if the memory map is the same.
|
||||
*/
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# error "No IRQ numbers for this Kinetis L part"
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#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_KL_IRQ_H */
|
||||
|
||||
@@ -0,0 +1,432 @@
|
||||
#
|
||||
# For a description of the syntax of this configuration file,
|
||||
# see misc/tools/kconfig-language.txt.
|
||||
#
|
||||
|
||||
comment "Kinetis Configuration Options"
|
||||
|
||||
choice
|
||||
prompt "Kinetis Chip Selection"
|
||||
default ARCH_CHIP_MKL25Z128
|
||||
depends on ARCH_CHIP_KL
|
||||
|
||||
config ARCH_CHIP_MKL25Z128
|
||||
bool "MKL25Z128"
|
||||
select ARCH_FAMILY_KL2X
|
||||
|
||||
endchoice
|
||||
|
||||
# Chip families
|
||||
|
||||
config ARCH_FAMILY_KL2X
|
||||
bool
|
||||
default n
|
||||
|
||||
menu "Kinetis Peripheral Support"
|
||||
|
||||
config KL_TRACE
|
||||
bool "Trace"
|
||||
default n
|
||||
---help---
|
||||
Enable trace clocking on power up.
|
||||
|
||||
config KL_FLEXBUS
|
||||
bool "FlexBus"
|
||||
default n
|
||||
---help---
|
||||
Enable flexbus clocking on power up.
|
||||
|
||||
config KL_UART0
|
||||
bool "UART0"
|
||||
default n
|
||||
select ARCH_HAVE_UART0
|
||||
---help---
|
||||
Support UART0
|
||||
|
||||
config KL_UART1
|
||||
bool "UART1"
|
||||
default n
|
||||
select ARCH_HAVE_UART1
|
||||
---help---
|
||||
Support UART1
|
||||
|
||||
config KL_UART2
|
||||
bool "UART2"
|
||||
default n
|
||||
select ARCH_HAVE_UART2
|
||||
---help---
|
||||
Support UART2
|
||||
|
||||
config KL_UART3
|
||||
bool "UART3"
|
||||
default n
|
||||
select ARCH_HAVE_UART3
|
||||
---help---
|
||||
Support UART3
|
||||
|
||||
config KL_UART4
|
||||
bool "UART4"
|
||||
default n
|
||||
select ARCH_HAVE_UART4
|
||||
---help---
|
||||
Support UART4
|
||||
|
||||
config KL_UART5
|
||||
bool "UART5"
|
||||
default n
|
||||
select ARCH_HAVE_UART5
|
||||
---help---
|
||||
Support UART5
|
||||
|
||||
config KL_ENET
|
||||
bool "Ethernet"
|
||||
default n
|
||||
depends on ARCH_FAMILY_K60
|
||||
select NET
|
||||
---help---
|
||||
Support Ethernet (K60 only)
|
||||
|
||||
config KL_RNGB
|
||||
bool "Random number generator"
|
||||
default n
|
||||
depends on ARCH_FAMILY_K60
|
||||
---help---
|
||||
Support the random number generator(K60 only)
|
||||
|
||||
config KL_FLEXCAN0
|
||||
bool "FlexCAN0"
|
||||
default n
|
||||
---help---
|
||||
Support FlexCAN0
|
||||
|
||||
config KL_FLEXCAN1
|
||||
bool "FlexCAN1"
|
||||
default n
|
||||
---help---
|
||||
Support FlexCAN1
|
||||
|
||||
config KL_SPI0
|
||||
bool "SPI0"
|
||||
default n
|
||||
---help---
|
||||
Support SPI0
|
||||
|
||||
config KL_SPI1
|
||||
bool "SPI1"
|
||||
default n
|
||||
---help---
|
||||
Support SPI1
|
||||
|
||||
config KL_SPI2
|
||||
bool "SPI2"
|
||||
default n
|
||||
---help---
|
||||
Support SPI2
|
||||
|
||||
config KL_I2C0
|
||||
bool "I2C0"
|
||||
default n
|
||||
---help---
|
||||
Support I2C0
|
||||
|
||||
config KL_I2C1
|
||||
bool "I2C1"
|
||||
default n
|
||||
---help---
|
||||
Support I2C1
|
||||
|
||||
config KL_I2S
|
||||
bool "I2S"
|
||||
default n
|
||||
---help---
|
||||
Support I2S
|
||||
|
||||
config KL_DAC0
|
||||
bool "DAC0"
|
||||
default n
|
||||
---help---
|
||||
Support DAC0
|
||||
|
||||
config KL_DAC1
|
||||
bool "DAC1"
|
||||
default n
|
||||
---help---
|
||||
Support DAC1
|
||||
|
||||
config KL_ADC0
|
||||
bool "ADC0"
|
||||
default n
|
||||
---help---
|
||||
Support ADC0
|
||||
|
||||
config KL_ADC1
|
||||
bool "ADC1"
|
||||
default n
|
||||
---help---
|
||||
Support ADC1
|
||||
|
||||
config KL_CMP
|
||||
bool "CMP"
|
||||
default n
|
||||
---help---
|
||||
Support CMP
|
||||
|
||||
config KL_VREF
|
||||
bool "VREF"
|
||||
default n
|
||||
---help---
|
||||
Support VREF
|
||||
|
||||
config KL_SDHC
|
||||
bool "SDHC"
|
||||
default n
|
||||
select MMCSD_SDIO
|
||||
---help---
|
||||
Support SD host controller
|
||||
|
||||
config KL_FTM0
|
||||
bool "FTM0"
|
||||
default n
|
||||
---help---
|
||||
Support FlexTimer 0
|
||||
|
||||
config KL_FTM1
|
||||
bool "FTM1"
|
||||
default n
|
||||
---help---
|
||||
Support FlexTimer 1
|
||||
|
||||
config KL_FTM2
|
||||
bool "FTM2"
|
||||
default n
|
||||
---help---
|
||||
Support FlexTimer 2
|
||||
|
||||
config KL_LPTIMER
|
||||
bool "Low power timer (LPTIMER)"
|
||||
default n
|
||||
---help---
|
||||
Support the low power timer
|
||||
|
||||
config KL_RTC
|
||||
bool "RTC"
|
||||
default n
|
||||
---help---
|
||||
Support RTC
|
||||
|
||||
config KL_SLCD
|
||||
bool "Segment LCD (SLCD)"
|
||||
default n
|
||||
depends on ARCH_FAMILY_K40
|
||||
---help---
|
||||
Support the segment LCD (K40 only)
|
||||
|
||||
config KL_EWM
|
||||
bool "External watchdog (WVM)"
|
||||
default n
|
||||
---help---
|
||||
Support the external watchdog
|
||||
|
||||
config KL_CMT
|
||||
bool "Carrier modulator transmitter (CMT)"
|
||||
default n
|
||||
---help---
|
||||
Support Carrier Modulator Transmitter
|
||||
|
||||
config KL_USBOTG
|
||||
bool "USB OTG"
|
||||
default n
|
||||
---help---
|
||||
Support USB OTG (see also USBHOST and USBDEV)
|
||||
|
||||
config KL_USBDCD
|
||||
bool "USB device controller"
|
||||
default n
|
||||
---help---
|
||||
Support the USB Device Charger Detection module
|
||||
|
||||
config KL_LLWU
|
||||
bool "Low leakage wake-up unit (LLWU)"
|
||||
default n
|
||||
---help---
|
||||
Support the Low Leakage Wake-Up Unit
|
||||
|
||||
config KL_TSI
|
||||
bool "Touchscreen interface (TSI)"
|
||||
default n
|
||||
---help---
|
||||
Support the touch screeen interface
|
||||
|
||||
config KL_FTFL
|
||||
bool "FLASH (FTFL)"
|
||||
default n
|
||||
---help---
|
||||
Support FLASH
|
||||
|
||||
config KL_DMA
|
||||
bool "DMA"
|
||||
default n
|
||||
---help---
|
||||
Support DMA
|
||||
|
||||
config KL_CRC
|
||||
bool "CRC"
|
||||
default n
|
||||
---help---
|
||||
Support CRC
|
||||
|
||||
config KL_PDB
|
||||
bool "Programmable delay block (PDB)"
|
||||
default n
|
||||
---help---
|
||||
Support the Programmable Delay Block
|
||||
|
||||
config KL_PIT
|
||||
bool "Programmable interval timer (PIT)"
|
||||
default n
|
||||
---help---
|
||||
Support Programmable Interval Timers
|
||||
|
||||
endmenu
|
||||
|
||||
comment "Kinetis GPIO Interrupt Configuration"
|
||||
|
||||
config GPIO_IRQ
|
||||
bool "GPIO pin interrupts"
|
||||
---help---
|
||||
Enable support for interrupting GPIO pins
|
||||
|
||||
if GPIO_IRQ
|
||||
|
||||
config KL_PORTAINTS
|
||||
bool "GPIOA interrupts"
|
||||
---help---
|
||||
Enable support for 32 interrupts from GPIO port A pins
|
||||
|
||||
config KL_PORTBINTS
|
||||
bool "GPIOB interrupts"
|
||||
---help---
|
||||
Enable support for 32 interrupts from GPIO port B pins
|
||||
|
||||
config KL_PORTCINTS
|
||||
bool "GPIOC interrupts"
|
||||
---help---
|
||||
Enable support for 32 interrupts from GPIO port C pins
|
||||
|
||||
config KL_PORTDINTS
|
||||
bool "GPIOD interrupts"
|
||||
---help---
|
||||
Enable support for 32 interrupts from GPIO port D pins
|
||||
|
||||
config KL_PORTEINTS
|
||||
bool "GPIOE interrupts"
|
||||
---help---
|
||||
Enable support for 32 interrupts from GPIO port E pins
|
||||
|
||||
endif
|
||||
|
||||
if KL_ENET
|
||||
|
||||
comment "Kinetis Ethernet Configuration"
|
||||
|
||||
config ENET_ENHANCEDBD
|
||||
bool "Use enhanced buffer descriptors"
|
||||
default n
|
||||
---help---
|
||||
Use enhanced, 32-byte buffer descriptors
|
||||
|
||||
config ENET_NETHIFS
|
||||
int "Number of Ethernet interfaces"
|
||||
default 1
|
||||
---help---
|
||||
Number of Ethernet interfaces supported by the hardware. Must be
|
||||
one for now.
|
||||
|
||||
config ENET_NRXBUFFERS
|
||||
int "Number of Ethernet Rx buffers"
|
||||
default 6
|
||||
---help---
|
||||
Number of Ethernet Rx buffers to use. The size of one buffer is
|
||||
determined by CONFIG_NET_BUFSIZE
|
||||
|
||||
config ENET_NTXBUFFERS
|
||||
int "Number of Ethernet Tx buffers"
|
||||
default 2
|
||||
---help---
|
||||
Number of Ethernet Tx buffers to use. The size of one buffer is
|
||||
determined by CONFIG_NET_BUFSIZE
|
||||
|
||||
config ENET_PHYADDR
|
||||
int "PHY address"
|
||||
default 1
|
||||
---help---
|
||||
MII/RMII address of the PHY
|
||||
|
||||
config ENET_USEMII
|
||||
bool "Use MII interface"
|
||||
default n
|
||||
---help---
|
||||
The the MII PHY interface. Default: Use RMII interface
|
||||
|
||||
endif
|
||||
|
||||
if KL_SDHC
|
||||
|
||||
comment "Kinetis SDHC Configuration"
|
||||
|
||||
config KL_SDHC_ABSFREQ
|
||||
bool "Custom transfer frequencies"
|
||||
default n
|
||||
---help---
|
||||
Select SDCLK frequencies corresponding to various modes of operation.
|
||||
These values may be provided in either the NuttX configuration file
|
||||
or in the board.h file
|
||||
|
||||
NOTE: These settings are not currently used. Since there are only
|
||||
four frequencies, it makes more sense to just "can" the fixed
|
||||
frequency prescaler and divider values.
|
||||
|
||||
if KL_SDHC_ABSFREQ
|
||||
|
||||
config KL_IDMODE_FREQ
|
||||
int "ID mode frequency"
|
||||
default 400000
|
||||
---help---
|
||||
Initial, ID mode SD frequency
|
||||
|
||||
config KL_MMCXFR_FREQ
|
||||
int "MMC transfer frequency"
|
||||
default 20000000
|
||||
---help---
|
||||
Frequency to use for transferring data to/from an MMC card
|
||||
|
||||
config KL_SD1BIT_FREQ
|
||||
int "SD 1-bit transfer frequency"
|
||||
default 20000000
|
||||
depends on CONFIG_SDIO_WIDTH_D1_ONLY
|
||||
---help---
|
||||
Frequency to use for transferring data to/from an SD card using on a single data liune.
|
||||
|
||||
config KL_SD4BIT_FREQ
|
||||
int "SD 4-bit transfer frequency"
|
||||
default 20000000
|
||||
depends on !CONFIG_SDIO_WIDTH_D1_ONLY
|
||||
---help---
|
||||
Frequency to use for transferring data to/from an SD card using all four data lines.
|
||||
|
||||
endif
|
||||
|
||||
config KL_SDHC_DMAPRIO
|
||||
int "SDHC DMA priority"
|
||||
depends on SDIO_DMA
|
||||
---help---
|
||||
SDHC DMA priority
|
||||
|
||||
endif
|
||||
|
||||
comment "Kinetis UART Configuration"
|
||||
|
||||
config KL_UARTFIFOS
|
||||
bool "Enable UART0 FIFO"
|
||||
default n
|
||||
depends on KL_UART0
|
||||
@@ -0,0 +1,80 @@
|
||||
############################################################################
|
||||
# arch/arm/src/kl/Make.defs
|
||||
#
|
||||
# Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
HEAD_ASRC =
|
||||
|
||||
CMN_ASRCS = up_exception.S up_saveusercontext.S up_fullcontextrestore.S
|
||||
CMN_ASRCS += up_switchcontext.S vfork.S
|
||||
|
||||
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c
|
||||
CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c
|
||||
CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c
|
||||
CMN_CSRCS += up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
|
||||
CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c
|
||||
CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_systemreset.c
|
||||
CMN_CSRCS += up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c
|
||||
CMN_CSRCS += up_svcall.c up_vectors.c up_vfork.c
|
||||
|
||||
ifeq ($(CONFIG_NUTTX_KERNEL),y)
|
||||
CMN_CSRCS += up_task_start.c up_pthread_start.c up_stackframe.c
|
||||
ifneq ($(CONFIG_DISABLE_SIGNALS),y)
|
||||
CMN_CSRCS += up_signal_dispatch.c
|
||||
CMN_UASRCS += up_signal_handler.S
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_DEBUG_STACK),y)
|
||||
CMN_CSRCS += up_checkstack.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ELF),y)
|
||||
CMN_CSRCS += up_elf.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_DEBUG),y)
|
||||
CMN_CSRCS += up_dumpnvic.c
|
||||
endif
|
||||
|
||||
CHIP_ASRCS =
|
||||
CHIP_CSRCS = kl_clockconfig.c kl_gpio.c kl_idle.c kl_irq.c kl_lowputc.c
|
||||
CHIP_CSRCS += kl_serial.c kl_start.c kl_timerisr.c kl_cfmconfig.c kl_led.c
|
||||
|
||||
ifeq ($(CONFIG_NUTTX_KERNEL),y)
|
||||
CHIP_CSRCS += kl_userspace.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_DEBUG),y)
|
||||
CHIP_CSRCS += kl_dumpgpio.c
|
||||
endif
|
||||
@@ -0,0 +1,75 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/kl/chip.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KL_CHIP_H
|
||||
#define __ARCH_ARM_SRC_KL_CHIP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/* Include the chip capabilities file */
|
||||
|
||||
#include <arch/kl/chip.h>
|
||||
|
||||
/* Define the number of interrupt vectors that needed to be support for this chip */
|
||||
|
||||
#define ARMV6M_PERIPHERAL_INTERRUPTS 32
|
||||
|
||||
/* Include the memory map file. Other chip hardware files should then include
|
||||
* this file for the proper setup.
|
||||
*/
|
||||
|
||||
#include "chip/kl_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KL_CHIP_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,288 @@
|
||||
/********************************************************************************************
|
||||
* arch/arm/src/nuc1xx/chip/nuc_clk.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KL_CHIP_KL_CLK_H
|
||||
#define __ARCH_ARM_SRC_KL_CHIP_KL_CLK_H
|
||||
|
||||
/********************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
********************************************************************************************/
|
||||
/* Well-known clock frequencies *************************************************************/
|
||||
|
||||
#define KL_INTHI_FREQUENCY 22118400
|
||||
#define KL_INTLO_FREQUENCY 10000
|
||||
|
||||
/* Register offsets *************************************************************************/
|
||||
|
||||
#define KL_CLK_PWRCON_OFFSET 0x0000 /* System power down control register */
|
||||
#define KL_CLK_AHBCLK_OFFSET 0x0004 /* AHB devices clock enable control register */
|
||||
#define KL_CLK_APBCLK_OFFSET 0x0008 /* APB devices clock enable control register */
|
||||
#define KL_CLK_CLKSTATUS_OFFSET 0x000c /* Clock status monitor register */
|
||||
#define KL_CLK_CLKSEL0_OFFSET 0x0010 /* Clock source select control register 0 */
|
||||
#define KL_CLK_CLKSEL1_OFFSET 0x0014 /* Clock source select control register 1 */
|
||||
#define KL_CLK_CLKSEL2_OFFSET 0x001c /* Clock source select control register 2 */
|
||||
#define KL_CLK_CLKDIV_OFFSET 0x0018 /* Clock divider number register */
|
||||
#define KL_CLK_PLLCON_OFFSET 0x0020 /* PLL control register */
|
||||
#define KL_CLK_FRQDIV_OFFSET 0x0024 /* Frequency divider control register */
|
||||
|
||||
/* Register addresses ***********************************************************************/
|
||||
|
||||
#define KL_CLK_PWRCON (KL_CLK_BASE+KL_CLK_PWRCON_OFFSET)
|
||||
#define KL_CLK_AHBCLK (KL_CLK_BASE+KL_CLK_AHBCLK_OFFSET)
|
||||
#define KL_CLK_APBCLK (KL_CLK_BASE+KL_CLK_APBCLK_OFFSET)
|
||||
#define KL_CLK_CLKSTATUS (KL_CLK_BASE+KL_CLK_CLKSTATUS_OFFSET)
|
||||
#define KL_CLK_CLKSEL0 (KL_CLK_BASE+KL_CLK_CLKSEL0_OFFSET)
|
||||
#define KL_CLK_CLKSEL1 (KL_CLK_BASE+KL_CLK_CLKSEL1_OFFSET)
|
||||
#define KL_CLK_CLKSEL2 (KL_CLK_BASE+KL_CLK_CLKSEL2_OFFSET)
|
||||
#define KL_CLK_CLKDIV (KL_CLK_BASE+KL_CLK_CLKDIV_OFFSET)
|
||||
#define KL_CLK_PLLCON (KL_CLK_BASE+KL_CLK_PLLCON_OFFSET)
|
||||
#define KL_CLK_FRQDIV (KL_CLK_BASE+KL_CLK_FRQDIV_OFFSET)
|
||||
|
||||
/* Register bit-field definitions ***********************************************************/
|
||||
|
||||
/* System power down control register */
|
||||
|
||||
#define CLK_PWRCON_XTL12M_EN (1 << 0) /* Bit 0: External 4~24 mhz high speed crystal enable */
|
||||
#define CLK_PWRCON_XTL32K_EN (1 << 1) /* Bit 1: External 32.768 khz low speed crystal enable */
|
||||
#define CLK_PWRCON_OSC22M_EN (1 << 2) /* Bit 2: Internal 22.1184 MHz high speed oscillator enable */
|
||||
#define CLK_PWRCON_OSC10K_EN (1 << 3) /* Bit 3: Internal 10KHz low speed oscillator enable */
|
||||
#define CLK_PWRCON_PD_WU_DLY (1 << 4) /* Bit 4: Enable the wake-up delay counter */
|
||||
#define CLK_PWRCON_PD_WU_INT_EN (1 << 5) /* Bit 5: Power down mode wake-up interrupt status */
|
||||
#define CLK_PWRCON_PD_WU_STS (1 << 6) /* Bit 6: Power down mode wake-up interupt status */
|
||||
#define CLK_PWRCON_PWR_DOWN_EN (1 << 7) /* Bit 7: System power down enable bit */
|
||||
#define CLK_PWRCON_PD_WAIT_CPU (1 << 8) /* Bit 8: Power down entry condition */
|
||||
|
||||
/* AHB devices clock enable control register */
|
||||
|
||||
#define CLK_AHBCLK_PDMA_EN (1 << 1) /* Bit 1: PDMA acontroller clock enable control */
|
||||
#define CLK_AHBCLK_ISP_EN (1 << 2) /* Bit 2: FLASH ISPO controller clock enable control */
|
||||
#define CLK_AHBCLK_EBI_EN (1 << 3) /* Bit 3: EBI controller clock enable control */
|
||||
|
||||
/* APB devices clock enable control register */
|
||||
|
||||
#define CLK_APBCLK_WDT_EN (1 << 0) /* Bit 0: Watchdog time clock enable */
|
||||
#define CLK_APBCLK_RTC_EN (1 << 1) /* Bit 1: Real time clock clock enable */
|
||||
#define CLK_APBCLK_TMR0_EN (1 << 2) /* Bit 2: Timer0 clock enable */
|
||||
#define CLK_APBCLK_TMR1_EN (1 << 3) /* Bit 3: Timer1 clock enable */
|
||||
#define CLK_APBCLK_TMR2_EN (1 << 4) /* Bit 4: Timer2 clock enable */
|
||||
#define CLK_APBCLK_TMR3_EN (1 << 5) /* Bit 5: Timer3 clock enable */
|
||||
#define CLK_APBCLK_FDIV_EN (1 << 6) /* Bit 6: Frequency divider output clock enable */
|
||||
#define CLK_APBCLK_I2C0_EN (1 << 8) /* Bit 8: I2C0 clock enable */
|
||||
#define CLK_APBCLK_I2C1_EN (1 << 9) /* Bit 9: I2C1 clock enable */
|
||||
#define CLK_APBCLK_SPI0_EN (1 << 12) /* Bit 12: SPI0 clock enable */
|
||||
#define CLK_APBCLK_SPI1_EN (1 << 13) /* Bit 13: SPI1 clock enable */
|
||||
#define CLK_APBCLK_SPI2_EN (1 << 14) /* Bit 14: SPI2 clock enable */
|
||||
#define CLK_APBCLK_SPI3_EN (1 << 15) /* Bit 15: SPI3 clock enable */
|
||||
#define CLK_APBCLK_UART0_EN (1 << 16) /* Bit 16: UART0 clock enable */
|
||||
#define CLK_APBCLK_UART1_EN (1 << 17) /* Bit 17: UART1 clock enable */
|
||||
#define CLK_APBCLK_UART2_EN (1 << 18) /* Bit 18: UART2 clock enable */
|
||||
#define CLK_APBCLK_PWM01_EN (1 << 20) /* Bit 20: PWM_01 clock enable */
|
||||
#define CLK_APBCLK_PWM23_EN (1 << 21) /* Bit 21: PWM_23 clock enable */
|
||||
#define CLK_APBCLK_PWM45_EN (1 << 22) /* Bit 22: PWM_45 clock enable */
|
||||
#define CLK_APBCLK_PWM67_EN (1 << 23) /* Bit 23: PWM_67 clock enable */
|
||||
#define CLK_APBCLK_USBD_EN (1 << 27) /* Bit 27: USB 2.0 FS device controller clock enable */
|
||||
#define CLK_APBCLK_ADC_EN (1 << 28) /* Bit 28: Analog-digital-converter clock enable */
|
||||
#define CLK_APBCLK_I2S_EN (1 << 29) /* Bit 29: I2S clock enable */
|
||||
#define CLK_APBCLK_ACMP_EN (1 << 30) /* Bit 30: Analog comparator clock enable */
|
||||
#define CLK_APBCLK_PS2_EN (1 << 31) /* Bit 31: PS/2 clock enable */
|
||||
|
||||
/* Clock status monitor register */
|
||||
|
||||
#define CLK_CLKSTATUS_XTL12M_STB (1 << 0) /* Bit 0: External 4~24 mhz high speed crystal
|
||||
* clock source stable flag */
|
||||
#define CLK_CLKSTATUS_STL32K_STB (1 << 1) /* Bit 1: External 32.768 kHz low speed crystal
|
||||
* clock source stable flag */
|
||||
#define CLK_CLKSTATUS_PLL_STB (1 << 2) /* Bit 2: Internal PLL clock source stable flag */
|
||||
#define CLK_CLKSTATUS_OSC10K_STB (1 << 3) /* Bit 3: Internal 10kHz low speed clock source
|
||||
* stable flag */
|
||||
#define CLK_CLKSTATUS_OSC22M_STB (1 << 4) /* Bit 4: Internal 22.1184MHz high speed
|
||||
* osciallator clock source stable flag */
|
||||
#define CLK_CLKSTATUS_CLK_SW_FAIL (1 << 7) /* Bit 7: Clock switching fail flag */
|
||||
|
||||
/* Clock source select control register 0 */
|
||||
|
||||
#define CLK_CLKSEL0_HCLK_S_SHIFT (0) /* Bits 0-2: HCLK clock source select */
|
||||
#define CLK_CLKSEL0_HCLK_S_MASK (7 << CLK_CLKSEL0_HCLK_S_SHIFT)
|
||||
# define CLK_CLKSEL0_HCLK_S_XTALHI (0 << CLK_CLKSEL0_HCLK_S_SHIFT) /* High speed XTAL clock */
|
||||
# define CLK_CLKSEL0_HCLK_S_XTALLO (1 << CLK_CLKSEL0_HCLK_S_SHIFT) /* Low speed XTAL clock */
|
||||
# define CLK_CLKSEL0_HCLK_S_PLL (2 << CLK_CLKSEL0_HCLK_S_SHIFT) /* PLL clock */
|
||||
# define CLK_CLKSEL0_HCLK_S_INTLO (3 << CLK_CLKSEL0_HCLK_S_SHIFT) /* Internal low speed clock */
|
||||
# define CLK_CLKSEL0_HCLK_S_INTHI (7 << CLK_CLKSEL0_HCLK_S_SHIFT) /* Internal high speed clock */
|
||||
#define CLK_CLKSEL0_STCLK_S_SHIFT (3) /* Bits 3-5: Cortex M0 Systick clock source select */
|
||||
#define CLK_CLKSEL0_STCLK_S_MASK (7 << CLK_CLKSEL0_STCLK_S_SHIFT)
|
||||
# define CLK_CLKSEL0_STCLK_S_XTALHI (0 << CLK_CLKSEL0_STCLK_S_SHIFT) /* High speed XTAL clock */
|
||||
# define CLK_CLKSEL0_STCLK_S_XTALLO (1 << CLK_CLKSEL0_STCLK_S_SHIFT) /* Low speed XTAL clock */
|
||||
# define CLK_CLKSEL0_STCLK_S_XTALDIV2 (2 << CLK_CLKSEL0_STCLK_S_SHIFT) /* High speed XTAL clock/2 */
|
||||
# define CLK_CLKSEL0_STCLK_S_HCLKDIV2 (3 << CLK_CLKSEL0_STCLK_S_SHIFT) /* HCLK/2 */
|
||||
# define CLK_CLKSEL0_STCLK_S_INTDIV2 (7 << CLK_CLKSEL0_STCLK_S_SHIFT) /* Internal high speed clock/2 */
|
||||
|
||||
/* Clock source select control register 1 */
|
||||
|
||||
#define CLK_CLKSEL1_WDT_S_SHIFT (0) /* Bits 0-1: Watchdog timer clock source select */
|
||||
#define CLK_CLKSEL1_WDT_S_MASK (3 << CLK_CLKSEL1_WDT_S_SHIFT)
|
||||
# define CLK_CLKSEL1_ADC_S_HCLKDIV (2 << CLK_CLKSEL1_WDT_S_SHIFT) /* HCLK / 2048 */
|
||||
# define CLK_CLKSEL1_ADC_S_INTLO (3 << CLK_CLKSEL1_WDT_S_SHIFT) /* Internal low speed clock */
|
||||
#define CLK_CLKSEL1_ADC_S_SHIFT (2) /* Bits 2-3: ADC clock source select */
|
||||
#define CLK_CLKSEL1_ADC_S_MASK (3 << CLK_CLKSEL1_ADC_S_SHIFT)
|
||||
# define CLK_CLKSEL1_ADC_S_XTALHI (0 << CLK_CLKSEL1_ADC_S_SHIFT) /* High speed XTAL clock */
|
||||
# define CLK_CLKSEL1_ADC_S_PLL (1 << CLK_CLKSEL1_ADC_S_SHIFT) /* PLL */
|
||||
# define CLK_CLKSEL1_ADC_S_INTHI (3 << CLK_CLKSEL1_ADC_S_SHIFT) /* Internal high speed clock */
|
||||
#define CLK_CLKSEL1_TMR0_S_SHIFT (8) /* Bits 8-10: Timer0 clock source select */
|
||||
#define CLK_CLKSEL1_TMR0_S_MASK (7 << CLK_CLKSEL1_TMR0_S_SHIFT)
|
||||
# define CLK_CLKSEL1_TMR0_S_XTALHI (0 << CLK_CLKSEL1_TMR0_S_SHIFT) /* High speed XTAL clock */
|
||||
# define CLK_CLKSEL1_TMR0_S_XTALLO (1 << CLK_CLKSEL1_TMR0_S_SHIFT) /* Low speed XTAL clock */
|
||||
# define CLK_CLKSEL1_TMR0_S_HCLK (2 << CLK_CLKSEL1_TMR0_S_SHIFT) /* HCLK */
|
||||
# define CLK_CLKSEL1_TMR0_S_INTHI (7 << CLK_CLKSEL1_TMR0_S_SHIFT) /* Internal high speed clock */
|
||||
#define CLK_CLKSEL1_TMR1_S_SHIFT (12) /* Bits 12-14: Timer1 clock source select */
|
||||
#define CLK_CLKSEL1_TMR1_S_MASK (7 << CLK_CLKSEL1_TMR1_S_SHIFT)
|
||||
# define CLK_CLKSEL1_TMR1_S_XTALHI (0 << CLK_CLKSEL1_TMR1_S_SHIFT) /* High speed XTAL clock */
|
||||
# define CLK_CLKSEL1_TMR1_S_XTALLO (1 << CLK_CLKSEL1_TMR1_S_SHIFT) /* Low speed XTAL clock */
|
||||
# define CLK_CLKSEL1_TMR1_S_HCLK (2 << CLK_CLKSEL1_TMR1_S_SHIFT) /* HCLK */
|
||||
# define CLK_CLKSEL1_TMR1_S_INTHI (7 << CLK_CLKSEL1_TMR1_S_SHIFT) /* Internal high speed clock */
|
||||
#define CLK_CLKSEL1_TMR2_S_SHIFT (16) /* Bits 16-18: Timer2 clock source select */
|
||||
#define CLK_CLKSEL1_TMR2_S_MASK (7 << CLK_CLKSEL1_TMR2_S_SHIFT)
|
||||
# define CLK_CLKSEL1_TMR2_S_XTALHI (0 << CLK_CLKSEL1_TMR2_S_SHIFT) /* High speed XTAL clock */
|
||||
# define CLK_CLKSEL1_TMR2_S_XTALLO (1 << CLK_CLKSEL1_TMR2_S_SHIFT) /* Low speed XTAL clock */
|
||||
# define CLK_CLKSEL1_TMR2_S_HCLK (2 << CLK_CLKSEL1_TMR2_S_SHIFT) /* HCLK */
|
||||
# define CLK_CLKSEL1_TMR2_S_INTHI (7 << CLK_CLKSEL1_TMR2_S_SHIFT) /* Internal high speed clock */
|
||||
#define CLK_CLKSEL1_TMR3_S_SHIFT (20) /* Bits 20-22: Timer3 clock source select */
|
||||
#define CLK_CLKSEL1_TMR3_S_MASK (7 << CLK_CLKSEL1_TMR3_S_SHIFT)
|
||||
# define CLK_CLKSEL1_TMR3_S_XTALHI (0 << CLK_CLKSEL1_TMR3_S_SHIFT) /* High speed XTAL clock */
|
||||
# define CLK_CLKSEL1_TMR3_S_XTALLO (1 << CLK_CLKSEL1_TMR3_S_SHIFT) /* Low speed XTAL clock */
|
||||
# define CLK_CLKSEL1_TMR3_S_HCLK (2 << CLK_CLKSEL1_TMR3_S_SHIFT) /* HCLK */
|
||||
# define CLK_CLKSEL1_TMR3_S_INTHI (7 << CLK_CLKSEL1_TMR3_S_SHIFT) /* Internal high speed clock */
|
||||
#define CLK_CLKSEL1_UART_S_SHIFT (24) /* Bits 24-25: UART clock source select */
|
||||
#define CLK_CLKSEL1_UART_S_MASK (3 << CLK_CLKSEL1_UART_S_SHIFT)
|
||||
# define CLK_CLKSEL1_UART_S_XTALHI (0 << CLK_CLKSEL1_UART_S_SHIFT) /* High speed XTAL clock */
|
||||
# define CLK_CLKSEL1_UART_S_PLL (1 << CLK_CLKSEL1_UART_S_SHIFT) /* PLL */
|
||||
# define CLK_CLKSEL1_UART_S_INTHI (3 << CLK_CLKSEL1_UART_S_SHIFT) /* Internal high speed clock */
|
||||
#define CLK_CLKSEL1_PWM01_S_SHIFT (28) /* Bits 28-29: PWM0 and PWM1 clock source select */
|
||||
#define CLK_CLKSEL1_PWM01_S_MASK (3 << CLK_CLKSEL1_PWM01_S_SHIFT)
|
||||
# define CLK_CLKSEL1_PWM01_S_XTALHI (0 << CLK_CLKSEL1_PWM01_S_SHIFT) /* High speed XTAL clock */
|
||||
# define CLK_CLKSEL1_PWM01_S_XTALLO (1 << CLK_CLKSEL1_PWM01_S_SHIFT) /* Low speed XTAL clock */
|
||||
# define CLK_CLKSEL1_PWM01_S_HCLK (2 << CLK_CLKSEL1_PWM01_S_SHIFT) /* HCLK */
|
||||
# define CLK_CLKSEL1_PWM01_S_INTHI (3 << CLK_CLKSEL1_PWM01_S_SHIFT) /* Internal high speed clock */
|
||||
#define CLK_CLKSEL1_PWM23_S_SHIFT (30) /* Bits 30-31: PWM2 and PWM3 clock source select */
|
||||
#define CLK_CLKSEL1_PWM23_S_MASK (3 << CLK_CLKSEL1_PWM23_S_SHIFT)
|
||||
# define CLK_CLKSEL1_PWM23_S_XTALHI (0 << CLK_CLKSEL1_PWM23_S_SHIFT) /* High speed XTAL clock */
|
||||
# define CLK_CLKSEL1_PWM23_S_XTALLO (1 << CLK_CLKSEL1_PWM23_S_SHIFT) /* Low speed XTAL clock */
|
||||
# define CLK_CLKSEL1_PWM23_S_HCLK (2 << CLK_CLKSEL1_PWM23_S_SHIFT) /* HCLK */
|
||||
# define CLK_CLKSEL1_PWM23_S_INTHI (3 << CLK_CLKSEL1_PWM23_S_SHIFT) /* Internal high speed clock */
|
||||
|
||||
/* Clock source select control register 2 */
|
||||
|
||||
#define CLK_CLKSEL2_I2S_S_SHIFT (0) /* Bits 0-1: I2S clock source select */
|
||||
#define CLK_CLKSEL2_I2S_S_MASK (3 << CLK_CLKSEL2_I2S_S_SHIFT)
|
||||
# define CLK_CLKSEL1_I2S_S_XTALHI (0 << CLK_CLKSEL2_I2S_S_SHIFT) /* High speed XTAL clock */
|
||||
# define CLK_CLKSEL1_I2S_S_XTALLO (1 << CLK_CLKSEL2_I2S_S_SHIFT) /* Low speed XTAL clock */
|
||||
# define CLK_CLKSEL1_I2S_S_HCLK (2 << CLK_CLKSEL2_I2S_S_SHIFT) /* HCLK */
|
||||
# define CLK_CLKSEL1_I2S_S_INTHI (3 << CLK_CLKSEL2_I2S_S_SHIFT) /* Internal high speed clock */
|
||||
#define CLK_CLKSEL2_FRQDIV_S_SHIFT (2) /* Bits 2-3: Frequency divider clock source select */
|
||||
#define CLK_CLKSEL2_FRQDIV_S_MASK (3 << CLK_CLKSEL2_FRQDIV_S_SHIFT)
|
||||
# define CLK_CLKSEL1_FRQDIV_S_XTALHI (0 << CLK_CLKSEL2_FRQDIV_S_SHIFT) /* High speed XTAL clock */
|
||||
# define CLK_CLKSEL1_FRQDIV_S_XTALLO (1 << CLK_CLKSEL2_FRQDIV_S_SHIFT) /* Low speed XTAL clock */
|
||||
# define CLK_CLKSEL1_FRQDIV_S_HCLK (2 << CLK_CLKSEL2_FRQDIV_S_SHIFT) /* HCLK */
|
||||
#define CLK_CLKSEL2_PWM45_S_SHIFT (4) /* Bits 4-5: PWM4 and PWM5 clock source select */
|
||||
#define CLK_CLKSEL2_PWM45_S_MASK (3 << CLK_CLKSEL2_PWM45_S_SHIFT)
|
||||
# define CLK_CLKSEL1_PWM45_S_XTALHI (0 << CLK_CLKSEL2_PWM45_S_SHIFT) /* High speed XTAL clock */
|
||||
# define CLK_CLKSEL1_PWM45_S_XTALLO (1 << CLK_CLKSEL2_PWM45_S_SHIFT) /* Low speed XTAL clock */
|
||||
# define CLK_CLKSEL1_PWM45_S_HCLK (2 << CLK_CLKSEL2_PWM45_S_SHIFT) /* HCLK */
|
||||
# define CLK_CLKSEL1_PWM45_S_INTHI (3 << CLK_CLKSEL2_PWM45_S_SHIFT) /* Internal high speed clock */
|
||||
#define CLK_CLKSEL2_PWM67_S_SHIFT (6) /* Bits 6-7: PWM6 and PWM7 clock source select */
|
||||
#define CLK_CLKSEL2_PWM67_S_MASK (3 << CLK_CLKSEL2_PWM67_S_SHIFT)
|
||||
# define CLK_CLKSEL1_PWM67_S_XTALHI (0 << CLK_CLKSEL2_PWM67_S_SHIFT) /* High speed XTAL clock */
|
||||
# define CLK_CLKSEL1_PWM67_S_XTALLO (1 << CLK_CLKSEL2_PWM67_S_SHIFT) /* Low speed XTAL clock */
|
||||
# define CLK_CLKSEL1_PWM67_S_HCLK (2 << CLK_CLKSEL2_PWM67_S_SHIFT) /* HCLK */
|
||||
# define CLK_CLKSEL1_PWM67_S_INTHI (3 << CLK_CLKSEL2_PWM67_S_SHIFT) /* Internal high speed clock */
|
||||
|
||||
/* Clock divider number register */
|
||||
|
||||
#define CLK_CLKDIV_HCLK_N_SHIFT (0) /* Bits 0-3: HCLCK divide from clock source */
|
||||
#define CLK_CLKDIV_HCLK_N_MASK (15 << CLK_CLKDIV_HCLK_N_SHIFT)
|
||||
# define CLK_CLKDIV_HCLK_N(n) (((n)-1) << CLK_CLKDIV_HCLK_N_SHIFT) /* n=1..16 */
|
||||
#define CLK_CLKDIV_USB_N_SHIFT (4) /* Bits 4-7: USBD divide from clock source */
|
||||
#define CLK_CLKDIV_USB_N_MASK (15 << CLK_CLKDIV_USB_N_SHIFT)
|
||||
# define CLK_CLKDIV_USB_N(n) (((n)-1) << CLK_CLKDIV_USB_N_SHIFT) /* n=1..16 */
|
||||
#define CLK_CLKDIV_UART_N_SHIFT (8) /* Bits 8-11 UART divide from clock source */
|
||||
#define CLK_CLKDIV_UART_N_MASK (15 << CLK_CLKDIV_UART_N_SHIFT)
|
||||
# define CLK_CLKDIV_UART_N(n) (((n)-1) << CLK_CLKDIV_UART_N_SHIFT) /* n=1..16 */
|
||||
#define CLK_CLKDIV_ADC_N_SHIFT (16) /* Bits 16-23: ADC divide from clock source */
|
||||
#define CLK_CLKDIV_ADC_N_MASK (255 << CLK_CLKDIV_ADC_N_SHIFT)
|
||||
# define CLK_CLKDIV_ADC_N(n) (((n)-1) << CLK_CLKDIV_UART_N_SHIFT) /* n=1..256 */
|
||||
|
||||
/* PLL control register */
|
||||
|
||||
#define CLK_PLLCON_FB_DV_SHIFT (0) /* Bits 0-8: PLL feedback divider control pins */
|
||||
#define CLK_PLLCON_FB_DV_MASK (0x1ff << CLK_PLLCON_FB_DV_SHIFT)
|
||||
# define CLK_PLLCON_FB_DV(n) ((n) << CLK_PLLCON_FB_DV_SHIFT)
|
||||
#define CLK_PLLCON_IN_DV_SHIFT (9) /* bits 9-13: PLL input divider control pins */
|
||||
#define CLK_PLLCON_IN_DV_MASK (0x1f << CLK_PLLCON_IN_DV_SHIFT)
|
||||
# define CLK_PLLCON_IN_DV(n) ((n) << CLK_PLLCON_IN_DV_SHIFT)
|
||||
#define CLK_PLLCON_OUT_DV_SHIFT (14) /* Bits 14-15: PLL output divider control pins */
|
||||
#define CLK_PLLCON_OUT_DV_MASK (3 << CLK_PLLCON_OUT_DV_SHIFT)
|
||||
# define CLK_PLLCON_OUT_DV(n) ((n) << CLK_PLLCON_OUT_DV_SHIFT)
|
||||
#define CLK_PLLCON_PD (1 << 16) /* Bit 16: Power down mode */
|
||||
#define CLK_PLLCON_BP (1 << 17) /* Bit 17: PLL bypass control */
|
||||
#define CLK_PLLCON_OE (1 << 18) /* Bit 18: PLL OE (FOUT enable) pin control */
|
||||
#define CLK_PLLCON_PLL_SRC (1 << 19) /* Bit 19: PLL source clock select */
|
||||
|
||||
/* Frequency divider control register */
|
||||
|
||||
#define CLK_FRQDIV_FSEL_SHIFT (0) /* Bits 0-3: Divider output frequency selection bits */
|
||||
#define CLK_FRQDIV_FSEL_MASK (15 << CLK_FRQDIV_FSEL_SHIFT)
|
||||
# define CLK_FRQDIV_FSEL(n) ((n) << CLK_FRQDIV_FSEL_SHIFT) /* fout = fin / (2^(n+1)) */
|
||||
#define CLK_FRQDIV_DIVIDER_EN (1 << 4) /* Bit 4: Frequency divider enable bit */
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Data
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Functions
|
||||
********************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KL_CHIP_KL_CLK_H */
|
||||
@@ -0,0 +1,389 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/kl/kl_fmc.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KL_KL_FMC_H
|
||||
#define __ARCH_ARM_SRC_KL_KL_FMC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define KL_FMC_PFAPR_OFFSET 0x0000 /* Flash Access Protection Register */
|
||||
#define KL_FMC_PFB0CR_OFFSET 0x0004 /* Flash Bank 0 Control Register */
|
||||
#define KL_FMC_PFB1CR_OFFSET 0x0008 /* Flash Bank 1 Control Register */
|
||||
|
||||
/* Cache Directory Storage for way=w and set=s, w=0..3, s=0..7 */
|
||||
|
||||
#define KL_FMC_TAGVD_OFFSET(w,s) (0x100+((w)<<5)+((s)<<2))
|
||||
|
||||
#define KL_FMC_TAGVDW0S0_OFFSET 0x0100 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW0S1_OFFSET 0x0104 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW0S2_OFFSET 0x0108 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW0S3_OFFSET 0x010c /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW0S4_OFFSET 0x0110 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW0S5_OFFSET 0x0114 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW0S6_OFFSET 0x0118 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW0S7_OFFSET 0x011c /* Cache Directory Storage */
|
||||
|
||||
#define KL_FMC_TAGVDW1S0_OFFSET 0x0120 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW1S1_OFFSET 0x0124 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW1S2_OFFSET 0x0128 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW1S3_OFFSET 0x012c /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW1S4_OFFSET 0x0130 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW1S5_OFFSET 0x0134 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW1S6_OFFSET 0x0138 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW1S7_OFFSET 0x013c /* Cache Directory Storage */
|
||||
|
||||
#define KL_FMC_TAGVDW2S0_OFFSET 0x0140 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW2S1_OFFSET 0x0144 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW2S2_OFFSET 0x0148 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW2S3_OFFSET 0x014c /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW2S4_OFFSET 0x0150 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW2S5_OFFSET 0x0154 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW2S6_OFFSET 0x0158 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW2S7_OFFSET 0x015c /* Cache Directory Storage */
|
||||
|
||||
#define KL_FMC_TAGVDW3S0_OFFSET 0x0160 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW3S1_OFFSET 0x0164 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW3S2_OFFSET 0x0168 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW3S3_OFFSET 0x016c /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW3S4_OFFSET 0x0170 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW3S5_OFFSET 0x0174 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW3S6_OFFSET 0x0178 /* Cache Directory Storage */
|
||||
#define KL_FMC_TAGVDW3S7_OFFSET 0x017c /* Cache Directory Storage */
|
||||
|
||||
/* Cache Data Storage (upper and lower) for way=w and set=s, w=0..3, s=0..7 */
|
||||
|
||||
#define KL_FMC_DATAU_OFFSET(w,s) (0x200+((w)<<6)+((s)<<2))
|
||||
#define KL_FMC_DATAL_OFFSET(w,s) (0x204+((w)<<6)+((s)<<2))
|
||||
|
||||
#define KL_FMC_DATAW0S0U_OFFSET 0x0200 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW0S0L_OFFSET 0x0204 /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW0S1U_OFFSET 0x0208 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW0S1L_OFFSET 0x020c /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW0S2U_OFFSET 0x0210 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW0S2L_OFFSET 0x0214 /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW0S3U_OFFSET 0x0218 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW0S3L_OFFSET 0x021c /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW0S4U_OFFSET 0x0220 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW0S4L_OFFSET 0x0224 /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW0S5U_OFFSET 0x0228 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW0S5L_OFFSET 0x022c /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW0S6U_OFFSET 0x0230 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW0S6L_OFFSET 0x0234 /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW0S7U_OFFSET 0x0238 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW0S7L_OFFSET 0x023c /* Cache Data Storage (lower word) */
|
||||
|
||||
#define KL_FMC_DATAW1S0U_OFFSET 0x0240 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW1S0L_OFFSET 0x0244 /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW1S1U_OFFSET 0x0248 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW1S1L_OFFSET 0x024c /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW1S2U_OFFSET 0x0250 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW1S2L_OFFSET 0x0254 /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW1S3U_OFFSET 0x0258 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW1S3L_OFFSET 0x025c /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW1S4U_OFFSET 0x0260 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW1S4L_OFFSET 0x0264 /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW1S5U_OFFSET 0x0268 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW1S5L_OFFSET 0x026c /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW1S6U_OFFSET 0x0270 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW1S6L_OFFSET 0x0274 /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW1S7U_OFFSET 0x0278 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW1S7L_OFFSET 0x027c /* Cache Data Storage (lower word) */
|
||||
|
||||
#define KL_FMC_DATAW2S0U_OFFSET 0x0280 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW2S0L_OFFSET 0x0284 /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW2S1U_OFFSET 0x0288 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW2S1L_OFFSET 0x028c /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW2S2U_OFFSET 0x0290 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW2S2L_OFFSET 0x0294 /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW2S3U_OFFSET 0x0298 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW2S3L_OFFSET 0x029c /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW2S4U_OFFSET 0x02a0 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW2S4L_OFFSET 0x02a4 /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW2S5U_OFFSET 0x02a8 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW2S5L_OFFSET 0x02ac /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW2S6U_OFFSET 0x02b0 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW2S6L_OFFSET 0x02b4 /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW2S7U_OFFSET 0x02b8 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW2S7L_OFFSET 0x02bc /* Cache Data Storage (lower word) */
|
||||
|
||||
#define KL_FMC_DATAW3S0U_OFFSET 0x02c0 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW3S0L_OFFSET 0x02c4 /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW3S1U_OFFSET 0x02c8 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW3S1L_OFFSET 0x02cc /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW3S2U_OFFSET 0x02d0 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW3S2L_OFFSET 0x02d4 /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW3S3U_OFFSET 0x02d8 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW3S3L_OFFSET 0x02dc /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW3S4U_OFFSET 0x02e0 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW3S4L_OFFSET 0x02e4 /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW3S5U_OFFSET 0x02e8 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW3S5L_OFFSET 0x02ec /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW3S6U_OFFSET 0x02f0 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW3S6L_OFFSET 0x02f4 /* Cache Data Storage (lower word) */
|
||||
#define KL_FMC_DATAW3S7U_OFFSET 0x02f8 /* Cache Data Storage (upper word) */
|
||||
#define KL_FMC_DATAW3S7L_OFFSET 0x02fc /* Cache Data Storage (lower word) */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define KL_FMC_PFAPR (KL_FMC_BASE+KL_FMC_PFAPR_OFFSET)
|
||||
#define KL_FMC_PFB0CR (KL_FMC_BASE+KL_FMC_PFB0CR_OFFSET)
|
||||
#define KL_FMC_PFB1CR (KL_FMC_BASE+KL_FMC_PFB1CR_OFFSET)
|
||||
|
||||
/* Cache Directory Storage for way=w and set=s, w=0..3, s=0..7 */
|
||||
|
||||
#define KL_FMC_TAGVD(w,s) (KL_FMC_BASE+KL_FMC_TAGVD_OFFSET(w,s))
|
||||
|
||||
#define KL_FMC_TAGVDW0S0 (KL_FMC_BASE+KL_FMC_TAGVDW0S0_OFFSET)
|
||||
#define KL_FMC_TAGVDW0S1 (KL_FMC_BASE+KL_FMC_TAGVDW0S1_OFFSET)
|
||||
#define KL_FMC_TAGVDW0S2 (KL_FMC_BASE+KL_FMC_TAGVDW0S2_OFFSET)
|
||||
#define KL_FMC_TAGVDW0S3 (KL_FMC_BASE+KL_FMC_TAGVDW0S3_OFFSET)
|
||||
#define KL_FMC_TAGVDW0S4 (KL_FMC_BASE+KL_FMC_TAGVDW0S4_OFFSET)
|
||||
#define KL_FMC_TAGVDW0S5 (KL_FMC_BASE+KL_FMC_TAGVDW0S5_OFFSET)
|
||||
#define KL_FMC_TAGVDW0S6 (KL_FMC_BASE+KL_FMC_TAGVDW0S6_OFFSET)
|
||||
#define KL_FMC_TAGVDW0S7 (KL_FMC_BASE+KL_FMC_TAGVDW0S7_OFFSET)
|
||||
|
||||
#define KL_FMC_TAGVDW1S0 (KL_FMC_BASE+KL_FMC_TAGVDW1S0_OFFSET)
|
||||
#define KL_FMC_TAGVDW1S1 (KL_FMC_BASE+KL_FMC_TAGVDW1S1_OFFSET)
|
||||
#define KL_FMC_TAGVDW1S2 (KL_FMC_BASE+KL_FMC_TAGVDW1S2_OFFSET)
|
||||
#define KL_FMC_TAGVDW1S3 (KL_FMC_BASE+KL_FMC_TAGVDW1S3_OFFSET)
|
||||
#define KL_FMC_TAGVDW1S4 (KL_FMC_BASE+KL_FMC_TAGVDW1S4_OFFSET)
|
||||
#define KL_FMC_TAGVDW1S5 (KL_FMC_BASE+KL_FMC_TAGVDW1S5_OFFSET)
|
||||
#define KL_FMC_TAGVDW1S6 (KL_FMC_BASE+KL_FMC_TAGVDW1S6_OFFSET)
|
||||
#define KL_FMC_TAGVDW1S7 (KL_FMC_BASE+KL_FMC_TAGVDW1S7_OFFSET)
|
||||
|
||||
#define KL_FMC_TAGVDW2S0 (KL_FMC_BASE+KL_FMC_TAGVDW2S0_OFFSET)
|
||||
#define KL_FMC_TAGVDW2S1 (KL_FMC_BASE+KL_FMC_TAGVDW2S1_OFFSET)
|
||||
#define KL_FMC_TAGVDW2S2 (KL_FMC_BASE+KL_FMC_TAGVDW2S2_OFFSET)
|
||||
#define KL_FMC_TAGVDW2S3 (KL_FMC_BASE+KL_FMC_TAGVDW2S3_OFFSET)
|
||||
#define KL_FMC_TAGVDW2S4 (KL_FMC_BASE+KL_FMC_TAGVDW2S4_OFFSET)
|
||||
#define KL_FMC_TAGVDW2S5 (KL_FMC_BASE+KL_FMC_TAGVDW2S5_OFFSET)
|
||||
#define KL_FMC_TAGVDW2S6 (KL_FMC_BASE+KL_FMC_TAGVDW2S6_OFFSET)
|
||||
#define KL_FMC_TAGVDW2S7 (KL_FMC_BASE+KL_FMC_TAGVDW2S7_OFFSET)
|
||||
|
||||
#define KL_FMC_TAGVDW3S0 (KL_FMC_BASE+KL_FMC_TAGVDW3S0_OFFSET)
|
||||
#define KL_FMC_TAGVDW3S1 (KL_FMC_BASE+KL_FMC_TAGVDW3S1_OFFSET)
|
||||
#define KL_FMC_TAGVDW3S2 (KL_FMC_BASE+KL_FMC_TAGVDW3S2_OFFSET)
|
||||
#define KL_FMC_TAGVDW3S3 (KL_FMC_BASE+KL_FMC_TAGVDW3S3_OFFSET)
|
||||
#define KL_FMC_TAGVDW3S4 (KL_FMC_BASE+KL_FMC_TAGVDW3S4_OFFSET)
|
||||
#define KL_FMC_TAGVDW3S5 (KL_FMC_BASE+KL_FMC_TAGVDW3S5_OFFSET)
|
||||
#define KL_FMC_TAGVDW3S6 (KL_FMC_BASE+KL_FMC_TAGVDW3S6_OFFSET)
|
||||
#define KL_FMC_TAGVDW3S7 (KL_FMC_BASE+KL_FMC_TAGVDW3S7_OFFSET)
|
||||
|
||||
/* Cache Data Storage (upper and lower) for way=w and set=s, w=0..3, s=0..7 */
|
||||
|
||||
#define KL_FMC_DATAU(w,s) (KL_FMC_BASE+KL_FMC_DATAU_OFFSET(w,s))
|
||||
#define KL_FMC_DATAL(w,s) (KL_FMC_BASE+KL_FMC_DATAL_OFFSET(w,s))
|
||||
|
||||
#define KL_FMC_DATAW0S0U (KL_FMC_BASE+KL_FMC_DATAW0S0U_OFFSET)
|
||||
#define KL_FMC_DATAW0S0L (KL_FMC_BASE+KL_FMC_DATAW0S0L_OFFSET)
|
||||
#define KL_FMC_DATAW0S1U (KL_FMC_BASE+KL_FMC_DATAW0S1U_OFFSET)
|
||||
#define KL_FMC_DATAW0S1L (KL_FMC_BASE+KL_FMC_DATAW0S1L_OFFSET)
|
||||
#define KL_FMC_DATAW0S2U (KL_FMC_BASE+KL_FMC_DATAW0S2U_OFFSET)
|
||||
#define KL_FMC_DATAW0S2L (KL_FMC_BASE+KL_FMC_DATAW0S2L_OFFSET)
|
||||
#define KL_FMC_DATAW0S3U (KL_FMC_BASE+KL_FMC_DATAW0S3U_OFFSET)
|
||||
#define KL_FMC_DATAW0S3L (KL_FMC_BASE+KL_FMC_DATAW0S3L_OFFSET)
|
||||
#define KL_FMC_DATAW0S4U (KL_FMC_BASE+KL_FMC_DATAW0S4U_OFFSET)
|
||||
#define KL_FMC_DATAW0S4L (KL_FMC_BASE+KL_FMC_DATAW0S4L_OFFSET)
|
||||
#define KL_FMC_DATAW0S5U (KL_FMC_BASE+KL_FMC_DATAW0S5U_OFFSET)
|
||||
#define KL_FMC_DATAW0S5L (KL_FMC_BASE+KL_FMC_DATAW0S5L_OFFSET)
|
||||
#define KL_FMC_DATAW0S6U (KL_FMC_BASE+KL_FMC_DATAW0S6U_OFFSET)
|
||||
#define KL_FMC_DATAW0S6L (KL_FMC_BASE+KL_FMC_DATAW0S6L_OFFSET)
|
||||
#define KL_FMC_DATAW0S7U (KL_FMC_BASE+KL_FMC_DATAW0S7U_OFFSET)
|
||||
#define KL_FMC_DATAW0S7L (KL_FMC_BASE+KL_FMC_DATAW0S7L_OFFSET)
|
||||
|
||||
#define KL_FMC_DATAW1S0U (KL_FMC_BASE+KL_FMC_DATAW1S0U_OFFSET)
|
||||
#define KL_FMC_DATAW1S0L (KL_FMC_BASE+KL_FMC_DATAW1S0L_OFFSET)
|
||||
#define KL_FMC_DATAW1S1U (KL_FMC_BASE+KL_FMC_DATAW1S1U_OFFSET)
|
||||
#define KL_FMC_DATAW1S1L (KL_FMC_BASE+KL_FMC_DATAW1S1L_OFFSET)
|
||||
#define KL_FMC_DATAW1S2U (KL_FMC_BASE+KL_FMC_DATAW1S2U_OFFSET)
|
||||
#define KL_FMC_DATAW1S2L (KL_FMC_BASE+KL_FMC_DATAW1S2L_OFFSET)
|
||||
#define KL_FMC_DATAW1S3U (KL_FMC_BASE+KL_FMC_DATAW1S3U_OFFSET)
|
||||
#define KL_FMC_DATAW1S3L (KL_FMC_BASE+KL_FMC_DATAW1S3L_OFFSET)
|
||||
#define KL_FMC_DATAW1S4U (KL_FMC_BASE+KL_FMC_DATAW1S4U_OFFSET)
|
||||
#define KL_FMC_DATAW1S4L (KL_FMC_BASE+KL_FMC_DATAW1S4L_OFFSET)
|
||||
#define KL_FMC_DATAW1S5U (KL_FMC_BASE+KL_FMC_DATAW1S5U_OFFSET)
|
||||
#define KL_FMC_DATAW1S5L (KL_FMC_BASE+KL_FMC_DATAW1S5L_OFFSET)
|
||||
#define KL_FMC_DATAW1S6U (KL_FMC_BASE+KL_FMC_DATAW1S6U_OFFSET)
|
||||
#define KL_FMC_DATAW1S6L (KL_FMC_BASE+KL_FMC_DATAW1S6L_OFFSET)
|
||||
#define KL_FMC_DATAW1S7U (KL_FMC_BASE+KL_FMC_DATAW1S7U_OFFSET)
|
||||
#define KL_FMC_DATAW1S7L (KL_FMC_BASE+KL_FMC_DATAW1S7L_OFFSET)
|
||||
|
||||
#define KL_FMC_DATAW2S0U (KL_FMC_BASE+KL_FMC_DATAW2S0U_OFFSET)
|
||||
#define KL_FMC_DATAW2S0L (KL_FMC_BASE+KL_FMC_DATAW2S0L_OFFSET)
|
||||
#define KL_FMC_DATAW2S1U (KL_FMC_BASE+KL_FMC_DATAW2S1U_OFFSET)
|
||||
#define KL_FMC_DATAW2S1L (KL_FMC_BASE+KL_FMC_DATAW2S1L_OFFSET)
|
||||
#define KL_FMC_DATAW2S2U (KL_FMC_BASE+KL_FMC_DATAW2S2U_OFFSET)
|
||||
#define KL_FMC_DATAW2S2L (KL_FMC_BASE+KL_FMC_DATAW2S2L_OFFSET)
|
||||
#define KL_FMC_DATAW2S3U (KL_FMC_BASE+KL_FMC_DATAW2S3U_OFFSET)
|
||||
#define KL_FMC_DATAW2S3L (KL_FMC_BASE+KL_FMC_DATAW2S3L_OFFSET)
|
||||
#define KL_FMC_DATAW2S4U (KL_FMC_BASE+KL_FMC_DATAW2S4U_OFFSET)
|
||||
#define KL_FMC_DATAW2S4L (KL_FMC_BASE+KL_FMC_DATAW2S4L_OFFSET)
|
||||
#define KL_FMC_DATAW2S5U (KL_FMC_BASE+KL_FMC_DATAW2S5U_OFFSET)
|
||||
#define KL_FMC_DATAW2S5L (KL_FMC_BASE+KL_FMC_DATAW2S5L_OFFSET)
|
||||
#define KL_FMC_DATAW2S6U (KL_FMC_BASE+KL_FMC_DATAW2S6U_OFFSET)
|
||||
#define KL_FMC_DATAW2S6L (KL_FMC_BASE+KL_FMC_DATAW2S6L_OFFSET)
|
||||
#define KL_FMC_DATAW2S7U (KL_FMC_BASE+KL_FMC_DATAW2S7U_OFFSET)
|
||||
#define KL_FMC_DATAW2S7L (KL_FMC_BASE+KL_FMC_DATAW2S7L_OFFSET)
|
||||
|
||||
#define KL_FMC_DATAW3S0U (KL_FMC_BASE+KL_FMC_DATAW3S0U_OFFSET)
|
||||
#define KL_FMC_DATAW3S0L (KL_FMC_BASE+KL_FMC_DATAW3S0L_OFFSET)
|
||||
#define KL_FMC_DATAW3S1U (KL_FMC_BASE+KL_FMC_DATAW3S1U_OFFSET)
|
||||
#define KL_FMC_DATAW3S1L (KL_FMC_BASE+KL_FMC_DATAW3S1L_OFFSET)
|
||||
#define KL_FMC_DATAW3S2U (KL_FMC_BASE+KL_FMC_DATAW3S2U_OFFSET)
|
||||
#define KL_FMC_DATAW3S2L (KL_FMC_BASE+KL_FMC_DATAW3S2L_OFFSET)
|
||||
#define KL_FMC_DATAW3S3U (KL_FMC_BASE+KL_FMC_DATAW3S3U_OFFSET)
|
||||
#define KL_FMC_DATAW3S3L (KL_FMC_BASE+KL_FMC_DATAW3S3L_OFFSET)
|
||||
#define KL_FMC_DATAW3S4U (KL_FMC_BASE+KL_FMC_DATAW3S4U_OFFSET)
|
||||
#define KL_FMC_DATAW3S4L (KL_FMC_BASE+KL_FMC_DATAW3S4L_OFFSET)
|
||||
#define KL_FMC_DATAW3S5U (KL_FMC_BASE+KL_FMC_DATAW3S5U_OFFSET)
|
||||
#define KL_FMC_DATAW3S5L (KL_FMC_BASE+KL_FMC_DATAW3S5L_OFFSET)
|
||||
#define KL_FMC_DATAW3S6U (KL_FMC_BASE+KL_FMC_DATAW3S6U_OFFSET)
|
||||
#define KL_FMC_DATAW3S6L (KL_FMC_BASE+KL_FMC_DATAW3S6L_OFFSET)
|
||||
#define KL_FMC_DATAW3S7U (KL_FMC_BASE+KL_FMC_DATAW3S7U_OFFSET)
|
||||
#define KL_FMC_DATAW3S7L (KL_FMC_BASE+KL_FMC_DATAW3S7L_OFFSET)
|
||||
|
||||
/* Register Bit Definitions *********************************************************/
|
||||
|
||||
/* Flash Access Protection Register */
|
||||
/* Access protection bits (all masters) */
|
||||
|
||||
#define FMC_PFAPR_NONE 0 /* No access may be performed by this master */
|
||||
#define FMC_PFAPR_RDONLY 1 /* Only read accesses may be performed by this master */
|
||||
#define FMC_PFAPR_WRONLY 2 /* Only write accesses may be performed by this master */
|
||||
#define FMC_PFAPR_RDWR 3 /* Both read and write accesses may be performed by this master */
|
||||
|
||||
#define FMC_PFAPR_M0AP_SHIFT (0) /* Bits 0-1: Master 0 Access Protection */
|
||||
#define FMC_PFAPR_M0AP_MASK (3 << FMC_PFAPR_M0AP_SHIFT)
|
||||
#define FMC_PFAPR_M1AP_SHIFT (2) /* Bits 2-3: Master 1 Access Protection */
|
||||
#define FMC_PFAPR_M1AP_MASK (3 << FMC_PFAPR_M1AP_SHIFT)
|
||||
#define FMC_PFAPR_M2AP_SHIFT (4) /* Bits 4-5: Master 2 Access Protection */
|
||||
#define FMC_PFAPR_M2AP_MASK (3 << FMC_PFAPR_M2AP_SHIFT)
|
||||
#define FMC_PFAPR_M3AP_SHIFT (6) /* Bits 6-7: Master 3 Access Protection */
|
||||
#define FMC_PFAPR_M3AP_MASK (3 << FMC_PFAPR_M3AP_SHIFT)
|
||||
#define FMC_PFAPR_M4AP_SHIFT (8) /* Bits 8-9: Master 4 Access Protection */
|
||||
#define FMC_PFAPR_M4AP_MASK (3 << FMC_PFAPR_M4AP_SHIFT)
|
||||
#define FMC_PFAPR_M5AP_SHIFT (10) /* Bits 10-11: Master 5 Access Protection */
|
||||
#define FMC_PFAPR_M5AP_MASK (3 << FMC_PFAPR_M5AP_SHIFT)
|
||||
#define FMC_PFAPR_M6AP_SHIFT (12) /* Bits 12-13: Master 6 Access Protection */
|
||||
#define FMC_PFAPR_M6AP_MASK (3 << FMC_PFAPR_M6AP_SHIFT)
|
||||
#define FMC_PFAPR_M7AP_SHIFT (14) /* Bits 14-15: Master 7 Access Protection */
|
||||
#define FMC_PFAPR_M7AP_MASK (3 << FMC_PFAPR_M7AP_SHIFT)
|
||||
#define FMC_PFAPR_M0PFD (1 << 16) /* Bit 16: Master 0 Prefetch Disable */
|
||||
#define FMC_PFAPR_M1PFD (1 << 17) /* Bit 17: Master 1 Prefetch Disable */
|
||||
#define FMC_PFAPR_M2PFD (1 << 18) /* Bit 18: Master 2 Prefetch Disable */
|
||||
#define FMC_PFAPR_M3PFD (1 << 19) /* Bit 19: Master 3 Prefetch Disable */
|
||||
#define FMC_PFAPR_M4PFD (1 << 20) /* Bit 20: Master 4 Prefetch Disable */
|
||||
#define FMC_PFAPR_M5PFD (1 << 21) /* Bit 21: Master 5 Prefetch Disable */
|
||||
#define FMC_PFAPR_M6PFD (1 << 22) /* Bit 22: Master 6 Prefetch Disable */
|
||||
#define FMC_PFAPR_M7PFD (1 << 23) /* Bit 23: Master 7 Prefetch Disable */
|
||||
/* Bits 24-31: Reserved */
|
||||
/* Flash Bank 0 Control Register */
|
||||
|
||||
#define FMC_PFB0CR_B0SEBE (1 << 0) /* Bit 0: Bank 0 Single Entry Buffer Enable */
|
||||
#define FMC_PFB0CR_B0IPE (1 << 1) /* Bit 1: Bank 0 Instruction Prefetch Enable */
|
||||
#define FMC_PFB0CR_B0DPE (1 << 2) /* Bit 2: Bank 0 Data Prefetch Enable */
|
||||
#define FMC_PFB0CR_B0ICE (1 << 3) /* Bit 3: Bank 0 Instruction Cache Enable */
|
||||
#define FMC_PFB0CR_B0DCE (1 << 4) /* Bit 4: Bank 0 Data Cache Enable */
|
||||
#define FMC_PFB0CR_CRC_SHIFT (5) /* Bits 5-7: Cache Replacement Control */
|
||||
#define FMC_PFB0CR_CRC_MASK (7 << FMC_PFB0CR_CRC_SHIFT)
|
||||
# define FMC_PFB0CR_CRC_ALL (0 << FMC_PFB0CR_CRC_SHIFT) /* LRU all four ways */
|
||||
# define FMC_PFB0CR_CRC_I01D23 (2 << FMC_PFB0CR_CRC_SHIFT) /* LRU ifetches 0-1 data 2-3 */
|
||||
# define FMC_PFB0CR_CRC_I012D3 (3 << FMC_PFB0CR_CRC_SHIFT) /* LRU ifetches 0-3 data 3 */
|
||||
/* Bits 8-16: Reserved */
|
||||
#define FMC_PFB0CR_B0MW_SHIFT (17) /* Bits 17-18: Bank 0 Memory Width */
|
||||
#define FMC_PFB0CR_B0MW_MASK (3 << FMC_PFB0CR_B0MW_SHIFT)
|
||||
# define FMC_PFB0CR_B0MW_32BITS (0 << FMC_PFB0CR_B0MW_SHIFT) /* 32 bits */
|
||||
# define FMC_PFB0CR_B0MW_64BITS (1 << FMC_PFB0CR_B0MW_SHIFT) /* 64 bits */
|
||||
#define FMC_PFB0CR_S_B_INV (1 << 19) /* Bit 19: Invalidate Prefetch Speculation Buffer */
|
||||
#define FMC_PFB0CR_CINV_WAY_SHIFT (20) /* Bits 20-23: Cache Invalidate Way x */
|
||||
#define FMC_PFB0CR_CINV_WAY_MASK (15 << FMC_PFB0CR_CINV_WAY_SHIFT)
|
||||
#define FMC_PFB0CR_CLCK_WAY_SHIFT (24) /* Bits 24-27: Cache Lock Way x */
|
||||
#define FMC_PFB0CR_CLCK_WAY_MASK (15 << FMC_PFB0CR_CLCK_WAY_SHIFT)
|
||||
#define FMC_PFB0CR_B0RWSC_SHIFT (28) /* Bits 28-31: Bank 0 Read Wait State Control */
|
||||
#define FMC_PFB0CR_B0RWSC_MASK (15 << FMC_PFB0CR_B0RWSC_SHIFT)
|
||||
|
||||
/* Flash Bank 1 Control Register */
|
||||
|
||||
#define FMC_PFB1CR_B1SEBE (1 << 0) /* Bit 0: Bank 1 Single Entry Buffer Enable */
|
||||
#define FMC_PFB1CR_B1IPE (1 << 1) /* Bit 1: Bank 1 Instruction Prefetch Enable */
|
||||
#define FMC_PFB1CR_B1DPE (1 << 2) /* Bit 2: Bank 1 Data Prefetch Enable */
|
||||
#define FMC_PFB1CR_B1ICE (1 << 3) /* Bit 3: Bank 1 Instruction Cache Enable */
|
||||
#define FMC_PFB1CR_B1DCE (1 << 4) /* Bit 4: Bank 1 Data Cache Enable */
|
||||
/* Bits 5-16: Reserved */
|
||||
#define FMC_PFB1CR_B1MW_SHIFT (17) /* Bits 17-18: Bank 1 Memory Width */
|
||||
#define FMC_PFB1CR_B1MW_MASK (3 << FMC_PFB1CR_B1MW_SHIFT)
|
||||
# define FMC_PFB1CR_B1MW_32BITS (0 << FMC_PFB1CR_B1MW_SHIFT) /* 32 bits */
|
||||
# define FMC_PFB1CR_B1MW_64BITS (1 << FMC_PFB1CR_B1MW_SHIFT) /* 64 bits */
|
||||
/* Bits 19-27: Reserved */
|
||||
#define FMC_PFB1CR_B1RWSC_SHIFT (28) /* Bits 28-31: Bank 1 Read Wait State Control */
|
||||
#define FMC_PFB1CR_B1RWSC_MASK (15 << FMC_PFB1CR_B0RWSC_SHIFT)
|
||||
|
||||
/* Cache Directory Storage for way=w and set=s, w=0..3, s=0..7 */
|
||||
|
||||
#define FMC_TAGVD_VALID (1 << 0) /* Bit 0: 1-bit valid for cache entry */
|
||||
/* Bits 1-5: Reserved */
|
||||
#define FMC_TAGVD_TAG_SHIFT (6) /* Bits 6-18: 13-bit tag for cache entry */
|
||||
#define FMC_TAGVD_TAG_MASK (0x1fff << FMC_TAGVD_TAG_SHIFT)
|
||||
/* Bits 19-31: Reserved */
|
||||
|
||||
/* Cache Data Storage (upper and lower) for way=w and set=s, w=0..3, s=0..7.
|
||||
* 64-bit data in two 32-bit registers.
|
||||
*/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KL_KL_FMC_H */
|
||||
@@ -0,0 +1,373 @@
|
||||
/********************************************************************************************
|
||||
* arch/arm/src/nuc1xx/chip/nuc_gcr.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KL_CHIP_KL_GCR_H
|
||||
#define __ARCH_ARM_SRC_KL_CHIP_KL_GCR_H
|
||||
|
||||
/********************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
********************************************************************************************/
|
||||
/* Register offsets *************************************************************************/
|
||||
|
||||
#define KL_GCR_PDID_OFFSET 0x0000 /* Part didentification number register */
|
||||
#define KL_GCR_RSTSRC_OFFSET 0x0004 /* System reset source register */
|
||||
#define KL_GCR_IPRSTC1_OFFSET 0x0008 /* IP Reset control register 1 */
|
||||
#define KL_GCR_IPRSTC2_OFFSET 0x000c /* IP Reset control register 2 */
|
||||
#define KL_GCR_CPR_OFFSET 0x0010 /* Chip performance register */
|
||||
#define KL_GCR_BODCR_OFFSET 0x0018 /* Brown-out detector control register */
|
||||
#define KL_GCR_TEMPCR_OFFSET 0x001c /* Temperature sensor control register */
|
||||
#define KL_GCR_PORCR_OFFSET 0x0024 /* Power-on-reset control register */
|
||||
#define KL_GCR_GPA_MFP_OFFSET 0x0030 /* Multiple function pin GPIOA control register */
|
||||
#define KL_GCR_GPB_MFP_OFFSET 0x0034 /* Multiple function pin GPIOB control register */
|
||||
#define KL_GCR_GPC_MFP_OFFSET 0x0038 /* Multiple function pin GPIOC control register */
|
||||
#define KL_GCR_GPD_MFP_OFFSET 0x003C /* Multiple function pin GPIOD control register */
|
||||
#define KL_GCR_GPE_MFP_OFFSET 0x0040 /* Multiple function pin GPIOE control register */
|
||||
#define KL_GCR_ALT_MFP_OFFSET 0x0050 /* Alternative multiple function pin control register */
|
||||
#define KL_GCR_REGWRPROT_OFFSET 0x0100 /* Register write-protection control register */
|
||||
|
||||
/* Register addresses ***********************************************************************/
|
||||
|
||||
#define KL_GCR_PDID (KL_GCR_BASE+KL_GCR_PDID_OFFSET)
|
||||
#define KL_GCR_RSTSRC (KL_GCR_BASE+KL_GCR_RSTSRC_OFFSET)
|
||||
#define KL_GCR_IPRSTC1 (KL_GCR_BASE+KL_GCR_IPRSTC1_OFFSET)
|
||||
#define KL_GCR_IPRSTC2 (KL_GCR_BASE+KL_GCR_IPRSTC2_OFFSET)
|
||||
#define KL_GCR_CPR (KL_GCR_BASE+KL_GCR_CPR_OFFSET)
|
||||
#define KL_GCR_BODCR (KL_GCR_BASE+KL_GCR_BODCR_OFFSET)
|
||||
#define KL_GCR_TEMPCR (KL_GCR_BASE+KL_GCR_TEMPCR_OFFSET)
|
||||
#define KL_GCR_PORCR (KL_GCR_BASE+KL_GCR_PORCR_OFFSET)
|
||||
#define KL_GCR_GPA_MFP (KL_GCR_BASE+KL_GCR_GPA_MFP_OFFSET)
|
||||
#define KL_GCR_GPB_MFP (KL_GCR_BASE+KL_GCR_GPB_MFP_OFFSET)
|
||||
#define KL_GCR_GPC_MFP (KL_GCR_BASE+KL_GCR_GPC_MFP_OFFSET)
|
||||
#define KL_GCR_GPD_MFP (KL_GCR_BASE+KL_GCR_GPD_MFP_OFFSET)
|
||||
#define KL_GCR_GPE_MFP (KL_GCR_BASE+KL_GCR_GPE_MFP_OFFSET)
|
||||
#define KL_GCR_ALT_MFP (KL_GCR_BASE+KL_GCR_ALT_MFP_OFFSET)
|
||||
#define KL_GCR_REGWRPROT (KL_GCR_BASE+KL_GCR_REGWRPROT_OFFSET)
|
||||
|
||||
/* Register bit-field definitions ***********************************************************/
|
||||
|
||||
/* Part didentification number register (32-bit part ID number) */
|
||||
|
||||
/* System reset source register */
|
||||
|
||||
#define GCR_RSTSRC_POR (1 << 0) /* Bit 0: Power-on reset (POR) or chip reset (CHIP_RST) */
|
||||
#define GCR_RSTSRC_RESET (1 << 1) /* Bit 1: /RESET pin */
|
||||
#define GCR_RSTSRC_WDT (1 << 2) /* Bit 2: Watchdog timer */
|
||||
#define GCR_RSTSRC_LVR (1 << 3) /* Bit 3: Low voltage reset controller */
|
||||
#define GCR_RSTSRC_BOD (1 << 4) /* Bit 4: Brown-out detection */
|
||||
#define GCR_RSTSRC_SYS (1 << 5) /* Bit 5: Software set AIRCR:SYSRESETREQ */
|
||||
#define GCR_RSTSRC_CPU (1 << 7) /* Bit 7: Sofware set CPU_RST */
|
||||
|
||||
/* IP Reset control register 1 */
|
||||
|
||||
#define GCR_IPRSTC1_CHIP_RST (1 << 0) /* Bit 0: Chip one-shot reset */
|
||||
#define GCR_IPRSTC1_CPU_RST (1 << 1) /* Bit 1: CPU kernel one-shot reset */
|
||||
#define GCR_IPRSTC1_PDMA_RST (1 << 2) /* Bit 2: PDMA controller reset */
|
||||
#define GCR_IPRSTC1_EBI_RST (1 << 3) /* Bit 3: EBI controller reset */
|
||||
|
||||
/* IP Reset control register 2 */
|
||||
|
||||
#define GCR_IPRSTC2_GPIO_RST (1 << 1) /* Bit 1: GPIO controller reset */
|
||||
#define GCR_IPRSTC2_TMR0_RST (1 << 2) /* Bit 2: Timer0 controller reset */
|
||||
#define GCR_IPRSTC2_TMR1_RST (1 << 3) /* Bit 3: Timer1 controller reset */
|
||||
#define GCR_IPRSTC2_TMR2_RST (1 << 4) /* Bit 4: Timer2 controller reset */
|
||||
#define GCR_IPRSTC2_TMR3_RST (1 << 5) /* Bit 5: Timer3 controller reset */
|
||||
#define GCR_IPRSTC2_I2C0_RST (1 << 8) /* Bit 8: I2C0 controller reset */
|
||||
#define GCR_IPRSTC2_I2C1_RST (1 << 9) /* Bit 9: I2C1 controller reset */
|
||||
#define GCR_IPRSTC2_SPI0_RST (1 << 12) /* Bit 12: SPI0 controller reset */
|
||||
#define GCR_IPRSTC2_SPI1_RST (1 << 13) /* Bit 13: SPI1 controller reset */
|
||||
#define GCR_IPRSTC2_SPI2_RST (1 << 14) /* Bit 14: SPI2 controller reset */
|
||||
#define GCR_IPRSTC2_SPI3_RST (1 << 15) /* Bit 15: SPI3 controller reset */
|
||||
#define GCR_IPRSTC2_UART0_RST (1 << 16) /* Bit 16: UART0 controller reset */
|
||||
#define GCR_IPRSTC2_UART1_RST (1 << 17) /* Bit 17: UART1 controller reset */
|
||||
#define GCR_IPRSTC2_UART2_RST (1 << 18) /* Bit 18: UART2 controller reset */
|
||||
#define GCR_IPRSTC2_PWM03_RST (1 << 20) /* Bit 20: PWM0/1/2/3 controller reset */
|
||||
#define GCR_IPRSTC2_PWM47_RST (1 << 21) /* Bit 21: PWM4/5/6/7 controller reset */
|
||||
#define GCR_IPRSTC2_ACMP_RST (1 << 22) /* Bit 22: Analog comparator controller reset */
|
||||
#define GCR_IPRSTC2_PS2_RST (1 << 23) /* Bit 23: PS/2 controller reset */
|
||||
#define GCR_IPRSTC2_USBD_RST (1 << 27) /* Bit 27: USB device controller reset */
|
||||
#define GCR_IPRSTC2_ADC_RST (1 << 28) /* Bit 28: ADC controller reset */
|
||||
#define GCR_IPRSTC2_I2S_RST (1 << 29) /* Bit 29: I2S controller reset */
|
||||
|
||||
/* Chip performance register */
|
||||
|
||||
#define GCR_CPR_HPE (1 << 0) /* Bit 0: High performance enable */
|
||||
|
||||
/* Brown-out detector control register */
|
||||
|
||||
#define GCR_BODCR_BOD_EN (1 << 0) /* Bit 0: Brown-ut detector enable */
|
||||
#define GCR_BODCR_BOD_VL_SHIFT (1) /* Bits 1-2: Brown-out detector threshold voltage selection */
|
||||
#define GCR_BODCR_BOD_VL_MASK (3 << GCR_BODCR_BOD_VL_SHIFT)
|
||||
# define GCR_BODCR_BOD_VL_2p2V (0 << GCR_BODCR_BOD_VL_SHIFT) /* 2.2V */
|
||||
# define GCR_BODCR_BOD_VL_2p7V (1 << GCR_BODCR_BOD_VL_SHIFT) /* 2.7V */
|
||||
# define GCR_BODCR_BOD_VL_3p8V (2 << GCR_BODCR_BOD_VL_SHIFT) /* 3.8V */
|
||||
# define GCR_BODCR_BOD_VL_4p5V (3 << GCR_BODCR_BOD_VL_SHIFT) /* 4.5V */
|
||||
#define GCR_BODCR_BOD_RSTEN (1 << 3) /* Bit 3: Brown-out reset enable */
|
||||
#define GCR_BODCR_BOD_INTF (1 << 4) /* Bit 4: Brown-out deletector interrupt flag */
|
||||
#define GCR_BODCR_BOD_LPM (1 << 5) /* Bit 5: Brown-out detector low power mode */
|
||||
#define GCR_BODCR_BOD_OUT (1 << 6) /* Bit 6: Brown-out detector output status */
|
||||
#define GCR_BODCR_LVR_EN (1 << 7) /* Bit 7: Low voltaghe reset enable */
|
||||
|
||||
/* Temperature sensor control register */
|
||||
|
||||
#define GCR_TEMPCR_VTEMP_EN (1 << 0) /* Bit 0: Temperature sensor enable */
|
||||
|
||||
/* Power-on-reset control register */
|
||||
|
||||
#define GCR_PORCR_MASK (0xffff) /* Bits 9-15: POR disable code */
|
||||
|
||||
/* Multiple function pin GPIOA control register */
|
||||
|
||||
#define GCR_GPA_MFP(n) (1 << (n)) /* Bits 0-15: PAn pin function selection */
|
||||
# define GCR_GPA_MFP0 (1 << 0)
|
||||
# define GCR_GPA_MFP1 (1 << 1)
|
||||
# define GCR_GPA_MFP2 (1 << 2)
|
||||
# define GCR_GPA_MFP3 (1 << 3)
|
||||
# define GCR_GPA_MFP4 (1 << 4)
|
||||
# define GCR_GPA_MFP5 (1 << 5)
|
||||
# define GCR_GPA_MFP6 (1 << 6)
|
||||
# define GCR_GPA_MFP7 (1 << 7)
|
||||
# define GCR_GPA_MFP8 (1 << 8)
|
||||
# define GCR_GPA_MFP9 (1 << 9)
|
||||
# define GCR_GPA_MFP10 (1 << 10)
|
||||
# define GCR_GPA_MFP11 (1 << 11)
|
||||
# define GCR_GPA_MFP12 (1 << 12)
|
||||
# define GCR_GPA_MFP13 (1 << 13)
|
||||
# define GCR_GPA_MFP14 (1 << 14)
|
||||
# define GCR_GPA_MFP15 (1 << 15)
|
||||
#define GCR_GPA_TYPE(n) (1 << ((n)+16)) /* Bits 16-31: Enable Schmitt trigger function */
|
||||
# define GCR_GPA_TYPE0 (1 << 0)
|
||||
# define GCR_GPA_TYPE1 (1 << 1)
|
||||
# define GCR_GPA_TYPE2 (1 << 2)
|
||||
# define GCR_GPA_TYPE3 (1 << 3)
|
||||
# define GCR_GPA_TYPE4 (1 << 4)
|
||||
# define GCR_GPA_TYPE5 (1 << 5)
|
||||
# define GCR_GPA_TYPE6 (1 << 6)
|
||||
# define GCR_GPA_TYPE7 (1 << 7)
|
||||
# define GCR_GPA_TYPE8 (1 << 8)
|
||||
# define GCR_GPA_TYPE9 (1 << 9)
|
||||
# define GCR_GPA_TYPE10 (1 << 10)
|
||||
# define GCR_GPA_TYPE11 (1 << 11)
|
||||
# define GCR_GPA_TYPE12 (1 << 12)
|
||||
# define GCR_GPA_TYPE13 (1 << 13)
|
||||
# define GCR_GPA_TYPE14 (1 << 14)
|
||||
# define GCR_GPA_TYPE15 (1 << 15)
|
||||
|
||||
/* Multiple function pin GPIOB control register */
|
||||
|
||||
#define GCR_GPB_MFP(n) (1 << (n)) /* Bits 0-15: PBn pin function selection */
|
||||
# define GCR_GPB_MFP0 (1 << 0)
|
||||
# define GCR_GPB_MFP1 (1 << 1)
|
||||
# define GCR_GPB_MFP2 (1 << 2)
|
||||
# define GCR_GPB_MFP3 (1 << 3)
|
||||
# define GCR_GPB_MFP4 (1 << 4)
|
||||
# define GCR_GPB_MFP5 (1 << 5)
|
||||
# define GCR_GPB_MFP6 (1 << 6)
|
||||
# define GCR_GPB_MFP7 (1 << 7)
|
||||
# define GCR_GPB_MFP8 (1 << 8)
|
||||
# define GCR_GPB_MFP9 (1 << 9)
|
||||
# define GCR_GPB_MFP10 (1 << 10)
|
||||
# define GCR_GPB_MFP11 (1 << 11)
|
||||
# define GCR_GPB_MFP12 (1 << 12)
|
||||
# define GCR_GPB_MFP13 (1 << 13)
|
||||
# define GCR_GPB_MFP14 (1 << 14)
|
||||
# define GCR_GPB_MFP15 (1 << 15)
|
||||
#define GCR_GPB_TYPE(n) (1 << ((n)+16)) /* Bits 16-31: Enable Schmitt trigger function */
|
||||
# define GCR_GPB_TYPE0 (1 << 0)
|
||||
# define GCR_GPB_TYPE1 (1 << 1)
|
||||
# define GCR_GPB_TYPE2 (1 << 2)
|
||||
# define GCR_GPB_TYPE3 (1 << 3)
|
||||
# define GCR_GPB_TYPE4 (1 << 4)
|
||||
# define GCR_GPB_TYPE5 (1 << 5)
|
||||
# define GCR_GPB_TYPE6 (1 << 6)
|
||||
# define GCR_GPB_TYPE7 (1 << 7)
|
||||
# define GCR_GPB_TYPE8 (1 << 8)
|
||||
# define GCR_GPB_TYPE9 (1 << 9)
|
||||
# define GCR_GPB_TYPE10 (1 << 10)
|
||||
# define GCR_GPB_TYPE11 (1 << 11)
|
||||
# define GCR_GPB_TYPE12 (1 << 12)
|
||||
# define GCR_GPB_TYPE13 (1 << 13)
|
||||
# define GCR_GPB_TYPE14 (1 << 14)
|
||||
# define GCR_GPB_TYPE15 (1 << 15)
|
||||
|
||||
/* Multiple function pin GPIOC control register */
|
||||
|
||||
#define GCR_GPC_MFP(n) (1 << (n)) /* Bits 0-15: PCn pin function selection */
|
||||
# define GCR_GPC_MFP0 (1 << 0)
|
||||
# define GCR_GPC_MFP1 (1 << 1)
|
||||
# define GCR_GPC_MFP2 (1 << 2)
|
||||
# define GCR_GPC_MFP3 (1 << 3)
|
||||
# define GCR_GPC_MFP4 (1 << 4)
|
||||
# define GCR_GPC_MFP5 (1 << 5)
|
||||
# define GCR_GPC_MFP6 (1 << 6)
|
||||
# define GCR_GPC_MFP7 (1 << 7)
|
||||
# define GCR_GPC_MFP8 (1 << 8)
|
||||
# define GCR_GPC_MFP9 (1 << 9)
|
||||
# define GCR_GPC_MFP10 (1 << 10)
|
||||
# define GCR_GPC_MFP11 (1 << 11)
|
||||
# define GCR_GPC_MFP12 (1 << 12)
|
||||
# define GCR_GPC_MFP13 (1 << 13)
|
||||
# define GCR_GPC_MFP14 (1 << 14)
|
||||
# define GCR_GPC_MFP15 (1 << 15)
|
||||
#define GCR_GPC_TYPE(n) (1 << ((n)+16)) /* Bits 16-31: Enable Schmitt trigger function */
|
||||
# define GCR_GPC_TYPE0 (1 << 0)
|
||||
# define GCR_GPC_TYPE1 (1 << 1)
|
||||
# define GCR_GPC_TYPE2 (1 << 2)
|
||||
# define GCR_GPC_TYPE3 (1 << 3)
|
||||
# define GCR_GPC_TYPE4 (1 << 4)
|
||||
# define GCR_GPC_TYPE5 (1 << 5)
|
||||
# define GCR_GPC_TYPE6 (1 << 6)
|
||||
# define GCR_GPC_TYPE7 (1 << 7)
|
||||
# define GCR_GPC_TYPE8 (1 << 8)
|
||||
# define GCR_GPC_TYPE9 (1 << 9)
|
||||
# define GCR_GPC_TYPE10 (1 << 10)
|
||||
# define GCR_GPC_TYPE11 (1 << 11)
|
||||
# define GCR_GPC_TYPE12 (1 << 12)
|
||||
# define GCR_GPC_TYPE13 (1 << 13)
|
||||
# define GCR_GPC_TYPE14 (1 << 14)
|
||||
# define GCR_GPC_TYPE15 (1 << 15)
|
||||
|
||||
/* Multiple function pin GPIOD control register */
|
||||
|
||||
#define GCR_GPD_MFP(n) (1 << (n)) /* Bits 0-15: PDn pin function selection */
|
||||
# define GCR_GPD_MFP0 (1 << 0)
|
||||
# define GCR_GPD_MFP1 (1 << 1)
|
||||
# define GCR_GPD_MFP2 (1 << 2)
|
||||
# define GCR_GPD_MFP3 (1 << 3)
|
||||
# define GCR_GPD_MFP4 (1 << 4)
|
||||
# define GCR_GPD_MFP5 (1 << 5)
|
||||
# define GCR_GPD_MFP6 (1 << 6)
|
||||
# define GCR_GPD_MFP7 (1 << 7)
|
||||
# define GCR_GPD_MFP8 (1 << 8)
|
||||
# define GCR_GPD_MFP9 (1 << 9)
|
||||
# define GCR_GPD_MFP10 (1 << 10)
|
||||
# define GCR_GPD_MFP11 (1 << 11)
|
||||
# define GCR_GPD_MFP12 (1 << 12)
|
||||
# define GCR_GPD_MFP13 (1 << 13)
|
||||
# define GCR_GPD_MFP14 (1 << 14)
|
||||
# define GCR_GPD_MFP15 (1 << 15)
|
||||
#define GCR_GPD_TYPE(n) (1 << ((n)+16)) /* Bits 16-31: Enable Schmitt trigger function */
|
||||
# define GCR_GPD_TYPE0 (1 << 0)
|
||||
# define GCR_GPD_TYPE1 (1 << 1)
|
||||
# define GCR_GPD_TYPE2 (1 << 2)
|
||||
# define GCR_GPD_TYPE3 (1 << 3)
|
||||
# define GCR_GPD_TYPE4 (1 << 4)
|
||||
# define GCR_GPD_TYPE5 (1 << 5)
|
||||
# define GCR_GPD_TYPE6 (1 << 6)
|
||||
# define GCR_GPD_TYPE7 (1 << 7)
|
||||
# define GCR_GPD_TYPE8 (1 << 8)
|
||||
# define GCR_GPD_TYPE9 (1 << 9)
|
||||
# define GCR_GPD_TYPE10 (1 << 10)
|
||||
# define GCR_GPD_TYPE11 (1 << 11)
|
||||
# define GCR_GPD_TYPE12 (1 << 12)
|
||||
# define GCR_GPD_TYPE13 (1 << 13)
|
||||
# define GCR_GPD_TYPE14 (1 << 14)
|
||||
# define GCR_GPD_TYPE15 (1 << 15)
|
||||
|
||||
/* Multiple function pin GPIOE control register */
|
||||
|
||||
#define GCR_GPE_MFP(n) (1 << (n)) /* Bits 0-15: PDn pin function selection */
|
||||
# define GCR_GPE_MFP0 (1 << 0)
|
||||
# define GCR_GPE_MFP1 (1 << 1)
|
||||
# define GCR_GPE_MFP2 (1 << 2)
|
||||
# define GCR_GPE_MFP3 (1 << 3)
|
||||
# define GCR_GPE_MFP4 (1 << 4)
|
||||
# define GCR_GPE_MFP5 (1 << 5)
|
||||
#define GCR_GPE_TYPE(n) (1 << ((n)+16)) /* Bits 16-31: Enable Schmitt trigger function */
|
||||
# define GCR_GPE_TYPE0 (1 << 0)
|
||||
# define GCR_GPE_TYPE1 (1 << 1)
|
||||
# define GCR_GPE_TYPE2 (1 << 2)
|
||||
# define GCR_GPE_TYPE3 (1 << 3)
|
||||
# define GCR_GPE_TYPE4 (1 << 4)
|
||||
# define GCR_GPE_TYPE5 (1 << 5)
|
||||
|
||||
/* Alternative multiple function pin control register */
|
||||
|
||||
#define GCR_ALT_MFP_PB10_S01 (1 << 0) /* Bit 0: Determines PB.10 function */
|
||||
#define GCR_ALT_MFP_PB9_S11 (1 << 1) /* Bit 1: Determines PB.9 function */
|
||||
#define GCR_ALT_MFP_PA7_S21 (1 << 2) /* Bit 2: Determines PA.7 function */
|
||||
#define GCR_ALT_MFP_PB14_S31 (1 << 3) /* Bit 3: Determines PB.14 function */
|
||||
#define GCR_ALT_MFP_PB11_PWM4 (1 << 4) /* Bit 4: Determines PB.11 function */
|
||||
#define GCR_ALT_MFP_PC0_I2SRCLK (1 << 5) /* Bit 5: Determines PC.0 function */
|
||||
#define GCR_ALT_MFP_PC1_I2SBCLK (1 << 6) /* Bit 6: Determines PC.1 function */
|
||||
#define GCR_ALT_MFP_PC2_I2SD1 (1 << 7) /* Bit 7: Determines PC.2 function */
|
||||
#define GCR_ALT_MFP_PC3_I2SD0 (1 << 8) /* Bit 8: Determines PC.3 function */
|
||||
#define GCR_ALT_MFP_PA15_I2SMCLK (1 << 9) /* Bit 9: Determines PA.15 function */
|
||||
#define GCR_ALT_MFP_PB12_CLKO (1 << 10) /* Bit 10: Determines PB.12 function */
|
||||
#define GCR_ALT_MFP_EBI_EN (1 << 11) /* Bit 11: Determines PA.6, PA.7, PA.10, PA.11,
|
||||
* PB.6, PB.7, PB.12, PB.13, PC.6, PC.7, PC.14,
|
||||
* PC.15 function */
|
||||
#define GCR_ALT_MFP_EBI_MCLK_EN (1 << 12) /* Bit 12: Determines PC.8 function */
|
||||
#define GCR_ALT_MFP_EBI_NWRL_EN (1 << 13) /* Bit 13: Determines PB.2 function */
|
||||
#define GCR_ALT_MFP_EBI_NWRH_WN (1 << 14) /* Bit 14: Determines PB.3 function */
|
||||
#define GCR_ALT_MFP_EBI_HB_EN0 (1 << 16) /* Bit 16: Determines PA.5 function */
|
||||
#define GCR_ALT_MFP_EBI_HB_EN1 (1 << 17) /* Bit 17: Determines PA.4 function */
|
||||
#define GCR_ALT_MFP_EBI_HB_EN2 (1 << 18) /* Bit 18: Determines PA.3 function */
|
||||
#define GCR_ALT_MFP_EBI_HB_EN3 (1 << 19) /* Bit 19: Determines PA.2 function */
|
||||
#define GCR_ALT_MFP_EBI_HB_EN4 (1 << 20) /* Bit 20: Determines PA.1 function */
|
||||
#define GCR_ALT_MFP_EBI_HB_EN5 (1 << 21) /* Bit 21: Determines PA.12 function */
|
||||
#define GCR_ALT_MFP_EBI_HB_EN6 (1 << 22) /* Bit 22: Determines PA.13 function */
|
||||
#define GCR_ALT_MFP_EBI_HB_EN7 (1 << 23) /* Bit 23: Determines PA.14 function */
|
||||
|
||||
/* Register write-protection control register */
|
||||
|
||||
/* Write: */
|
||||
#define GCR_REGWRPROT_MASK (0xff) /* Bits 0-7: Register write protection code */
|
||||
# define GCR_REGWRPROT_1 (0x59) /* Disable sequence */
|
||||
# define GCR_REGWRPROT_2 (0x16)
|
||||
# define GCR_REGWRPROT_3 (0x88)
|
||||
/* Read: */
|
||||
#define GCR_REGWRPROT_DIS (1 << 0) /* Bit 0: Register write protectino disable index */
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Data
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Functions
|
||||
********************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KL_CHIP_KL_GCR_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,252 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/kl/kl_llwu.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KL_KL_LLWU_H
|
||||
#define __ARCH_ARM_SRC_KL_KL_LLWU_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define KL_LLWU_PE1_OFFSET 0x0000 /* LLWU Pin Enable 1 Register */
|
||||
#define KL_LLWU_PE2_OFFSET 0x0001 /* LLWU Pin Enable 2 Register */
|
||||
#define KL_LLWU_PE3_OFFSET 0x0002 /* LLWU Pin Enable 3 Register */
|
||||
#define KL_LLWU_PE4_OFFSET 0x0003 /* LLWU Pin Enable 4 Register */
|
||||
#define KL_LLWU_ME_OFFSET 0x0004 /* LLWU Module Enable Register */
|
||||
#define KL_LLWU_F1_OFFSET 0x0005 /* LLWU Flag 1 Register */
|
||||
#define KL_LLWU_F2_OFFSET 0x0006 /* LLWU Flag 2 Register */
|
||||
#define KL_LLWU_F3_OFFSET 0x0007 /* LLWU Flag 3 Register */
|
||||
#define KL_LLWU_CS_OFFSET 0x0008 /* LLWU Control and Status Register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define KL_LLWU_PE1 (KL_LLWU_BASE+KL_LLWU_PE1_OFFSET)
|
||||
#define KL_LLWU_PE2 (KL_LLWU_BASE+KL_LLWU_PE2_OFFSET)
|
||||
#define KL_LLWU_PE3 (KL_LLWU_BASE+KL_LLWU_PE3_OFFSET)
|
||||
#define KL_LLWU_PE4 (KL_LLWU_BASE+KL_LLWU_PE4_OFFSET)
|
||||
#define KL_LLWU_ME (KL_LLWU_BASE+KL_LLWU_ME_OFFSET)
|
||||
#define KL_LLWU_F1 (KL_LLWU_BASE+KL_LLWU_F1_OFFSET)
|
||||
#define KL_LLWU_F2 (KL_LLWU_BASE+KL_LLWU_F2_OFFSET)
|
||||
#define KL_LLWU_F3 (KL_LLWU_BASE+KL_LLWU_F3_OFFSET)
|
||||
#define KL_LLWU_CS (KL_LLWU_BASE+KL_LLWU_CS_OFFSET)
|
||||
|
||||
/* Register Bit Definitions *********************************************************/
|
||||
|
||||
/* LLWU Pin Enable 1 Register */
|
||||
|
||||
#define LLWU_PE1_WUPE0_SHIFT (0) /* Bits 0-1: Wakeup Pin Enable for LLWU_P0 */
|
||||
#define LLWU_PE1_WUPE0_MASK (3 << LLWU_PE1_WUPE0_SHIFT)
|
||||
# define LLWU_PE1_WUPE0_DISABLED (0 << LLWU_PE1_WUPE0_SHIFT) /* Ext input disabled as wakeup input */
|
||||
# define LLWU_PE1_WUPE0_RISING (1 << LLWU_PE1_WUPE0_SHIFT) /* Ext input enabled for rising edge */
|
||||
# define LLWU_PE1_WUPE0_FALLING (2 << LLWU_PE1_WUPE0_SHIFT) /* Ext input enabled for falling edge */
|
||||
# define LLWU_PE1_WUPE0_BOTH (3 << LLWU_PE1_WUPE0_SHIFT) /* Ext input enabled for any change */
|
||||
#define LLWU_PE1_WUPE1_SHIFT (2) /* Bits 2-3: Wakeup Pin Enable for LLWU_P1 */
|
||||
#define LLWU_PE1_WUPE1_MASK (3 << LLWU_PE1_WUPE1_SHIFT)
|
||||
# define LLWU_PE1_WUPE1_DISABLED (0 << LLWU_PE1_WUPE1_SHIFT) /* Ext input disabled as wakeup input */
|
||||
# define LLWU_PE1_WUPE1_RISING (1 << LLWU_PE1_WUPE1_SHIFT) /* Ext input enabled for rising edge */
|
||||
# define LLWU_PE1_WUPE1_FALLING (2 << LLWU_PE1_WUPE1_SHIFT) /* Ext input enabled for falling edge */
|
||||
# define LLWU_PE1_WUPE1_BOTH (3 << LLWU_PE1_WUPE1_SHIFT) /* Ext input enabled for any change */
|
||||
#define LLWU_PE1_WUPE2_SHIFT (4) /* Bits 4-5: Wakeup Pin Enable for LLWU_P2 */
|
||||
#define LLWU_PE1_WUPE2_MASK (3 << LLWU_PE1_WUPE2_SHIFT)
|
||||
# define LLWU_PE1_WUPE2_DISABLED (0 << LLWU_PE1_WUPE2_SHIFT) /* Ext input disabled as wakeup input */
|
||||
# define LLWU_PE1_WUPE2_RISING (1 << LLWU_PE1_WUPE2_SHIFT) /* Ext input enabled for rising edge */
|
||||
# define LLWU_PE1_WUPE2_FALLING (2 << LLWU_PE1_WUPE2_SHIFT) /* Ext input enabled for falling edge */
|
||||
# define LLWU_PE1_WUPE2_BOTH (3 << LLWU_PE1_WUPE2_SHIFT) /* Ext input enabled for any change */
|
||||
#define LLWU_PE1_WUPE3_SHIFT (6) /* Bits 6-7: Wakeup Pin Enable for LLWU_P3 */
|
||||
#define LLWU_PE1_WUPE3_MASK (3 << LLWU_PE1_WUPE3_SHIFT)
|
||||
# define LLWU_PE1_WUPE3_DISABLED (0 << LLWU_PE1_WUPE3_SHIFT) /* Ext input disabled as wakeup input */
|
||||
# define LLWU_PE1_WUPE3_RISING (1 << LLWU_PE1_WUPE3_SHIFT) /* Ext input enabled for rising edge */
|
||||
# define LLWU_PE1_WUPE3_FALLING (2 << LLWU_PE1_WUPE3_SHIFT) /* Ext input enabled for falling edge */
|
||||
# define LLWU_PE1_WUPE3_BOTH (3 << LLWU_PE1_WUPE3_SHIFT) /* Ext input enabled for any change */
|
||||
|
||||
/* LLWU Pin Enable 2 Register */
|
||||
|
||||
#define LLWU_PE2_WUPE4_SHIFT (0) /* Bits 0-1: Wakeup Pin Enable for LLWU_P4 */
|
||||
#define LLWU_PE2_WUPE4_MASK (3 << LLWU_PE2_WUPE4_SHIFT)
|
||||
# define LLWU_PE2_WUPE4_DISABLED (0 << LLWU_PE2_WUPE4_SHIFT) /* Ext input disabled as wakeup input */
|
||||
# define LLWU_PE2_WUPE4_RISING (1 << LLWU_PE2_WUPE4_SHIFT) /* Ext input enabled for rising edge */
|
||||
# define LLWU_PE2_WUPE4_FALLING (2 << LLWU_PE2_WUPE4_SHIFT) /* Ext input enabled for falling edge */
|
||||
# define LLWU_PE2_WUPE4_BOTH (3 << LLWU_PE2_WUPE4_SHIFT) /* Ext input enabled for any change */
|
||||
#define LLWU_PE2_WUPE5_SHIFT (2) /* Bits 2-3: Wakeup Pin Enable for LLWU_P5 */
|
||||
#define LLWU_PE2_WUPE5_MASK (3 << LLWU_PE2_WUPE5_SHIFT)
|
||||
# define LLWU_PE2_WUPE5_DISABLED (0 << LLWU_PE2_WUPE5_SHIFT) /* Ext input disabled as wakeup input */
|
||||
# define LLWU_PE2_WUPE5_RISING (1 << LLWU_PE2_WUPE5_SHIFT) /* Ext input enabled for rising edge */
|
||||
# define LLWU_PE2_WUPE5_FALLING (2 << LLWU_PE2_WUPE5_SHIFT) /* Ext input enabled for falling edge */
|
||||
# define LLWU_PE2_WUPE5_BOTH (3 << LLWU_PE2_WUPE5_SHIFT) /* Ext input enabled for any change */
|
||||
#define LLWU_PE2_WUPE6_SHIFT (4) /* Bits 4-5: Wakeup Pin Enable for LLWU_P6 */
|
||||
#define LLWU_PE2_WUPE6_MASK (3 << LLWU_PE2_WUPE6_SHIFT)
|
||||
# define LLWU_PE2_WUPE6_DISABLED (0 << LLWU_PE2_WUPE6_SHIFT) /* Ext input disabled as wakeup input */
|
||||
# define LLWU_PE2_WUPE6_RISING (1 << LLWU_PE2_WUPE6_SHIFT) /* Ext input enabled for rising edge */
|
||||
# define LLWU_PE2_WUPE6_FALLING (2 << LLWU_PE2_WUPE6_SHIFT) /* Ext input enabled for falling edge */
|
||||
# define LLWU_PE2_WUPE6_BOTH (3 << LLWU_PE2_WUPE6_SHIFT) /* Ext input enabled for any change */
|
||||
#define LLWU_PE2_WUPE7_SHIFT (6) /* Bits 6-7: Wakeup Pin Enable for LLWU_P7 */
|
||||
#define LLWU_PE2_WUPE7_MASK (3 << LLWU_PE2_WUPE7_SHIFT)
|
||||
# define LLWU_PE2_WUPE7_DISABLED (0 << LLWU_PE2_WUPE7_SHIFT) /* Ext input disabled as wakeup input */
|
||||
# define LLWU_PE2_WUPE7_RISING (1 << LLWU_PE2_WUPE7_SHIFT) /* Ext input enabled for rising edge */
|
||||
# define LLWU_PE2_WUPE7_FALLING (2 << LLWU_PE2_WUPE7_SHIFT) /* Ext input enabled for falling edge */
|
||||
# define LLWU_PE2_WUPE7_BOTH (3 << LLWU_PE2_WUPE7_SHIFT) /* Ext input enabled for any change */
|
||||
|
||||
/* LLWU Pin Enable 3 Register */
|
||||
|
||||
#define LLWU_PE3_WUPE8_SHIFT (0) /* Bits 0-1: Wakeup Pin Enable for LLWU_P8 */
|
||||
#define LLWU_PE3_WUPE8_MASK (3 << LLWU_PE3_WUPE8_SHIFT)
|
||||
# define LLWU_PE3_WUPE8_DISABLED (0 << LLWU_PE3_WUPE8_SHIFT) /* Ext input disabled as wakeup input */
|
||||
# define LLWU_PE3_WUPE8_RISING (1 << LLWU_PE3_WUPE8_SHIFT) /* Ext input enabled for rising edge */
|
||||
# define LLWU_PE3_WUPE8_FALLING (2 << LLWU_PE3_WUPE8_SHIFT) /* Ext input enabled for falling edge */
|
||||
# define LLWU_PE3_WUPE8_BOTH (3 << LLWU_PE3_WUPE8_SHIFT) /* Ext input enabled for any change */
|
||||
#define LLWU_PE3_WUPE9_SHIFT (2) /* Bits 2-3: Wakeup Pin Enable for LLWU_P9 */
|
||||
#define LLWU_PE3_WUPE9_MASK (3 << LLWU_PE3_WUPE9_SHIFT)
|
||||
# define LLWU_PE3_WUPE9_DISABLED (0 << LLWU_PE3_WUPE9_SHIFT) /* Ext input disabled as wakeup input */
|
||||
# define LLWU_PE3_WUPE9_RISING (1 << LLWU_PE3_WUPE9_SHIFT) /* Ext input enabled for rising edge */
|
||||
# define LLWU_PE3_WUPE9_FALLING (2 << LLWU_PE3_WUPE9_SHIFT) /* Ext input enabled for falling edge */
|
||||
# define LLWU_PE3_WUPE9_BOTH (3 << LLWU_PE3_WUPE9_SHIFT) /* Ext input enabled for any change */
|
||||
#define LLWU_PE3_WUPE10_SHIFT (4) /* Bits 4-5: Wakeup Pin Enable for LLWU_P10 */
|
||||
#define LLWU_PE3_WUPE10_MASK (3 << LLWU_PE3_WUPE10_SHIFT)
|
||||
# define LLWU_PE3_WUPE10_DISABLED (0 << LLWU_PE3_WUPE10_SHIFT) /* Ext input disabled as wakeup input */
|
||||
# define LLWU_PE3_WUPE10_RISING (1 << LLWU_PE3_WUPE10_SHIFT) /* Ext input enabled for rising edge */
|
||||
# define LLWU_PE3_WUPE10_FALLING (2 << LLWU_PE3_WUPE10_SHIFT) /* Ext input enabled for falling edge */
|
||||
# define LLWU_PE3_WUPE10_BOTH (3 << LLWU_PE3_WUPE10_SHIFT) /* Ext input enabled for any change */
|
||||
#define LLWU_PE3_WUPE11_SHIFT (6) /* Bits 6-7: Wakeup Pin Enable for LLWU_P11 */
|
||||
#define LLWU_PE3_WUPE11_MASK (3 << LLWU_PE3_WUPE11_SHIFT)
|
||||
# define LLWU_PE3_WUPE11_DISABLED (0 << LLWU_PE3_WUPE11_SHIFT) /* Ext input disabled as wakeup input */
|
||||
# define LLWU_PE3_WUPE11_RISING (1 << LLWU_PE3_WUPE11_SHIFT) /* Ext input enabled for rising edge */
|
||||
# define LLWU_PE3_WUPE11_FALLING (2 << LLWU_PE3_WUPE11_SHIFT) /* Ext input enabled for falling edge */
|
||||
# define LLWU_PE3_WUPE11_BOTH (3 << LLWU_PE3_WUPE11_SHIFT) /* Ext input enabled for any change */
|
||||
|
||||
/* LLWU Pin Enable 4 Register */
|
||||
|
||||
#define LLWU_PE4_WUPE12_SHIFT (0) /* Bits 0-1: Wakeup Pin Enable for LLWU_P12 */
|
||||
#define LLWU_PE4_WUPE12_MASK (3 << LLWU_PE4_WUPE12_SHIFT)
|
||||
# define LLWU_PE4_WUPE12_DISABLED (0 << LLWU_PE4_WUPE12_SHIFT) /* Ext input disabled as wakeup input */
|
||||
# define LLWU_PE4_WUPE12_RISING (1 << LLWU_PE4_WUPE12_SHIFT) /* Ext input enabled for rising edge */
|
||||
# define LLWU_PE4_WUPE12_FALLING (2 << LLWU_PE4_WUPE12_SHIFT) /* Ext input enabled for falling edge */
|
||||
# define LLWU_PE4_WUPE12_BOTH (3 << LLWU_PE4_WUPE12_SHIFT) /* Ext input enabled for any change */
|
||||
#define LLWU_PE4_WUPE13_SHIFT (2) /* Bits 2-3: Wakeup Pin Enable for LLWU_P13 */
|
||||
#define LLWU_PE4_WUPE13_MASK (3 << LLWU_PE4_WUPE13_SHIFT)
|
||||
# define LLWU_PE4_WUPE13_DISABLED (0 << LLWU_PE4_WUPE13_SHIFT) /* Ext input disabled as wakeup input */
|
||||
# define LLWU_PE4_WUPE13_RISING (1 << LLWU_PE4_WUPE13_SHIFT) /* Ext input enabled for rising edge */
|
||||
# define LLWU_PE4_WUPE13_FALLING (2 << LLWU_PE4_WUPE13_SHIFT) /* Ext input enabled for falling edge */
|
||||
# define LLWU_PE4_WUPE13_BOTH (3 << LLWU_PE4_WUPE13_SHIFT) /* Ext input enabled for any change */
|
||||
#define LLWU_PE4_WUPE14_SHIFT (4) /* Bits 4-5: Wakeup Pin Enable for LLWU_P14 */
|
||||
#define LLWU_PE4_WUPE14_MASK (3 << LLWU_PE4_WUPE14_SHIFT)
|
||||
# define LLWU_PE4_WUPE14_DISABLED (0 << LLWU_PE4_WUPE14_SHIFT) /* Ext input disabled as wakeup input */
|
||||
# define LLWU_PE4_WUPE14_RISING (1 << LLWU_PE4_WUPE14_SHIFT) /* Ext input enabled for rising edge */
|
||||
# define LLWU_PE4_WUPE14_FALLING (2 << LLWU_PE4_WUPE14_SHIFT) /* Ext input enabled for falling edge */
|
||||
# define LLWU_PE4_WUPE14_BOTH (3 << LLWU_PE4_WUPE14_SHIFT) /* Ext input enabled for any change */
|
||||
#define LLWU_PE4_WUPE15_SHIFT (6) /* Bits 6-7: Wakeup Pin Enable for LLWU_P15 */
|
||||
#define LLWU_PE4_WUPE15_MASK (3 << LLWU_PE4_WUPE15_SHIFT)
|
||||
# define LLWU_PE4_WUPE15_DISABLED (0 << LLWU_PE4_WUPE15_SHIFT) /* Ext input disabled as wakeup input */
|
||||
# define LLWU_PE4_WUPE15_RISING (1 << LLWU_PE4_WUPE15_SHIFT) /* Ext input enabled for rising edge */
|
||||
# define LLWU_PE4_WUPE15_FALLING (2 << LLWU_PE4_WUPE15_SHIFT) /* Ext input enabled for falling edge */
|
||||
# define LLWU_PE4_WUPE15_BOTH (3 << LLWU_PE4_WUPE15_SHIFT) /* Ext input enabled for any change */
|
||||
|
||||
/* LLWU Module Enable Register */
|
||||
|
||||
#define LLWU_ME_WUME(n) (1 << (n))
|
||||
#define LLWU_ME_WUME0 (1 << 0) /* Bit 0: Wakeup Module Enable for Module 0 */
|
||||
#define LLWU_ME_WUME1 (1 << 1) /* Bit 1: Wakeup Module Enable for Module 1 */
|
||||
#define LLWU_ME_WUME2 (1 << 2) /* Bit 2: Wakeup Module Enable for Module 2 */
|
||||
#define LLWU_ME_WUME3 (1 << 3) /* Bit 3: Wakeup Module Enable for Module 3 */
|
||||
#define LLWU_ME_WUME4 (1 << 4) /* Bit 4: Wakeup Module Enable for Module 4 */
|
||||
#define LLWU_ME_WUME5 (1 << 5) /* Bit 5: Wakeup Module Enable for Module 5 */
|
||||
#define LLWU_ME_WUME6 (1 << 6) /* Bit 6: Wakeup Module Enable for Module 6 */
|
||||
#define LLWU_ME_WUME7 (1 << 7) /* Bit 7: Wakeup Module Enable for Module 7 */
|
||||
|
||||
/* LLWU Flag 1 Register */
|
||||
|
||||
#define LLWU_F1_WUF(n) (1 << (n))
|
||||
#define LLWU_F1_WUF0 (1 << 0) /* Bit 0: Wakeup Flag for LLWU_P0 */
|
||||
#define LLWU_F1_WUF1 (1 << 1) /* Bit 1: Wakeup Flag for LLWU_P1 */
|
||||
#define LLWU_F1_WUF2 (1 << 2) /* Bit 2: Wakeup Flag for LLWU_P2 */
|
||||
#define LLWU_F1_WUF3 (1 << 3) /* Bit 3: Wakeup Flag for LLWU_P3 */
|
||||
#define LLWU_F1_WUF4 (1 << 4) /* Bit 4: Wakeup Flag for LLWU_P4 */
|
||||
#define LLWU_F1_WUF5 (1 << 5) /* Bit 5: Wakeup Flag for LLWU_P5 */
|
||||
#define LLWU_F1_WUF6 (1 << 6) /* Bit 6: Wakeup Flag for LLWU_P6 */
|
||||
#define LLWU_F1_WUF7 (1 << 7) /* Bit 7: Wakeup Flag for LLWU_P7 */
|
||||
|
||||
/* LLWU Flag 2 Register */
|
||||
|
||||
#define LLWU_F2_WUF(n) (1 << ((n)-8))
|
||||
#define LLWU_F2_WUF8 (1 << 8) /* Bit 0: Wakeup Flag for LLWU_P8 */
|
||||
#define LLWU_F2_WUF9 (1 << 9) /* Bit 1: Wakeup Flag for LLWU_P9 */
|
||||
#define LLWU_F2_WUF10 (1 << 10) /* Bit 2: Wakeup Flag for LLWU_P10 */
|
||||
#define LLWU_F2_WUF11 (1 << 11) /* Bit 3: Wakeup Flag for LLWU_P11 */
|
||||
#define LLWU_F2_WUF12 (1 << 12) /* Bit 4: Wakeup Flag for LLWU_P12 */
|
||||
#define LLWU_F2_WUF13 (1 << 13) /* Bit 5: Wakeup Flag for LLWU_P13 */
|
||||
#define LLWU_F2_WUF14 (1 << 14) /* Bit 6: Wakeup Flag for LLWU_P14 */
|
||||
#define LLWU_F2_WUF15 (1 << 15) /* Bit 7: Wakeup Flag for LLWU_P15 */
|
||||
|
||||
/* LLWU Flag 3 Register */
|
||||
|
||||
#define LLWU_F3_MWUF(n) (1 << (n))
|
||||
#define LLWU_F3_MWUF0 (1 << 0) /* Bit 0: Wakeup flag for module 0 */
|
||||
#define LLWU_F3_MWUF1 (1 << 1) /* Bit 1: Wakeup flag for module 1 */
|
||||
#define LLWU_F3_MWUF2 (1 << 2) /* Bit 2: Wakeup flag for module 2 */
|
||||
#define LLWU_F3_MWUF3 (1 << 3) /* Bit 3: Wakeup flag for module 3 */
|
||||
#define LLWU_F3_MWUF4 (1 << 4) /* Bit 4: Wakeup flag for module 4 */
|
||||
#define LLWU_F3_MWUF5 (1 << 5) /* Bit 5: Wakeup flag for module 5 */
|
||||
#define LLWU_F3_MWUF6 (1 << 6) /* Bit 6: Wakeup flag for module 6 */
|
||||
#define LLWU_F3_MWUF7 (1 << 7) /* Bit 7: Wakeup flag for module 7 */
|
||||
|
||||
/* LLWU Control and Status Register */
|
||||
|
||||
#define LLWU_CS_ACKISO (1 << 7) /* Bit 7: Acknowledge Isolation */
|
||||
/* Bits 2-6: Reserved */
|
||||
#define LLWU_CS_FLTEP (1 << 1) /* Bit 1: Digital Filter on External Pin */
|
||||
#define LLWU_CS_FLTR (1 << 0) /* Bit 0: Digital Filter on RESET Pin */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KL_KL_LLWU_H */
|
||||
@@ -0,0 +1,186 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/kl/kl_mcg.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KL_KL_MCG_H
|
||||
#define __ARCH_ARM_SRC_KL_KL_MCG_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define KL_MCG_C1_OFFSET 0x0000 /* MCG Control 1 Register */
|
||||
#define KL_MCG_C2_OFFSET 0x0001 /* MCG Control 2 Register */
|
||||
#define KL_MCG_C3_OFFSET 0x0002 /* MCG Control 3 Register */
|
||||
#define KL_MCG_C4_OFFSET 0x0003 /* MCG Control 4 Register */
|
||||
#define KL_MCG_C5_OFFSET 0x0004 /* MCG Control 5 Register */
|
||||
#define KL_MCG_C6_OFFSET 0x0005 /* MCG Control 6 Register */
|
||||
#define KL_MCG_S_OFFSET 0x0006 /* MCG Status Register */
|
||||
#define KL_MCG_ATC_OFFSET 0x0008 /* MCG Auto Trim Control Register */
|
||||
#define KL_MCG_ATCVH_OFFSET 0x000a /* MCG Auto Trim Compare Value High Register */
|
||||
#define KL_MCG_ATCVL_OFFSET 0x000b /* MCG Auto Trim Compare Value Low Register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define KL_MCG_C1 (KL_MCG_BASE+KL_MCG_C1_OFFSET)
|
||||
#define KL_MCG_C2 (KL_MCG_BASE+KL_MCG_C2_OFFSET)
|
||||
#define KL_MCG_C3 (KL_MCG_BASE+KL_MCG_C3_OFFSET)
|
||||
#define KL_MCG_C4 (KL_MCG_BASE+KL_MCG_C4_OFFSET)
|
||||
#define KL_MCG_C5 (KL_MCG_BASE+KL_MCG_C5_OFFSET)
|
||||
#define KL_MCG_C6 (KL_MCG_BASE+KL_MCG_C6_OFFSET)
|
||||
#define KL_MCG_S (KL_MCG_BASE+KL_MCG_S_OFFSET)
|
||||
#define KL_MCG_ATC (KL_MCG_BASE+KL_MCG_ATC_OFFSET)
|
||||
#define KL_MCG_ATCVH (KL_MCG_BASE+KL_MCG_ATCVH_OFFSET)
|
||||
#define KL_MCG_ATCVL (KL_MCG_BASE+KL_MCG_ATCVL_OFFSET)
|
||||
|
||||
/* Register Bit Definitions *********************************************************/
|
||||
|
||||
/* MCG Control 1 Register (8-bit) */
|
||||
|
||||
#define MCG_C1_IREFSTEN (1 << 0) /* Bit 0: Internal Reference Stop Enable */
|
||||
#define MCG_C1_IRCLKEN (1 << 1) /* Bit 1: Internal Reference Clock Enable */
|
||||
#define MCG_C1_IREFS (1 << 2) /* Bit 2: Internal Reference Select */
|
||||
#define MCG_C1_FRDIV_SHIFT (3) /* Bits 3-5: FLL External Reference Divider */
|
||||
#define MCG_C1_FRDIV_MASK (7 << MCG_C1_FRDIV_SHIFT)
|
||||
# define MCG_C1_FRDIV_R0DIV1 (0 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=1 */
|
||||
# define MCG_C1_FRDIV_R0DIV2 (1 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=2 */
|
||||
# define MCG_C1_FRDIV_R0DIV4 (2 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=4 */
|
||||
# define MCG_C1_FRDIV_R0DIV8 (3 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=8 */
|
||||
# define MCG_C1_FRDIV_R0DIV16 (4 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=16 */
|
||||
# define MCG_C1_FRDIV_R0DIV32 (5 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=32 */
|
||||
# define MCG_C1_FRDIV_R0DIV64 (6 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=64 */
|
||||
# define MCG_C1_FRDIV_R0DIV128 (7 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=128 */
|
||||
# define MCG_C1_FRDIV_DIV32 (0 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=32 */
|
||||
# define MCG_C1_FRDIV_DIV64 (1 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=64 */
|
||||
# define MCG_C1_FRDIV_DIV128 (2 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=128 */
|
||||
# define MCG_C1_FRDIV_DIV256 (3 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=256 */
|
||||
# define MCG_C1_FRDIV_DIV512 (4 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=512 */
|
||||
# define MCG_C1_FRDIV_DIV1024 (5 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=1024 */
|
||||
#define MCG_C1_CLKS_SHIFT (6) /* Bits 6-7: Clock Source Select */
|
||||
#define MCG_C1_CLKS_MASK (3 << MCG_C1_CLKS_SHIFT)
|
||||
# define MCG_C1_CLKS_PLL (0 << MCG_C1_CLKS_SHIFT) /* FLL or PLL output */
|
||||
# define MCG_C1_CLKS_INTREF (1 << MCG_C1_CLKS_SHIFT) /* Internal reference clock */
|
||||
# define MCG_C1_CLKS_EXTREF (2 << MCG_C1_CLKS_SHIFT) /* External reference clock */
|
||||
|
||||
/* MCG Control 2 Register */
|
||||
|
||||
#define MCG_C2_IRCS (1 << 0) /* Bit 0: Internal Reference Clock Select */
|
||||
#define MCG_C2_LP (1 << 1) /* Bit 1: Low Power Select */
|
||||
#define MCG_C2_EREFS (1 << 2) /* Bit 2: External Reference Select */
|
||||
#define MCG_C2_HGO (1 << 3) /* Bit 3: High Gain Oscillator Select */
|
||||
#define MCG_C2_RANGE_SHIFT (4) /* Bits 4-5: Frequency Range Select */
|
||||
#define MCG_C2_RANGE_MASK (3 << MCG_C2_RANGE_SHIFT)
|
||||
# define MCG_C2_RANGE_LOW (0 << MCG_C2_RANGE_SHIFT) /* Oscillator of 32 kHz to 40 kHz */
|
||||
# define MCG_C2_RANGE_HIGH (1 << MCG_C2_RANGE_SHIFT) /* Oscillator of 1 MHz to 8 MHz */
|
||||
# define MCG_C2_RANGE_VHIGH (2 << MCG_C2_RANGE_SHIFT) /* Oscillator of 8 MHz to 32 MHz */
|
||||
/* Bits 6-7: Reserved */
|
||||
/* MCG Control 3 Register (8-bit Slow Internal Reference Clock Trim Setting) */
|
||||
|
||||
/* MCG Control 4 Register (8-bit) */
|
||||
|
||||
#define MCG_C4_SCFTRIM (1 << 0) /* Bit 0: Slow Internal Reference Clock Fine Trim */
|
||||
#define MCG_C4_FCTRIM_SHIFT (1) /* Bits 1-4: Fast Internal Reference Clock Trim Setting */
|
||||
#define MCG_C4_FCTRIM_MASK (15 << MCG_C4_FCTRIM_SHIFT)
|
||||
#define MCG_C4_DRST_DRS_SHIFT (5) /* Bits 5-6: DCO Range Select */
|
||||
#define MCG_C4_DRST_DRS_MASK (3 << MCG_C4_DRST_DRS_SHIFT)
|
||||
# define MCG_C4_DRST_DRS_LOW (0 << MCG_C4_DRST_DRS_SHIFT)
|
||||
# define MCG_C4_DRST_DRS_MID (1 << MCG_C4_DRST_DRS_SHIFT)
|
||||
# define MCG_C4_DRST_DRS_MIDHIGH (2 << MCG_C4_DRST_DRS_SHIFT)
|
||||
# define MCG_C4_DRST_DRS_HIGH (3 << MCG_C4_DRST_DRS_SHIFT)
|
||||
#define MCG_C4_DMX32 (1 << 7) /* Bit 7: DCO Maximum Frequency with 32.768 kHz Reference */
|
||||
|
||||
/* MCG Control 5 Register */
|
||||
|
||||
#define MCG_C5_PRDIV_SHIFT (0) /* Bits 0-4: PLL External Reference Divider */
|
||||
#define MCG_C5_PRDIV_MASK (31 << MCG_C5_PRDIV_SHIFT)
|
||||
# define MCG_C5_PRDIV(n) (n << MCG_C5_PRDIV_SHIFT) /* Divide factor n=1..25 */
|
||||
#define MCG_C5_PLLSTEN (1 << 5) /* Bit 5: PLL Stop Enable */
|
||||
#define MCG_C5_PLLCLKEN (1 << 6) /* Bit 6: PLL Clock Enable */
|
||||
/* Bit 7: Reserved */
|
||||
|
||||
/* MCG Control 6 Register */
|
||||
|
||||
#define MCG_C6_VDIV_SHIFT (0) /* Bits 0-4: VCO Divider */
|
||||
#define MCG_C6_VDIV_MASK (31 << MCG_C6_VDIV_SHIFT)
|
||||
# define MCG_C6_VDIV(n) (((n)-24) << MCG_C6_VDIV_SHIFT) /* Divide factor n=24..55 */
|
||||
#define MCG_C6_CME (1 << 5) /* Bit 5: Clock Monitor Enable */
|
||||
#define MCG_C6_PLLS (1 << 6) /* Bit 6: PLL Select */
|
||||
#define MCG_C6_LOLIE (1 << 7) /* Bit 7: Loss of Lock Interrrupt Enable */
|
||||
|
||||
/* MCG Status Register */
|
||||
|
||||
#define MCG_S_IRCST (1 << 0) /* Bit 0: Internal Reference Clock Status */
|
||||
#define MCG_S_OSCINIT (1 << 1) /* Bit 1: OSC Initialization */
|
||||
#define MCG_S_CLKST_SHIFT (2) /* Bits 2-3: Clock Mode Status */
|
||||
#define MCG_S_CLKST_MASK (3 << MCG_S_CLKST_SHIFT)
|
||||
# define MCG_S_CLKST_FLL (0 << MCG_S_CLKST_SHIFT) /* Output of the FLL */
|
||||
# define MCG_S_CLKST_INTREF (1 << MCG_S_CLKST_SHIFT) /* Internal reference clock */
|
||||
# define MCG_S_CLKST_EXTREF (2 << MCG_S_CLKST_SHIFT) /* External reference clock */
|
||||
# define MCG_S_CLKST_PLL (3 << MCG_S_CLKST_SHIFT) /* Output of the PLL */
|
||||
#define MCG_S_IREFST (1 << 4) /* Bit 4: Internal Reference Status */
|
||||
#define MCG_S_PLLST (1 << 5) /* Bit 5: PLL Select Status */
|
||||
#define MCG_S_LOCK (1 << 6) /* Bit 6: Lock Status */
|
||||
#define MCG_S_LOLS (1 << 7) /* Bit 7: Loss of Lock Status */
|
||||
|
||||
/* MCG Auto Trim Control Register */
|
||||
/* Bits 0-4: Reserved */
|
||||
#define MCG_ATC_ATMF (1 << 5) /* Bit 5: Automatic Trim machine Fail Flag */
|
||||
#define MCG_ATC_ATMS (1 << 6) /* Bit 6: Automatic Trim Machine Select */
|
||||
#define MCG_ATC_ATME (1 << 7) /* Bit 7: Automatic Trim Machine Enable */
|
||||
|
||||
/* MCG Auto Trim Compare Value High/Low Registers (8-bit compare value) */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KL_KL_MCG_H */
|
||||
@@ -0,0 +1,196 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/kl/kl_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KL_KL_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_KL_KL_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* from NUC memmap */
|
||||
#define KL_GPIO_BASEOLD 0x50004000 /* -0x50007fff: GPIO control registers */
|
||||
#define KL_GCR_BASE 0x50000000 /* -0x500001ff: System global control registers */
|
||||
|
||||
/* Memory Map ***********************************************************************/
|
||||
/* K40 Family
|
||||
*
|
||||
* The memory map for the following parts is defined in Freescale document
|
||||
* K40P144M100SF2RM
|
||||
*/
|
||||
|
||||
# define KL_FLASH_BASE 0x00000000 /* –0x0fffffff Program flash and read-
|
||||
* only data (Includes exception
|
||||
* vectors in first 1024 bytes) */
|
||||
# define KL_SRAML_BASE 0x18000000 /* –0x1fffffff SRAM_L: Lower SRAM
|
||||
* (ICODE/DCODE) */
|
||||
# define KL_SRAMU_BASE 0x20000000 /* –0x200fffff SRAM_U: Upper SRAM bitband
|
||||
* region */
|
||||
/* 0x20100000 * –0x21ffffff Reserved */
|
||||
# define KL_SALIAS_BASE 0x22000000 /* –0x23ffffff Aliased to SRAM_U bitband */
|
||||
/* 0x24000000 * –0x3fffffff Reserved */
|
||||
# define KL_BRIDGE0_BASE 0x40000000 /* –0x4007ffff Bitband region for peripheral
|
||||
* bridge 0 (AIPS-Lite0) */
|
||||
# define KL_BRIDGE1_BASE 0x40080000 /* –0x400fffff Bitband region for peripheral
|
||||
* bridge 1 (AIPS-Lite1) */
|
||||
# define KL_GPIOBB_BASE 0x400ff000 /* –0x400fffff Bitband region for general
|
||||
* purpose input/output (GPIO) */
|
||||
/* 0x40100000 * –0x41ffffff Reserved */
|
||||
# define KL_PALIAS_BASE 0x42000000 /* –0x43ffffff Aliased to peripheral bridge
|
||||
* (AIPS-Lite) and general purpose
|
||||
* input/output (GPIO) bitband */
|
||||
/* 0x44000000 * –0x5fffffff Reserved */
|
||||
# define KL_FLEXBUS_WBBASE 0x60000000 /* –0x7fffffff FlexBus (External Memory -
|
||||
* Write-back) */
|
||||
# define KL_FLEXBUS_WTBASE 0x80000000 /* –0x9fffffff FlexBus (External Memory -
|
||||
* Write-through) */
|
||||
# define KL_FLEXBUS_NXBASE 0xa0000000 /* –0xdfffffff FlexBus (External Memory -
|
||||
* Non-executable) */
|
||||
# define KL_PERIPH_BASE 0xe0000000 /* –0xe00fffff Private peripherals */
|
||||
/* 0xe0100000 * –0xffffffff Reserved */
|
||||
|
||||
/* Peripheral Bridge 0 Memory Map ***************************************************/
|
||||
|
||||
# define KL_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
|
||||
# define KL_XBAR_BASE 0x40004000 /* Crossbar switch */
|
||||
# define KL_DMAC_BASE 0x40008000 /* DMA controller */
|
||||
# define KL_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
|
||||
# define KL_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
|
||||
# define KL_MPU_BASE 0x4000d000 /* MPU */
|
||||
# define KL_FMC_BASE 0x4001f000 /* Flash memory controller */
|
||||
# define KL_FTFL_BASE 0x40020000 /* Flash memory */
|
||||
# define KL_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */
|
||||
# define KL_CAN0_BASE 0x40024000 /* FlexCAN 0 */
|
||||
# define KL_SPI0_BASE 0x4002c000 /* SPI 0 */
|
||||
# define KL_SPI1_BASE 0x4002d000 /* SPI 1 */
|
||||
# define KL_I2S0_BASE 0x4002f000 /* I2S 0 */
|
||||
# define KL_CRC_BASE 0x40032000 /* CRC */
|
||||
# define KL_USBDCD_BASE 0x40035000 /* USB DCD */
|
||||
# define KL_PDB0_BASE 0x40036000 /* Programmable delay block */
|
||||
# define KL_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
|
||||
# define KL_FTM0_BASE 0x40038000 /* FlexTimer 0 */
|
||||
# define KL_FTM1_BASE 0x40039000 /* FlexTimer 1 */
|
||||
# define KL_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
|
||||
# define KL_RTC_BASE 0x4003d000 /* Real time clock */
|
||||
# define KL_VBATR_BASE 0x4003e000 /* VBAT register file */
|
||||
# define KL_LPTMR_BASE 0x40040000 /* Low power timer */
|
||||
# define KL_SYSR_BASE 0x40041000 /* System register file */
|
||||
# define KL_DRYICE_BASE 0x40042000 /* DryIce */
|
||||
# define KL_DRYICESS_BASE 0x40043000 /* DryIce secure storage */
|
||||
# define KL_TSI0_BASE 0x40045000 /* Touch sense interface */
|
||||
# define KL_SIMLP_BASE 0x40047000 /* SIM low-power logic */
|
||||
# define KL_SIM_BASE 0x40048000 /* System integration module (SIM) */
|
||||
# define KL_PORT_BASE(n) (0x40049000 + ((n) << 12))
|
||||
# define KL_PORTA_BASE 0x40049000 /* Port A multiplexing control */
|
||||
# define KL_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
|
||||
# define KL_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
|
||||
# define KL_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
|
||||
# define KL_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
|
||||
# define KL_WDOG_BASE 0x40052000 /* Software watchdog */
|
||||
# define KL_EWM_BASE 0x40061000 /* External watchdog */
|
||||
# define KL_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
|
||||
# define KL_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
|
||||
# define KL_OSC_BASE 0x40065000 /* System oscillator (OSC) */
|
||||
# define KL_I2C0_BASE 0x40066000 /* I2C 0 */
|
||||
# define KL_I2C1_BASE 0x40067000 /* I2C 1 */
|
||||
# define KL_UART0_BASE 0x4006a000 /* UART0 */
|
||||
# define KL_UART1_BASE 0x4006b000 /* UART1 */
|
||||
# define KL_UART2_BASE 0x4006c000 /* UART2 */
|
||||
# define KL_UART3_BASE 0x4006d000 /* UART3 */
|
||||
# define KL_USB0_BASE 0x40072000 /* USB OTG FS/LS */
|
||||
# define KL_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
|
||||
# define KL_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
|
||||
# define KL_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
|
||||
# define KL_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
|
||||
# define KL_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
|
||||
|
||||
/* Peripheral Bridge 1 Memory Map ***************************************************/
|
||||
|
||||
# define KL_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
|
||||
# define KL_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
|
||||
# define KL_SPI2_BASE 0x400ac000 /* SPI 2 */
|
||||
# define KL_SDHC_BASE 0x400b1000 /* SDHC */
|
||||
# define KL_FTM2_BASE 0x400b8000 /* FlexTimer 2 */
|
||||
# define KL_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
|
||||
# define KL_SLCD_BASE 0x400be000 /* Segment LCD */
|
||||
# define KL_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
|
||||
# define KL_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
|
||||
# define KL_UART4_BASE 0x400ea000 /* UART4 */
|
||||
# define KL_UART5_BASE 0x400eb000 /* UART5 */
|
||||
# define KL_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
|
||||
* purpose input/output module that shares the
|
||||
* crossbar switch slave port with the AIPS-Lite
|
||||
* is accessed at this address. */
|
||||
# define KL_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
|
||||
# define KL_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
|
||||
# define KL_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
|
||||
# define KL_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
|
||||
# define KL_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
|
||||
# define KL_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
|
||||
|
||||
/* Private Peripheral Bus (PPB) Memory Map ******************************************/
|
||||
|
||||
# define KL_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
|
||||
# define KL_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
|
||||
# define KL_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
|
||||
# define KL_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
|
||||
# define KL_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
|
||||
# define KL_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
|
||||
# define KL_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
|
||||
# define KL_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
|
||||
# define KL_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
|
||||
# define KL_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KL_KL_MEMORYMAP_H */
|
||||
@@ -0,0 +1,84 @@
|
||||
/********************************************************************************************
|
||||
* arch/arm/src/kl/kl_osc.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KL_KL_OSC_H
|
||||
#define __ARCH_ARM_SRC_KL_KL_OSC_H
|
||||
|
||||
/********************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
********************************************************************************************/
|
||||
|
||||
/* Register Offsets *************************************************************************/
|
||||
|
||||
#define KL_OSC_CR_OFFSET 0x0000 /* OSC Control Register */
|
||||
|
||||
/* Register Addresses ***********************************************************************/
|
||||
|
||||
#define KL_OSC_CR (KL_OSC_BASE+KL_OSC_CR_OFFSET)
|
||||
|
||||
/* Register Bit Definitions *****************************************************************/
|
||||
|
||||
/* OSC Control Register (8-bit) */
|
||||
|
||||
#define OSC_CR_ERCLKEN (1 << 7) /* Bit 7: External Reference Enable */
|
||||
/* Bit 6: Reserved */
|
||||
#define OSC_CR_EREFSTEN (1 << 5) /* Bit 5: External Reference Stop Enable */
|
||||
/* Bit 4: Reserved */
|
||||
#define OSC_CR_SC2P (1 << 3) /* Bit 3: Oscillator 2 pF Capacitor Load Configure */
|
||||
#define OSC_CR_SC4P (1 << 2) /* Bit 2: Oscillator 4 pF Capacitor Load Configure */
|
||||
#define OSC_CR_SC8P (1 << 1) /* Bit 1: Oscillator 8 pF Capacitor Load Configure */
|
||||
#define OSC_CR_SC16P (1 << 0) /* Bit 0: Oscillator 16 pF Capacitor Load Configure */
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Data
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Functions
|
||||
********************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KL_KL_OSC_H */
|
||||
@@ -0,0 +1,69 @@
|
||||
/********************************************************************************************
|
||||
* arch/arm/src/kl/kl_pinmux.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KL_KL_PINMUX_H
|
||||
#define __ARCH_ARM_SRC_KL_KL_PINMUX_H
|
||||
|
||||
/********************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/* This file is just a wrapper around pin muxing header files for the Kinetis family selected
|
||||
* by the logic in chip.h.
|
||||
*/
|
||||
|
||||
#include "k25z120_pinmux.h"
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Data
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Functions
|
||||
********************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KL_KL_PINMUX_H */
|
||||
@@ -0,0 +1,431 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/kl/kl_port.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KL_KL_PORT_H
|
||||
#define __ARCH_ARM_SRC_KL_KL_PORT_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* General Definitions **************************************************************/
|
||||
|
||||
#define KL_PORTA (0)
|
||||
#define KL_PORTB (1)
|
||||
#define KL_PORTC (2)
|
||||
#define KL_PORTD (3)
|
||||
#define KL_PORTE (4)
|
||||
#define KL_NPORTS (5)
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define KL_PORT_PCR_OFFSET(n) ((n) << 2) /* Pin Control Register n, n=0..31 */
|
||||
#define KL_PORT_PCR0_OFFSET 0x0000 /* Pin Control Register 0 */
|
||||
#define KL_PORT_PCR1_OFFSET 0x0004 /* Pin Control Register 1 */
|
||||
#define KL_PORT_PCR2_OFFSET 0x0008 /* Pin Control Register 2 */
|
||||
#define KL_PORT_PCR3_OFFSET 0x000C /* Pin Control Register 3 */
|
||||
#define KL_PORT_PCR4_OFFSET 0x0010 /* Pin Control Register 4 */
|
||||
#define KL_PORT_PCR5_OFFSET 0x0014 /* Pin Control Register 5 */
|
||||
#define KL_PORT_PCR6_OFFSET 0x0018 /* Pin Control Register 6 */
|
||||
#define KL_PORT_PCR7_OFFSET 0x001c /* Pin Control Register 7 */
|
||||
#define KL_PORT_PCR8_OFFSET 0x0020 /* Pin Control Register 8 */
|
||||
#define KL_PORT_PCR9_OFFSET 0x0024 /* Pin Control Register 9 */
|
||||
#define KL_PORT_PCR10_OFFSET 0x0028 /* Pin Control Register 10 */
|
||||
#define KL_PORT_PCR11_OFFSET 0x002c /* Pin Control Register 11 */
|
||||
#define KL_PORT_PCR12_OFFSET 0x0030 /* Pin Control Register 12 */
|
||||
#define KL_PORT_PCR13_OFFSET 0x0034 /* Pin Control Register 13 */
|
||||
#define KL_PORT_PCR14_OFFSET 0x0038 /* Pin Control Register 14 */
|
||||
#define KL_PORT_PCR15_OFFSET 0x003c /* Pin Control Register 15 */
|
||||
#define KL_PORT_PCR16_OFFSET 0x0040 /* Pin Control Register 16 */
|
||||
#define KL_PORT_PCR17_OFFSET 0x0044 /* Pin Control Register 17 */
|
||||
#define KL_PORT_PCR18_OFFSET 0x0048 /* Pin Control Register 18 */
|
||||
#define KL_PORT_PCR19_OFFSET 0x004c /* Pin Control Register 19 */
|
||||
#define KL_PORT_PCR20_OFFSET 0x0050 /* Pin Control Register 20 */
|
||||
#define KL_PORT_PCR21_OFFSET 0x0054 /* Pin Control Register 21 */
|
||||
#define KL_PORT_PCR22_OFFSET 0x0058 /* Pin Control Register 22 */
|
||||
#define KL_PORT_PCR23_OFFSET 0x005c /* Pin Control Register 23 */
|
||||
#define KL_PORT_PCR24_OFFSET 0x0060 /* Pin Control Register 24 */
|
||||
#define KL_PORT_PCR25_OFFSET 0x0064 /* Pin Control Register 25 */
|
||||
#define KL_PORT_PCR26_OFFSET 0x0068 /* Pin Control Register 26 */
|
||||
#define KL_PORT_PCR27_OFFSET 0x006c /* Pin Control Register 27 */
|
||||
#define KL_PORT_PCR28_OFFSET 0x0070 /* Pin Control Register 28 */
|
||||
#define KL_PORT_PCR29_OFFSET 0x0074 /* Pin Control Register 29 */
|
||||
#define KL_PORT_PCR30_OFFSET 0x0078 /* Pin Control Register 30 */
|
||||
#define KL_PORT_PCR31_OFFSET 0x007c /* Pin Control Register 31 */
|
||||
#define KL_PORT_GPCLR_OFFSET 0x0080 /* Global Pin Control Low Register */
|
||||
#define KL_PORT_GPCHR_OFFSET 0x0084 /* Global Pin Control High Register */
|
||||
#define KL_PORT_ISFR_OFFSET 0x00a0 /* Interrupt Status Flag Register */
|
||||
#define KL_PORT_DFER_OFFSET 0x00c0 /* Digital Filter Enable Register */
|
||||
#define KL_PORT_DFCR_OFFSET 0x00c4 /* Digital Filter Clock Register */
|
||||
#define KL_PORT_DFWR_OFFSET 0x00c8 /* Digital Filter Width Register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define KL_PORT_PCR(p,n) (KL_PORT_BASE(p)+KL_PORT_PCR_OFFSET(n)
|
||||
#define KL_PORT_PCR0(p) (KL_PORT_BASE(p)+KL_PORT_PCR0_OFFSET)
|
||||
#define KL_PORT_PCR1(p) (KL_PORT_BASE(p)+KL_PORT_PCR1_OFFSET)
|
||||
#define KL_PORT_PCR2(p) (KL_PORT_BASE(p)+KL_PORT_PCR2_OFFSET)
|
||||
#define KL_PORT_PCR3(p) (KL_PORT_BASE(p)+KL_PORT_PCR3_OFFSET)
|
||||
#define KL_PORT_PCR4(p) (KL_PORT_BASE(p)+KL_PORT_PCR4_OFFSET)
|
||||
#define KL_PORT_PCR5(p) (KL_PORT_BASE(p)+KL_PORT_PCR5_OFFSET)
|
||||
#define KL_PORT_PCR6(p) (KL_PORT_BASE(p)+KL_PORT_PCR6_OFFSET)
|
||||
#define KL_PORT_PCR7(p) (KL_PORT_BASE(p)+KL_PORT_PCR7_OFFSET)
|
||||
#define KL_PORT_PCR8(p) (KL_PORT_BASE(p)+KL_PORT_PCR8_OFFSET)
|
||||
#define KL_PORT_PCR9(p) (KL_PORT_BASE(p)+KL_PORT_PCR9_OFFSET)
|
||||
#define KL_PORT_PCR10(p) (KL_PORT_BASE(p)+KL_PORT_PCR10_OFFSET)
|
||||
#define KL_PORT_PCR11(p) (KL_PORT_BASE(p)+KL_PORT_PCR11_OFFSET)
|
||||
#define KL_PORT_PCR12(p) (KL_PORT_BASE(p)+KL_PORT_PCR12_OFFSET)
|
||||
#define KL_PORT_PCR13(p) (KL_PORT_BASE(p)+KL_PORT_PCR13_OFFSET)
|
||||
#define KL_PORT_PCR14(p) (KL_PORT_BASE(p)+KL_PORT_PCR14_OFFSET)
|
||||
#define KL_PORT_PCR15(p) (KL_PORT_BASE(p)+KL_PORT_PCR15_OFFSET)
|
||||
#define KL_PORT_PCR16(p) (KL_PORT_BASE(p)+KL_PORT_PCR16_OFFSET)
|
||||
#define KL_PORT_PCR17(p) (KL_PORT_BASE(p)+KL_PORT_PCR17_OFFSET)
|
||||
#define KL_PORT_PCR18(p) (KL_PORT_BASE(p)+KL_PORT_PCR18_OFFSET)
|
||||
#define KL_PORT_PCR19(p) (KL_PORT_BASE(p)+KL_PORT_PCR19_OFFSET)
|
||||
#define KL_PORT_PCR20(p) (KL_PORT_BASE(p)+KL_PORT_PCR20_OFFSET)
|
||||
#define KL_PORT_PCR21(p) (KL_PORT_BASE(p)+KL_PORT_PCR21_OFFSET)
|
||||
#define KL_PORT_PCR22(p) (KL_PORT_BASE(p)+KL_PORT_PCR22_OFFSET)
|
||||
#define KL_PORT_PCR23(p) (KL_PORT_BASE(p)+KL_PORT_PCR23_OFFSET)
|
||||
#define KL_PORT_PCR24(p) (KL_PORT_BASE(p)+KL_PORT_PCR24_OFFSET)
|
||||
#define KL_PORT_PCR25(p) (KL_PORT_BASE(p)+KL_PORT_PCR25_OFFSET)
|
||||
#define KL_PORT_PCR26(p) (KL_PORT_BASE(p)+KL_PORT_PCR26_OFFSET)
|
||||
#define KL_PORT_PCR27(p) (KL_PORT_BASE(p)+KL_PORT_PCR27_OFFSET)
|
||||
#define KL_PORT_PCR28(p) (KL_PORT_BASE(p)+KL_PORT_PCR28_OFFSET)
|
||||
#define KL_PORT_PCR29(p) (KL_PORT_BASE(p)+KL_PORT_PCR29_OFFSET)
|
||||
#define KL_PORT_PCR30(p) (KL_PORT_BASE(p)+KL_PORT_PCR30_OFFSET)
|
||||
#define KL_PORT_PCR31(p) (KL_PORT_BASE(p)+KL_PORT_PCR31_OFFSET)
|
||||
#define KL_PORT_GPCLR(p) (KL_PORT_BASE(p)+KL_PORT_GPCLR_OFFSET)
|
||||
#define KL_PORT_GPCHR(p) (KL_PORT_BASE(p)+KL_PORT_GPCHR_OFFSET)
|
||||
#define KL_PORT_ISFR(p) (KL_PORT_BASE(p)+KL_PORT_ISFR_OFFSET)
|
||||
#define KL_PORT_DFER(p) (KL_PORT_BASE(p)+KL_PORT_DFER_OFFSET)
|
||||
#define KL_PORT_DFCR(p) (KL_PORT_BASE(p)+KL_PORT_DFCR_OFFSET)
|
||||
#define KL_PORT_DFWR(p) (KL_PORT_BASE(p)+KL_PORT_DFWR_OFFSET)
|
||||
|
||||
#define KL_PORTA_PCR(n) (KL_PORTA_BASE+KL_PORT_PCR_OFFSET(n)
|
||||
#define KL_PORTA_PCR0 (KL_PORTA_BASE+KL_PORT_PCR0_OFFSET)
|
||||
#define KL_PORTA_PCR1 (KL_PORTA_BASE+KL_PORT_PCR1_OFFSET)
|
||||
#define KL_PORTA_PCR2 (KL_PORTA_BASE+KL_PORT_PCR2_OFFSET)
|
||||
#define KL_PORTA_PCR3 (KL_PORTA_BASE+KL_PORT_PCR3_OFFSET)
|
||||
#define KL_PORTA_PCR4 (KL_PORTA_BASE+KL_PORT_PCR4_OFFSET)
|
||||
#define KL_PORTA_PCR5 (KL_PORTA_BASE+KL_PORT_PCR5_OFFSET)
|
||||
#define KL_PORTA_PCR6 (KL_PORTA_BASE+KL_PORT_PCR6_OFFSET)
|
||||
#define KL_PORTA_PCR7 (KL_PORTA_BASE+KL_PORT_PCR7_OFFSET)
|
||||
#define KL_PORTA_PCR8 (KL_PORTA_BASE+KL_PORT_PCR8_OFFSET)
|
||||
#define KL_PORTA_PCR9 (KL_PORTA_BASE+KL_PORT_PCR9_OFFSET)
|
||||
#define KL_PORTA_PCR10 (KL_PORTA_BASE+KL_PORT_PCR10_OFFSET)
|
||||
#define KL_PORTA_PCR11 (KL_PORTA_BASE+KL_PORT_PCR11_OFFSET)
|
||||
#define KL_PORTA_PCR12 (KL_PORTA_BASE+KL_PORT_PCR12_OFFSET)
|
||||
#define KL_PORTA_PCR13 (KL_PORTA_BASE+KL_PORT_PCR13_OFFSET)
|
||||
#define KL_PORTA_PCR14 (KL_PORTA_BASE+KL_PORT_PCR14_OFFSET)
|
||||
#define KL_PORTA_PCR15 (KL_PORTA_BASE+KL_PORT_PCR15_OFFSET)
|
||||
#define KL_PORTA_PCR16 (KL_PORTA_BASE+KL_PORT_PCR16_OFFSET)
|
||||
#define KL_PORTA_PCR17 (KL_PORTA_BASE+KL_PORT_PCR17_OFFSET)
|
||||
#define KL_PORTA_PCR18 (KL_PORTA_BASE+KL_PORT_PCR18_OFFSET)
|
||||
#define KL_PORTA_PCR19 (KL_PORTA_BASE+KL_PORT_PCR19_OFFSET)
|
||||
#define KL_PORTA_PCR20 (KL_PORTA_BASE+KL_PORT_PCR20_OFFSET)
|
||||
#define KL_PORTA_PCR21 (KL_PORTA_BASE+KL_PORT_PCR21_OFFSET)
|
||||
#define KL_PORTA_PCR22 (KL_PORTA_BASE+KL_PORT_PCR22_OFFSET)
|
||||
#define KL_PORTA_PCR23 (KL_PORTA_BASE+KL_PORT_PCR23_OFFSET)
|
||||
#define KL_PORTA_PCR24 (KL_PORTA_BASE+KL_PORT_PCR24_OFFSET)
|
||||
#define KL_PORTA_PCR25 (KL_PORTA_BASE+KL_PORT_PCR25_OFFSET)
|
||||
#define KL_PORTA_PCR26 (KL_PORTA_BASE+KL_PORT_PCR26_OFFSET)
|
||||
#define KL_PORTA_PCR27 (KL_PORTA_BASE+KL_PORT_PCR27_OFFSET)
|
||||
#define KL_PORTA_PCR28 (KL_PORTA_BASE+KL_PORT_PCR28_OFFSET)
|
||||
#define KL_PORTA_PCR29 (KL_PORTA_BASE+KL_PORT_PCR29_OFFSET)
|
||||
#define KL_PORTA_PCR30 (KL_PORTA_BASE+KL_PORT_PCR30_OFFSET)
|
||||
#define KL_PORTA_PCR31 (KL_PORTA_BASE+KL_PORT_PCR31_OFFSET)
|
||||
#define KL_PORTA_GPCLR (KL_PORTA_BASE+KL_PORT_GPCLR_OFFSET)
|
||||
#define KL_PORTA_GPCHR (KL_PORTA_BASE+KL_PORT_GPCHR_OFFSET)
|
||||
#define KL_PORTA_ISFR (KL_PORTA_BASE+KL_PORT_ISFR_OFFSET)
|
||||
#define KL_PORTA_DFER (KL_PORTA_BASE+KL_PORT_DFER_OFFSET)
|
||||
#define KL_PORTA_DFCR (KL_PORTA_BASE+KL_PORT_DFCR_OFFSET)
|
||||
#define KL_PORTA_DFWR (KL_PORTA_BASE+KL_PORT_DFWR_OFFSET)
|
||||
|
||||
#define KL_PORTB_PCR(n) (KL_PORTB_BASE+KL_PORT_PCR_OFFSET(n)
|
||||
#define KL_PORTB_PCR0 (KL_PORTB_BASE+KL_PORT_PCR0_OFFSET)
|
||||
#define KL_PORTB_PCR1 (KL_PORTB_BASE+KL_PORT_PCR1_OFFSET)
|
||||
#define KL_PORTB_PCR2 (KL_PORTB_BASE+KL_PORT_PCR2_OFFSET)
|
||||
#define KL_PORTB_PCR3 (KL_PORTB_BASE+KL_PORT_PCR3_OFFSET)
|
||||
#define KL_PORTB_PCR4 (KL_PORTB_BASE+KL_PORT_PCR4_OFFSET)
|
||||
#define KL_PORTB_PCR5 (KL_PORTB_BASE+KL_PORT_PCR5_OFFSET)
|
||||
#define KL_PORTB_PCR6 (KL_PORTB_BASE+KL_PORT_PCR6_OFFSET)
|
||||
#define KL_PORTB_PCR7 (KL_PORTB_BASE+KL_PORT_PCR7_OFFSET)
|
||||
#define KL_PORTB_PCR8 (KL_PORTB_BASE+KL_PORT_PCR8_OFFSET)
|
||||
#define KL_PORTB_PCR9 (KL_PORTB_BASE+KL_PORT_PCR9_OFFSET)
|
||||
#define KL_PORTB_PCR10 (KL_PORTB_BASE+KL_PORT_PCR10_OFFSET)
|
||||
#define KL_PORTB_PCR11 (KL_PORTB_BASE+KL_PORT_PCR11_OFFSET)
|
||||
#define KL_PORTB_PCR12 (KL_PORTB_BASE+KL_PORT_PCR12_OFFSET)
|
||||
#define KL_PORTB_PCR13 (KL_PORTB_BASE+KL_PORT_PCR13_OFFSET)
|
||||
#define KL_PORTB_PCR14 (KL_PORTB_BASE+KL_PORT_PCR14_OFFSET)
|
||||
#define KL_PORTB_PCR15 (KL_PORTB_BASE+KL_PORT_PCR15_OFFSET)
|
||||
#define KL_PORTB_PCR16 (KL_PORTB_BASE+KL_PORT_PCR16_OFFSET)
|
||||
#define KL_PORTB_PCR17 (KL_PORTB_BASE+KL_PORT_PCR17_OFFSET)
|
||||
#define KL_PORTB_PCR18 (KL_PORTB_BASE+KL_PORT_PCR18_OFFSET)
|
||||
#define KL_PORTB_PCR19 (KL_PORTB_BASE+KL_PORT_PCR19_OFFSET)
|
||||
#define KL_PORTB_PCR20 (KL_PORTB_BASE+KL_PORT_PCR20_OFFSET)
|
||||
#define KL_PORTB_PCR21 (KL_PORTB_BASE+KL_PORT_PCR21_OFFSET)
|
||||
#define KL_PORTB_PCR22 (KL_PORTB_BASE+KL_PORT_PCR22_OFFSET)
|
||||
#define KL_PORTB_PCR23 (KL_PORTB_BASE+KL_PORT_PCR23_OFFSET)
|
||||
#define KL_PORTB_PCR24 (KL_PORTB_BASE+KL_PORT_PCR24_OFFSET)
|
||||
#define KL_PORTB_PCR25 (KL_PORTB_BASE+KL_PORT_PCR25_OFFSET)
|
||||
#define KL_PORTB_PCR26 (KL_PORTB_BASE+KL_PORT_PCR26_OFFSET)
|
||||
#define KL_PORTB_PCR27 (KL_PORTB_BASE+KL_PORT_PCR27_OFFSET)
|
||||
#define KL_PORTB_PCR28 (KL_PORTB_BASE+KL_PORT_PCR28_OFFSET)
|
||||
#define KL_PORTB_PCR29 (KL_PORTB_BASE+KL_PORT_PCR29_OFFSET)
|
||||
#define KL_PORTB_PCR30 (KL_PORTB_BASE+KL_PORT_PCR30_OFFSET)
|
||||
#define KL_PORTB_PCR31 (KL_PORTB_BASE+KL_PORT_PCR31_OFFSET)
|
||||
#define KL_PORTB_GPCLR (KL_PORTB_BASE+KL_PORT_GPCLR_OFFSET)
|
||||
#define KL_PORTB_GPCHR (KL_PORTB_BASE+KL_PORT_GPCHR_OFFSET)
|
||||
#define KL_PORTB_ISFR (KL_PORTB_BASE+KL_PORT_ISFR_OFFSET)
|
||||
#define KL_PORTB_DFER (KL_PORTB_BASE+KL_PORT_DFER_OFFSET)
|
||||
#define KL_PORTB_DFCR (KL_PORTB_BASE+KL_PORT_DFCR_OFFSET)
|
||||
#define KL_PORTB_DFWR (KL_PORTB_BASE+KL_PORT_DFWR_OFFSET)
|
||||
|
||||
#define KL_PORTC_PCR(n) (KL_PORTC_BASE+KL_PORT_PCR_OFFSET(n)
|
||||
#define KL_PORTC_PCR0 (KL_PORTC_BASE+KL_PORT_PCR0_OFFSET)
|
||||
#define KL_PORTC_PCR1 (KL_PORTC_BASE+KL_PORT_PCR1_OFFSET)
|
||||
#define KL_PORTC_PCR2 (KL_PORTC_BASE+KL_PORT_PCR2_OFFSET)
|
||||
#define KL_PORTC_PCR3 (KL_PORTC_BASE+KL_PORT_PCR3_OFFSET)
|
||||
#define KL_PORTC_PCR4 (KL_PORTC_BASE+KL_PORT_PCR4_OFFSET)
|
||||
#define KL_PORTC_PCR5 (KL_PORTC_BASE+KL_PORT_PCR5_OFFSET)
|
||||
#define KL_PORTC_PCR6 (KL_PORTC_BASE+KL_PORT_PCR6_OFFSET)
|
||||
#define KL_PORTC_PCR7 (KL_PORTC_BASE+KL_PORT_PCR7_OFFSET)
|
||||
#define KL_PORTC_PCR8 (KL_PORTC_BASE+KL_PORT_PCR8_OFFSET)
|
||||
#define KL_PORTC_PCR9 (KL_PORTC_BASE+KL_PORT_PCR9_OFFSET)
|
||||
#define KL_PORTC_PCR10 (KL_PORTC_BASE+KL_PORT_PCR10_OFFSET)
|
||||
#define KL_PORTC_PCR11 (KL_PORTC_BASE+KL_PORT_PCR11_OFFSET)
|
||||
#define KL_PORTC_PCR12 (KL_PORTC_BASE+KL_PORT_PCR12_OFFSET)
|
||||
#define KL_PORTC_PCR13 (KL_PORTC_BASE+KL_PORT_PCR13_OFFSET)
|
||||
#define KL_PORTC_PCR14 (KL_PORTC_BASE+KL_PORT_PCR14_OFFSET)
|
||||
#define KL_PORTC_PCR15 (KL_PORTC_BASE+KL_PORT_PCR15_OFFSET)
|
||||
#define KL_PORTC_PCR16 (KL_PORTC_BASE+KL_PORT_PCR16_OFFSET)
|
||||
#define KL_PORTC_PCR17 (KL_PORTC_BASE+KL_PORT_PCR17_OFFSET)
|
||||
#define KL_PORTC_PCR18 (KL_PORTC_BASE+KL_PORT_PCR18_OFFSET)
|
||||
#define KL_PORTC_PCR19 (KL_PORTC_BASE+KL_PORT_PCR19_OFFSET)
|
||||
#define KL_PORTC_PCR20 (KL_PORTC_BASE+KL_PORT_PCR20_OFFSET)
|
||||
#define KL_PORTC_PCR21 (KL_PORTC_BASE+KL_PORT_PCR21_OFFSET)
|
||||
#define KL_PORTC_PCR22 (KL_PORTC_BASE+KL_PORT_PCR22_OFFSET)
|
||||
#define KL_PORTC_PCR23 (KL_PORTC_BASE+KL_PORT_PCR23_OFFSET)
|
||||
#define KL_PORTC_PCR24 (KL_PORTC_BASE+KL_PORT_PCR24_OFFSET)
|
||||
#define KL_PORTC_PCR25 (KL_PORTC_BASE+KL_PORT_PCR25_OFFSET)
|
||||
#define KL_PORTC_PCR26 (KL_PORTC_BASE+KL_PORT_PCR26_OFFSET)
|
||||
#define KL_PORTC_PCR27 (KL_PORTC_BASE+KL_PORT_PCR27_OFFSET)
|
||||
#define KL_PORTC_PCR28 (KL_PORTC_BASE+KL_PORT_PCR28_OFFSET)
|
||||
#define KL_PORTC_PCR29 (KL_PORTC_BASE+KL_PORT_PCR29_OFFSET)
|
||||
#define KL_PORTC_PCR30 (KL_PORTC_BASE+KL_PORT_PCR30_OFFSET)
|
||||
#define KL_PORTC_PCR31 (KL_PORTC_BASE+KL_PORT_PCR31_OFFSET)
|
||||
#define KL_PORTC_GPCLR (KL_PORTC_BASE+KL_PORT_GPCLR_OFFSET)
|
||||
#define KL_PORTC_GPCHR (KL_PORTC_BASE+KL_PORT_GPCHR_OFFSET)
|
||||
#define KL_PORTC_ISFR (KL_PORTC_BASE+KL_PORT_ISFR_OFFSET)
|
||||
#define KL_PORTC_DFER (KL_PORTC_BASE+KL_PORT_DFER_OFFSET)
|
||||
#define KL_PORTC_DFCR (KL_PORTC_BASE+KL_PORT_DFCR_OFFSET)
|
||||
#define KL_PORTC_DFWR (KL_PORTC_BASE+KL_PORT_DFWR_OFFSET)
|
||||
|
||||
#define KL_PORTD_PCR(n) (KL_PORTD_BASE+KL_PORT_PCR_OFFSET(n)
|
||||
#define KL_PORTD_PCR0 (KL_PORTD_BASE+KL_PORT_PCR0_OFFSET)
|
||||
#define KL_PORTD_PCR1 (KL_PORTD_BASE+KL_PORT_PCR1_OFFSET)
|
||||
#define KL_PORTD_PCR2 (KL_PORTD_BASE+KL_PORT_PCR2_OFFSET)
|
||||
#define KL_PORTD_PCR3 (KL_PORTD_BASE+KL_PORT_PCR3_OFFSET)
|
||||
#define KL_PORTD_PCR4 (KL_PORTD_BASE+KL_PORT_PCR4_OFFSET)
|
||||
#define KL_PORTD_PCR5 (KL_PORTD_BASE+KL_PORT_PCR5_OFFSET)
|
||||
#define KL_PORTD_PCR6 (KL_PORTD_BASE+KL_PORT_PCR6_OFFSET)
|
||||
#define KL_PORTD_PCR7 (KL_PORTD_BASE+KL_PORT_PCR7_OFFSET)
|
||||
#define KL_PORTD_PCR8 (KL_PORTD_BASE+KL_PORT_PCR8_OFFSET)
|
||||
#define KL_PORTD_PCR9 (KL_PORTD_BASE+KL_PORT_PCR9_OFFSET)
|
||||
#define KL_PORTD_PCR10 (KL_PORTD_BASE+KL_PORT_PCR10_OFFSET)
|
||||
#define KL_PORTD_PCR11 (KL_PORTD_BASE+KL_PORT_PCR11_OFFSET)
|
||||
#define KL_PORTD_PCR12 (KL_PORTD_BASE+KL_PORT_PCR12_OFFSET)
|
||||
#define KL_PORTD_PCR13 (KL_PORTD_BASE+KL_PORT_PCR13_OFFSET)
|
||||
#define KL_PORTD_PCR14 (KL_PORTD_BASE+KL_PORT_PCR14_OFFSET)
|
||||
#define KL_PORTD_PCR15 (KL_PORTD_BASE+KL_PORT_PCR15_OFFSET)
|
||||
#define KL_PORTD_PCR16 (KL_PORTD_BASE+KL_PORT_PCR16_OFFSET)
|
||||
#define KL_PORTD_PCR17 (KL_PORTD_BASE+KL_PORT_PCR17_OFFSET)
|
||||
#define KL_PORTD_PCR18 (KL_PORTD_BASE+KL_PORT_PCR18_OFFSET)
|
||||
#define KL_PORTD_PCR19 (KL_PORTD_BASE+KL_PORT_PCR19_OFFSET)
|
||||
#define KL_PORTD_PCR20 (KL_PORTD_BASE+KL_PORT_PCR20_OFFSET)
|
||||
#define KL_PORTD_PCR21 (KL_PORTD_BASE+KL_PORT_PCR21_OFFSET)
|
||||
#define KL_PORTD_PCR22 (KL_PORTD_BASE+KL_PORT_PCR22_OFFSET)
|
||||
#define KL_PORTD_PCR23 (KL_PORTD_BASE+KL_PORT_PCR23_OFFSET)
|
||||
#define KL_PORTD_PCR24 (KL_PORTD_BASE+KL_PORT_PCR24_OFFSET)
|
||||
#define KL_PORTD_PCR25 (KL_PORTD_BASE+KL_PORT_PCR25_OFFSET)
|
||||
#define KL_PORTD_PCR26 (KL_PORTD_BASE+KL_PORT_PCR26_OFFSET)
|
||||
#define KL_PORTD_PCR27 (KL_PORTD_BASE+KL_PORT_PCR27_OFFSET)
|
||||
#define KL_PORTD_PCR28 (KL_PORTD_BASE+KL_PORT_PCR28_OFFSET)
|
||||
#define KL_PORTD_PCR29 (KL_PORTD_BASE+KL_PORT_PCR29_OFFSET)
|
||||
#define KL_PORTD_PCR30 (KL_PORTD_BASE+KL_PORT_PCR30_OFFSET)
|
||||
#define KL_PORTD_PCR31 (KL_PORTD_BASE+KL_PORT_PCR31_OFFSET)
|
||||
#define KL_PORTD_GPCLR (KL_PORTD_BASE+KL_PORT_GPCLR_OFFSET)
|
||||
#define KL_PORTD_GPCHR (KL_PORTD_BASE+KL_PORT_GPCHR_OFFSET)
|
||||
#define KL_PORTD_ISFR (KL_PORTD_BASE+KL_PORT_ISFR_OFFSET)
|
||||
#define KL_PORTD_DFER (KL_PORTD_BASE+KL_PORT_DFER_OFFSET)
|
||||
#define KL_PORTD_DFCR (KL_PORTD_BASE+KL_PORT_DFCR_OFFSET)
|
||||
#define KL_PORTD_DFWR (KL_PORTD_BASE+KL_PORT_DFWR_OFFSET)
|
||||
|
||||
#define KL_PORTE_PCR(n) (KL_PORTE_BASE+KL_PORT_PCR_OFFSET(n)
|
||||
#define KL_PORTE_PCR0 (KL_PORTE_BASE+KL_PORT_PCR0_OFFSET)
|
||||
#define KL_PORTE_PCR1 (KL_PORTE_BASE+KL_PORT_PCR1_OFFSET)
|
||||
#define KL_PORTE_PCR2 (KL_PORTE_BASE+KL_PORT_PCR2_OFFSET)
|
||||
#define KL_PORTE_PCR3 (KL_PORTE_BASE+KL_PORT_PCR3_OFFSET)
|
||||
#define KL_PORTE_PCR4 (KL_PORTE_BASE+KL_PORT_PCR4_OFFSET)
|
||||
#define KL_PORTE_PCR5 (KL_PORTE_BASE+KL_PORT_PCR5_OFFSET)
|
||||
#define KL_PORTE_PCR6 (KL_PORTE_BASE+KL_PORT_PCR6_OFFSET)
|
||||
#define KL_PORTE_PCR7 (KL_PORTE_BASE+KL_PORT_PCR7_OFFSET)
|
||||
#define KL_PORTE_PCR8 (KL_PORTE_BASE+KL_PORT_PCR8_OFFSET)
|
||||
#define KL_PORTE_PCR9 (KL_PORTE_BASE+KL_PORT_PCR9_OFFSET)
|
||||
#define KL_PORTE_PCR10 (KL_PORTE_BASE+KL_PORT_PCR10_OFFSET)
|
||||
#define KL_PORTE_PCR11 (KL_PORTE_BASE+KL_PORT_PCR11_OFFSET)
|
||||
#define KL_PORTE_PCR12 (KL_PORTE_BASE+KL_PORT_PCR12_OFFSET)
|
||||
#define KL_PORTE_PCR13 (KL_PORTE_BASE+KL_PORT_PCR13_OFFSET)
|
||||
#define KL_PORTE_PCR14 (KL_PORTE_BASE+KL_PORT_PCR14_OFFSET)
|
||||
#define KL_PORTE_PCR15 (KL_PORTE_BASE+KL_PORT_PCR15_OFFSET)
|
||||
#define KL_PORTE_PCR16 (KL_PORTE_BASE+KL_PORT_PCR16_OFFSET)
|
||||
#define KL_PORTE_PCR17 (KL_PORTE_BASE+KL_PORT_PCR17_OFFSET)
|
||||
#define KL_PORTE_PCR18 (KL_PORTE_BASE+KL_PORT_PCR18_OFFSET)
|
||||
#define KL_PORTE_PCR19 (KL_PORTE_BASE+KL_PORT_PCR19_OFFSET)
|
||||
#define KL_PORTE_PCR20 (KL_PORTE_BASE+KL_PORT_PCR20_OFFSET)
|
||||
#define KL_PORTE_PCR21 (KL_PORTE_BASE+KL_PORT_PCR21_OFFSET)
|
||||
#define KL_PORTE_PCR22 (KL_PORTE_BASE+KL_PORT_PCR22_OFFSET)
|
||||
#define KL_PORTE_PCR23 (KL_PORTE_BASE+KL_PORT_PCR23_OFFSET)
|
||||
#define KL_PORTE_PCR24 (KL_PORTE_BASE+KL_PORT_PCR24_OFFSET)
|
||||
#define KL_PORTE_PCR25 (KL_PORTE_BASE+KL_PORT_PCR25_OFFSET)
|
||||
#define KL_PORTE_PCR26 (KL_PORTE_BASE+KL_PORT_PCR26_OFFSET)
|
||||
#define KL_PORTE_PCR27 (KL_PORTE_BASE+KL_PORT_PCR27_OFFSET)
|
||||
#define KL_PORTE_PCR28 (KL_PORTE_BASE+KL_PORT_PCR28_OFFSET)
|
||||
#define KL_PORTE_PCR29 (KL_PORTE_BASE+KL_PORT_PCR29_OFFSET)
|
||||
#define KL_PORTE_PCR30 (KL_PORTE_BASE+KL_PORT_PCR30_OFFSET)
|
||||
#define KL_PORTE_PCR31 (KL_PORTE_BASE+KL_PORT_PCR31_OFFSET)
|
||||
#define KL_PORTE_GPCLR (KL_PORTE_BASE+KL_PORT_GPCLR_OFFSET)
|
||||
#define KL_PORTE_GPCHR (KL_PORTE_BASE+KL_PORT_GPCHR_OFFSET)
|
||||
#define KL_PORTE_ISFR (KL_PORTE_BASE+KL_PORT_ISFR_OFFSET)
|
||||
#define KL_PORTE_DFER (KL_PORTE_BASE+KL_PORT_DFER_OFFSET)
|
||||
#define KL_PORTE_DFCR (KL_PORTE_BASE+KL_PORT_DFCR_OFFSET)
|
||||
#define KL_PORTE_DFWR (KL_PORTE_BASE+KL_PORT_DFWR_OFFSET)
|
||||
|
||||
/* Register Bit Definitions *********************************************************/
|
||||
/* Pin Control Register n, n=0..31 */
|
||||
|
||||
#define PORT_PCR_PS (1 << 0) /* Bit 0: Pull Select */
|
||||
#define PORT_PCR_PE (1 << 1) /* Bit 1: Pull Enable */
|
||||
#define PORT_PCR_SRE (1 << 2) /* Bit 2: Slew Rate Enable */
|
||||
/* Bit 3: Reserved */
|
||||
#define PORT_PCR_PFE (1 << 4) /* Bit 4: Passive Filter Enable */
|
||||
#define PORT_PCR_ODE (1 << 5) /* Bit 5: Open Drain Enable */
|
||||
#define PORT_PCR_DSE (1 << 6) /* Bit 6: Drive Strength Enable */
|
||||
/* Bit 7: Reserved */
|
||||
#define PORT_PCR_MUX_SHIFT (8) /* Bits 8-10: Pin Mux Control */
|
||||
#define PORT_PCR_MUX_MASK (7 << PORT_PCR_MUX_SHIFT)
|
||||
# define PORT_PCR_MUX_ANALOG (0 << PORT_PCR_MUX_SHIFT) /* Pin Disabled (Analog) */
|
||||
# define PORT_PCR_MUX_GPIO (1 << PORT_PCR_MUX_SHIFT) /* Alternative 1 (GPIO) */
|
||||
# define PORT_PCR_MUX_ALT1 (1 << PORT_PCR_MUX_SHIFT) /* Alternative 1 (GPIO) */
|
||||
# define PORT_PCR_MUX_ALT2 (2 << PORT_PCR_MUX_SHIFT) /* Alternative 2 (chip specific) */
|
||||
# define PORT_PCR_MUX_ALT3 (3 << PORT_PCR_MUX_SHIFT) /* Alternative 3 (chip specific) */
|
||||
# define PORT_PCR_MUX_ALT4 (4 << PORT_PCR_MUX_SHIFT) /* Alternative 4 (chip specific) */
|
||||
# define PORT_PCR_MUX_ALT5 (5 << PORT_PCR_MUX_SHIFT) /* Alternative 5 (chip specific) */
|
||||
# define PORT_PCR_MUX_ALT6 (6 << PORT_PCR_MUX_SHIFT) /* Alternative 6 (chip specific) */
|
||||
# define PORT_PCR_MUX_ALT7 (7 << PORT_PCR_MUX_SHIFT) /* Alternative 7 (chip specific / JTAG / NMI) */
|
||||
/* Bits 11-14: Reserved */
|
||||
#define PORT_PCR_LK (1 << 15) /* Bit 15: Lock Register */
|
||||
#define PORT_PCR_IRQC_SHIFT (16) /* Bits 16-19: Interrupt Configuration */
|
||||
#define PORT_PCR_IRQC_MASK (15 << PORT_PCR_IRQC_SHIFT)
|
||||
# define PORT_PCR_IRQC_DISABLED (0 << PORT_PCR_IRQC_SHIFT) /* Interrupt/DMA Request disabled */
|
||||
# define PORT_PCR_IRQC_DMARISING (1 << PORT_PCR_IRQC_SHIFT) /* DMA Request on rising edge */
|
||||
# define PORT_PCR_IRQC_DMAFALLING (2 << PORT_PCR_IRQC_SHIFT) /* DMA Request on falling edge */
|
||||
# define PORT_PCR_IRQC_DMABOTH (3 << PORT_PCR_IRQC_SHIFT) /* DMA Request on either edge */
|
||||
# define PORT_PCR_IRQC_ZERO (8 << PORT_PCR_IRQC_SHIFT) /* Interrupt when logic zero */
|
||||
# define PORT_PCR_IRQC_RISING (9 << PORT_PCR_IRQC_SHIFT) /* Interrupt on rising edge */
|
||||
# define PORT_PCR_IRQC_FALLING (10 << PORT_PCR_IRQC_SHIFT) /* Interrupt on falling edge */
|
||||
# define PORT_PCR_IRQC_BOTH (11 << PORT_PCR_IRQC_SHIFT) /* Interrupt on either edge */
|
||||
# define PORT_PCR_IRQC_ONE (12 << PORT_PCR_IRQC_SHIFT) /* Interrupt when logic one */
|
||||
/* Bits 20-23: Reserved */
|
||||
#define PORT_PCR_ISF (1 << 24) /* Bit 24: Interrupt Status Flag */
|
||||
/* Bits 25-31: Reserved */
|
||||
|
||||
/* Global Pin Control Low Register */
|
||||
|
||||
#define PORT_GPCLR_GPWD_SHIFT (0) /* Bits 0-15: Global Pin Write Data */
|
||||
#define PORT_GPCLR_GPWD_MASK (0xffff << PORT_GPCLR_GPWD_SHIFT)
|
||||
# define PORT_GPCLR_GPWD(n) ((1 << (n)) << PORT_GPCLR_GPWD_SHIFT)
|
||||
#define PORT_GPCLR_GPWE_SHIFT (16) /* Bits 16-31: Global Pin Write Enable */
|
||||
#define PORT_GPCLR_GPWE_MASK (0xffff << PORT_GPCLR_GPWE_SHIFT)
|
||||
# define PORT_GPCLR_GPWE(n) ((1 << (n)) << PORT_GPCLR_GPWE_SHIFT)
|
||||
|
||||
/* Global Pin Control High Register */
|
||||
|
||||
#define PORT_GPCHR_
|
||||
|
||||
#define PORT_GPCHR_GPWD_SHIFT (0) /* Bits 0-15: Global Pin Write Data */
|
||||
#define PORT_GPCHR_GPWD_MASK (0xffff << PORT_GPCHR_GPWD_SHIFT)
|
||||
# define PORT_GPCHR_GPWD(n) ((1 << (n)) << PORT_GPCHR_GPWD_SHIFT)
|
||||
#define PORT_GPCHR_GPWE_SHIFT (16) /* Bits 16-31: Global Pin Write Enable */
|
||||
#define PORT_GPCHR_GPWE_MASK (0xffff << PORT_GPCHR_GPWE_SHIFT)
|
||||
# define PORT_GPCHR_GPWE(n) ((1 << (n)) << PORT_GPCHR_GPWE_SHIFT)
|
||||
|
||||
/* Interrupt Status Flag Register */
|
||||
|
||||
#define PORT_ISFR(n) (1 << (n))
|
||||
|
||||
/* Digital Filter Enable Register */
|
||||
|
||||
#define PORT_DFER(n) (1 << (n))
|
||||
|
||||
/* Digital Filter Clock Register */
|
||||
|
||||
#define PORT_DFCR_CS (1 << 0) /* Bit 0: Clock Source */
|
||||
|
||||
/* Digital Filter Width Register */
|
||||
|
||||
#define PORT_DFWR_FILT_SHIFT (0) /* Bits 0-4: Filter Length */
|
||||
#define PORT_DFWR_FILT_MASK (31 << PORT_DFWR_FILT_SHIFT)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KL_KL_PORT_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,42 @@
|
||||
/* Barely based on "bare metal" sample from Freedom board:
|
||||
Copyright (c) 2012-2013 Andrew Payne
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights to
|
||||
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
const uint8_t _cfmconfig[16] __attribute__((section(".cfmconfig"))) =
|
||||
{
|
||||
0xFF, /* NV_BACKKEY3: KEY=0xFF */
|
||||
0xFF, /* NV_BACKKEY2: KEY=0xFF */
|
||||
0xFF, /* NV_BACKKEY1: KEY=0xFF */
|
||||
0xFF, /* NV_BACKKEY0: KEY=0xFF */
|
||||
0xFF, /* NV_BACKKEY7: KEY=0xFF */
|
||||
0xFF, /* NV_BACKKEY6: KEY=0xFF */
|
||||
0xFF, /* NV_BACKKEY5: KEY=0xFF */
|
||||
0xFF, /* NV_BACKKEY4: KEY=0xFF */
|
||||
0xFF, /* NV_FPROT3: PROT=0xFF */
|
||||
0xFF, /* NV_FPROT2: PROT=0xFF */
|
||||
0xFF, /* NV_FPROT1: PROT=0xFF */
|
||||
0xFF, /* NV_FPROT0: PROT=0xFF */
|
||||
0x7E, /* NV_FSEC: KEYEN=1,MEEN=3,FSLACC=3,SEC=2 */
|
||||
0xFF, /* NV_FOPT: ??=1,??=1,FAST_INIT=1,LPBOOT1=1,RESET_PIN_CFG=1,
|
||||
NMI_DIS=1,EZPORT_DIS=1,LPBOOT0=1 */
|
||||
0xFF,
|
||||
0xFF
|
||||
};
|
||||
@@ -0,0 +1,275 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/kl/kl_clockconfig.c
|
||||
* arch/arm/src/chip/kl_clockconfig.c
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/kl_internal.h"
|
||||
#include "chip/kl_mcg.h"
|
||||
#include "chip/kl_sim.h"
|
||||
#include "chip/kl_osc.h"
|
||||
#include "chip/kl_fmc.h"
|
||||
#include "chip/kl_llwu.h"
|
||||
#include "chip/kl_pinmux.h"
|
||||
#include "MKL25Z4.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_portclocks
|
||||
*
|
||||
* Description:
|
||||
* Enable all of the port clocks
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if 0
|
||||
static inline void kl_portclocks(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Enable all of the port clocks */
|
||||
|
||||
regval = getreg32(KL_SIM_SCGC5);
|
||||
regval |= (SIM_SCGC5_PORTA | SIM_SCGC5_PORTB | SIM_SCGC5_PORTC |
|
||||
SIM_SCGC5_PORTD | SIM_SCGC5_PORTE);
|
||||
putreg32(regval, KL_SIM_SCGC5);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_pllconfig
|
||||
*
|
||||
* Description:
|
||||
* Initialize the PLL using the settings in board.h. This assumes that
|
||||
* the MCG is in default FLL Engaged Internal (FEI mode) out of reset.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if 0
|
||||
void kl_pllconfig(void)
|
||||
{
|
||||
uint32_t regval32;
|
||||
uint8_t regval8;
|
||||
|
||||
/* Enable clock gate to Port A module to enable pin routing (PORTA=1) */
|
||||
regval32 = getreg32(KL_SIM_SCGC5);
|
||||
regval32 |= SIM_SCGC5_PORTA;
|
||||
putreg32(regval32, KL_SIM_SCGC5);
|
||||
|
||||
/* Divide-by-2 for clock 1 and clock 4 (OUTDIV1=1, OUTDIV4=1) */
|
||||
regval32 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV4(1);
|
||||
putreg32(regval32, KL_SIM_CLKDIV1);
|
||||
|
||||
/* System oscillator drives 32 kHz clock for various peripherals (OSC32KSEL=0) */
|
||||
regval32 = getreg32(KL_SIM_SOPT1);
|
||||
regval32 &= ~(SIM_SOPT1_OSC32KSEL);
|
||||
putreg32(regval32, KL_SIM_SOPT1);
|
||||
|
||||
/* Select PLL as a clock source for various peripherals (PLLFLLSEL=1)
|
||||
Clock source for TPM counter clock is MCGFLLCLK or MCGPLLCLK/2 */
|
||||
regval32 = getreg32(KL_SIM_SOPT2);
|
||||
regval32 |= SIM_SOPT2_PLLFLLSEL;
|
||||
putreg32(regval32, KL_SIM_SOPT2);
|
||||
regval32 = (regval32 & ~(SIM_SOPT2_TPMSRC_OCSERCLK)) | SIM_SOPT2_TPMSRC_MCGCLK;
|
||||
putreg32(regval32, KL_SIM_SOPT2);
|
||||
|
||||
/* PORTA_PCR18: ISF=0,MUX=0 */
|
||||
/* PORTA_PCR19: ISF=0,MUX=0 */
|
||||
regval32 = getreg32(KL_PORTA_PCR18);
|
||||
regval32 = ~(PORT_PCR_ISF | PORT_PCR_MUX_ALT7);
|
||||
putreg32(regval32, KL_PORTA_PCR18);
|
||||
regval32 = getreg32(KL_PORTA_PCR19);
|
||||
regval32 = ~(PORT_PCR_ISF | PORT_PCR_MUX_ALT7);
|
||||
putreg32(regval32, KL_PORTA_PCR19);
|
||||
|
||||
/* Switch to FBE Mode */
|
||||
/* OSC0_CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
putreg8(0, KL_OSC_CR);
|
||||
/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
|
||||
//regval8 = (MCG_C2_RANGE_VHIGH | MCG_C2_EREFS);
|
||||
regval8 = MCG_C2_EREFS;
|
||||
putreg8(regval8, KL_MCG_C2);
|
||||
/* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
|
||||
regval8 = (MCG_C1_CLKS_EXTREF | MCG_C1_FRDIV_R0DIV8);
|
||||
putreg8(regval8, KL_MCG_C1);
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0 */
|
||||
regval8 = ~(MCG_C4_DMX32 | MCG_C4_DRST_DRS_HIGH);
|
||||
putreg8(regval8, KL_MCG_C4);
|
||||
/* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
|
||||
regval8 = MCG_C5_PRDIV(1);
|
||||
putreg8(regval8, KL_MCG_C5);
|
||||
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||
putreg8(0, KL_MCG_C6);
|
||||
|
||||
/* Check that the source of the FLL reference clock is
|
||||
the external reference clock. */
|
||||
while((getreg8(KL_MCG_S) & MCG_S_IREFST) != 0)
|
||||
;
|
||||
|
||||
/* Wait until external reference */
|
||||
while((getreg8(KL_MCG_S) & MCG_S_CLKST_MASK) != 8)
|
||||
;
|
||||
|
||||
/* Switch to PBE mode
|
||||
Select PLL as MCG source (PLLS=1) */
|
||||
putreg8(MCG_C6_PLLS, KL_MCG_C6);
|
||||
/* Wait until PLL locked */
|
||||
while((getreg8(KL_MCG_S) & MCG_S_LOCK) != 0)
|
||||
;
|
||||
|
||||
/* Switch to PEE mode
|
||||
Select PLL output (CLKS=0)
|
||||
FLL external reference divider (FRDIV=3)
|
||||
External reference clock for FLL (IREFS=0) */
|
||||
putreg8(MCG_C1_FRDIV_R0DIV8, KL_MCG_C1);
|
||||
|
||||
/* Wait until PLL output */
|
||||
while((getreg8(KL_MCG_S) & MCG_S_CLKST_MASK) != 0x0C)
|
||||
;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void init_clocks(void)
|
||||
{
|
||||
// Enable clock gate to Port A module to enable pin routing (PORTA=1)
|
||||
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
|
||||
|
||||
// Divide-by-2 for clock 1 and clock 4 (OUTDIV1=1, OUTDIV4=1)
|
||||
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x01) | SIM_CLKDIV1_OUTDIV4(0x01);
|
||||
|
||||
// System oscillator drives 32 kHz clock for various peripherals (OSC32KSEL=0)
|
||||
SIM_SOPT1 &= ~SIM_SOPT1_OSC32KSEL(0x03);
|
||||
|
||||
// Select PLL as a clock source for various peripherals (PLLFLLSEL=1)
|
||||
// Clock source for TPM counter clock is MCGFLLCLK or MCGPLLCLK/2
|
||||
SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK;
|
||||
SIM_SOPT2 = (SIM_SOPT2 & ~(SIM_SOPT2_TPMSRC(0x02))) | SIM_SOPT2_TPMSRC(0x01);
|
||||
|
||||
/* PORTA_PCR18: ISF=0,MUX=0 */
|
||||
/* PORTA_PCR19: ISF=0,MUX=0 */
|
||||
PORTA_PCR18 &= ~((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
|
||||
PORTA_PCR19 &= ~((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
|
||||
/* Switch to FBE Mode */
|
||||
|
||||
/* OSC0_CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
OSC0_CR = 0;
|
||||
/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
|
||||
MCG_C2 = (MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK);
|
||||
/* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
|
||||
MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x03));
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0 */
|
||||
MCG_C4 &= ~((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
|
||||
/* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
|
||||
MCG_C5 = MCG_C5_PRDIV0(0x01);
|
||||
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||
MCG_C6 = 0;
|
||||
|
||||
|
||||
// Check that the source of the FLL reference clock is
|
||||
// the external reference clock.
|
||||
while((MCG_S & MCG_S_IREFST_MASK) != 0)
|
||||
;
|
||||
|
||||
while((MCG_S & MCG_S_CLKST_MASK) != 8) // Wait until external reference
|
||||
;
|
||||
|
||||
// Switch to PBE mode
|
||||
// Select PLL as MCG source (PLLS=1)
|
||||
MCG_C6 = MCG_C6_PLLS_MASK;
|
||||
while((MCG_S & MCG_S_LOCK0_MASK) == 0) // Wait until PLL locked
|
||||
;
|
||||
|
||||
// Switch to PEE mode
|
||||
// Select PLL output (CLKS=0)
|
||||
// FLL external reference divider (FRDIV=3)
|
||||
// External reference clock for FLL (IREFS=0)
|
||||
MCG_C1 = MCG_C1_FRDIV(0x03);
|
||||
while((MCG_S & MCG_S_CLKST_MASK) != 0x0CU) // Wait until PLL output
|
||||
;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_clockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to initialize the Kinetis chip. This does whatever setup is
|
||||
* needed to put the MCU in a usable state. This includes the
|
||||
* initialization of clocking using the settings in board.h.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void kl_clockconfig(void)
|
||||
{
|
||||
/* Enable all of the port clocks */
|
||||
|
||||
//kl_portclocks();
|
||||
|
||||
/* Configure the PLL based on settings in the board.h file */
|
||||
|
||||
//kl_pllconfig();
|
||||
init_clocks();
|
||||
|
||||
/* For debugging, we will normally want to enable the trace clock and/or
|
||||
* the FlexBus clock.
|
||||
*/
|
||||
|
||||
//kl_traceconfig();
|
||||
//kl_fbconfig();
|
||||
}
|
||||
|
||||
@@ -0,0 +1,209 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/kl/kl_clockconfig.c
|
||||
* arch/arm/src/chip/kl_clockconfig.c
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/kl_internal.h"
|
||||
#include "chip/kl_mcg.h"
|
||||
#include "chip/kl_sim.h"
|
||||
#include "chip/kl_osc.h"
|
||||
#include "chip/kl_fmc.h"
|
||||
#include "chip/kl_llwu.h"
|
||||
#include "chip/kl_pinmux.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_portclocks
|
||||
*
|
||||
* Description:
|
||||
* Enable all of the port clocks
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void kl_portclocks(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Enable all of the port clocks */
|
||||
|
||||
regval = getreg32(KL_SIM_SCGC5);
|
||||
regval |= (SIM_SCGC5_PORTA | SIM_SCGC5_PORTB | SIM_SCGC5_PORTC |
|
||||
SIM_SCGC5_PORTD | SIM_SCGC5_PORTE);
|
||||
putreg32(regval, KL_SIM_SCGC5);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_pllconfig
|
||||
*
|
||||
* Description:
|
||||
* Initialize the PLL using the settings in board.h. This assumes that
|
||||
* the MCG is in default FLL Engaged Internal (FEI mode) out of reset.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void kl_pllconfig(void)
|
||||
{
|
||||
uint32_t regval32;
|
||||
uint8_t regval8;
|
||||
|
||||
/* Enable clock gate to Port A module to enable pin routing (PORTA=1) */
|
||||
regval32 = getreg32(KL_SIM_SCGC5);
|
||||
regval32 |= SIM_SCGC5_PORTA;
|
||||
putreg32(regval32, KL_SIM_SCGC5);
|
||||
|
||||
/* Divide-by-2 for clock 1 and clock 4 (OUTDIV1=1, OUTDIV4=1) */
|
||||
regval32 = (SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV4(1));
|
||||
putreg32(regval32, KL_SIM_CLKDIV1);
|
||||
|
||||
/* System oscillator drives 32 kHz clock for various peripherals (OSC32KSEL=0) */
|
||||
regval32 = getreg32(KL_SIM_SOPT1);
|
||||
regval32 &= ~(SIM_SOPT1_OSC32KSEL);
|
||||
putreg32(regval32, KL_SIM_SOPT1);
|
||||
|
||||
/* Select PLL as a clock source for various peripherals (PLLFLLSEL=1)
|
||||
Clock source for TPM counter clock is MCGFLLCLK or MCGPLLCLK/2 */
|
||||
regval32 = getreg32(KL_SIM_SOPT2);
|
||||
regval32 |= SIM_SOPT2_PLLFLLSEL;
|
||||
putreg32(regval32, KL_SIM_SOPT2);
|
||||
regval32 = (regval32 & ~(SIM_SOPT2_TPMSRC_OCSERCLK)) | SIM_SOPT2_TPMSRC_MCGCLK;
|
||||
putreg32(regval32, KL_SIM_SOPT2);
|
||||
|
||||
/* PORTA_PCR18: ISF=0,MUX=0 */
|
||||
/* PORTA_PCR19: ISF=0,MUX=0 */
|
||||
regval32 = getreg32(KL_PORTA_PCR18);
|
||||
regval32 = ~(PORT_PCR_ISF | PORT_PCR_MUX_ALT7);
|
||||
putreg32(regval32, KL_PORTA_PCR18);
|
||||
regval32 = getreg32(KL_PORTA_PCR19);
|
||||
regval32 = ~(PORT_PCR_ISF | PORT_PCR_MUX_ALT7);
|
||||
putreg32(regval32, KL_PORTA_PCR19);
|
||||
|
||||
/* Switch to FBE Mode */
|
||||
/* OSC0_CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
putreg8(0, KL_OSC_CR);
|
||||
/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
|
||||
regval8 = (MCG_C2_RANGE_VHIGH | MCG_C2_EREFS);
|
||||
putreg8(regval8, KL_MCG_C2);
|
||||
/* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
|
||||
regval8 = (MCG_C1_CLKS_EXTREF | MCG_C1_FRDIV_R0DIV8);
|
||||
putreg8(regval8, KL_MCG_C1);
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0 */
|
||||
regval8 = ~(MCG_C4_DMX32 | MCG_C4_DRST_DRS_HIGH);
|
||||
putreg8(regval8, KL_MCG_C4);
|
||||
/* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
|
||||
regval8 = MCG_C5_PRDIV(1);
|
||||
putreg8(regval8, KL_MCG_C5);
|
||||
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||
putreg8(0, KL_MCG_C6);
|
||||
|
||||
/* Check that the source of the FLL reference clock is
|
||||
the external reference clock. */
|
||||
while((getreg8(KL_MCG_S) & MCG_S_IREFST) != 0)
|
||||
;
|
||||
|
||||
/* Wait until external reference */
|
||||
while((getreg8(KL_MCG_S) & MCG_S_CLKST_MASK) != 8)
|
||||
;
|
||||
|
||||
/* Switch to PBE mode
|
||||
Select PLL as MCG source (PLLS=1) */
|
||||
putreg8(MCG_C6_PLLS, KL_MCG_C6);
|
||||
/* Wait until PLL locked */
|
||||
while((getreg8(KL_MCG_S) & MCG_S_LOCK) == 0)
|
||||
;
|
||||
|
||||
/* Switch to PEE mode
|
||||
Select PLL output (CLKS=0)
|
||||
FLL external reference divider (FRDIV=3)
|
||||
External reference clock for FLL (IREFS=0) */
|
||||
putreg8(MCG_C1_FRDIV_R0DIV8, KL_MCG_C1);
|
||||
|
||||
/* Wait until PLL output */
|
||||
while((getreg8(KL_MCG_S) & MCG_S_CLKST_MASK) != 0x0C)
|
||||
;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_clockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to initialize the Kinetis chip. This does whatever setup is
|
||||
* needed to put the MCU in a usable state. This includes the
|
||||
* initialization of clocking using the settings in board.h.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void kl_clockconfig(void)
|
||||
{
|
||||
/* Enable all of the port clocks */
|
||||
|
||||
//kl_portclocks();
|
||||
|
||||
/* Configure the PLL based on settings in the board.h file */
|
||||
|
||||
kl_pllconfig();
|
||||
|
||||
/* For debugging, we will normally want to enable the trace clock and/or
|
||||
* the FlexBus clock.
|
||||
*/
|
||||
|
||||
//kl_traceconfig();
|
||||
//kl_fbconfig();
|
||||
}
|
||||
|
||||
@@ -0,0 +1,235 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/kl/kl_config.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KINETISXX_KL_CONFIG_H
|
||||
#define __ARCH_ARM_SRC_KINETISXX_KL_CONFIG_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Configuration *********************************************************************/
|
||||
/* Make that no unsupport UARTs are enabled */
|
||||
|
||||
#ifndef KL_NISO7816
|
||||
# define KL_NISO7816 0
|
||||
#endif
|
||||
|
||||
#if (KL_NISO7816 + KL_NUART) < 6
|
||||
# undef CONFIG_KL_UART5
|
||||
# if (KL_NISO7816 + KL_NUART) < 5
|
||||
# undef CONFIG_KL_UART4
|
||||
# if (KL_NISO7816 + KL_NUART) < 4
|
||||
# undef CONFIG_KL_UART3
|
||||
# if (KL_NISO7816 + KL_NUART) < 3
|
||||
# undef CONFIG_KL_UART2
|
||||
# if (KL_NISO7816 + KL_NUART) < 2
|
||||
# undef CONFIG_KL_UART1
|
||||
# if (KL_NISO7816 + KL_NUART) < 1
|
||||
# undef CONFIG_KL_UART0
|
||||
# endif
|
||||
# endif
|
||||
# endif
|
||||
# endif
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Are any UARTs enabled? */
|
||||
|
||||
#undef HAVE_UART_DEVICE
|
||||
#if defined(CONFIG_KL_UART0) || defined(CONFIG_KL_UART1) || \
|
||||
defined(CONFIG_KL_UART2) || defined(CONFIG_KL_UART3) || \
|
||||
defined(CONFIG_KL_UART5)
|
||||
# define HAVE_UART_DEVICE 1
|
||||
#endif
|
||||
|
||||
/* Is there a serial console? There should be at most one defined. It could be on
|
||||
* any UARTn, n=0,1,2,3,4,5
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_KL_UART0)
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_KL_UART1)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_KL_UART2)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_KL_UART3)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_KL_UART4)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_KL_UART5)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
#else
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# undef HAVE_SERIAL_CONSOLE
|
||||
#endif
|
||||
|
||||
/* Check UART flow control (Not yet supported) */
|
||||
|
||||
# undef CONFIG_UART0_FLOWCONTROL
|
||||
# undef CONFIG_UART1_FLOWCONTROL
|
||||
# undef CONFIG_UART2_FLOWCONTROL
|
||||
# undef CONFIG_UART3_FLOWCONTROL
|
||||
# undef CONFIG_UART4_FLOWCONTROL
|
||||
# undef CONFIG_UART5_FLOWCONTROL
|
||||
|
||||
/* UART FIFO support is not fully implemented.
|
||||
*
|
||||
* NOTE: UART0 has an 8-byte deep FIFO; the other UARTs have no FIFOs
|
||||
* (1-deep). There appears to be no way to know when the FIFO is not
|
||||
* full (other than reading the FIFO length and comparing the FIFO count).
|
||||
* Hence, the FIFOs are not used in this implementation and, as a result
|
||||
* TDRE indeed mean that the single output buffer is available.
|
||||
*
|
||||
* Performance on UART0 could be improved by enabling the FIFO and by
|
||||
* redesigning all of the FIFO status logic.
|
||||
*/
|
||||
|
||||
#undef CONFIG_KL_UARTFIFOS
|
||||
|
||||
/* UART Default Interrupt Priorities */
|
||||
|
||||
#ifndef CONFIG_KL_UART0PRIO
|
||||
# define CONFIG_KL_UART0PRIO NVIC_SYSH_PRIORITY_DEFAULT
|
||||
#endif
|
||||
#ifndef CONFIG_KL_UART1PRIO
|
||||
# define CONFIG_KL_UART1PRIO NVIC_SYSH_PRIORITY_DEFAULT
|
||||
#endif
|
||||
#ifndef CONFIG_KL_UART2PRIO
|
||||
# define CONFIG_KL_UART2PRIO NVIC_SYSH_PRIORITY_DEFAULT
|
||||
#endif
|
||||
#ifndef CONFIG_KL_UART3PRIO
|
||||
# define CONFIG_KL_UART3PRIO NVIC_SYSH_PRIORITY_DEFAULT
|
||||
#endif
|
||||
#ifndef CONFIG_KL_UART4PRIO
|
||||
# define CONFIG_KL_UART4PRIO NVIC_SYSH_PRIORITY_DEFAULT
|
||||
#endif
|
||||
#ifndef CONFIG_KL_UART5PRIO
|
||||
# define CONFIG_KL_UART5PRIO NVIC_SYSH_PRIORITY_DEFAULT
|
||||
#endif
|
||||
|
||||
/* Ethernet controller configuration */
|
||||
|
||||
#ifndef CONFIG_ENET_NRXBUFFERS
|
||||
# define CONFIG_ENET_NRXBUFFERS 6
|
||||
#endif
|
||||
#ifndef CONFIG_ENET_NTXBUFFERS
|
||||
# define CONFIG_ENET_NTXBUFFERS 2
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_ENET_PHYADDR
|
||||
# define CONFIG_ENET_PHYADDR 1
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_ENET_NETHIFS
|
||||
# define CONFIG_ENET_NETHIFS 1
|
||||
#endif
|
||||
|
||||
/* EMAC Default Interrupt Priorities */
|
||||
|
||||
#ifndef CONFIG_KL_EMACTMR_PRIO
|
||||
# define CONFIG_KL_EMACTMR_PRIO NVIC_SYSH_PRIORITY_DEFAULT
|
||||
#endif
|
||||
#ifndef CONFIG_KL_EMACTX_PRIO
|
||||
# define CONFIG_KL_EMACTX_PRIO NVIC_SYSH_PRIORITY_DEFAULT
|
||||
#endif
|
||||
#ifndef CONFIG_KL_EMACRX_PRIO
|
||||
# define CONFIG_KL_EMACRX_PRIO NVIC_SYSH_PRIORITY_DEFAULT
|
||||
#endif
|
||||
#ifndef CONFIG_KL_EMACMISC_PRIO
|
||||
# define CONFIG_KL_EMACMISC_PRIO NVIC_SYSH_PRIORITY_DEFAULT
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KINETISXX_KL_CONFIG_H */
|
||||
@@ -0,0 +1,143 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/kl/kl_gpio.c
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
#include "kl_gpio.h"
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
/* Port letters for prettier debug output */
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
static const char g_portchar[KL_GPIO_NPORTS] =
|
||||
{
|
||||
#if KL_GPIO_NPORTS > 9
|
||||
# error "Additional support required for this number of GPIOs"
|
||||
#elif KL_GPIO_NPORTS > 8
|
||||
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I'
|
||||
#elif KL_GPIO_NPORTS > 7
|
||||
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H'
|
||||
#elif KL_GPIO_NPORTS > 6
|
||||
'A', 'B', 'C', 'D', 'E', 'F', 'G'
|
||||
#elif KL_GPIO_NPORTS > 5
|
||||
'A', 'B', 'C', 'D', 'E', 'F'
|
||||
#elif KL_GPIO_NPORTS > 4
|
||||
'A', 'B', 'C', 'D', 'E'
|
||||
#elif KL_GPIO_NPORTS > 3
|
||||
'A', 'B', 'C', 'D'
|
||||
#elif KL_GPIO_NPORTS > 2
|
||||
'A', 'B', 'C'
|
||||
#elif KL_GPIO_NPORTS > 1
|
||||
'A', 'B'
|
||||
#elif KL_GPIO_NPORTS > 0
|
||||
'A'
|
||||
#else
|
||||
# error "Bad number of GPIOs"
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Function: kl_dumpgpio
|
||||
*
|
||||
* Description:
|
||||
* Dump all GPIO registers associated with the provided pin description
|
||||
* along with a descriptive messasge.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void kl_dumpgpio(gpio_cfgset_t pinset, const char *msg)
|
||||
{
|
||||
irqstate_t flags;
|
||||
uintptr_t base;
|
||||
int port;
|
||||
|
||||
/* Decode the port and pin. Use the port number to get the GPIO base
|
||||
* address.
|
||||
*/
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
DEBUGASSERT((unsigned)port <= KL_GPIO_PORTE);
|
||||
base = KL_GPIO_CTRL_BASE(port);
|
||||
|
||||
/* The following requires exclusive access to the GPIO registers */
|
||||
|
||||
flags = irqsave();
|
||||
|
||||
lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
|
||||
g_portchar[port], pinset, base, msg);
|
||||
lldbg(" PMD: %08x OFFD: %08x DOUT: %08x DMASK: %08x\n",
|
||||
getreg32(base + KL_GPIO_PMD_OFFSET),
|
||||
getreg32(base + KL_GPIO_OFFD_OFFSET),
|
||||
getreg32(base + KL_GPIO_DOUT_OFFSET),
|
||||
getreg32(base + KL_GPIO_DMASK_OFFSET));
|
||||
lldbg(" PIN: %08x DBEN: %08x IMD: %08x IEN: %08x\n",
|
||||
getreg32(base + KL_GPIO_PIN_OFFSET),
|
||||
getreg32(base + KL_GPIO_DBEN_OFFSET),
|
||||
getreg32(base + KL_GPIO_IMD_OFFSET),
|
||||
getreg32(base + KL_GPIO_IEN_OFFSET));
|
||||
lldbg(" ISRC: %08x\n",
|
||||
getreg32(base + KL_GPIO_ISRC_OFFSET));
|
||||
|
||||
irqrestore(flags);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_DEBUG */
|
||||
@@ -0,0 +1,309 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/kl/kl_gpio.c
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <arch/kl/chip.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/kl_gpio.h"
|
||||
|
||||
#include "kl_gpio.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_configgpio
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin based on bit-encoded description of the pin.
|
||||
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
|
||||
* function, it must be unconfigured with kl_unconfiggpio() with
|
||||
* the same cfgset first before it can be set to non-alternative function.
|
||||
*
|
||||
* Returns:
|
||||
* OK on success
|
||||
* ERROR on invalid port, or when pin is locked as ALT function.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int kl_configgpio(gpio_cfgset_t cfgset)
|
||||
{
|
||||
uintptr_t base;
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
uint32_t isrc;
|
||||
uint32_t imd;
|
||||
uint32_t ien;
|
||||
uint32_t value;
|
||||
int port;
|
||||
int pin;
|
||||
|
||||
/* Decode the port and pin. Use the port number to get the GPIO base
|
||||
* address.
|
||||
*/
|
||||
|
||||
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
|
||||
DEBUGASSERT((unsigned)port <= KL_GPIO_PORTE);
|
||||
base = KL_GPIO_CTRL_BASE(port);
|
||||
|
||||
/* Set the the GPIO PMD register */
|
||||
|
||||
regaddr = base + KL_GPIO_PMD_OFFSET;
|
||||
regval = getreg32(regaddr);
|
||||
regval &= ~GPIO_PMD_MASK(pin);
|
||||
|
||||
switch (cfgset & GPIO_MODE_MASK)
|
||||
{
|
||||
default:
|
||||
case GPIO_INPUT: /* Input */
|
||||
value = GPIO_PMD_INPUT;
|
||||
break;
|
||||
|
||||
case GPIO_OUTPUT: /* Push-pull output */
|
||||
value = GPIO_PMD_OUTPUT;
|
||||
break;
|
||||
|
||||
case GPIO_OPENDRAIN: /* Open drain output */
|
||||
value = GPIO_PMD_OPENDRAIN;
|
||||
break;
|
||||
|
||||
case GPIO_BIDI: /* Quasi bi-directional */
|
||||
value = GPIO_PMD_BIDI;
|
||||
break;
|
||||
}
|
||||
|
||||
regval |= GPIO_PMD(pin, value);
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
/* Check if we need to disable the digital input path */
|
||||
|
||||
regaddr = base + KL_GPIO_OFFD_OFFSET;
|
||||
regval = getreg32(regaddr);
|
||||
regval &= ~GPIO_OFFD(pin);
|
||||
|
||||
if ((cfgset & GPIO_ANALOG) != 0)
|
||||
{
|
||||
regval |= GPIO_OFFD(pin);
|
||||
}
|
||||
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
/* Check if we need to enable debouncing */
|
||||
|
||||
regaddr = base + KL_GPIO_DBEN_OFFSET;
|
||||
regval = getreg32(regaddr);
|
||||
regval &= ~GPIO_DBEN(pin);
|
||||
|
||||
if ((cfgset & GPIO_DEBOUNCE) != 0)
|
||||
{
|
||||
regval |= GPIO_DBEN(pin);
|
||||
}
|
||||
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
/* Configure interrupting pins */
|
||||
|
||||
isrc = getreg32(base + KL_GPIO_ISRC_OFFSET);
|
||||
isrc &= ~GPIO_ISRC(pin);
|
||||
|
||||
imd = getreg32(base + KL_GPIO_IMD_OFFSET);
|
||||
imd &= ~GPIO_IMD(pin);
|
||||
|
||||
ien = getreg32(base + KL_GPIO_IEN_OFFSET);
|
||||
ien &= ~(GPIO_IF_EN(pin) | GPIO_IR_EN(pin));
|
||||
|
||||
switch (cfgset & GPIO_INTERRUPT_MASK)
|
||||
{
|
||||
case GPIO_INTERRUPT_RISING_EDGE:
|
||||
isrc |= GPIO_ISRC(pin);
|
||||
ien |= GPIO_IR_EN(pin);
|
||||
break;
|
||||
|
||||
case GPIO_INTERRUPT_FALLING_EDGE:
|
||||
isrc |= GPIO_ISRC(pin);
|
||||
ien |= GPIO_IF_EN(pin);
|
||||
break;
|
||||
|
||||
case GPIO_INTERRUPT_BOTH_EDGES:
|
||||
isrc |= GPIO_ISRC(pin);
|
||||
ien |= (GPIO_IF_EN(pin) | GPIO_IR_EN(pin));
|
||||
break;
|
||||
|
||||
case GPIO_INTERRUPT_HIGH_LEVEL:
|
||||
isrc |= GPIO_ISRC(pin);
|
||||
imd |= GPIO_IMD(pin);
|
||||
ien |= GPIO_IR_EN(pin);
|
||||
break;
|
||||
|
||||
case GPIO_INTERRUPT_LOW_LEVEL:
|
||||
isrc |= GPIO_ISRC(pin);
|
||||
imd |= GPIO_IMD(pin);
|
||||
ien |= GPIO_IF_EN(pin);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
putreg32(ien, base + KL_GPIO_IEN_OFFSET);
|
||||
putreg32(imd, base + KL_GPIO_IMD_OFFSET);
|
||||
putreg32(isrc, base + KL_GPIO_ISRC_OFFSET);
|
||||
|
||||
/* If the pin is an output, set the initial output value */
|
||||
|
||||
if ((cfgset & GPIO_MODE_MASK) == GPIO_OUTPUT)
|
||||
{
|
||||
kl_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_gpiowrite
|
||||
*
|
||||
* Description:
|
||||
* Write one or zero to the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void kl_gpiowrite(gpio_cfgset_t pinset, bool value)
|
||||
{
|
||||
#ifndef KL_LOW
|
||||
irqstate_t flags;
|
||||
uintptr_t base;
|
||||
#endif
|
||||
int port;
|
||||
int pin;
|
||||
|
||||
/* Decode the port and pin. Use the port number to get the GPIO base
|
||||
* address.
|
||||
*/
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
|
||||
DEBUGASSERT((unsigned)port <= KL_GPIO_PORTE);
|
||||
|
||||
/* Only the low density K25Z100/120 chips support bit-band access to GPIO
|
||||
* pins.
|
||||
*/
|
||||
|
||||
#ifdef KL_LOW
|
||||
putreg32((uint32_t)value, KL_PORT_PDIO(port, pin));
|
||||
#else
|
||||
/* Get the base address of the GPIO port registers */
|
||||
|
||||
base = KL_GPIO_CTRL_BASE(port);
|
||||
|
||||
/* Disable interrupts -- the following operations must be atomic */
|
||||
|
||||
flags = irqsave();
|
||||
|
||||
/* Allow writing only to the selected pin in the DOUT register */
|
||||
|
||||
putreg32(~(1 << pin), base + KL_GPIO_DMASK_OFFSET);
|
||||
|
||||
/* Set the pin to the selected value and re-enable interrupts */
|
||||
|
||||
putreg32(((uint32_t)value << pin), base + KL_GPIO_DOUT_OFFSET);
|
||||
irqrestore(flags);
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_gpioread
|
||||
*
|
||||
* Description:
|
||||
* Read one or zero from the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool kl_gpioread(gpio_cfgset_t pinset)
|
||||
{
|
||||
#ifndef KL_LOW
|
||||
uintptr_t base;
|
||||
#endif
|
||||
int port;
|
||||
int pin;
|
||||
|
||||
/* Decode the port and pin. Use the port number to get the GPIO base
|
||||
* address.
|
||||
*/
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
|
||||
DEBUGASSERT((unsigned)port <= KL_GPIO_PORTE);
|
||||
|
||||
/* Only the low density K25Z100/120 chips support bit-band access to GPIO
|
||||
* pins.
|
||||
*/
|
||||
|
||||
#ifdef KL_LOW
|
||||
return (getreg32(KL_PORT_PDIO(port, pin)) & PORT_MASK) != 0;
|
||||
#else
|
||||
/* Get the base address of the GPIO port registers */
|
||||
|
||||
base = KL_GPIO_CTRL_BASE(port);
|
||||
|
||||
/* Return the state of the selected pin */
|
||||
|
||||
return (getreg32(base + KL_GPIO_PIN_OFFSET) & (1 << pin)) != 0;
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,259 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/kl/kl_gpio.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KL_KINETIS_GPIO_H
|
||||
#define __ARCH_ARM_SRC_KL_KINETIS_GPIO_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
# include <stdbool.h>
|
||||
#endif
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/kl_gpio.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Declarations
|
||||
****************************************************************************/
|
||||
|
||||
/* Bit-encoded input to kl_configgpio() */
|
||||
|
||||
/* 16-bit Encoding:
|
||||
*
|
||||
* 1111 1100 0000 0000
|
||||
* 5432 1098 7654 3210
|
||||
* ---- ---- ---- ----
|
||||
* MMAD III. VPPP BBBB
|
||||
*/
|
||||
|
||||
/* GPIO mode:
|
||||
*
|
||||
* 1111 1100 0000 0000
|
||||
* 5432 1098 7654 3210
|
||||
* ---- ---- ---- ----
|
||||
* MM.. .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_MODE_SHIFT (14) /* Bits 14-15: GPIO mode */
|
||||
#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT)
|
||||
# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input */
|
||||
# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* Push-pull output */
|
||||
# define GPIO_OPENDRAIN (2 << GPIO_MODE_SHIFT) /* Open drain output */
|
||||
# define GPIO_BIDI (3 << GPIO_MODE_SHIFT) /* Quasi bi-directional */
|
||||
|
||||
/* GPIO analog: If the pin is an analog input, then it would be necessary to
|
||||
* disable the digital input
|
||||
*
|
||||
* 1111 1100 0000 0000
|
||||
* 5432 1098 7654 3210
|
||||
* ---- ---- ---- ----
|
||||
* ..A. .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_ANALOG (1 << 13) /* Bit 13: Disable digital input */
|
||||
|
||||
/* De-bounce enable:
|
||||
*
|
||||
* 1111 1100 0000 0000
|
||||
* 5432 1098 7654 3210
|
||||
* ---- ---- ---- ----
|
||||
* ...D .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_DEBOUNCE (1 << 12) /* Bit 12: Debounce enable */
|
||||
|
||||
/* Interrupt Controls:
|
||||
*
|
||||
* 1111 1100 0000 0000
|
||||
* 5432 1098 7654 3210
|
||||
* ---- ---- ---- ----
|
||||
* .... III. .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_INTERRUPT_SHIFT (9) /* Bits 9-11: Interrupt controls */
|
||||
#define GPIO_INTERRUPT_MASK (7 << GPIO_INTERRUPT_SHIFT)
|
||||
# define GPIO_INTERRUPT_NONE (0 << GPIO_INTERRUPT_SHIFT)
|
||||
# define GPIO_INTERRUPT_RISING_EDGE (1 << GPIO_INTERRUPT_SHIFT)
|
||||
# define GPIO_INTERRUPT_FALLING_EDGE (2 << GPIO_INTERRUPT_SHIFT)
|
||||
# define GPIO_INTERRUPT_BOTH_EDGES (3 << GPIO_INTERRUPT_SHIFT)
|
||||
# define GPIO_INTERRUPT_HIGH_LEVEL (4 << GPIO_INTERRUPT_SHIFT)
|
||||
# define GPIO_INTERRUPT_LOW_LEVEL (5 << GPIO_INTERRUPT_SHIFT)
|
||||
|
||||
/* If the pin is a GPIO digital output, then this identifies the initial output value.
|
||||
*
|
||||
* 1111 1100 0000 0000
|
||||
* 5432 1098 7654 3210
|
||||
* ---- ---- ---- ----
|
||||
* .... .... V... ....
|
||||
*/
|
||||
|
||||
#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: If output, inital value of output */
|
||||
#define GPIO_OUTPUT_CLEAR (0)
|
||||
|
||||
/* This identifies the GPIO port:
|
||||
*
|
||||
* 1111 1100 0000 0000
|
||||
* 5432 1098 7654 3210
|
||||
* ---- ---- ---- ----
|
||||
* .... .... .PPP ....
|
||||
*/
|
||||
|
||||
#define GPIO_PORT_SHIFT 4 /* Bit 4-6: Port number */
|
||||
#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */
|
||||
# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */
|
||||
# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */
|
||||
# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
|
||||
# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */
|
||||
#
|
||||
|
||||
/* This identifies the bit in the port:
|
||||
*
|
||||
* 1111 1100 0000 0000
|
||||
* 5432 1098 7654 3210
|
||||
* ---- ---- ---- ----
|
||||
* .... .... .... BBBB
|
||||
*/
|
||||
|
||||
#define GPIO_PIN_SHIFT 0 /* Bits 0-3: GPIO number: 0-15 */
|
||||
#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
typedef uint16_t gpio_cfgset_t;
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_configgpio
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin based on bit-encoded description of the pin.
|
||||
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
|
||||
* function, it must be unconfigured with kl_unconfiggpio() with
|
||||
* the same cfgset first before it can be set to non-alternative function.
|
||||
*
|
||||
* Returns:
|
||||
* OK on success
|
||||
* ERROR on invalid port, or when pin is locked as ALT function.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int kl_configgpio(gpio_cfgset_t cfgset);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_gpiowrite
|
||||
*
|
||||
* Description:
|
||||
* Write one or zero to the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void kl_gpiowrite(gpio_cfgset_t pinset, bool value);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_gpioread
|
||||
*
|
||||
* Description:
|
||||
* Read one or zero from the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool kl_gpioread(gpio_cfgset_t pinset);
|
||||
|
||||
/****************************************************************************
|
||||
* Function: kl_dumpgpio
|
||||
*
|
||||
* Description:
|
||||
* Dump all GPIO registers associated with the provided pin description
|
||||
* along with a descriptive messasge.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
void kl_dumpgpio(gpio_cfgset_t pinset, const char *msg);
|
||||
#else
|
||||
# define kl_dumpgpio(p,m)
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_KL_KINETIS_GPIO_H */
|
||||
@@ -0,0 +1,187 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32/kl_idle.c
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/power/pm.h>
|
||||
|
||||
#include <arch/irq.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Does the board support an IDLE LED to indicate that the board is in the
|
||||
* IDLE state?
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
|
||||
# define BEGIN_IDLE() up_ledon(LED_IDLE)
|
||||
# define END_IDLE() up_ledoff(LED_IDLE)
|
||||
#else
|
||||
# define BEGIN_IDLE()
|
||||
# define END_IDLE()
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_idlepm
|
||||
*
|
||||
* Description:
|
||||
* Perform IDLE state power management.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static void up_idlepm(void)
|
||||
{
|
||||
static enum pm_state_e oldstate = PM_NORMAL;
|
||||
enum pm_state_e newstate;
|
||||
irqstate_t flags;
|
||||
int ret;
|
||||
|
||||
/* Decide, which power saving level can be obtained */
|
||||
|
||||
newstate = pm_checkstate();
|
||||
|
||||
/* Check for state changes */
|
||||
|
||||
if (newstate != oldstate)
|
||||
{
|
||||
flags = irqsave();
|
||||
|
||||
/* Perform board-specific, state-dependent logic here */
|
||||
|
||||
llvdbg("newstate= %d oldstate=%d\n", newstate, oldstate);
|
||||
|
||||
/* Then force the global state change */
|
||||
|
||||
ret = pm_changestate(newstate);
|
||||
if (ret < 0)
|
||||
{
|
||||
/* The new state change failed, revert to the preceding state */
|
||||
|
||||
(void)pm_changestate(oldstate);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Save the new state */
|
||||
|
||||
oldstate = newstate;
|
||||
}
|
||||
|
||||
/* MCU-specific power management logic */
|
||||
|
||||
switch (newstate)
|
||||
{
|
||||
case PM_NORMAL:
|
||||
break;
|
||||
|
||||
case PM_IDLE:
|
||||
break;
|
||||
|
||||
case PM_STANDBY:
|
||||
kl_pmstop(true);
|
||||
break;
|
||||
|
||||
case PM_SLEEP:
|
||||
(void)kl_pmstandby();
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
irqrestore(flags);
|
||||
}
|
||||
}
|
||||
#else
|
||||
# define up_idlepm()
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_idle
|
||||
*
|
||||
* Description:
|
||||
* up_idle() is the logic that will be executed when their is no other
|
||||
* ready-to-run task. This is processor idle time and will continue until
|
||||
* some interrupt occurs to cause a context switch from the idle task.
|
||||
*
|
||||
* Processing in this state may be processor-specific. e.g., this is where
|
||||
* power management operations might be performed.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_idle(void)
|
||||
{
|
||||
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
|
||||
/* If the system is idle and there are no timer interrupts, then process
|
||||
* "fake" timer interrupts. Hopefully, something will wake up.
|
||||
*/
|
||||
|
||||
sched_process_timer();
|
||||
#else
|
||||
|
||||
/* Perform IDLE mode power management */
|
||||
|
||||
up_idlepm();
|
||||
|
||||
/* Sleep until an interrupt occurs to save power. */
|
||||
|
||||
BEGIN_IDLE();
|
||||
asm("WFI");
|
||||
END_IDLE();
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,435 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32/kl_irq.c
|
||||
* arch/arm/src/chip/kl_irq.c
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/irq.h>
|
||||
|
||||
#include "nvic.h"
|
||||
#include "up_arch.h"
|
||||
#include "os_internal.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
#include "kl_irq.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Get a 32-bit version of the default priority */
|
||||
|
||||
#define DEFPRIORITY32 \
|
||||
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 |\
|
||||
NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
volatile uint32_t *current_regs;
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_dumpnvic
|
||||
*
|
||||
* Description:
|
||||
* Dump some interesting NVIC registers
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_DEBUG_IRQ) && defined (CONFIG_DEBUG)
|
||||
static void kl_dumpnvic(const char *msg, int irq)
|
||||
{
|
||||
irqstate_t flags;
|
||||
|
||||
flags = irqsave();
|
||||
|
||||
slldbg("NVIC (%s, irq=%d):\n", msg, irq);
|
||||
slldbg(" ISER: %08x ICER: %08x\n",
|
||||
getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
|
||||
slldbg(" ISPR: %08x ICPR: %08x\n",
|
||||
getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
|
||||
slldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
|
||||
getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
|
||||
getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
|
||||
slldbg(" %08x %08x %08x %08x\n",
|
||||
getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
|
||||
getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
|
||||
|
||||
slldbg("SYSCON:\n");
|
||||
slldbg(" CPUID: %08x\n",
|
||||
getreg32(ARMV6M_SYSCON_CPUID));
|
||||
slldbg(" ICSR: %08x AIRCR: %08x\n",
|
||||
getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
|
||||
slldbg(" SCR: %08x CCR: %08x\n",
|
||||
getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
|
||||
slldbg(" SHPR2: %08x SHPR3: %08x\n",
|
||||
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
|
||||
|
||||
irqrestore(flags);
|
||||
}
|
||||
|
||||
#else
|
||||
# define kl_dumpnvic(msg, irq)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_nmi, kl_busfault, kl_usagefault, kl_pendsv,
|
||||
* kl_dbgmonitor, kl_pendsv, kl_reserved
|
||||
*
|
||||
* Description:
|
||||
* Handlers for various execptions. None are handled and all are fatal
|
||||
* error conditions. The only advantage these provided over the default
|
||||
* unexpected interrupt handler is that they provide a diagnostic output.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
static int kl_nmi(int irq, FAR void *context)
|
||||
{
|
||||
(void)irqsave();
|
||||
dbg("PANIC!!! NMI received\n");
|
||||
PANIC(OSERR_UNEXPECTEDISR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int kl_pendsv(int irq, FAR void *context)
|
||||
{
|
||||
(void)irqsave();
|
||||
dbg("PANIC!!! PendSV received\n");
|
||||
PANIC(OSERR_UNEXPECTEDISR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int kl_reserved(int irq, FAR void *context)
|
||||
{
|
||||
(void)irqsave();
|
||||
dbg("PANIC!!! Reserved interrupt\n");
|
||||
PANIC(OSERR_UNEXPECTEDISR);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_prioritize_syscall
|
||||
*
|
||||
* Description:
|
||||
* Set the priority of an exception. This function may be needed
|
||||
* internally even if support for prioritized interrupts is not enabled.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void kl_prioritize_syscall(int priority)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* SVCALL is system handler 11 */
|
||||
|
||||
regval = getreg32(ARMV6M_SYSCON_SHPR2);
|
||||
regval &= ~SYSCON_SHPR2_PRI_11_MASK;
|
||||
regval |= (priority << SYSCON_SHPR2_PRI_11_SHIFT);
|
||||
putreg32(regval, ARMV6M_SYSCON_SHPR2);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_clrpend
|
||||
*
|
||||
* Description:
|
||||
* Clear a pending interrupt at the NVIC.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void kl_clrpend(int irq)
|
||||
{
|
||||
/* This will be called on each interrupt exit whether the interrupt can be
|
||||
* enambled or not. So this assertion is necessarily lame.
|
||||
*/
|
||||
|
||||
DEBUGASSERT((unsigned)irq < NR_IRQS);
|
||||
|
||||
/* Check for an external interrupt */
|
||||
|
||||
if (irq >= KL_IRQ_INTERRUPT && irq < KL_IRQ_INTERRUPT + 32)
|
||||
{
|
||||
/* Set the appropriate bit in the ISER register to enable the
|
||||
* interrupt
|
||||
*/
|
||||
|
||||
putreg32((1 << (irq - KL_IRQ_INTERRUPT)), ARMV6M_NVIC_ICPR);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_irqinitialize
|
||||
****************************************************************************/
|
||||
|
||||
void up_irqinitialize(void)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
int i;
|
||||
|
||||
/* Disable all interrupts */
|
||||
|
||||
putreg32(0xffffffff, ARMV6M_NVIC_ICER);
|
||||
|
||||
/* Set all interrupts (and exceptions) to the default priority */
|
||||
|
||||
putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR2);
|
||||
putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR3);
|
||||
|
||||
/* Now set all of the interrupt lines to the default priority */
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
regaddr = ARMV6M_NVIC_IPR(i);
|
||||
putreg32(DEFPRIORITY32, regaddr);
|
||||
}
|
||||
|
||||
/* currents_regs is non-NULL only while processing an interrupt */
|
||||
|
||||
current_regs = NULL;
|
||||
|
||||
/* Attach the SVCall and Hard Fault exception handlers. The SVCall
|
||||
* exception is used for performing context switches; The Hard Fault
|
||||
* must also be caught because a SVCall may show up as a Hard Fault
|
||||
* under certain conditions.
|
||||
*/
|
||||
|
||||
irq_attach(KL_IRQ_SVCALL, up_svcall);
|
||||
irq_attach(KL_IRQ_HARDFAULT, up_hardfault);
|
||||
|
||||
/* Set the priority of the SVCall interrupt */
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
/* up_prioritize_irq(KL_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
|
||||
#endif
|
||||
kl_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
|
||||
|
||||
/* Attach all other processor exceptions (except reset and sys tick) */
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
irq_attach(KL_IRQ_NMI, kl_nmi);
|
||||
irq_attach(KL_IRQ_PENDSV, kl_pendsv);
|
||||
irq_attach(KL_IRQ_RESERVED, kl_reserved);
|
||||
#endif
|
||||
|
||||
kl_dumpnvic("initial", NR_IRQS);
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_INTERRUPTS
|
||||
|
||||
/* And finally, enable interrupts */
|
||||
|
||||
irqenable();
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_disable_irq
|
||||
*
|
||||
* Description:
|
||||
* Disable the IRQ specified by 'irq'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_disable_irq(int irq)
|
||||
{
|
||||
/* This will be called on each interrupt (via up_maskack_irq()) whether
|
||||
* the interrupt can be disabled or not. So this assertion is necessarily
|
||||
* lame.
|
||||
*/
|
||||
|
||||
DEBUGASSERT((unsigned)irq < NR_IRQS);
|
||||
|
||||
/* Check for an external interrupt */
|
||||
|
||||
if (irq >= KL_IRQ_INTERRUPT && irq < KL_IRQ_INTERRUPT + 32)
|
||||
{
|
||||
/* Set the appropriate bit in the ICER register to disable the
|
||||
* interrupt
|
||||
*/
|
||||
|
||||
putreg32((1 << (irq - KL_IRQ_INTERRUPT)), ARMV6M_NVIC_ICER);
|
||||
}
|
||||
|
||||
/* Handle processor exceptions. Only SysTick can be disabled */
|
||||
|
||||
else if (irq == KL_IRQ_SYSTICK)
|
||||
{
|
||||
modifyreg32(ARMV6M_SYSTICK_CSR, SYSTICK_CSR_ENABLE, 0);
|
||||
}
|
||||
|
||||
kl_dumpnvic("disable", irq);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_enable_irq
|
||||
*
|
||||
* Description:
|
||||
* Enable the IRQ specified by 'irq'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_enable_irq(int irq)
|
||||
{
|
||||
/* This will be called on each interrupt exit whether the interrupt can be
|
||||
* enambled or not. So this assertion is necessarily lame.
|
||||
*/
|
||||
|
||||
DEBUGASSERT((unsigned)irq < NR_IRQS);
|
||||
|
||||
/* Check for external interrupt */
|
||||
|
||||
if (irq >= KL_IRQ_INTERRUPT && irq < KL_IRQ_INTERRUPT + 32)
|
||||
{
|
||||
/* Set the appropriate bit in the ISER register to enable the
|
||||
* interrupt
|
||||
*/
|
||||
|
||||
putreg32((1 << (irq - KL_IRQ_INTERRUPT)), ARMV6M_NVIC_ISER);
|
||||
}
|
||||
|
||||
/* Handle processor exceptions. Only SysTick can be disabled */
|
||||
|
||||
else if (irq == KL_IRQ_SYSTICK)
|
||||
{
|
||||
modifyreg32(ARMV6M_SYSTICK_CSR, 0, SYSTICK_CSR_ENABLE);
|
||||
}
|
||||
|
||||
kl_dumpnvic("enable", irq);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_maskack_irq
|
||||
*
|
||||
* Description:
|
||||
* Mask the IRQ and acknowledge it
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_maskack_irq(int irq)
|
||||
{
|
||||
up_disable_irq(irq);
|
||||
kl_clrpend(irq);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_prioritize_irq
|
||||
*
|
||||
* Description:
|
||||
* Set the priority of an IRQ.
|
||||
*
|
||||
* Since this API is not supported on all architectures, it should be
|
||||
* avoided in common implementations where possible.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
int up_prioritize_irq(int irq, int priority)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
DEBUGASSERT(irq == KL_IRQ_SVCALL ||
|
||||
irq == KL_IRQ_PENDSV ||
|
||||
irq == KL_IRQ_SYSTICK ||
|
||||
(irq >= KL_IRQ_INTERRUPT && irq < NR_IRQS));
|
||||
DEBUGASSERT(priority >= NVIC_SYSH_DISABLE_PRIORITY &&
|
||||
priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
|
||||
/* Check for external interrupt */
|
||||
|
||||
if (irq >= KL_IRQ_INTERRUPT && irq < KL_IRQ_INTERRUPT + 32)
|
||||
{
|
||||
/* ARMV6M_NVIC_IPR() maps register IPR0-IPR7 with four settings per
|
||||
* register.
|
||||
*/
|
||||
|
||||
regaddr = ARMV6M_NVIC_IPR(irq >> 2);
|
||||
shift = (irq & 3) << 3;
|
||||
}
|
||||
|
||||
/* Handle processor exceptions. Only SVCall, PendSV, and SysTick can be
|
||||
* reprioritized. And we will not permit modification of SVCall through
|
||||
* this function.
|
||||
*/
|
||||
|
||||
else if (irq == KL_IRQ_PENDSV)
|
||||
{
|
||||
regaddr = ARMV6M_SYSCON_SHPR2;
|
||||
shift = SYSCON_SHPR3_PRI_14_SHIFT;
|
||||
}
|
||||
else if (irq == KL_IRQ_SYSTICK)
|
||||
{
|
||||
regaddr = ARMV6M_SYSCON_SHPR2;
|
||||
shift = SYSCON_SHPR3_PRI_15_SHIFT;
|
||||
}
|
||||
else
|
||||
{
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/* Set the priority */
|
||||
|
||||
regval = getreg32(regaddr);
|
||||
regval &= ~((uint32_t)0xff << shift);
|
||||
regval |= ((uint32_t)priority << shift);
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
kl_dumpnvic("prioritize", irq);
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,65 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/kl/kl_irq.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KL_KINETIS_IRQ_H
|
||||
#define __ARCH_ARM_SRC_KL_KINETIS_IRQ_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KL_KINETIS_IRQ_H */
|
||||
@@ -0,0 +1,28 @@
|
||||
void blueled(int on)
|
||||
{
|
||||
volatile unsigned int *SIM_COPC = ((volatile unsigned int *)0x40048100);
|
||||
volatile unsigned int *SIM_SCGC5 = ((volatile unsigned int *)0x40048038);
|
||||
volatile unsigned int *PORTD_PCR1 = ((volatile unsigned int *)0x4004C004);
|
||||
volatile unsigned int *GPIOD_PSOR = ((volatile unsigned int *)0x400FF0C4);
|
||||
volatile unsigned int *GPIOD_PCOR = ((volatile unsigned int *)0x400FF0C8);
|
||||
volatile unsigned int *GPIOD_PDDR = ((volatile unsigned int *)0x400FF0D4);
|
||||
|
||||
/*acassis: disable SIM_COP*/
|
||||
*SIM_COPC = 0;
|
||||
|
||||
/* enable clocks for PORTD */
|
||||
*SIM_SCGC5 = 0x1000;
|
||||
|
||||
/* set D1 to GPIO */
|
||||
*PORTD_PCR1 = 0x100;
|
||||
|
||||
/* set D1 DDR to output */
|
||||
*GPIOD_PDDR |= 2;
|
||||
|
||||
if(on)
|
||||
*GPIOD_PCOR = 2;
|
||||
else
|
||||
*GPIOD_PSOR = 2;
|
||||
|
||||
}
|
||||
|
||||
@@ -0,0 +1,403 @@
|
||||
/**************************************************************************
|
||||
* arch/arm/src/kl/kl_lowputc.c
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Included Files
|
||||
**************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <arch/irq.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "kl_config.h"
|
||||
//#include "kl_lowputc.h"
|
||||
//#include "chip/kl_internal.h"
|
||||
#include "chip/kl_uart.h"
|
||||
#include "chip/kl_sim.h"
|
||||
#include "chip/kl_port.h"
|
||||
#include "chip/kl_uart.h"
|
||||
#include "chip/kl_pinmux.h"
|
||||
|
||||
|
||||
/**************************************************************************
|
||||
* Private Definitions
|
||||
**************************************************************************/
|
||||
|
||||
/* Select UART parameters for the selected console */
|
||||
|
||||
# define CONSOLE_BASE KL_UART0_BASE
|
||||
# define CONSOLE_FREQ 48000000
|
||||
# define CONSOLE_BAUD CONFIG_UART0_BAUD
|
||||
# define CONSOLE_BITS CONFIG_UART0_BITS
|
||||
# define CONSOLE_PARITY CONFIG_UART0_PARITY
|
||||
|
||||
/**************************************************************************
|
||||
* Private Types
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Private Function Prototypes
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Global Variables
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Private Variables
|
||||
**************************************************************************/
|
||||
|
||||
/* This array maps an encoded FIFO depth (index) to the actual size of the
|
||||
* FIFO (indexed value). NOTE: That there is no 8th value.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_KL_UARTFIFOS
|
||||
static uint8_t g_sizemap[8] = {1, 4, 8, 16, 32, 64, 128, 0};
|
||||
#endif
|
||||
|
||||
/**************************************************************************
|
||||
* Private Functions
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Public Functions
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Name: up_lowputc
|
||||
*
|
||||
* Description:
|
||||
* Output one byte on the serial console
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
void kl_lowputc(char ch)
|
||||
{
|
||||
#if defined HAVE_UART_DEVICE && defined HAVE_SERIAL_CONSOLE
|
||||
#ifdef CONFIG_KL_UARTFIFOS
|
||||
/* Wait until there is space in the TX FIFO: Read the number of bytes
|
||||
* currently in the FIFO and compare that to the size of the FIFO. If
|
||||
* there are fewer bytes in the FIFO than the size of the FIFO, then we
|
||||
* are able to transmit.
|
||||
*/
|
||||
|
||||
# error "Missing logic"
|
||||
#else
|
||||
/* Wait until the transmit data register is "empty" (TDRE). This state
|
||||
* depends on the TX watermark setting and may not mean that the transmit
|
||||
* buffer is truly empty. It just means that we can now add another
|
||||
* characterto the transmit buffer without exceeding the watermark.
|
||||
*
|
||||
* NOTE: UART0 has an 8-byte deep FIFO; the other UARTs have no FIFOs
|
||||
* (1-deep). There appears to be no way to know when the FIFO is not
|
||||
* full (other than reading the FIFO length and comparing the FIFO count).
|
||||
* Hence, the FIFOs are not used in this implementation and, as a result
|
||||
* TDRE indeed mean that the single output buffer is available.
|
||||
*
|
||||
* Performance on UART0 could be improved by enabling the FIFO and by
|
||||
* redesigning all of the FIFO status logic.
|
||||
*/
|
||||
|
||||
while ((getreg8(CONSOLE_BASE+KL_UART_S1_OFFSET) & UART_S1_TDRE) == 0);
|
||||
|
||||
#endif
|
||||
|
||||
/* Then write the character to the UART data register */
|
||||
|
||||
putreg8((uint8_t)ch, CONSOLE_BASE+KL_UART_D_OFFSET);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
* Name: kl_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* This performs basic initialization of the UART used for the serial
|
||||
* console. Its purpose is to get the console output availabe as soon
|
||||
* as possible.
|
||||
*
|
||||
**************************************************************************/
|
||||
void kl_lowsetup(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint8_t regval8;
|
||||
|
||||
//regval = getreg32(KL_SIM_SOPT2);
|
||||
//regval |= SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_UART0SRC_MCGCLK ;
|
||||
//putreg32(regval, KL_SIM_SOPT2);
|
||||
|
||||
regval = getreg32(KL_SIM_SCGC5);
|
||||
regval |= SIM_SCGC5_PORTA;
|
||||
putreg32(regval, KL_SIM_SCGC5);
|
||||
|
||||
regval = getreg32(KL_SIM_SCGC4);
|
||||
regval |= SIM_SCGC4_UART0;
|
||||
putreg32(regval, KL_SIM_SCGC4);
|
||||
|
||||
regval = getreg32(KL_SIM_SOPT2);
|
||||
regval &= ~(SIM_SOPT2_UART0SRC_MASK);
|
||||
putreg32(regval, KL_SIM_SOPT2);
|
||||
|
||||
regval = getreg32(KL_SIM_SOPT2);
|
||||
regval |= SIM_SOPT2_UART0SRC_MCGCLK;
|
||||
putreg32(regval, KL_SIM_SOPT2);
|
||||
|
||||
putreg32((PORT_PCR_MUX_ALT2), KL_PORTA_PCR1);
|
||||
putreg32((PORT_PCR_MUX_ALT2), KL_PORTA_PCR2);
|
||||
|
||||
/* Disable UART before changing registers */
|
||||
putreg8(0, KL_UART0_C2);
|
||||
putreg8(0, KL_UART0_C1);
|
||||
putreg8(0, KL_UART0_C3);
|
||||
putreg8(0, KL_UART0_S2);
|
||||
|
||||
// Set the baud rate divisor
|
||||
#define CORE_CLOCK 48000000
|
||||
#define OVER_SAMPLE 16
|
||||
uint16_t divisor = (CORE_CLOCK / OVER_SAMPLE) / CONSOLE_BAUD;
|
||||
regval8 = OVER_SAMPLE - 1;
|
||||
putreg8(regval8, KL_UART0_C4);
|
||||
|
||||
regval8 = (divisor >> 8) & UARTLP_BDH_SBR_MASK;
|
||||
putreg8(regval8, KL_UART0_BDH);
|
||||
|
||||
regval8 = (divisor & UARTLP_BDL_SBR_MASK);
|
||||
putreg8(regval8, KL_UART0_BDL);
|
||||
|
||||
/* Enable UART before changing registers */
|
||||
regval8 = getreg8(KL_UART0_C2);
|
||||
regval8 |= (UART_C2_RE | UART_C2_TE);
|
||||
putreg8(regval8, KL_UART0_C2);
|
||||
|
||||
/* Configure the console (only) now. Other UARTs will be configured
|
||||
* when the serial driver is opened.
|
||||
*/
|
||||
|
||||
//#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
|
||||
// kl_uartconfigure(CONSOLE_BASE, CONSOLE_BAUD, CONSOLE_FREQ,
|
||||
// CONSOLE_PARITY, CONSOLE_BITS);
|
||||
//#endif
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Name: kl_uartreset
|
||||
*
|
||||
* Description:
|
||||
* Reset a UART.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef HAVE_UART_DEVICE
|
||||
void kl_uartreset(uintptr_t uart_base)
|
||||
{
|
||||
uint8_t regval;
|
||||
|
||||
/* Just disable the transmitter and receiver */
|
||||
|
||||
regval = getreg8(uart_base+KL_UART_C2_OFFSET);
|
||||
regval &= ~(UART_C2_RE|UART_C2_TE);
|
||||
putreg8(regval, uart_base+KL_UART_C2_OFFSET);
|
||||
}
|
||||
#endif
|
||||
|
||||
/******************************************************************************
|
||||
* Name: kl_uartconfigure
|
||||
*
|
||||
* Description:
|
||||
* Configure a UART as a RS-232 UART.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef HAVE_UART_DEVICE
|
||||
void kl_uartconfigure(uintptr_t uart_base, uint32_t baud,
|
||||
uint32_t clock, unsigned int parity,
|
||||
unsigned int nbits)
|
||||
{
|
||||
uint32_t sbr;
|
||||
uint32_t brfa;
|
||||
uint32_t tmp;
|
||||
uint8_t regval;
|
||||
#ifdef CONFIG_KL_UARTFIFOS
|
||||
unsigned int depth;
|
||||
#endif
|
||||
|
||||
/* Disable the transmitter and receiver throughout the reconfiguration */
|
||||
|
||||
regval = getreg8(uart_base+KL_UART_C2_OFFSET);
|
||||
regval &= ~(UART_C2_RE|UART_C2_TE);
|
||||
putreg8(regval, uart_base+KL_UART_C2_OFFSET);
|
||||
|
||||
/* Configure number of bits, stop bits and parity */
|
||||
|
||||
regval = 0;
|
||||
|
||||
/* Check for odd parity */
|
||||
|
||||
if (parity == 1)
|
||||
{
|
||||
regval |= (UART_C1_PE|UART_C1_PT); /* Enable + odd parity type */
|
||||
}
|
||||
|
||||
/* Check for even parity */
|
||||
|
||||
else if (parity == 2)
|
||||
{
|
||||
regval |= UART_C1_PE; /* Enable (even parity default) */
|
||||
}
|
||||
|
||||
/* The only other option is no parity */
|
||||
|
||||
else
|
||||
{
|
||||
DEBUGASSERT(parity == 0);
|
||||
}
|
||||
|
||||
/* Check for 9-bit operation */
|
||||
|
||||
if (nbits == 9)
|
||||
{
|
||||
regval |= UART_C1_M;
|
||||
}
|
||||
|
||||
/* The only other option is 8-bit operation */
|
||||
|
||||
else
|
||||
{
|
||||
DEBUGASSERT(nbits == 8);
|
||||
}
|
||||
|
||||
putreg8(regval, uart_base+KL_UART_C1_OFFSET);
|
||||
|
||||
/* Calculate baud settings (truncating) */
|
||||
|
||||
sbr = clock / (baud << 4);
|
||||
DEBUGASSERT(sbr < 0x2000);
|
||||
|
||||
/* Save the new baud divisor, retaining other bits in the UARTx_BDH
|
||||
* register.
|
||||
*/
|
||||
|
||||
regval = getreg8(uart_base+KL_UART_BDH_OFFSET) & UART_BDH_SBR_MASK;
|
||||
tmp = sbr >> 8;
|
||||
regval |= (((uint8_t)tmp) << UART_BDH_SBR_SHIFT) & UART_BDH_SBR_MASK;
|
||||
putreg8(regval, uart_base+KL_UART_BDH_OFFSET);
|
||||
|
||||
regval = sbr & 0xff;
|
||||
putreg8(regval, uart_base+KL_UART_BDL_OFFSET);
|
||||
|
||||
/* Calculate a fractional divider to get closer to the requested baud.
|
||||
* The fractional divider, BRFA, is a 5 bit fractional value that is
|
||||
* logically added to the SBR:
|
||||
*
|
||||
* UART baud rate = clock / (16 × (SBR + BRFD))
|
||||
*
|
||||
* The BRFA the remainder. This will be a non-negative value since the SBR
|
||||
* was calculated by truncation.
|
||||
*/
|
||||
|
||||
tmp = clock - (sbr * (baud << 4));
|
||||
brfa = (tmp << 5) / (baud << 4);
|
||||
|
||||
/* Set the BRFA field (retaining other bits in the UARTx_C4 register) */
|
||||
|
||||
regval = getreg8(uart_base+KL_UART_C4_OFFSET) & UART_C4_BRFA_MASK;
|
||||
regval |= ((uint8_t)brfa << UART_C4_BRFA_SHIFT) & UART_C4_BRFA_MASK;
|
||||
putreg8(regval, uart_base+KL_UART_C4_OFFSET);
|
||||
|
||||
/* Set the FIFO watermarks.
|
||||
*
|
||||
* NOTE: UART0 has an 8-byte deep FIFO; the other UARTs have no FIFOs
|
||||
* (1-deep). There appears to be no way to know when the FIFO is not
|
||||
* full (other than reading the FIFO length and comparing the FIFO count).
|
||||
* Hence, the FIFOs are not used in this implementation and, as a result
|
||||
* TDRE indeed mean that the single output buffer is available.
|
||||
*
|
||||
* Performance on UART0 could be improved by enabling the FIFO and by
|
||||
* redesigning all of the FIFO status logic.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_KL_UARTFIFOS
|
||||
depth = g_sizemap[(regval & UART_PFIFO_RXFIFOSIZE_MASK) >> UART_PFIFO_RXFIFOSIZE_SHIFT];
|
||||
if (depth > 1)
|
||||
{
|
||||
depth = (3 * depth) >> 2;
|
||||
}
|
||||
putreg8(depth , uart_base+KL_UART_RWFIFO_OFFSET);
|
||||
|
||||
depth = g_sizemap[(regval & UART_PFIFO_TXFIFOSIZE_MASK) >> UART_PFIFO_TXFIFOSIZE_SHIFT];
|
||||
if (depth > 3)
|
||||
{
|
||||
depth = (depth >> 2);
|
||||
}
|
||||
putreg8(depth, uart_base+KL_UART_TWFIFO_OFFSET);
|
||||
|
||||
/* Enable RX and TX FIFOs */
|
||||
|
||||
putreg8(UART_PFIFO_RXFE | UART_PFIFO_TXFE, uart_base+KL_UART_PFIFO_OFFSET);
|
||||
#else
|
||||
/* Otherwise, disable the FIFOs. Then the FIFOs are disable, the effective
|
||||
* FIFO depth is 1. So set the watermarks as follows:
|
||||
*
|
||||
* TWFIFO[TXWATER] = 0: TDRE will be set when the number of queued bytes
|
||||
* (1 in this case) is less than or equal to 0.
|
||||
* RWFIFO[RXWATER] = 1: RDRF will be set when the number of queued bytes
|
||||
* (1 in this case) is greater than or equal to 1.
|
||||
*
|
||||
* Set the watermarks to one/zero and disable the FIFOs
|
||||
*/
|
||||
|
||||
putreg8(1, uart_base+KL_UART_RWFIFO_OFFSET);
|
||||
putreg8(0, uart_base+KL_UART_TWFIFO_OFFSET);
|
||||
putreg8(0, uart_base+KL_UART_PFIFO_OFFSET);
|
||||
#endif
|
||||
|
||||
/* Now we can (re-)enable the transmitter and receiver */
|
||||
|
||||
regval = getreg8(uart_base+KL_UART_C2_OFFSET);
|
||||
regval |= (UART_C2_RE | UART_C2_TE);
|
||||
putreg8(regval, uart_base+KL_UART_C2_OFFSET);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,125 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/kl/kl_lowputc.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KL_KINETIS_LOWPUTC_H
|
||||
#define __ARCH_ARM_SRC_KL_KINETIS_LOWPUTC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "kl_config.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: kl_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* Called at the very beginning of _start. Performs low level initialization.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void kl_lowsetup(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_setbaud
|
||||
*
|
||||
* Description:
|
||||
* Set the BAUD divxisor for the selected UART
|
||||
*
|
||||
* Mode DIV_X_EN DIV_X_ONE Divider X BRD (Baud rate equation)
|
||||
* -------------------------------------------------------------
|
||||
* 0 Disable 0 B A UART_CLK / [16 * (A+2)]
|
||||
* 1 Enable 0 B A UART_CLK / [(B+1) * (A+2)] , B must >= 8
|
||||
* 2 Enable 1 Don't care A UART_CLK / (A+2), A must >=3
|
||||
*
|
||||
* Here we assume that the default clock source for the UART modules is
|
||||
* the external high speed crystal.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifdef HAVE_UART
|
||||
void kl_setbaud(uintptr_t base, uint32_t baud);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_lowputc
|
||||
*
|
||||
* Description:
|
||||
* Output one character to the UART using a simple polling method.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifdef HAVE_SERIAL_CONSOLE
|
||||
void kl_lowputc(uint32_t ch);
|
||||
#endif
|
||||
|
||||
void kl_uartconfigure(uintptr_t uart_base, uint32_t baud,
|
||||
uint32_t clock, unsigned int parity,
|
||||
unsigned int nbits);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_KL_KINETIS_LOWPUTC_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,199 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/kl/kl_start.c
|
||||
* arch/arm/src/chip/kl_start.c
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/init.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
#include "kl_config.h"
|
||||
#include "kl_lowputc.h"
|
||||
//#include "kl_clockconfig.h"
|
||||
#include "kl_userspace.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Memory Map:
|
||||
*
|
||||
* 0x0000:0000 - Beginning of FLASH. Address of exception vectors.
|
||||
* 0x0001:ffff - End of flash (assuming 128KB of FLASH)
|
||||
* 0x2000:0000 - Start of SRAM and start of .data (_sdata)
|
||||
* - End of .data (_edata) abd start of .bss (_sbss)
|
||||
* - End of .bss (_ebss) and bottom of idle stack
|
||||
* - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack,
|
||||
* start of heap
|
||||
* 0x2000:3fff - End of SRAM and end of heap (assuming 16KB of SRAM)
|
||||
*/
|
||||
|
||||
#define IDLE_STACK ((uint32_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
|
||||
#define HEAP_BASE ((uint32_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
const uint32_t g_idle_topstack = HEAP_BASE;
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: showprogress
|
||||
*
|
||||
* Description:
|
||||
* Print a character on the UART to show boot status.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_DEBUG) && defined(HAVE_SERIAL_CONSOLE)
|
||||
# define showprogress(c) kl_lowputc((uint32_t)c)
|
||||
#else
|
||||
# define showprogress(c)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
void iprintf(const char *string)
|
||||
{
|
||||
while(*string != NULL)
|
||||
kl_lowputc((char) *string++);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: _start
|
||||
*
|
||||
* Description:
|
||||
* This is the reset entry point.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void __start(void)
|
||||
{
|
||||
const uint32_t *src;
|
||||
uint32_t *dest, i=0;
|
||||
volatile unsigned int *SIM_COPC = ((volatile unsigned int *)0x40048100);
|
||||
|
||||
/*acassis: disable SIM_COP*/
|
||||
*SIM_COPC = 0;
|
||||
|
||||
/* Configure the uart so that we can get debug output as soon as possible */
|
||||
|
||||
kl_clockconfig();
|
||||
kl_lowsetup();
|
||||
//uart_init();
|
||||
showprogress('A');
|
||||
|
||||
/* Blink blue LED to indicate we are here */
|
||||
//for (; ; i++)
|
||||
// blueled(i & 0x10000);
|
||||
|
||||
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
|
||||
* certain that there are no issues with the state of global variables.
|
||||
*/
|
||||
|
||||
for (dest = &_sbss; dest < &_ebss; )
|
||||
{
|
||||
*dest++ = 0;
|
||||
}
|
||||
showprogress('B');
|
||||
|
||||
/* Move the intialized data section from his temporary holding spot in
|
||||
* FLASH into the correct place in SRAM. The correct place in SRAM is
|
||||
* give by _sdata and _edata. The temporary location is in FLASH at the
|
||||
* end of all of the other read-only data (.text, .rodata) at _eronly.
|
||||
*/
|
||||
|
||||
for (src = &_eronly, dest = &_sdata; dest < &_edata; )
|
||||
{
|
||||
*dest++ = *src++;
|
||||
}
|
||||
showprogress('C');
|
||||
|
||||
/* Perform early serial initialization */
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
up_earlyserialinit();
|
||||
#endif
|
||||
showprogress('D');
|
||||
|
||||
/* For the case of the separate user-/kernel-space build, perform whatever
|
||||
* platform specific initialization of the user memory is required.
|
||||
* Normally this just means initializing the user space .data and .bss
|
||||
* segments.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_NUTTX_KERNEL
|
||||
kl_userspace();
|
||||
showprogress('E');
|
||||
#endif
|
||||
|
||||
/* Initialize onboard resources */
|
||||
|
||||
kl_boardinitialize();
|
||||
showprogress('F');
|
||||
|
||||
/* Then start NuttX */
|
||||
|
||||
//iprintf("\r\nWelcome to NuttX!\r\n");
|
||||
|
||||
//showprogress('\r');
|
||||
//showprogress('\n');
|
||||
|
||||
iprintf("\r\n\r\n");
|
||||
|
||||
os_start();
|
||||
|
||||
/* Shoulnd't get here */
|
||||
|
||||
for(;;);
|
||||
}
|
||||
|
||||
@@ -0,0 +1,249 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/kl/kl_timerisr.c
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <time.h>
|
||||
#include <debug.h>
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "nvic.h"
|
||||
#include "clock_internal.h"
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/kl_clk.h"
|
||||
#include "chip/kl_gcr.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
/* Get the frequency of the selected clock source */
|
||||
|
||||
#if defined(CONFIG_KL_SYSTICK_CORECLK)
|
||||
# define SYSTICK_CLOCK BOARD_HCLK_FREQUENCY /* Core clock */
|
||||
#elif defined(CONFIG_KL_SYSTICK_XTALHI)
|
||||
# define SYSTICK_CLOCK BOARD_XTALHI_FREQUENCY /* High speed XTAL clock */
|
||||
#elif defined(CONFIG_KL_SYSTICK_XTALLO)
|
||||
# define SYSTICK_CLOCK BOARD_XTALLO_FREQUENCY /* Low speed XTAL clock */
|
||||
#elif defined(CONFIG_KL_SYSTICK_XTALHId2)
|
||||
# define SYSTICK_CLOCK (BOARD_XTALHI_FREQUENCY/2) /* High speed XTAL clock/2 */
|
||||
#elif defined(CONFIG_KL_SYSTICK_HCLKd2)
|
||||
# define SYSTICK_CLOCK (BOARD_HCLK_FREQUENCY/2) /* HCLK/2 */
|
||||
#elif defined(CONFIG_KL_SYSTICK_INTHId2)
|
||||
# define SYSTICK_CLOCK (KL_INTHI_FREQUENCY/2) /* Internal high speed clock/2 */
|
||||
#endif
|
||||
|
||||
/* The desired timer interrupt frequency is provided by the definition
|
||||
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
|
||||
* system clock ticks per second. That value is a user configurable setting
|
||||
* that defaults to 100 (100 ticks per second = 10 MS interval).
|
||||
*
|
||||
* Then, for example, if the external high speed crystal is the SysTick
|
||||
* clock source and BOARD_XTALHI_FREQUENCY is 12MHz and CLK_TCK is 100, then
|
||||
* the reload value would be:
|
||||
*
|
||||
* SYSTICK_RELOAD = (12,000,000 / 100) - 1
|
||||
* = 119,999
|
||||
* = 0x1d4bf
|
||||
*
|
||||
* Which fits within the maximum 14-bit reload value.
|
||||
*/
|
||||
|
||||
#define SYSTICK_RELOAD ((SYSTICK_CLOCK / CLK_TCK) - 1)
|
||||
|
||||
/* The size of the reload field is 24 bits. Verify that the reload value
|
||||
* will fit in the reload register.
|
||||
*/
|
||||
|
||||
#if SYSTICK_RELOAD > 0x00ffffff
|
||||
# error SYSTICK_RELOAD exceeds the range of the RELOAD register
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_unlock
|
||||
*
|
||||
* Description:
|
||||
* Unlock registers
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_KL_SYSTICK_CORECLK
|
||||
static inline void kl_unlock(void)
|
||||
{
|
||||
putreg32(0x59, KL_GCR_REGWRPROT);
|
||||
putreg32(0x16, KL_GCR_REGWRPROT);
|
||||
putreg32(0x88, KL_GCR_REGWRPROT);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_clock
|
||||
*
|
||||
* Description:
|
||||
* Lok registers
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_KL_SYSTICK_CORECLK
|
||||
static inline void kl_lock(void)
|
||||
{
|
||||
putreg32(0, KL_GCR_REGWRPROT);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Global Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Function: up_timerisr
|
||||
*
|
||||
* Description:
|
||||
* The timer ISR will perform a variety of services for various portions
|
||||
* of the systems.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_timerisr(int irq, uint32_t *regs)
|
||||
{
|
||||
/* Process timer interrupt */
|
||||
|
||||
sched_process_timer();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Function: up_timerinit
|
||||
*
|
||||
* Description:
|
||||
* This function is called during start-up to initialize
|
||||
* the timer interrupt.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_timerinit(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Configure the SysTick clock source. This is only necessary if we are not
|
||||
* using the Cortex-M0 core clock as the frequency source.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_KL_SYSTICK_CORECLK
|
||||
|
||||
/* This field is write protected and must be unlocked */
|
||||
|
||||
kl_unlock();
|
||||
|
||||
/* Read the CLKSEL0 register and set the STCLK_S field appropriately */
|
||||
|
||||
regval = getreg32(KL_CLK_CLKSEL0);
|
||||
regval &= ~CLK_CLKSEL0_STCLK_S_MASK;
|
||||
#if defined(CONFIG_KL_SYSTICK_XTALHI)
|
||||
regval |= CLK_CLKSEL0_STCLK_S_XTALHI; /* High speed XTAL clock */
|
||||
#elif defined(CONFIG_KL_SYSTICK_XTALLO)
|
||||
regval |= CLK_CLKSEL0_STCLK_S_XTALLO; /* Low speed XTAL clock */
|
||||
#elif defined(CONFIG_KL_SYSTICK_XTALHId2)
|
||||
regval |= CLK_CLKSEL0_STCLK_S_XTALDIV2; /* High speed XTAL clock/2 */
|
||||
#elif defined(CONFIG_KL_SYSTICK_HCLKd2)
|
||||
regval |= CLK_CLKSEL0_STCLK_S_HCLKDIV2; /* HCLK/2 */
|
||||
#elif defined(CONFIG_KL_SYSTICK_INTHId2)
|
||||
regval |= CLK_CLKSEL0_STCLK_S_INTDIV2; /* Internal high speed clock/2 */
|
||||
#endif
|
||||
putreg32(regval, KL_CLK_CLKSEL0);
|
||||
|
||||
/* Re-lock the register */
|
||||
|
||||
kl_lock();
|
||||
#endif
|
||||
|
||||
/* Set the SysTick interrupt to the default priority */
|
||||
|
||||
regval = getreg32(ARMV6M_SYSCON_SHPR3);
|
||||
regval &= ~SYSCON_SHPR3_PRI_15_MASK;
|
||||
regval |= (NVIC_SYSH_PRIORITY_DEFAULT << SYSCON_SHPR3_PRI_15_SHIFT);
|
||||
putreg32(regval, ARMV6M_SYSCON_SHPR3);
|
||||
|
||||
/* Configure SysTick to interrupt at the requested rate */
|
||||
|
||||
putreg32(SYSTICK_RELOAD, ARMV6M_SYSTICK_RVR);
|
||||
|
||||
/* Attach the timer interrupt vector */
|
||||
|
||||
(void)irq_attach(KL_IRQ_SYSTICK, (xcpt_t)up_timerisr);
|
||||
|
||||
/* Enable SysTick interrupts. We need to select the core clock here if
|
||||
* we are not using one of the alternative clock sources above.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_KL_SYSTICK_CORECLK
|
||||
putreg32((SYSTICK_CSR_CLKSOURCE | SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE),
|
||||
ARMV6M_SYSTICK_CSR);
|
||||
#else
|
||||
putreg32((SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), ARMV6M_SYSTICK_CSR);
|
||||
#endif
|
||||
|
||||
/* And enable the timer interrupt */
|
||||
|
||||
up_enable_irq(KL_IRQ_SYSTICK);
|
||||
}
|
||||
@@ -0,0 +1,114 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/kl/kl_userspace.c
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
|
||||
#include <nuttx/userspace.h>
|
||||
|
||||
#include "kl_userspace.h"
|
||||
|
||||
#ifdef CONFIG_NUTTX_KERNEL
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_userspace
|
||||
*
|
||||
* Description:
|
||||
* For the case of the separate user-/kernel-space build, perform whatever
|
||||
* platform specific initialization of the user memory is required.
|
||||
* Normally this just means initializing the user space .data and .bss
|
||||
* segments.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void kl_userspace(void)
|
||||
{
|
||||
uint8_t *src;
|
||||
uint8_t *dest;
|
||||
uint8_t *end;
|
||||
|
||||
/* Clear all of user-space .bss */
|
||||
|
||||
DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 &&
|
||||
USERSPACE->us_bssstart <= USERSPACE->us_bssend);
|
||||
|
||||
dest = (uint8_t*)USERSPACE->us_bssstart;
|
||||
end = (uint8_t*)USERSPACE->us_bssend;
|
||||
|
||||
while (dest != end)
|
||||
{
|
||||
*dest++ = 0;
|
||||
}
|
||||
|
||||
/* Initialize all of user-space .data */
|
||||
|
||||
DEBUGASSERT(USERSPACE->us_datasource != 0 &&
|
||||
USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 &&
|
||||
USERSPACE->us_datastart <= USERSPACE->us_dataend);
|
||||
|
||||
src = (uint8_t*)USERSPACE->us_datasource;
|
||||
dest = (uint8_t*)USERSPACE->us_datastart;
|
||||
end = (uint8_t*)USERSPACE->us_dataend;
|
||||
|
||||
while (dest != end)
|
||||
{
|
||||
*dest++ = *src++;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_NUTTX_KERNEL */
|
||||
|
||||
@@ -0,0 +1,76 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/kl/kl_userspace.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KL_KINETIS_USERSPACE_H
|
||||
#define __ARCH_ARM_SRC_KL_KINETIS_USERSPACE_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kl_userspace
|
||||
*
|
||||
* Description:
|
||||
* For the case of the separate user-/kernel-space build, perform whatever
|
||||
* platform specific initialization of the user memory is required.
|
||||
* Normally this just means initializing the user space .data and .bss
|
||||
* segments.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_NUTTX_KERNEL
|
||||
void kl_userspace(void);
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KL_KINETIS_USERSPACE_H */
|
||||
@@ -0,0 +1,7 @@
|
||||
#
|
||||
# For a description of the syntax of this configuration file,
|
||||
# see misc/tools/kconfig-language.txt.
|
||||
#
|
||||
|
||||
if ARCH_BOARD_FREEDOM_KL25Z
|
||||
endif
|
||||
@@ -0,0 +1,383 @@
|
||||
README.txt
|
||||
==========
|
||||
|
||||
This is the README file for the port of NuttX to the Freescale
|
||||
Freedom K25Z board. This board has the K25Z120LE3AN chip
|
||||
with a built-in NuLink debugger.
|
||||
|
||||
Contents
|
||||
========
|
||||
|
||||
- Development Environment
|
||||
- GNU Toolchain Options
|
||||
- NuttX Buildroot Toolchain
|
||||
- LEDs
|
||||
- Serial Console
|
||||
- Debugging
|
||||
- NuTiny-specific Configuration Options
|
||||
- Configurations
|
||||
|
||||
Development Environment
|
||||
=======================
|
||||
|
||||
Either Linux or Cygwin on Windows can be used for the development environment.
|
||||
The source has been built only using the GNU toolchain (see below). Other
|
||||
toolchains will likely cause problems.
|
||||
|
||||
GNU Toolchain Options
|
||||
=====================
|
||||
|
||||
As of this writing, all testing has been performed using the NuttX buildroot
|
||||
toolchain described below. I have also verified the build using the
|
||||
CodeSourcery GCC toolchain for windows. Most any contemporary EABI GCC
|
||||
toolchain should work will a little tinkering.
|
||||
|
||||
NuttX Buildroot Toolchain
|
||||
=========================
|
||||
|
||||
A GNU GCC-based toolchain is assumed. The files */setenv.sh should
|
||||
be modified to point to the correct path to the Cortex-M3 GCC toolchain (if
|
||||
different from the default in your PATH variable).
|
||||
|
||||
If you have no Cortex-M0 toolchain, one can be downloaded from the NuttX
|
||||
SourceForge download site (https://sourceforge.net/projects/nuttx/files/buildroot/).
|
||||
This GNU toolchain builds and executes in the Linux or Cygwin environment.
|
||||
|
||||
1. You must have already configured Nuttx in <some-dir>/nuttx.
|
||||
|
||||
cd tools
|
||||
./configure.sh freedom-kl25z/<sub-dir>
|
||||
|
||||
2. Download the latest buildroot package into <some-dir>
|
||||
|
||||
3. unpack the buildroot tarball. The resulting directory may
|
||||
have versioning information on it like buildroot-x.y.z. If so,
|
||||
rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
|
||||
|
||||
4. cd <some-dir>/buildroot
|
||||
|
||||
5. cp configs/cortexm0-eabi-defconfig-4.6.3 .config
|
||||
|
||||
6. make oldconfig
|
||||
|
||||
7. make
|
||||
|
||||
8. Edit setenv.h, if necessary, so that the PATH variable includes
|
||||
the path to the newly built binaries.
|
||||
|
||||
See the file configs/README.txt in the buildroot source tree. That has more
|
||||
details PLUS some special instructions that you will need to follow if you are
|
||||
building a Cortex-M3 toolchain for Cygwin under Windows.
|
||||
|
||||
LEDs
|
||||
====
|
||||
|
||||
The NuTiny has a single green LED that can be controlled from sofware.
|
||||
This LED is connected to PIN17. It is pulled high so a low value will
|
||||
illuminate the LED.
|
||||
|
||||
If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board the
|
||||
NuTiny. The following definitions describe how NuttX controls the LEDs:
|
||||
|
||||
SYMBOL Meaning LED state
|
||||
Initially all LED is OFF
|
||||
------------------- ----------------------- ------------- ------------
|
||||
LED_STARTED NuttX has been started LED ON
|
||||
LED_HEAPALLOCATE Heap has been allocated LED ON
|
||||
LED_IRQSENABLED Interrupts enabled LED ON
|
||||
LED_STACKCREATED Idle stack created LED ON
|
||||
LED_INIRQ In an interrupt LED should glow
|
||||
LED_SIGNAL In a signal handler LED might glow
|
||||
LED_ASSERTION An assertion failed LED ON while handling the assertion
|
||||
LED_PANIC The system has crashed LED Blinking at 2Hz
|
||||
LED_IDLE K25Z1XX is in sleep mode (Optional, not used)
|
||||
|
||||
Serial Console
|
||||
==============
|
||||
|
||||
As with most NuttX configurations, the Freedom K25Z configurations
|
||||
depend on having a serial console to interact with the software. The
|
||||
Freedom K25Z, however, has not on-board RS-232 drivers so will be
|
||||
necessary to connect the Freedom K25Z UART pins to an external
|
||||
RS-232 driver board or TTL-to-Serial USB adaptor.
|
||||
|
||||
By default UART1 is used as the serial console on these boards. K25Z120LE3AN
|
||||
is provided as an LQFP48 package and, for this case, the UART1 RX signal
|
||||
(RXD1) is on PB.4, pin 8, and the TX signal (TXD1) is on PB.5, pin 9.
|
||||
These pins are available on the Freedom K25Z JP5.
|
||||
|
||||
NOTE: The TX vs RX labeling may be confusing. On one RS-232 driver board,
|
||||
I had to connect the K25Z120 TXD0 pin to the driver boards RXD pin. How
|
||||
confusing!
|
||||
|
||||
UART0 is an alternative that can be selected by modifying the default
|
||||
configuation. UART0 RX (RXD0) is on PB.0, pin 17, and the TX signal (TXD0)
|
||||
is on PB.1, pin 18. These pins are available on the Freedom K25Z JP1.
|
||||
|
||||
NOTE: PB.0, pin 17, is also used to control the user LED on board (labeled
|
||||
"IO"). CONFIG_ARCH_LED should not be selected if UART0 is used.
|
||||
|
||||
The K25Z120LE3AN does not support UART2.
|
||||
|
||||
Debugging
|
||||
=========
|
||||
|
||||
The Freedom K25Z includes a built-in NuLink debugger. Unfortunately,
|
||||
full debug support is available only with the Keil and IAR toolchains.
|
||||
There is, however, a free program called ICP (In-Circuit Programmer). It
|
||||
can be used to burn programs into FLASH (aka APROM).
|
||||
|
||||
The ICP program can also be used to burn an ISP program into LDROM. The
|
||||
ISP (In-System Programmer) is available free from the Nuvton website.
|
||||
|
||||
Then NuttX build does not set the configuration words at 0x0030000-0x00300004.
|
||||
You should uncheck the Config box when burning APROM or the previous contents
|
||||
of the configuration words will be erased.
|
||||
|
||||
NuTiny-specific Configuration Options
|
||||
=====================================
|
||||
|
||||
CONFIG_ARCH - Identifies the arch/ subdirectory. This should
|
||||
be set to:
|
||||
|
||||
CONFIG_ARCH=arm
|
||||
|
||||
CONFIG_ARCH_family - For use in C code:
|
||||
|
||||
CONFIG_ARCH_ARM=y
|
||||
|
||||
CONFIG_ARCH_architecture - For use in C code:
|
||||
|
||||
CONFIG_ARCH_CORTEXM0=y
|
||||
|
||||
CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
|
||||
|
||||
CONFIG_ARCH_CHIP=kl
|
||||
|
||||
CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
|
||||
chip:
|
||||
|
||||
CONFIG_ARCH_CHIP_K25Z120LE3AN=y
|
||||
|
||||
CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
|
||||
hence, the board that supports the particular chip or SoC.
|
||||
|
||||
CONFIG_ARCH_BOARD=freedom-kl25z (for the Freescale FRDM-KL25Z development board)
|
||||
|
||||
CONFIG_ARCH_BOARD_name - For use in C code
|
||||
|
||||
CONFIG_ARCH_BOARD_FREEDOM_K25Z128=y
|
||||
|
||||
CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
|
||||
of delay loops
|
||||
|
||||
CONFIG_ENDIAN_BIG - define if big endian (default is little
|
||||
endian)
|
||||
|
||||
CONFIG_DRAM_SIZE - Describes the installed DRAM (SRAM in this case):
|
||||
|
||||
CONFIG_DRAM_SIZE=16384 (16Kb)
|
||||
|
||||
CONFIG_DRAM_START - The start address of installed DRAM
|
||||
|
||||
CONFIG_DRAM_START=0x20000000
|
||||
|
||||
CONFIG_ARCH_IRQPRIO - The Cortex-M0 supports interrupt prioritization
|
||||
|
||||
CONFIG_ARCH_IRQPRIO=y
|
||||
|
||||
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
|
||||
have LEDs
|
||||
|
||||
CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
|
||||
stack. If defined, this symbol is the size of the interrupt
|
||||
stack in bytes. If not defined, the user task stacks will be
|
||||
used during interrupt handling.
|
||||
|
||||
CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
|
||||
|
||||
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
|
||||
|
||||
CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
|
||||
cause a 100 second delay during boot-up. This 100 second delay
|
||||
serves no purpose other than it allows you to calibratre
|
||||
CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure
|
||||
the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
|
||||
the delay actually is 100 seconds.
|
||||
|
||||
Individual subsystems can be enabled as follows. These settings are for
|
||||
all of the K25Z100/120 line and may not be available for the K25Z120LE3AN
|
||||
in particular:
|
||||
|
||||
AHB
|
||||
---
|
||||
|
||||
CONFIG_KL_PDMA Peripheral DMA
|
||||
CONFIG_KL_FMC Flash memory
|
||||
CONFIG_KL_EBI External bus interface
|
||||
|
||||
APB1
|
||||
----
|
||||
|
||||
CONFIG_KL_WDT Watchdog timer
|
||||
CONFIG_KL_RTC Real time clock (RTC)
|
||||
CONFIG_KL_TMR0 Timer0
|
||||
CONFIG_KL_TMR1 Timer1
|
||||
CONFIG_KL_I2C0 I2C interface
|
||||
CONFIG_KL_SPI0 SPI0 master/slave
|
||||
CONFIG_KL_SPI1 SPI1 master/slave
|
||||
CONFIG_KL_PWM0 PWM0
|
||||
CONFIG_KL_PWM1 PWM1
|
||||
CONFIG_KL_PWM2 PWM2
|
||||
CONFIG_KL_PWM3 PWM3
|
||||
CONFIG_KL_UART0 UART0
|
||||
CONFIG_KL_USBD USB 2.0 FS device controller
|
||||
CONFIG_KL_ACMP Analog comparator
|
||||
CONFIG_KL_ADC Analog-digital-converter (ADC)
|
||||
|
||||
APB2
|
||||
---
|
||||
|
||||
CONFIG_KL_PS2 PS/2 interface
|
||||
CONFIG_KL_TIMR2 Timer2
|
||||
CONFIG_KL_TIMR3 Timer3
|
||||
CONFIG_KL_I2C1 I2C1 interface
|
||||
CONFIG_KL_SPI2 SPI2 master/slave
|
||||
CONFIG_KL_SPI3 SPI3 master/slave
|
||||
CONFIG_KL_PWM4 PWM4
|
||||
CONFIG_KL_PWM5 PWM5
|
||||
CONFIG_KL_PWM6 PWM6
|
||||
CONFIG_KL_PWM7 PWM7
|
||||
CONFIG_KL_UART1 UART1
|
||||
CONFIG_KL_UART2 UART2
|
||||
CONFIG_KL_I2S I2S interface
|
||||
|
||||
K25Z1XX specific device driver settings
|
||||
|
||||
CONFIG_UARTn_SERIAL_CONSOLE - Selects the UARTn (n=0,1,2) for the
|
||||
console and ttys0.
|
||||
CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received.
|
||||
This specific the size of the receive buffer for UARTn.
|
||||
CONFIG_UARTn_TXBUFSIZE - Characters are buffered before
|
||||
being sent. This specific the size of the transmit buffer
|
||||
for UARTn.
|
||||
CONFIG_UARTn_BAUD - The configure BAUD of UARTn,
|
||||
CONFIG_UARTn_BITS - The number of bits. Must be 5, 6, 7, or 8.
|
||||
CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
||||
CONFIG_UARTn_2STOP - Two stop bits
|
||||
|
||||
Configurations
|
||||
==============
|
||||
|
||||
Each FREEDOM-KL25Z configuration is maintained in a sub-directory and
|
||||
can be selected as follow:
|
||||
|
||||
cd tools
|
||||
./configure.sh freedom-kl25z/<subdir>
|
||||
cd -
|
||||
. ./setenv.sh
|
||||
|
||||
If this is a Windows native build, then configure.bat should be used
|
||||
instead of configure.sh:
|
||||
|
||||
configure.bat freedom-kl25z\<subdir>
|
||||
|
||||
Where <subdir> is one of the following:
|
||||
|
||||
ostest:
|
||||
------
|
||||
This configuration directory, performs a simple OS test using
|
||||
apps/examples/ostest.
|
||||
|
||||
NOTES:
|
||||
|
||||
1. This configuration uses the mconf-based configuration tool. To
|
||||
change this configuration using that tool, you should:
|
||||
|
||||
a. Build and install the kconfig-mconf tool. See nuttx/README.txt
|
||||
and misc/tools/
|
||||
|
||||
b. Execute 'make menuconfig' in nuttx/ in order to start the
|
||||
reconfiguration process.
|
||||
|
||||
2. Default toolchain:
|
||||
|
||||
CONFIG_HOST_WINDOWS=y : Builds under Windows
|
||||
CONFIG_WINDOWS_CYGWIN=y : Using Cygwin
|
||||
CONFIG_ARMV6M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery for Windows
|
||||
|
||||
3. Serial Console. A serial console is required to see the OS test
|
||||
output. The serial console is configured on UART1 which is available
|
||||
on JP5:
|
||||
|
||||
UART1 RX signal (RXD1) is on PB.4, pin 8, and
|
||||
UART1 TX signal (TXD1) is on PB.5, pin 9.
|
||||
|
||||
nsh:
|
||||
---
|
||||
Configures the NuttShell (nsh) located at apps/examples/nsh. The
|
||||
Configuration enables the serial interfaces on UART1. Support for
|
||||
builtin applications is disabled.
|
||||
|
||||
NOTES:
|
||||
|
||||
1. This configuration uses the mconf-based configuration tool. To
|
||||
change this configuration using that tool, you should:
|
||||
|
||||
a. Build and install the kconfig-mconf tool. See nuttx/README.txt
|
||||
and misc/tools/
|
||||
|
||||
b. Execute 'make menuconfig' in nuttx/ in order to start the
|
||||
reconfiguration process.
|
||||
|
||||
2. By default, this configuration uses the CodeSourcery toolchain
|
||||
for Windows and builds under Cygwin (or probably MSYS). That
|
||||
can easily be reconfigured, of course.
|
||||
|
||||
CONFIG_HOST_WINDOWS=y : Builds under Windows
|
||||
CONFIG_WINDOWS_CYGWIN=y : Using Cygwin
|
||||
CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery for Windows
|
||||
|
||||
3. Serial Console. A serial console is necessary to interrupt with
|
||||
NSH. The serial console is configured on UART1 which is available
|
||||
on JP5:
|
||||
|
||||
UART1 RX signal (RXD1) is on PB.4, pin 8, and
|
||||
UART1 TX signal (TXD1) is on PB.5, pin 9.
|
||||
|
||||
It is possible to configure NSH to use a USB serial console instead
|
||||
of an RS-232 serial console. However, that configuration has not
|
||||
been impelmented as of this writing.
|
||||
|
||||
4. Memory Usage. The size command gives us the static memory usage.
|
||||
This is what I get:
|
||||
|
||||
$ size nuttx
|
||||
text data bss dec hex filename
|
||||
35037 106 1092 36235 8d8b nuttx
|
||||
|
||||
And we can get the runtime memory usage from the NSH free command:
|
||||
|
||||
NuttShell (NSH) NuttX-6.25
|
||||
nsh> free
|
||||
total used free largest
|
||||
Mem: 14160 3944 10216 10216
|
||||
nsh>
|
||||
|
||||
Summary:
|
||||
|
||||
- This slightly tuned NSH example uses 34.2KB of FLASH leaving 93.8KB
|
||||
of FLASH (72%) free from additional application development.
|
||||
|
||||
I did not do all of the arithmetic, but it appears to me that of this
|
||||
34+KB of FLASH usage, probably 20-30% of the FLASH is used by libgcc!
|
||||
libgcc has gotten very fat!
|
||||
|
||||
- Static SRAM usage is about 1.2KB (<4%).
|
||||
|
||||
- At run time, 10.0KB of SRAM (62%) is still available for additional
|
||||
applications. Most of the memory used at runtime is allocated I/O
|
||||
buffers and the stack for the NSH main thread (1.5KB).
|
||||
|
||||
There is probably enough free memroy to support 3 or 4 application
|
||||
threads in addition to NSH.
|
||||
@@ -0,0 +1,286 @@
|
||||
/************************************************************************************
|
||||
* configs/kwikstik-k40/include/board.h
|
||||
* include/arch/board/board.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_BOARD_BOARD_H
|
||||
#define __ARCH_BOARD_BOARD_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Clocking *************************************************************************/
|
||||
/* The Kwikstik-K40 has a 4MHz crystal on board */
|
||||
|
||||
#undef BOARD_EXTCLOCK /* Crystal */
|
||||
#define BOARD_EXTAL_FREQ 8000000 /* 8MHz crystal frequency (REFCLK) */
|
||||
#define BOARD_HCLK_FREQUENCY BOARD_EXTAL_FREQ
|
||||
#define BOARD_XTAL32_FREQ 32768 /* 32KHz RTC Oscillator */
|
||||
|
||||
/* PLL Configuration. NOTE: Only even frequency crystals are supported that will
|
||||
* produce a 2MHz reference clock to the PLL.
|
||||
*
|
||||
* PLL Input frequency: PLLIN = REFCLK/PRDIV = 4MHz/2 = 2MHz
|
||||
* PLL Output frequency: PLLOUT = PLLIN*VDIV = 2Mhz*48 = 96MHz
|
||||
* MCG Frequency: PLLOUT = 96MHz
|
||||
*/
|
||||
|
||||
#define BOARD_PRDIV 2 /* PLL External Reference Divider */
|
||||
#define BOARD_VDIV 48 /* PLL VCO Divider (frequency multiplier) */
|
||||
|
||||
#define BOARD_PLLIN_FREQ (BOARD_EXTAL_FREQ / BOARD_PRDIV)
|
||||
#define BOARD_PLLOUT_FREQ (BOARD_PLLIN_FREQ * BOARD_VDIV)
|
||||
#define BOARD_MCG_FREQ BOARD_PLLOUT_FREQ
|
||||
|
||||
/* SIM CLKDIV1 dividers */
|
||||
|
||||
#define BOARD_OUTDIV1 1 /* Core = MCG, 96MHz */
|
||||
#define BOARD_OUTDIV2 2 /* Bus = MCG/2, 48MHz */
|
||||
#define BOARD_OUTDIV3 2 /* FlexBus = MCG/2, 48MHz */
|
||||
#define BOARD_OUTDIV4 4 /* Flash clock = MCG/4, 24MHz */
|
||||
|
||||
#define BOARD_CORECLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV1)
|
||||
#define BOARD_BUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV2)
|
||||
#define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3)
|
||||
#define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4)
|
||||
|
||||
/* SDHC clocking ********************************************************************/
|
||||
|
||||
/* SDCLK configurations corresponding to various modes of operation. Formula is:
|
||||
*
|
||||
* SDCLK frequency = (base clock) / (prescaler * divisor)
|
||||
*
|
||||
* The SDHC module is always configure configured so that the core clock is the base
|
||||
* clock.
|
||||
*/
|
||||
|
||||
/* Identification mode: 400KHz = 96MHz / ( 16 * 15) */
|
||||
|
||||
#define BOARD_SDHC_IDMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV16
|
||||
#define BOARD_SDHC_IDMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(15)
|
||||
|
||||
/* MMC normal mode: 16MHz = 96MHz / (2 * 3) */
|
||||
|
||||
#define BOARD_SDHC_MMCMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
|
||||
#define BOARD_SDHC_MMCMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3)
|
||||
|
||||
/* SD normal mode (1-bit): 16MHz = 96MHz / (2 * 3) */
|
||||
|
||||
#define BOARD_SDHC_SD1MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
|
||||
#define BOARD_SDHC_SD1MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3)
|
||||
|
||||
/* SD normal mode (4-bit): 24MHz = 96MHz / (2 * 2) (with DMA)
|
||||
* SD normal mode (4-bit): 16MHz = 96MHz / (2 * 3) (no DMA)
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
|
||||
# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(2)
|
||||
#else
|
||||
//# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
|
||||
//# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3)
|
||||
# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV16
|
||||
# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(15)
|
||||
#endif
|
||||
|
||||
/* LED definitions ******************************************************************/
|
||||
/* The KwikStik-K40 board has no MCU driven, GPIO-based LEDs */
|
||||
|
||||
#define LED_STARTED 0
|
||||
#define LED_HEAPALLOCATE 1
|
||||
#define LED_IRQSENABLED 2
|
||||
#define LED_STACKCREATED 3
|
||||
#define LED_INIRQ 4
|
||||
#define LED_SIGNAL 5
|
||||
#define LED_ASSERTION 6
|
||||
#define LED_PANIC 7
|
||||
|
||||
/* Button definitions ***************************************************************/
|
||||
/* The KwikStik-K40 board has no standard GPIO contact buttons */
|
||||
|
||||
/* Alternative pin resolution *******************************************************/
|
||||
/* If there are alternative configurations for various pins in the
|
||||
* kinetis_k40pinmux.h header file, those alternative pins will be labeled with a
|
||||
* suffix like _1, _2, etc. The logic in this file must select the correct pin
|
||||
* configuration for the board by defining a pin configuration (with no suffix) that
|
||||
* maps to the correct alternative.
|
||||
*/
|
||||
|
||||
/* On-Board Connections
|
||||
*
|
||||
* ------------------- -------------------------- -------- -------------------
|
||||
* FEATURE CONNECTION PORT/PIN PIN FUNCTION
|
||||
* ------------------- -------------------------- -------- -------------------
|
||||
* Audio Jack Output Audio Amp On PTE28 PTE28
|
||||
* Audio Output DAC1_OUT DAC1_OUT
|
||||
* Volume Up PTD10 PTD10
|
||||
* Volume Down PTD11 PTD11
|
||||
* Buzzer Audio Out PTA8 FTM1_CH0
|
||||
* Microphone Microphone input PTA7 ADC0_SE10
|
||||
* SD Card Slot SD Clock PTE2 SDHC0_DCLK
|
||||
* SD Command PTE3 SDHC0_CMD
|
||||
* SD Data0 PTD12 SDHC0_D4
|
||||
* SD Data1 PTD13 SDHC0_D5
|
||||
* SD Data2 PTD14 SDHC0_D6
|
||||
* SD Data3 PTD15 SDHC0_D7
|
||||
* SD Card Detect PTE27 PTE27
|
||||
* SD Card On PTE6 PTE6
|
||||
* Infrared Port IR Transmit PTE4 IR_TX
|
||||
* IR Receive PTA13 CMP2_IN0
|
||||
* Touch Pads E1 / Touch PTB0 TSI0_CH0
|
||||
* E2 / Touch PTA4 TSI0_CH5
|
||||
* E3 / Touch PTA24 PTA24
|
||||
* E4 / Touch PTA25 PTA25
|
||||
* E5 / Touch PTA26 PTA26
|
||||
* E6 / Touch PTA27 PTA27
|
||||
*/
|
||||
|
||||
#define PIN_FTM1_CH0 PIN_FTM1_CH0_1
|
||||
|
||||
/* Connections via the General Purpose Tower Plug-in (TWRPI) Socket
|
||||
* ------------------- -------------------------- -------- -------------------
|
||||
* FEATURE CONNECTION PORT/PIN PIN FUNCTION
|
||||
* ------------------- -------------------------- -------- -------------------
|
||||
* General Purpose TWRPI AN0 (J8 Pin 8) ? ADC0_DP0/ADC1_DP3
|
||||
* TWRPI Socket TWRPI AN1 (J8 Pin 9) ? ADC0_DM0/ADC1_DM3
|
||||
* TWRPI AN2 (J8 Pin 12) ? ADC1_DP0/ADC0_DP3
|
||||
* TWRPI ID0 (J8 Pin 17) ? ADC0_DP1
|
||||
* TWRPI ID1 (J8 Pin 18) ? ADC0_DM1
|
||||
* TWRPI I2C SCL (J9 Pin 3) PTC10 I2C1_SCL
|
||||
* TWRPI I2C SDA (J9 Pin 4) PTC11 I2C1_SDA
|
||||
* TWRPI SPI MISO (J9 Pin 9) PTB23 SPI2_SIN
|
||||
* TWRPI SPI MOSI (J9 Pin 10) PTB22 SPI2_SOUT
|
||||
* TWRPI SPI SS (J9 Pin 11) PTB20 SPI2_PCS0
|
||||
* TWRPI SPI CLK (J9 Pin 12) PTB21 SPI2_SCK
|
||||
* TWRPI GPIO0 (J9 Pin 15) PTC12 PTC12
|
||||
* TWRPI GPIO1 (J9 Pin 16) PTB9 PTB9
|
||||
* TWRPI GPIO2 (J9 Pin 17) PTB10 PTB10
|
||||
* TWRPI GPIO3 (J9 Pin 18) PTC5 PTC5
|
||||
* TWRPI GPIO4 (J9 Pin 19) PTA5 PTA5
|
||||
*/
|
||||
|
||||
#define PIN_I2C1_SCL PIN_I2C1_SCL_1
|
||||
#define PIN_I2C1_SDA PIN_I2C1_SDA_1
|
||||
#define PIN_SPI2_SIN PIN_SPI2_SIN_1
|
||||
#define PIN_SPI2_SOUT PIN_SPI2_SOUT_1
|
||||
#define PIN_SPI2_PCS0 PIN_SPI2_PCS0_1
|
||||
#define PIN_SPI2_SCK PIN_SPI2_SCK_1
|
||||
|
||||
/* Connections via the Tower Primary Connector Side A
|
||||
* --- -------------------- --------------------------------
|
||||
* PIN NAME USAGE
|
||||
* --- -------------------- --------------------------------
|
||||
* A9 GPIO9 / CTS1 PTE10/UART_CTS
|
||||
* A43 RXD1 PTE9/UART_RX
|
||||
* A44 TXD1 PTE8/UART_TX
|
||||
* A63 RSTOUT_b PTA9/FTM1_CH1
|
||||
*/
|
||||
|
||||
#define PIN_UART5_CTS PIN_UART5_CTS_2
|
||||
#define PIN_FTM1_CH1 PIN_FTM1_CH1_1
|
||||
|
||||
/* Connections via the Tower Primary Connector Side B
|
||||
* --- -------------------- --------------------------------
|
||||
* PIN NAME USAGE
|
||||
* --- -------------------- --------------------------------
|
||||
* B21 GPIO1 / RTS1 PTE7/UART_RTS
|
||||
* B37 PWM7 PTA8/FTM1_CH0
|
||||
* B38 PWM6 PTA9/FTM1_CH1
|
||||
* B41 CANRX0 PTE25/CAN1_RX
|
||||
* B42 CANTX0 PTE24/CAN1_TX
|
||||
* B44 SPI0_MISO PTA17/SPI0_SIN
|
||||
* B45 SPI0_MOSI PTA16/SPI0_SOUT
|
||||
* B46 SPI0_CS0_b PTA14/SPI0_PCS0
|
||||
* B48 SPI0_CLK PTA15/SPI0_SCK
|
||||
* B50 SCL1 PTE1/I2C1_SCL
|
||||
* B51 SDA1 PTE0/I2C1_SDA
|
||||
* B52 GPIO5 / SD_CARD_DET PTA16
|
||||
*/
|
||||
|
||||
#define PIN_UART3_RTS PIN_UART3_RTS_3
|
||||
#define PIN_CAN1_RX PIN_CAN1_RX_2
|
||||
#define PIN_CAN1_TX PIN_CAN1_TX_2
|
||||
#define PIN_SPI0_SIN PIN_SPI0_SIN_1
|
||||
#define PIN_SPI0_SOUT PIN_SPI0_SOUT_1
|
||||
#define PIN_SPI0_SCK PIN_SPI0_SCK_1
|
||||
#define PIN_SPI0_PCS0 PIN_SPI0_PCS0_1
|
||||
#define PIN_I2C1_SCL PIN_I2C1_SCL_2
|
||||
#define PIN_I2C1_SDA PIN_I2C1_SDA_2
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
/************************************************************************************
|
||||
* Name: kinetis_boardinitialize
|
||||
*
|
||||
* Description:
|
||||
* All STM32 architectures must provide the following entry point. This entry point
|
||||
* is called early in the intitialization -- after all memory has been configured
|
||||
* and mapped but before any devices have been initialized.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
EXTERN void kinetis_boardinitialize(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_BOARD_BOARD_H */
|
||||
@@ -0,0 +1,170 @@
|
||||
/************************************************************************************
|
||||
* configs/freedom-kl25z/include/board.h
|
||||
* include/arch/board/board.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __CONFIGS_FREEDOM_KL25Z_INCLUDE_BOARD_H
|
||||
#define __CONFIGS_FREEDOM_KL25Z_INCLUDE_BOARD_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
/* Clocking *************************************************************************/
|
||||
/* Crystal frequencies */
|
||||
|
||||
#define BOARD_XTALHI_FREQUENCY 12000000
|
||||
#define BOARD_XTALLO_FREQUENCY 32768
|
||||
|
||||
/* PLL: The PLL must be 48MHz x N times when using USB
|
||||
*
|
||||
* FOUT = FIN x (NF/NR) x (1 / NO)
|
||||
* FIN = Input reference clock frequency
|
||||
* NF = Feedback divider
|
||||
* = (FB_DV + 2)
|
||||
* NR = Input divider
|
||||
* = (IN_DV + 2)
|
||||
* NO = 1 if OUT_DV == 0
|
||||
* 2 if OUT_DV == 1 or 2
|
||||
* 4 if OUT_DV == 3
|
||||
*
|
||||
* FOUT = 12000000 x 48 / 3 / 4
|
||||
* = 48MHz
|
||||
*/
|
||||
|
||||
#define BOARD_PLL_FIN BOARD_XTALHI_FREQUENCY
|
||||
#define BOARD_PLL_FB_DV 46
|
||||
#define BOARD_PLL_NF (BOARD_PLL_FB_DV+2)
|
||||
#define BOARD_PLL_IN_DV 1
|
||||
#define BOARD_PLL_NR (BOARD_PLL_IN_DV+2)
|
||||
#define BOARD_PLL_OUT_DV 3
|
||||
#define BOARD_PLL_NO 4
|
||||
|
||||
#define BOARD_PLL_FOUT \
|
||||
(BOARD_PLL_FIN * BOARD_PLL_NF / BOARD_PLL_NR / BOARD_PLL_NO)
|
||||
|
||||
/* HCLK. FOUT is the HCLK source clock. */
|
||||
|
||||
#define BOARD_HCLK_N 1
|
||||
#define BOARD_HCLK_FREQUENCY (BOARD_PLL_FOUT / BOARD_HCLK_N)
|
||||
|
||||
/* USB. FOUT is the source. The USB CLK must be 48MHz */
|
||||
|
||||
#define BOARD_USB_N 1
|
||||
#define BOARD_USB_FREQUENCY (BOARD_PLL_FOUT / BOARD_USB_N)
|
||||
|
||||
/* LED definitions ******************************************************************/
|
||||
/* The NuTiny has a single green LED that can be controlled from sofware. This LED
|
||||
* is connected to PIN17. It is pulled high so a low value will illuminate the LED.
|
||||
*/
|
||||
|
||||
#define BOARD_NLEDS 1
|
||||
|
||||
/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board the
|
||||
* NuTiny. The following definitions describe how NuttX controls the LEDs:
|
||||
*
|
||||
* SYMBOL Meaning LED state
|
||||
* Initially all LED is OFF
|
||||
* ------------------- ----------------------- ------------- ------------
|
||||
* LED_STARTED NuttX has been started LED ON
|
||||
* LED_HEAPALLOCATE Heap has been allocated LED ON
|
||||
* LED_IRQSENABLED Interrupts enabled LED ON
|
||||
* LED_STACKCREATED Idle stack created LED ON
|
||||
* LED_INIRQ In an interrupt LED should glow
|
||||
* LED_SIGNAL In a signal handler LED might glow
|
||||
* LED_ASSERTION An assertion failed LED ON while handling the assertion
|
||||
* LED_PANIC The system has crashed LED Blinking at 2Hz
|
||||
* LED_IDLE K25Z is is sleep mode (Optional, not used)
|
||||
*/
|
||||
|
||||
#define LED_STARTED 0
|
||||
#define LED_HEAPALLOCATE 0
|
||||
#define LED_IRQSENABLED 0
|
||||
#define LED_STACKCREATED 0
|
||||
#define LED_INIRQ 0
|
||||
#define LED_SIGNAL 0
|
||||
#define LED_ASSERTION 0
|
||||
#define LED_PANIC 0
|
||||
|
||||
/* Button definitions ***************************************************************/
|
||||
/* The NuTiny has no buttons */
|
||||
|
||||
#define NUM_BUTTONS 0
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
/************************************************************************************
|
||||
* Name: kl_boardinitialize
|
||||
*
|
||||
* Description:
|
||||
* All K25Z architectures must provide the following entry point. This entry point
|
||||
* is called early in the intitialization -- after all memory has been configured
|
||||
* and mapped but before any devices have been initialized.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void kl_boardinitialize(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __CONFIGS_FREEDOM_KL25Z_INCLUDE_BOARD_H */
|
||||
@@ -0,0 +1,122 @@
|
||||
############################################################################
|
||||
# configs/freedom-kl25z/nsh/Make.defs
|
||||
#
|
||||
# Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
include ${TOPDIR}/.config
|
||||
include ${TOPDIR}/tools/Config.mk
|
||||
include ${TOPDIR}/arch/arm/src/armv6-m/Toolchain.defs
|
||||
|
||||
LDSCRIPT = ld.script
|
||||
|
||||
ifeq ($(WINTOOL),y)
|
||||
# Windows-native toolchains
|
||||
ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
|
||||
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
|
||||
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
|
||||
MAXOPTIMIZATION = -O2
|
||||
else
|
||||
# Linux/Cygwin-native toolchain
|
||||
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
|
||||
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
|
||||
ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
|
||||
endif
|
||||
|
||||
CC = $(CROSSDEV)gcc
|
||||
CXX = $(CROSSDEV)g++
|
||||
CPP = $(CROSSDEV)gcc -E
|
||||
LD = $(CROSSDEV)ld
|
||||
AR = $(ARCROSSDEV)ar rcs
|
||||
NM = $(ARCROSSDEV)nm
|
||||
OBJCOPY = $(CROSSDEV)objcopy
|
||||
OBJDUMP = $(CROSSDEV)objdump
|
||||
|
||||
ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
|
||||
ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
|
||||
|
||||
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
|
||||
ARCHOPTIMIZATION = -g
|
||||
else
|
||||
ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
|
||||
endif
|
||||
|
||||
ARCHCFLAGS = -fno-builtin
|
||||
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti
|
||||
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow
|
||||
ARCHWARNINGSXX = -Wall -Wshadow
|
||||
ARCHDEFINES =
|
||||
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
|
||||
|
||||
CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
|
||||
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
|
||||
CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
|
||||
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
|
||||
CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
|
||||
AFLAGS = $(CFLAGS) -D__ASSEMBLY__
|
||||
|
||||
NXFLATLDFLAGS1 = -r -d -warn-common
|
||||
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
|
||||
LDNXFLATFLAGS = -e main -s 2048
|
||||
|
||||
OBJEXT = .o
|
||||
LIBEXT = .a
|
||||
EXEEXT =
|
||||
|
||||
ifneq ($(CROSSDEV),arm-nuttx-elf-)
|
||||
LDFLAGS += -nostartfiles -nodefaultlibs
|
||||
endif
|
||||
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
|
||||
LDFLAGS += -g
|
||||
endif
|
||||
|
||||
|
||||
HOSTCC = gcc
|
||||
HOSTINCLUDES = -I.
|
||||
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe
|
||||
HOSTLDFLAGS =
|
||||
ifeq ($(CONFIG_HOST_WINDOWS),y)
|
||||
HOSTEXEEXT = .exe
|
||||
else
|
||||
HOSTEXEEXT =
|
||||
endif
|
||||
|
||||
ifeq ($(WINTOOL),y)
|
||||
# Windows-native host tools
|
||||
DIRLINK = $(TOPDIR)/tools/copydir.sh
|
||||
DIRUNLINK = $(TOPDIR)/tools/unlink.sh
|
||||
MKDEP = $(TOPDIR)/tools/mknulldeps.sh
|
||||
else
|
||||
# Linux/Cygwin-native host tools
|
||||
MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
|
||||
endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,75 @@
|
||||
#!/bin/bash
|
||||
# configs/freedom-kl25z/nsh/setenv.sh
|
||||
#
|
||||
# Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
|
||||
if [ "$_" = "$0" ] ; then
|
||||
echo "You must source this script, not run it!" 1>&2
|
||||
exit 1
|
||||
fi
|
||||
|
||||
WD=`pwd`
|
||||
if [ ! -x "setenv.sh" ]; then
|
||||
echo "This script must be executed from the top-level NuttX build directory"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [ -z "${PATH_ORIG}" ]; then
|
||||
export PATH_ORIG="${PATH}"
|
||||
fi
|
||||
|
||||
# This is the Cygwin path to the location where I installed the RIDE
|
||||
# toolchain under windows. You will also have to edit this if you install
|
||||
# the RIDE toolchain in any other location
|
||||
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin"
|
||||
|
||||
# This is the Cygwin path to the location where I installed the CodeSourcery
|
||||
# toolchain under windows. You will also have to edit this if you install
|
||||
# the CodeSourcery toolchain in any other location
|
||||
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
|
||||
|
||||
# These are the Cygwin paths to the locations where I installed the Atollic
|
||||
# toolchain under windows. You will also have to edit this if you install
|
||||
# the Atollic toolchain in any other location. /usr/bin is added before
|
||||
# the Atollic bin path because there is are binaries named gcc.exe and g++.exe
|
||||
# at those locations as well.
|
||||
#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin"
|
||||
#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin"
|
||||
|
||||
# This is the Cygwin path to the location where I build the buildroot
|
||||
# toolchain.
|
||||
export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin"
|
||||
|
||||
# Add the path to the toolchain to the PATH varialble
|
||||
export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
|
||||
|
||||
echo "PATH : ${PATH}"
|
||||
@@ -0,0 +1,122 @@
|
||||
############################################################################
|
||||
# configs/freedom-kl25z/ostest/Make.defs
|
||||
#
|
||||
# Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
include ${TOPDIR}/.config
|
||||
include ${TOPDIR}/tools/Config.mk
|
||||
include ${TOPDIR}/arch/arm/src/armv6-m/Toolchain.defs
|
||||
|
||||
LDSCRIPT = ld.script
|
||||
|
||||
ifeq ($(WINTOOL),y)
|
||||
# Windows-native toolchains
|
||||
ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
|
||||
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
|
||||
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
|
||||
MAXOPTIMIZATION = -O2
|
||||
else
|
||||
# Linux/Cygwin-native toolchain
|
||||
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
|
||||
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
|
||||
ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
|
||||
endif
|
||||
|
||||
CC = $(CROSSDEV)gcc
|
||||
CXX = $(CROSSDEV)g++
|
||||
CPP = $(CROSSDEV)gcc -E
|
||||
LD = $(CROSSDEV)ld
|
||||
AR = $(ARCROSSDEV)ar rcs
|
||||
NM = $(ARCROSSDEV)nm
|
||||
OBJCOPY = $(CROSSDEV)objcopy
|
||||
OBJDUMP = $(CROSSDEV)objdump
|
||||
|
||||
ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
|
||||
ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
|
||||
|
||||
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
|
||||
ARCHOPTIMIZATION = -g
|
||||
else
|
||||
ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
|
||||
endif
|
||||
|
||||
ARCHCFLAGS = -fno-builtin
|
||||
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti
|
||||
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow
|
||||
ARCHWARNINGSXX = -Wall -Wshadow
|
||||
ARCHDEFINES =
|
||||
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
|
||||
|
||||
CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
|
||||
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
|
||||
CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
|
||||
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
|
||||
CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
|
||||
AFLAGS = $(CFLAGS) -D__ASSEMBLY__
|
||||
|
||||
NXFLATLDFLAGS1 = -r -d -warn-common
|
||||
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
|
||||
LDNXFLATFLAGS = -e main -s 2048
|
||||
|
||||
OBJEXT = .o
|
||||
LIBEXT = .a
|
||||
EXEEXT =
|
||||
|
||||
ifneq ($(CROSSDEV),arm-nuttx-elf-)
|
||||
LDFLAGS += -nostartfiles -nodefaultlibs
|
||||
endif
|
||||
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
|
||||
LDFLAGS += -g
|
||||
endif
|
||||
|
||||
|
||||
HOSTCC = gcc
|
||||
HOSTINCLUDES = -I.
|
||||
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe
|
||||
HOSTLDFLAGS =
|
||||
ifeq ($(CONFIG_HOST_WINDOWS),y)
|
||||
HOSTEXEEXT = .exe
|
||||
else
|
||||
HOSTEXEEXT =
|
||||
endif
|
||||
|
||||
ifeq ($(WINTOOL),y)
|
||||
# Windows-native host tools
|
||||
DIRLINK = $(TOPDIR)/tools/copydir.sh
|
||||
DIRUNLINK = $(TOPDIR)/tools/unlink.sh
|
||||
MKDEP = $(TOPDIR)/tools/mknulldeps.sh
|
||||
else
|
||||
# Linux/Cygwin-native host tools
|
||||
MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
|
||||
endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,75 @@
|
||||
#!/bin/bash
|
||||
# configs/freedom-kl25z/ostest/setenv.sh
|
||||
#
|
||||
# Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
|
||||
if [ "$_" = "$0" ] ; then
|
||||
echo "You must source this script, not run it!" 1>&2
|
||||
exit 1
|
||||
fi
|
||||
|
||||
WD=`pwd`
|
||||
if [ ! -x "setenv.sh" ]; then
|
||||
echo "This script must be executed from the top-level NuttX build directory"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [ -z "${PATH_ORIG}" ]; then
|
||||
export PATH_ORIG="${PATH}"
|
||||
fi
|
||||
|
||||
# This is the Cygwin path to the location where I installed the RIDE
|
||||
# toolchain under windows. You will also have to edit this if you install
|
||||
# the RIDE toolchain in any other location
|
||||
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin"
|
||||
|
||||
# This is the Cygwin path to the location where I installed the CodeSourcery
|
||||
# toolchain under windows. You will also have to edit this if you install
|
||||
# the CodeSourcery toolchain in any other location
|
||||
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
|
||||
|
||||
# These are the Cygwin paths to the locations where I installed the Atollic
|
||||
# toolchain under windows. You will also have to edit this if you install
|
||||
# the Atollic toolchain in any other location. /usr/bin is added before
|
||||
# the Atollic bin path because there is are binaries named gcc.exe and g++.exe
|
||||
# at those locations as well.
|
||||
#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin"
|
||||
#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin"
|
||||
|
||||
# This is the Cygwin path to the location where I build the buildroot
|
||||
# toolchain.
|
||||
export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin"
|
||||
|
||||
# Add the path to the toolchain to the PATH varialble
|
||||
export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
|
||||
|
||||
echo "PATH : ${PATH}"
|
||||
@@ -0,0 +1,134 @@
|
||||
/****************************************************************************
|
||||
* configs/kwikstik-k40/scripts/ld.script
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* The MKL25Z128 has 128Kb of FLASH beginning at address 0x00000000 and
|
||||
* 16Kb of SRAM at address 0x1ffff000.
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
vectflash (rx) : ORIGIN = 0x00000000, LENGTH = 0x00c0
|
||||
cfmprotect (rx) : ORIGIN = 0x00000400, LENGTH = 0x10
|
||||
progflash (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x410
|
||||
datasram (rwx) : ORIGIN = 0x1ffff000, LENGTH = 16K
|
||||
}
|
||||
|
||||
OUTPUT_ARCH(arm)
|
||||
EXTERN(_vectors)
|
||||
EXTERN(_cfmconfig)
|
||||
ENTRY(_stext)
|
||||
SECTIONS
|
||||
{
|
||||
.vectors : {
|
||||
_svectors = ABSOLUTE(.);
|
||||
*(.vectors)
|
||||
_evectors = ABSOLUTE(.);
|
||||
} > vectflash
|
||||
|
||||
.cfmprotect : {
|
||||
*(.cfmconfig)
|
||||
} > cfmprotect
|
||||
|
||||
.text : {
|
||||
_stext = ABSOLUTE(.);
|
||||
*(.text .text.*)
|
||||
*(.fixup)
|
||||
*(.gnu.warning)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.got)
|
||||
*(.gcc_except_table)
|
||||
*(.gnu.linkonce.r.*)
|
||||
_etext = ABSOLUTE(.);
|
||||
} > progflash
|
||||
|
||||
.init_section : {
|
||||
_sinit = ABSOLUTE(.);
|
||||
*(.init_array .init_array.*)
|
||||
_einit = ABSOLUTE(.);
|
||||
} > progflash
|
||||
|
||||
.ARM.extab : {
|
||||
*(.ARM.extab*)
|
||||
} > progflash
|
||||
|
||||
__exidx_start = ABSOLUTE(.);
|
||||
.ARM.exidx : {
|
||||
*(.ARM.exidx*)
|
||||
} > progflash
|
||||
__exidx_end = ABSOLUTE(.);
|
||||
|
||||
.data : {
|
||||
_sdata = ABSOLUTE(.);
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
CONSTRUCTORS
|
||||
_edata = ABSOLUTE(.);
|
||||
} > datasram AT > progflash
|
||||
|
||||
_eronly = LOADADDR(.data);
|
||||
|
||||
.ramfunc ALIGN(4): {
|
||||
_sramfuncs = ABSOLUTE(.);
|
||||
*(.ramfunc .ramfunc.*)
|
||||
_eramfuncs = ABSOLUTE(.);
|
||||
} > datasram AT > progflash
|
||||
|
||||
_framfuncs = LOADADDR(.ramfunc);
|
||||
|
||||
.bss : {
|
||||
_sbss = ABSOLUTE(.);
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
_ebss = ABSOLUTE(.);
|
||||
} > datasram
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user