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SAMA5 EMAC and GMAC: More additions to register definition files
This commit is contained in:
Gregory Nutt
+280
-138
@@ -48,53 +48,53 @@
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************************************************************************************/
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/* EMAC Register Offsets ************************************************************/
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#define SAM_EMAC_NCR_OFFSET 0x0000 /* Network Control Register */
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#define SAM_EMAC_NCFGR_OFFSET 0x0004 /* Network Configuration Register */
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#define SAM_EMAC_NSR_OFFSET 0x0008 /* Network Status Register */
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#define SAM_EMAC_NCR_OFFSET 0x0000 /* Network Control Register */
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#define SAM_EMAC_NCFGR_OFFSET 0x0004 /* Network Configuration Register */
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#define SAM_EMAC_NSR_OFFSET 0x0008 /* Network Status Register */
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/* 0x000c-0x0010 Reserved */
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#define SAM_EMAC_TSR_OFFSET 0x0014 /* Transmit Status Register */
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#define SAM_EMAC_RBQP_OFFSET 0x0018 /* Receive Buffer Queue Pointer Register */
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#define SAM_EMAC_TBQP_OFFSET 0x001c /* Transmit Buffer Queue Pointer Register */
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#define SAM_EMAC_RSR_OFFSET 0x0020 /* Receive Status Register */
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#define SAM_EMAC_ISR_OFFSET 0x0024 /* Interrupt Status Register */
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#define SAM_EMAC_IER_OFFSET 0x0028 /* Interrupt Enable Register */
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#define SAM_EMAC_IDR_OFFSET 0x002c /* Interrupt Disable Register */
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#define SAM_EMAC_IMR_OFFSET 0x0030 /* Interrupt Mask Register */
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#define SAM_EMAC_MAN_OFFSET 0x0034 /* Phy Maintenance Register */
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#define SAM_EMAC_PTR_OFFSET 0x0038 /* Pause Time Register */
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#define SAM_EMAC_PFR_OFFSET 0x003c /* Pause Frames Received Register */
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#define SAM_EMAC_FTO_OFFSET 0x0040 /* Frames Transmitted Ok Register */
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#define SAM_EMAC_SCF_OFFSET 0x0044 /* Single Collision Frames Register */
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#define SAM_EMAC_MCF_OFFSET 0x0048 /* Multiple Collision Frames Register */
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#define SAM_EMAC_FRO_OFFSET 0x004c /* Frames Received Ok Register */
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#define SAM_EMAC_FCSE_OFFSET 0x0050 /* Frame Check Sequence Errors Register */
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#define SAM_EMAC_ALE_OFFSET 0x0054 /* Alignment Errors Register */
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#define SAM_EMAC_DTF_OFFSET 0x0058 /* Deferred Transmission Frames Register */
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#define SAM_EMAC_LCOL_OFFSET 0x005c /* Late Collisions Register */
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#define SAM_EMAC_ECOL_OFFSET 0x0060 /* Excessive Collisions Register */
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#define SAM_EMAC_TUND_OFFSET 0x0064 /* Transmit Underrun Errors Register */
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#define SAM_EMAC_CSE_OFFSET 0x0068 /* Carrier Sense Errors Register */
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#define SAM_EMAC_RRE_OFFSET 0x006c /* Receive Resource Errors Register */
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#define SAM_EMAC_ROV_OFFSET 0x0070 /* Receive Overrun Errors Register */
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#define SAM_EMAC_RSE_OFFSET 0x0074 /* Receive Symbol Errors Register */
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#define SAM_EMAC_ELE_OFFSET 0x0078 /* Excessive Length Errors Register */
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#define SAM_EMAC_RJA_OFFSET 0x007c /* Receive Jabbers Register */
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#define SAM_EMAC_USF_OFFSET 0x0080 /* Undersize Frames Register */
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#define SAM_EMAC_STE_OFFSET 0x0084 /* SQE Test Errors Register */
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#define SAM_EMAC_RLE_OFFSET 0x0088 /* Received Length Field Mismatch Register */
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#define SAM_EMAC_HRB_OFFSET 0x0090 /* Hash Register Bottom [31:0] Register */
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#define SAM_EMAC_HRT_OFFSET 0x0094 /* Hash Register Top [63:32] Register */
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#define SAM_EMAC_SA1B_OFFSET 0x0098 /* Specific Address 1 Bottom Register */
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#define SAM_EMAC_SA1T_OFFSET 0x009c /* Specific Address 1 Top Register */
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#define SAM_EMAC_SA2B_OFFSET 0x00a0 /* Specific Address 2 Bottom Register */
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#define SAM_EMAC_SA2T_OFFSET 0x00a4 /* Specific Address 2 Top Register */
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#define SAM_EMAC_SA3B_OFFSET 0x00a8 /* Specific Address 3 Bottom Register */
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#define SAM_EMAC_SA3T_OFFSET 0x00ac /* Specific Address 3 Top Register */
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#define SAM_EMAC_SA4B_OFFSET 0x00b0 /* Specific Address 4 Bottom Register */
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#define SAM_EMAC_SA4T_OFFSET 0x00b4 /* Specific Address 4 Top Register */
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#define SAM_EMAC_TID_OFFSET 0x00b8 /* Type ID Checking Register */
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#define SAM_EMAC_USRIO_OFFSET 0x00c0 /* User Input/Output Register */
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#define SAM_EMAC_WOL_OFFSET 0x00c4 /* Wake on LAN Register */
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#define SAM_EMAC_TSR_OFFSET 0x0014 /* Transmit Status Register */
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#define SAM_EMAC_RBQP_OFFSET 0x0018 /* Receive Buffer Queue Pointer Register */
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#define SAM_EMAC_TBQP_OFFSET 0x001c /* Transmit Buffer Queue Pointer Register */
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#define SAM_EMAC_RSR_OFFSET 0x0020 /* Receive Status Register */
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#define SAM_EMAC_ISR_OFFSET 0x0024 /* Interrupt Status Register */
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#define SAM_EMAC_IER_OFFSET 0x0028 /* Interrupt Enable Register */
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#define SAM_EMAC_IDR_OFFSET 0x002c /* Interrupt Disable Register */
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#define SAM_EMAC_IMR_OFFSET 0x0030 /* Interrupt Mask Register */
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#define SAM_EMAC_MAN_OFFSET 0x0034 /* Phy Maintenance Register */
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#define SAM_EMAC_PTR_OFFSET 0x0038 /* Pause Time Register */
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#define SAM_EMAC_PFR_OFFSET 0x003c /* Pause Frames Received Register */
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#define SAM_EMAC_FTO_OFFSET 0x0040 /* Frames Transmitted Ok Register */
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#define SAM_EMAC_SCF_OFFSET 0x0044 /* Single Collision Frames Register */
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#define SAM_EMAC_MCF_OFFSET 0x0048 /* Multiple Collision Frames Register */
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#define SAM_EMAC_FRO_OFFSET 0x004c /* Frames Received Ok Register */
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#define SAM_EMAC_FCSE_OFFSET 0x0050 /* Frame Check Sequence Errors Register */
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#define SAM_EMAC_ALE_OFFSET 0x0054 /* Alignment Errors Register */
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#define SAM_EMAC_DTF_OFFSET 0x0058 /* Deferred Transmission Frames Register */
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#define SAM_EMAC_LCOL_OFFSET 0x005c /* Late Collisions Register */
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#define SAM_EMAC_ECOL_OFFSET 0x0060 /* Excessive Collisions Register */
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#define SAM_EMAC_TUND_OFFSET 0x0064 /* Transmit Underrun Errors Register */
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#define SAM_EMAC_CSE_OFFSET 0x0068 /* Carrier Sense Errors Register */
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#define SAM_EMAC_RRE_OFFSET 0x006c /* Receive Resource Errors Register */
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#define SAM_EMAC_ROV_OFFSET 0x0070 /* Receive Overrun Errors Register */
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#define SAM_EMAC_RSE_OFFSET 0x0074 /* Receive Symbol Errors Register */
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#define SAM_EMAC_ELE_OFFSET 0x0078 /* Excessive Length Errors Register */
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#define SAM_EMAC_RJA_OFFSET 0x007c /* Receive Jabbers Register */
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#define SAM_EMAC_USF_OFFSET 0x0080 /* Undersize Frames Register */
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#define SAM_EMAC_STE_OFFSET 0x0084 /* SQE Test Errors Register */
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#define SAM_EMAC_RLE_OFFSET 0x0088 /* Received Length Field Mismatch Register */
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#define SAM_EMAC_HRB_OFFSET 0x0090 /* Hash Register Bottom [31:0] Register */
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#define SAM_EMAC_HRT_OFFSET 0x0094 /* Hash Register Top [63:32] Register */
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#define SAM_EMAC_SA1B_OFFSET 0x0098 /* Specific Address 1 Bottom Register */
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#define SAM_EMAC_SA1T_OFFSET 0x009c /* Specific Address 1 Top Register */
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#define SAM_EMAC_SA2B_OFFSET 0x00a0 /* Specific Address 2 Bottom Register */
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#define SAM_EMAC_SA2T_OFFSET 0x00a4 /* Specific Address 2 Top Register */
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#define SAM_EMAC_SA3B_OFFSET 0x00a8 /* Specific Address 3 Bottom Register */
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#define SAM_EMAC_SA3T_OFFSET 0x00ac /* Specific Address 3 Top Register */
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#define SAM_EMAC_SA4B_OFFSET 0x00b0 /* Specific Address 4 Bottom Register */
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#define SAM_EMAC_SA4T_OFFSET 0x00b4 /* Specific Address 4 Top Register */
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#define SAM_EMAC_TID_OFFSET 0x00b8 /* Type ID Checking Register */
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#define SAM_EMAC_USRIO_OFFSET 0x00c0 /* User Input/Output Register */
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#define SAM_EMAC_WOL_OFFSET 0x00c4 /* Wake on LAN Register */
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/* 0x00c8-0x00fc Reserved */
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/* EMAC Register Addresses **********************************************************/
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@@ -148,97 +148,239 @@
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/* EMAC Register Bit Definitions ****************************************************/
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/* Network Control Register */
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#define EMAC_NCR_
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/* Network Configuration Register */
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#define EMAC_NCFGR_
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/* Network Status Register */
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#define EMAC_NSR_
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/* Transmit Status Register */
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#define EMAC_TSR_
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/* Receive Buffer Queue Pointer Register */
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#define EMAC_RBQP_
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/* Transmit Buffer Queue Pointer Register */
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#define EMAC_TBQP_
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/* Receive Status Register */
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#define EMAC_RSR_
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/* Interrupt Status Register */
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#define EMAC_ISR_
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/* Interrupt Enable Register */
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#define EMAC_IER_
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/* Interrupt Disable Register */
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#define EMAC_IDR_
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/* Interrupt Mask Register */
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#define EMAC_IMR_
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/* Phy Maintenance Register */
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#define EMAC_MAN_
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/* Pause Time Register */
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#define EMAC_PTR_
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/* Pause Frames Received Register */
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#define EMAC_PFR_
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/* Frames Transmitted Ok Register */
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#define EMAC_FTO_
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/* Single Collision Frames Register */
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#define EMAC_SCF_
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/* Multiple Collision Frames Register */
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#define EMAC_MCF_
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/* Frames Received Ok Register */
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#define EMAC_FRO_
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/* Frame Check Sequence Errors Register */
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#define EMAC_FCSE_
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/* Alignment Errors Register */
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#define EMAC_ALE_
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/* Deferred Transmission Frames Register */
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#define EMAC_DTF_
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/* Late Collisions Register */
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#define EMAC_LCOL_
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/* Excessive Collisions Register */
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#define EMAC_ECOL_
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/* Transmit Underrun Errors Register */
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#define EMAC_TUND_
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/* Carrier Sense Errors Register */
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#define EMAC_CSE_
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/* Receive Resource Errors Register */
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#define EMAC_RRE_
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/* Receive Overrun Errors Register */
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#define EMAC_ROV_
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/* Receive Symbol Errors Register */
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#define EMAC_RSE_
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/* Excessive Length Errors Register */
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#define EMAC_ELE_
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/* Receive Jabbers Register */
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#define EMAC_RJA_
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/* Undersize Frames Register */
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#define EMAC_USF_
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/* SQE Test Errors Register */
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#define EMAC_STE_
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/* Received Length Field Mismatch Register */
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#define EMAC_RLE_
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/* Hash Register Bottom [31:0] Register */
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#define EMAC_HRB_
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/* Hash Register Top [63:32] Register */
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#define EMAC_HRT_
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/* Specific Address 1 Bottom Register */
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#define EMAC_SA1B_
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/* Specific Address 1 Top Register */
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#define EMAC_SA1T_
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/* Specific Address 2 Bottom Register */
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#define EMAC_SA2B_
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/* Specific Address 2 Top Register */
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#define EMAC_SA2T_
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/* Specific Address 3 Bottom Register */
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#define EMAC_SA3B_
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/* Specific Address 3 Top Register */
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#define EMAC_SA3T_
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/* Specific Address 4 Bottom Register */
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#define EMAC_SA4B_
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/* Specific Address 4 Top Register */
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#define EMAC_SA4T_
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/* Type ID Checking Register */
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#define EMAC_TID_
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/* User Input/Output Register */
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#define EMAC_USRIO_
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/* Wake on LAN Register */
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#define EMAC_WOL_
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/* Network Control Register */
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#define EMAC_NCR_LB (1 << 0) /* Bit 0: LoopBack */
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#define EMAC_NCR_LLB (1 << 1) /* Bit 1: Loopback local */
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#define EMAC_NCR_RE (1 << 2) /* Bit 2: Receive enable */
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#define EMAC_NCR_TE (1 << 3) /* Bit 3: Transmit enable */
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#define EMAC_NCR_MPE (1 << 4) /* Bit 4: Management port enable */
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#define EMAC_NCR_CLRSTAT (1 << 5) /* Bit 5: Clear statistics registers */
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#define EMAC_NCR_INCSTAT (1 << 6) /* Bit 6: Increment statistics registers */
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#define EMAC_NCR_WESTAT (1 << 7) /* Bit 7: Write enable for statistics registers */
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#define EMAC_NCR_BP (1 << 8) /* Bit 8: Back pressure */
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#define EMAC_NCR_TSTART (1 << 9) /* Bit 9: Start transmission */
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#define EMAC_NCR_THALT (1 << 10) /* Bit 10: Transmit halt */
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/* Network Configuration Register */
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#define EMAC_NCFGR_SPD (1 << 0) /* Bit 0: Speed */
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#define EMAC_NCFGR_FD (1 << 1) /* Bit 1: Full Duplex */
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#define EMAC_NCFGR_JFRAME (1 << 3) /* Bit 3: Jumbo Frames */
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#define EMAC_NCFGR_CAF (1 << 4) /* Bit 4: Copy All Frames */
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#define EMAC_NCFGR_NBC (1 << 5) /* Bit 5: No Broadcast */
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#define EMAC_NCFGR_MTI (1 << 6) /* Bit 6: Multicast Hash Enable */
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#define EMAC_NCFGR_UNI (1 << 7) /* Bit 7: Unicast Hash Enable */
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#define EMAC_NCFGR_BIG (1 << 8) /* Bit 8: Receive 1536 bytes frames */
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#define EMAC_NCFGR_CLK_SHIFT (10) /* Bits 10-11: MDC clock divider */
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#define EMAC_NCFGR_CLK_MASK (3 << EMAC_NCFGR_CLK_SHIFT)
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# define EMAC_NCFGR_CLK_DIV8 (0 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 8 (MCK up to 20 MHz) */
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# define EMAC_NCFGR_CLK_DIV16 (1 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 16 (MCK up to 40 MHz) */
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# define EMAC_NCFGR_CLK_DIV32 (2 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 32 (MCK up to 80 MHz) */
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# define EMAC_NCFGR_CLK_DIV64 (3 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 64 (MCK up to 160 MHz) */
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#define EMAC_NCFGR_RTY (1 << 12) /* Bit 12: Retry test */
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#define EMAC_NCFGR_PAE (1 << 13) /* Bit 13: Pause Enable */
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#define EMAC_NCFGR_RBOF_SHIFT (14) /* Bits 14-15: Receive Buffer Offset */
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#define EMAC_NCFGR_RBOF_MASK (3 << EMAC_NCFGR_RBOF_SHIFT)
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# define EMAC_NCFGR_RBOF_NONE (0 << EMAC_NCFGR_RBOF_SHIFT) /* No offset from RX buffer start */
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# define EMAC_NCFGR_RBOF_1 (1 << EMAC_NCFGR_RBOF_SHIFT) /* One-byte offset from RX buffer start */
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# define EMAC_NCFGR_RBOF_2 (2 << EMAC_NCFGR_RBOF_SHIFT) /* Two-byte offset from RX buffer start */
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# define EMAC_NCFGR_RBOF_3 (3 << EMAC_NCFGR_RBOF_SHIFT) /* Three-byte offset fromRX buffer start */
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#define EMAC_NCFGR_RLCE (1 << 16) /* Bit 16: Receive Length field Checking Enable */
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#define EMAC_NCFGR_DRFCS (1 << 17) /* Bit 17: Discard Receive FCS */
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#define EMAC_NCFGR_EFRHD (1 << 18) /* Bit 18: Enable RX frames in HD mode while transmitting */
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#define EMAC_NCFGR_IRXFCS (1 << 19) /* Bit 19: Ignore RX FCS */
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/* Network Status Register */
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#define EMAC_NSR_MDIO (1 << 0) /* Bit 0: Status of the mdio_in pin */
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#define EMAC_NSR_IDLE (1 << 1) /* Bit 1: PHY management logic is idle */
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/* Transmit Status Register */
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#define EMAC_TSR_UBR (1 << 0) /* Bit 0: Used Bit Read */
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#define EMAC_TSR_COL (1 << 1) /* Bit 1: Collision Occurred */
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#define EMAC_TSR_RLES (1 << 2) /* Bit 2: Retry Limit exceeded */
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#define EMAC_TSR_TGO (1 << 3) /* Bit 3: Transmit Go */
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#define EMAC_TSR_BEX (1 << 4) /* Bit 4: Buffers exhausted mid frame */
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#define EMAC_TSR_COMP (1 << 5) /* Bit 5: Transmit Complete */
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#define EMAC_TSR_UND (1 << 6) /* Bit 6: Transmit Underrun */
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/* Receive Buffer Queue Pointer Register */
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#define EMAC_RBQP_MASK (0xfffffffc) /* Bits 2-31: Receive buffer queue pointer address */
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/* Transmit Buffer Queue Pointer Register */
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#define EMAC_TBQP_MASK (0xfffffffc) /* Bits 2-31: Transmit buffer queue pointer address */
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/* Receive Status Register */
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#define EMAC_RSR_BNA (1 << 0) /* Bit 0: Buffer Not Available */
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#define EMAC_RSR_REC (1 << 1) /* Bit 1: Frame Received */
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#define EMAC_RSR_OVR (1 << 2) /* Bit 2: Receive Overrun */
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/* Interrupt Status Register (ISR), Interrupt Enable Register (IER), Interrupt Disable Register (IDR) and Interrupt Mask Register (IMR) */
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#define EMAC_INT_MFD (1 << 0) /* Bit 0: Management Frame Done */
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#define EMAC_INT_RCOMP (1 << 1) /* Bit 1: Receive Complete */
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#define EMAC_INT_RXUBR (1 << 2) /* Bit 2: Receive Used Bit Read */
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#define EMAC_INT_TXUBR (1 << 3) /* Bit 3: Transmit Used Bit Read */
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#define EMAC_INT_TUND (1 << 4) /* Bit 4: Ethernet Transmit Buffer Underrun */
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#define EMAC_INT_RLE (1 << 5) /* Bit 5: Retry Limit Exceeded */
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#define EMAC_INT_TXERR (1 << 6) /* Bit 6: Transmit Error */
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#define EMAC_INT_TCOMP (1 << 7) /* Bit 7: Transmit Complete */
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#define EMAC_INT_ROVR (1 << 10) /* Bit 10: Receive Overrun */
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#define EMAC_INT_HRESP (1 << 11) /* Bit 11: Hresp not OK */
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#define EMAC_INT_PFR (1 << 12) /* Bit 12: Pause Frame Received */
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#define EMAC_INT_PTZ (1 << 13) /* Bit 13: Pause Time Zero */
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#define EMAC_INT_WOL (1 << 14) /* Bit 14: Wake On LAN */
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/* Phy Maintenance Register */
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#define EMAC_MAN_DATA_SHIFT (0) /* Bits 0-15: Read/write data */
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#define EMAC_MAN_DATA_MASK (0x0000ffff << EMAC_MAN_DATA_SHIFT)
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# define EMAC_MAN_DATA(n) ((n) << EMAC_MAN_DATA_SHIFT)
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#define EMAC_MAN_CODE_SHIFT (16) /* Bits 16-17: Must be written to b10 */
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#define EMAC_MAN_CODE_MASK (3 << EMAC_MAN_CODE_SHIFT)
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# define EMAC_MAN_CODE (2 << EMAC_MAN_CODE_SHIFT)
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#define EMAC_MAN_REGA_SHIFT (18) /* Bits 18-22: Register Address */
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#define EMAC_MAN_REGA_MASK (31 << EMAC_MAN_REGA_SHIFT)
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# define EMAC_MAN_REGA(n) ((n) << EMAC_MAN_REGA_SHIFT)
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#define EMAC_MAN_PHYA_SHIFT (23) /* Bits 23-27: PHY Address */
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#define EMAC_MAN_PHYA_MASK (31 << EMAC_MAN_PHYA_SHIFT)
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# define EMAC_MAN_PHYA(n) ((n) << EMAC_MAN_PHYA_SHIFT)
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#define EMAC_MAN_RW_SHIFT (28) /* Bits 28-29: Read-write */
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#define EMAC_MAN_RW_MASK (3 << EMAC_MAN_RW_SHIFT)
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# define EMAC_MAN_READ (2 << EMAC_MAN_RW_SHIFT)
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# define EMAC_MAN_WRITE (1 << EMAC_MAN_RW_SHIFT)
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#define EMAC_MAN_SOF_SHIFT (30) /* Bits 30-31: Start of frame */
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#define EMAC_MAN_SOF_MASK (3 << EMAC_MAN_SOF_SHIFT)
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# define EMAC_MAN_SOF_MASK (1 << EMAC_MAN_SOF_SHIFT) /* Must be written b01 */
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/* Pause Time Register */
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#define EMAC_PTR_MASK (0x0000ffff) /* Bits 0-15: Pause Time */
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/* Pause Frames Received Register */
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#define EMAC_PFR_MASK (0x0000ffff) /* Bits 0-15: Pause Frames received OK */
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/* Frames Transmitted Ok Register */
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#define EMAC_FTO_MASK (0x00ffffff) /* Bits 0-23: Frames Transmitted OK */
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/* Single Collision Frames Register */
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#define EMAC_SCF_MASK (0x0000ffff) /* Bits 0-15: Single Collision Frames */
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/* Multiple Collision Frames Register */
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||||
#define EMAC_MCF_MASK (0x0000ffff) /* Bits 0-15: Multicollision Frames */
|
||||
|
||||
/* Frames Received Ok Register */
|
||||
|
||||
#define EMAC_FRO_MASK (0x00ffffff) /* Bits 0-23: Frames received OK */
|
||||
|
||||
/* Frame Check Sequence Errors Register */
|
||||
|
||||
#define EMAC_FCSE_MASK (0x000000ff) /* Bits 0-7:Frame Check Sequence Errors */
|
||||
|
||||
/* Alignment Errors Register */
|
||||
|
||||
#define EMAC_ALE_MASK (0x000000ff) /* Bits 0-7:Alignment Errors */
|
||||
|
||||
/* Deferred Transmission Frames Register */
|
||||
|
||||
#define EMAC_DTF_MASK (0x0000ffff) /* Bits 0-15: Deferred Transmission Frames */
|
||||
|
||||
/* Late Collisions Register */
|
||||
|
||||
#define EMAC_LCOL_MASK (0x000000ff) /* Bits 0-7: Late Collisions */
|
||||
|
||||
/* Excessive Collisions Register */
|
||||
|
||||
#define EMAC_ECOL_MASK (0x000000ff) /* Bits 0-7: Excessive Collisions Register */
|
||||
|
||||
/* Transmit Underrun Errors Register */
|
||||
|
||||
#define EMAC_TUND_MASK (0x000000ff) /* Bits 0-7: Transmit Underruns */
|
||||
|
||||
/* Carrier Sense Errors Register */
|
||||
|
||||
#define EMAC_CSE_MASK (0x000000ff) /* Bits 0-7: Carrier Sense Errors */
|
||||
|
||||
/* Receive Resource Errors Register */
|
||||
|
||||
#define EMAC_RRE_MASK (0x0000ffff) /* Bits 0-15: Receive Resource Errors */
|
||||
|
||||
/* Receive Overrun Errors Register */
|
||||
|
||||
#define EMAC_ROV_MASK (0x000000ff) /* Bits 0-7: Receive Overrun */
|
||||
|
||||
/* Receive Symbol Errors Register */
|
||||
|
||||
#define EMAC_RSE_MASK (0x000000ff) /* Bits 0-7: Receive Symbol Errors */
|
||||
|
||||
/* Excessive Length Errors Register */
|
||||
|
||||
#define EMAC_ELE_MASK (0x000000ff) /* Bits 0-7: Excessive Length Errors */
|
||||
|
||||
/* Receive Jabbers Register */
|
||||
|
||||
#define EMAC_RJA_MASK (0x000000ff) /* Bits 0-7: Receive Jabbers */
|
||||
|
||||
/* Undersize Frames Register */
|
||||
|
||||
#define EMAC_USF_MASK (0x000000ff) /* Bits 0-7: Undersize frames */
|
||||
|
||||
/* SQE Test Errors Register */
|
||||
|
||||
#define EMAC_STE_MASK (0x000000ff) /* Bits 0-7: SQE test errors */
|
||||
|
||||
/* Received Length Field Mismatch Register */
|
||||
|
||||
#define EMAC_RLE_MASK (0x000000ff) /* Bits 0-7: Receive Length Field Mismatch */
|
||||
|
||||
/* Hash Register Bottom [31:0] Register (LS 32-bit hash address) */
|
||||
/* Hash Register Top [63:32] Register (MS 32-bit hash address) */
|
||||
|
||||
/* Specific Address 1 Bottom [31:0] Register (LS 32-bit address) */
|
||||
/* Specific Address 1 Top [47:32] Register */
|
||||
|
||||
#define EMAC_SA1T_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */
|
||||
|
||||
/* Specific Address 2 Bottom [31:0] Register (LS 32-bit address) */
|
||||
/* Specific Address 2 Top [47:32] Register */
|
||||
|
||||
#define EMAC_SA2T_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */
|
||||
|
||||
/* Specific Address 3 Bottom [31:0] Register (LS 32-bit address) */
|
||||
/* Specific Address 3 Top [47:32] Register */
|
||||
|
||||
#define EMAC_SA3T_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */
|
||||
|
||||
/* Specific Address 4 Bottom [31:0] Register (LS 32-bit address) */
|
||||
/* Specific Address 4 Top [47:32] Register */
|
||||
|
||||
#define EMAC_SA4T_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */
|
||||
|
||||
/* Type ID Checking Register */
|
||||
|
||||
#define EMAC_TID_MASK (0x0000ffff) /* Bits 0-15: For comparisons with received frames TypeID/Length field. */
|
||||
|
||||
/* User Input/Output Register */
|
||||
|
||||
#define EMAC_USRIO_RMII (1 << 0) /* Bit 0: Reduce MII */
|
||||
#define EMAC_USRIO_CLKEN (1 << 1) /* Bit 1: Clock Enable */
|
||||
|
||||
/* Wake on LAN Register */
|
||||
|
||||
#define EMAC_WOL_IP_SHIFT (0) /* Bits 0-15: ARP request IP address */
|
||||
#define EMAC_WOL_IP_MASK (0x0000ffff << EMAC_WOL_IP_SHIFT)
|
||||
#define EMAC_WOL_MAG (1 << 16) /* Bit 16: Magic packet event enable */
|
||||
#define EMAC_WOL_ARP (1 << 17) /* Bit 17: ARP request event enable */
|
||||
#define EMAC_WOL_SA1 (1 << 18) /* Bit 18: Specific address register 1 event enable */
|
||||
#define EMAC_WOL_MTI (1 << 19) /* Bit 19: Multicast hash event enable */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EMAC_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -891,6 +891,33 @@ Configurations
|
||||
|
||||
Configuration sub-directories
|
||||
-----------------------------
|
||||
Summary: Some of the descriptions below are long and wordy. Here is the
|
||||
concise summary of the available SAMA5D3x-EK configurations:
|
||||
|
||||
demo: This is an NSH configuration that supports as much functionality
|
||||
as possible. That is why it gets its name: It attempts to show as
|
||||
much as possible
|
||||
hello: The tiniest configuration possible (almost). It just says
|
||||
"Hello, World!" On the serial console. It is so tiny that it is
|
||||
able to run entirely out of internal SRAM (all of the other
|
||||
configurations except norboot use NOR FLASH for .text and internal
|
||||
SRAM for .data and .bass). This configuration is only useful for
|
||||
bring-up.
|
||||
norboot:
|
||||
This is a little program to help debug of code in NOR flash. I wrote
|
||||
it because I don't yet understand how to get the SAMA5 to boot from
|
||||
NOR FLASH. See the description below and the section above entitled
|
||||
"Creating and Using NORBOOT" for more information
|
||||
nsh: This is another NSH configuration, not too different from the
|
||||
demo configuration. The nsh configuration is, however, bare bones.
|
||||
It is the simplest possible NSH configuration and is useful as a
|
||||
platform for debugging and integrating new features in isolation.
|
||||
ostest: This is another configuration that is only useful for bring-up.
|
||||
It executes an exhaustive OS test to verify a correct port of NuttX
|
||||
to the SAMA5D3-EK. Since it now passes that test, the configuration
|
||||
has little further use other than for reference.
|
||||
|
||||
Now for the gory details:
|
||||
|
||||
demo:
|
||||
This configuration directory provide the NuttShell (NSH). There are
|
||||
|
||||
Reference in New Issue
Block a user