mirror of
https://github.com/apache/nuttx.git
synced 2026-06-06 16:50:55 +08:00
More progress on the PIC32MX Ethernet driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4282 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -124,6 +124,7 @@ struct up_dev_s
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const uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */
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const uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */
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const uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */
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int (* const vector)(int irq, void *context); /* Interrupt handler */
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};
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@@ -545,8 +545,8 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX534F064H)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX4
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# define CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX6
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 64 /* Package PT,MR */
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@@ -574,8 +574,8 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX564F064H)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX4
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# define CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX6
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 64 /* Package PT,MR */
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@@ -603,8 +603,8 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX564F128H)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX4
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# define CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX6
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 64 /* Package PT,MR */
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@@ -632,8 +632,8 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX575F256H)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX4
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# define CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX6
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 64 /* Package PT,MR */
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@@ -661,8 +661,8 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX575F512H)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX4
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# define CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX6
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 64 /* Package PT,MR */
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@@ -690,8 +690,8 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX534F064L)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX4
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# define CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX6
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 100 /* Package PT,PF,BG */
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@@ -719,8 +719,8 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX564F064L)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX4
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# define CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX6
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 100 /* Package PT,PF,BG */
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@@ -748,8 +748,8 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX564F128L)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX4
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# define CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX6
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 100 /* Package PT,PF,BG */
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@@ -777,8 +777,8 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX575F256L)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX4
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# define CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX6
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 100 /* Package PT,PF,BG */
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@@ -806,8 +806,8 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX575F512L)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX4
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# define CHIP_PIC32MX5 1
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# undef CHIP_PIC32MX6
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 100 /* Package PT,PF,BG */
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@@ -835,9 +835,9 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX664F064H)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX4
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# undef CHIP_PIC32MX5
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# undef CHIP_PIC32MX6 1
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# define CHIP_PIC32MX6 1
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 64 /* Package PT,MR */
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# define CHIP_MHZ 80 /* 80MHz maximum frequency */
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@@ -864,9 +864,9 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX664F128H)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX4
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# undef CHIP_PIC32MX5
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# undef CHIP_PIC32MX6 1
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# define CHIP_PIC32MX6 1
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 64 /* Package PT,MR */
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# define CHIP_MHZ 80 /* 80MHz maximum frequency */
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@@ -893,9 +893,9 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX675F256H)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX4
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# undef CHIP_PIC32MX5
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# undef CHIP_PIC32MX6 1
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# define CHIP_PIC32MX6 1
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 64 /* Package PT,MR */
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# define CHIP_MHZ 80 /* 80MHz maximum frequency */
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@@ -922,9 +922,9 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX675F512H)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX4
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# undef CHIP_PIC32MX5
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# undef CHIP_PIC32MX6 1
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# define CHIP_PIC32MX6 1
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 64 /* Package PT,MR */
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# define CHIP_MHZ 80 /* 80MHz maximum frequency */
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@@ -951,9 +951,9 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX695F512H)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX4
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# undef CHIP_PIC32MX5
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# undef CHIP_PIC32MX6 1
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# define CHIP_PIC32MX6 1
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 64 /* Package PT,MR */
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# define CHIP_MHZ 80 /* 80MHz maximum frequency */
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@@ -980,9 +980,9 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX664F064L)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX4
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# undef CHIP_PIC32MX5
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# undef CHIP_PIC32MX6 1
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# define CHIP_PIC32MX6 1
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 100 /* Package PT,PF,BG */
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# define CHIP_MHZ 80 /* 80MHz maximum frequency */
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@@ -1009,9 +1009,9 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX664F128L)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX4
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# undef CHIP_PIC32MX5
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# undef CHIP_PIC32MX6 1
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# define CHIP_PIC32MX6 1
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 100 /* Package PT,PF,BG */
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# define CHIP_MHZ 80 /* 80MHz maximum frequency */
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@@ -1038,9 +1038,9 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX675F256L)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX4
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# undef CHIP_PIC32MX5
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# undef CHIP_PIC32MX6 1
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# define CHIP_PIC32MX6 1
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 100 /* Package PT,PF,BG */
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# define CHIP_MHZ 80 /* 80MHz maximum frequency */
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@@ -1067,9 +1067,9 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX675F512L)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX4
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# undef CHIP_PIC32MX5
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# undef CHIP_PIC32MX6 1
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# define CHIP_PIC32MX6 1
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 100 /* Package PT,PF,BG */
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# define CHIP_MHZ 80 /* 80MHz maximum frequency */
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@@ -1096,9 +1096,9 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX695F512L)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX4
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# undef CHIP_PIC32MX5
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# undef CHIP_PIC32MX6 1
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# define CHIP_PIC32MX6 1
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# undef CHIP_PIC32MX7
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# define CHIP_NPINS 100 /* Package PT,PF,BG */
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# define CHIP_MHZ 80 /* 80MHz maximum frequency */
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@@ -1125,10 +1125,10 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX764F128H)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX4
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# undef CHIP_PIC32MX5
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# undef CHIP_PIC32MX6
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# undef CHIP_PIC32MX7 1
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# define CHIP_PIC32MX7 1
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# define CHIP_NPINS 64 /* Package PT,MR */
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# define CHIP_MHZ 80 /* 80MHz maximum frequency */
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# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
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@@ -1154,10 +1154,10 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX775F256H)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX4
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# undef CHIP_PIC32MX5
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# undef CHIP_PIC32MX6
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# undef CHIP_PIC32MX7 1
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# define CHIP_PIC32MX7 1
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# define CHIP_NPINS 64 /* Package PT,MR */
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# define CHIP_MHZ 80 /* 80MHz maximum frequency */
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# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
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@@ -1183,10 +1183,10 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX775F512H)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX4
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# undef CHIP_PIC32MX5
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# undef CHIP_PIC32MX6
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# undef CHIP_PIC32MX7 1
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# define CHIP_PIC32MX7 1
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# define CHIP_NPINS 64 /* Package PT,MR */
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# define CHIP_MHZ 80 /* 80MHz maximum frequency */
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# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
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@@ -1212,10 +1212,10 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX795F512H)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX4
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# undef CHIP_PIC32MX5
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# undef CHIP_PIC32MX6
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# undef CHIP_PIC32MX7 1
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# define CHIP_PIC32MX7 1
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# define CHIP_NPINS 64 /* Package PT,MR */
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# define CHIP_MHZ 80 /* 80MHz maximum frequency */
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# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
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@@ -1241,10 +1241,10 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX764F128L)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX4
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# undef CHIP_PIC32MX5
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# undef CHIP_PIC32MX6
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# undef CHIP_PIC32MX7 1
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# define CHIP_PIC32MX7 1
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# define CHIP_NPINS 100 /* Package PT,PF,BG */
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# define CHIP_MHZ 80 /* 80MHz maximum frequency */
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# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
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@@ -1270,10 +1270,10 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX775F256L)
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
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# undef CHIP_PIC32MX4
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# undef CHIP_PIC32MX5
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# undef CHIP_PIC32MX6
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# undef CHIP_PIC32MX7 1
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# define CHIP_PIC32MX7 1
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# define CHIP_NPINS 100 /* Package PT,PF,BG */
|
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# define CHIP_MHZ 80 /* 80MHz maximum frequency */
|
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# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
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@@ -1299,10 +1299,10 @@
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# define CHIP_JTAG
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#elif defined(CONFIG_ARCH_CHIP_PIC32MX775F512L)
|
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# undef CHIP_PIC32MX3
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# define CHIP_PIC32MX4
|
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# undef CHIP_PIC32MX4
|
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# undef CHIP_PIC32MX5
|
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# undef CHIP_PIC32MX6
|
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# undef CHIP_PIC32MX7 1
|
||||
# define CHIP_PIC32MX7 1
|
||||
# define CHIP_NPINS 100 /* Package PT,PF,BG */
|
||||
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
@@ -1328,10 +1328,10 @@
|
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# define CHIP_JTAG
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX795F512L)
|
||||
# undef CHIP_PIC32MX3
|
||||
# define CHIP_PIC32MX4
|
||||
# undef CHIP_PIC32MX4
|
||||
# undef CHIP_PIC32MX5
|
||||
# undef CHIP_PIC32MX6
|
||||
# undef CHIP_PIC32MX7 1
|
||||
# define CHIP_PIC32MX7 1
|
||||
# define CHIP_NPINS 100 /* Package PT,PF,BG */
|
||||
# define CHIP_MHZ 80 /* 80MHz maximum frequency */
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -73,9 +73,9 @@
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||||
#define PIC32MX_ETH_IENCLR_OFFSET 0x00c8
|
||||
#define PIC32MX_ETH_IENINV_OFFSET 0x00cc
|
||||
#define PIC32MX_ETH_IRQ_OFFSET 0x00d0 /* Ethernet Controller Interrupt Request Register */
|
||||
#define PIC32MX_ETH_IENSET_OFFSET 0x00d4
|
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#define PIC32MX_ETH_IENCLR_OFFSET 0x00d8
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#define PIC32MX_ETH_IENINV_OFFSET 0x00dc
|
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#define PIC32MX_ETH_IRQSET_OFFSET 0x00d4
|
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#define PIC32MX_ETH_IRQCLR_OFFSET 0x00d8
|
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#define PIC32MX_ETH_IRQINV_OFFSET 0x00dc
|
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#define PIC32MX_ETH_STAT_OFFSET 0x00e0 /* Ethernet Controller Status Register */
|
||||
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||||
/* RX Filtering Configuration Registers */
|
||||
@@ -248,9 +248,9 @@
|
||||
#define PIC32MX_ETH_IENCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IENCLR_OFFSET)
|
||||
#define PIC32MX_ETH_IENINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IENINV_OFFSET)
|
||||
#define PIC32MX_ETH_IRQ (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IRQ_OFFSET)
|
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#define PIC32MX_ETH_IENSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IENSET_OFFSET)
|
||||
#define PIC32MX_ETH_IENCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IENCLR_OFFSET)
|
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#define PIC32MX_ETH_IENINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IENINV_OFFSET)
|
||||
#define PIC32MX_ETH_IRQSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IRQSET_OFFSET)
|
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#define PIC32MX_ETH_IRQCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IRQCLR_OFFSET)
|
||||
#define PIC32MX_ETH_IRQINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IRQINV_OFFSET)
|
||||
#define PIC32MX_ETH_STAT (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_STAT_OFFSET)
|
||||
|
||||
/* RX Filtering Configuration Registers */
|
||||
@@ -441,6 +441,8 @@
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#define ETH_INT_RXBUSE (1 << 13) /* Bit 13: Receive BVCI bus error interrupt */
|
||||
#define ETH_INT_TXBUSE (1 << 14) /* Bit 14: TXBUSEIE: Transmit BVCI bus error interrupt */
|
||||
/* Bits 15-31: Reserved */
|
||||
#define ETH_INT_ALLINTS (0x000063ef)
|
||||
|
||||
/* Ethernet Controller Status Register */
|
||||
|
||||
/* Bits 0-4: Reserved */
|
||||
@@ -591,7 +593,7 @@
|
||||
/* Bits 16-31: Reserved */
|
||||
/* Ethernet Controller MAC Configuration 2 Register */
|
||||
|
||||
#define EMAC1_CFG2_FULLDPLX: (1 << 0) /* Bit 0: Full duplex operation */
|
||||
#define EMAC1_CFG2_FULLDPLX (1 << 0) /* Bit 0: Full duplex operation */
|
||||
#define EMAC1_CFG2_LENGTHCK (1 << 1) /* Bit 1: Frame length checking */
|
||||
#define EMAC1_CFG2_HUGEFRM (1 << 2) /* Bit 2: Huge frame enable */
|
||||
#define EMAC1_CFG2_DELAYCRC (1 << 3) /* Bit 3: Delayed CRC */
|
||||
@@ -633,7 +635,6 @@
|
||||
#define EMAC1_MAXF_MASK (0xffff << EMAC1_MAXF_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
/* Ethernet Controller MAC PHY Support Register */
|
||||
#define EMAC1_SUPP_
|
||||
/* Bits 0-7: Reserved */
|
||||
#define EMAC1_SUPP_SPEEDRMII (1 << 8) /* Bit 8: RMII Speed0=10Bps 1=100Bps */
|
||||
/* Bits 9-10: Reserved */
|
||||
|
||||
@@ -854,6 +854,36 @@ PIC32MX Configuration Options
|
||||
CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
||||
CONFIG_UARTn_2STOP - Two stop bits
|
||||
|
||||
PIC32MX specific PHY/Ethernet device driver settings
|
||||
|
||||
CONFIG_PHY_KS8721 - Selects the Micrel KS8721 PHY
|
||||
CONFIG_PHY_DP83848C - Selects the National Semiconduction DP83848C PHY
|
||||
CONFIG_PHY_LAN8720 - Selects the SMSC LAN8720 PHY
|
||||
CONFIG_PHY_AUTONEG - Enable auto-negotion
|
||||
CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed.
|
||||
CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex
|
||||
CONFIG_NET_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb
|
||||
CONFIG_NET_NTXDESC - Configured number of Tx descriptors. Default: 18
|
||||
CONFIG_NET_NRXDESC - Configured number of Rx descriptors. Default: 18
|
||||
CONFIG_NET_PRIORITY - Ethernet interrupt priority. The is default is
|
||||
the higest priority.
|
||||
CONFIG_NET_WOL - Enable Wake-up on Lan (not fully implemented).
|
||||
CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets.
|
||||
Also needs CONFIG_DEBUG.
|
||||
CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs
|
||||
CONFIG_DEBUG.
|
||||
CONFIG_NET_HASH - Enable receipt of near-perfect match frames.
|
||||
CONFIG_NET_MULTICAST - Enable receipt of multicast (and unicast) frames.
|
||||
Automatically set if CONFIG_NET_IGMP is selected.
|
||||
|
||||
Related DEVCFG3 Configuration Settings:
|
||||
CONFIG_PIC32MX_FETHIO: Ethernet I/O Pin Selection bit:
|
||||
1 = Default Ethernet I/O Pins
|
||||
0 = Alternate Ethernet I/O Pins
|
||||
CONFIG_PIC32MX_FMIIEN: Ethernet MII Enable bit
|
||||
1 = MII enabled
|
||||
0 = RMII enabled
|
||||
|
||||
PIC32MXx USB Device Configuration
|
||||
|
||||
PIC32MXx USB Host Configuration (the PIC32MX does not support USB Host)
|
||||
|
||||
@@ -160,6 +160,9 @@ CONFIG_PIC32MX_DMA=n
|
||||
CONFIG_PIC32MX_CHE=n
|
||||
CONFIG_PIC32MX_USBDEV=n
|
||||
CONFIG_PIC32MX_USBHOST=n
|
||||
CONFIG_PIC32MX_CAN1=n
|
||||
CONFIG_PIC32MX_CAN2=n
|
||||
CONFIG_PIC32MX_ETHERNET=n
|
||||
CONFIG_PIC32MX_IOPORTA=y
|
||||
CONFIG_PIC32MX_IOPORTB=y
|
||||
CONFIG_PIC32MX_IOPORTC=y
|
||||
@@ -255,6 +258,48 @@ CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
CONFIG_UART6_2STOP=0
|
||||
|
||||
#
|
||||
# PIC32MX specific PHY/Ethernet device driver settings
|
||||
#
|
||||
# CONFIG_PHY_KS8721 - Selects the Micrel KS8721 PHY
|
||||
# CONFIG_PHY_DP83848C - Selects the National Semiconduction DP83848C PHY
|
||||
# CONFIG_PHY_LAN8720 - Selects the SMSC LAN8720 PHY
|
||||
# CONFIG_PHY_AUTONEG - Enable auto-negotion
|
||||
# CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed.
|
||||
# CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex
|
||||
# CONFIG_NET_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb
|
||||
# CONFIG_NET_NTXDESC - Configured number of Tx descriptors. Default: 18
|
||||
# CONFIG_NET_NRXDESC - Configured number of Rx descriptors. Default: 18
|
||||
# CONFIG_NET_PRIORITY - Ethernet interrupt priority. The is default is
|
||||
# the higest priority.
|
||||
# CONFIG_NET_WOL - Enable Wake-up on Lan (not fully implemented).
|
||||
# CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets.
|
||||
# Also needs CONFIG_DEBUG.
|
||||
# CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs
|
||||
# CONFIG_DEBUG.
|
||||
# CONFIG_NET_HASH - Enable receipt of near-perfect match frames.
|
||||
# CONFIG_NET_MULTICAST - Enable receipt of multicast (and unicast) frames.
|
||||
# Automatically set if CONFIG_NET_IGMP is selected.
|
||||
#
|
||||
# Related DEVCFG3 Configuration Settings:
|
||||
# CONFIG_PIC32MX_FETHIO: Ethernet I/O Pin Selection bit:
|
||||
# 1 = Default Ethernet I/O Pins
|
||||
# 0 = Alternate Ethernet I/O Pins
|
||||
# CONFIG_PIC32MX_FMIIEN: Ethernet MII Enable bit
|
||||
# 1 = MII enabled
|
||||
# 0 = RMII enabled
|
||||
#
|
||||
CONFIG_PHY_KS8721=n
|
||||
CONFIG_PHY_DP83848C=y
|
||||
CONFIG_PHY_LAN8720=n
|
||||
CONFIG_PHY_AUTONEG=y
|
||||
CONFIG_PHY_SPEED100=n
|
||||
CONFIG_PHY_FDUPLEX=y
|
||||
CONFIG_NET_EMACRAM_SIZE=8192
|
||||
CONFIG_NET_NTXDESC=7
|
||||
CONFIG_NET_NRXDESC=7
|
||||
CONFIG_NET_REGDEBUG=n
|
||||
|
||||
#
|
||||
# General build options
|
||||
#
|
||||
|
||||
Reference in New Issue
Block a user