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arm/armv7-a/r: set the default CPU mode to System

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In SVC mode, the banked register will be inconsistent with the user mode register:

arch/arm/src/armv7-a/arm_vectors.S

 276   .globl  arm_syscall
 277   .globl  arm_vectorsvc
 278   .type arm_vectorsvc, %function
 279
 280 arm_vectorsvc:
...
 286   sub   sp, sp, #XCPTCONTEXT_SIZE        // < SVC mode SP
...
 308   stmia   r0, {r13, r14}^                // < USR mode SP/LR
...

[    2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 4
[    2.200000] [ 4] [ ALERT]   R0: 00000004 80001229 00000001 80202018 00000000 00000000 00000000 802027d0
[    2.200000] [ 4] [ ALERT]   R8: 00000000 00000000 00000000 00000000 00000000 802027d0 1080f710 1080f710
[    2.200000] [ 4] [ ALERT] CPSR: 00000073
[    2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[    2.200000] [ 4] [ ALERT]   R0: 1 80202018 1 80202018 0 0 0 802027d0
[    2.200000] [ 4] [ ALERT]   R8: 0 0 0 0 0 802027d0 1080f710 80001229
[    2.200000] [ 4] [ ALERT] CPSR: 00000070

SVC SP is 0x80202708
USR SP is 0x802027d0
0x802027d0 - 0x80202708 should be XCPTCONTEXT_SIZE

[    2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 51
[    2.200000] [ 4] [ ALERT]   R0: 00000033 00000000 80202780 00000000 00000000 00000000 00000000 80202710
[    2.200000] [ 4] [ ALERT]   R8: 00000000 00000000 00000000 00000000 00000000 80202710 800039d5 800039b2
[    2.200000] [ 4] [ ALERT] CPSR: 00000070
[    2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[    2.200000] [ 4] [ ALERT]   R0: 2b 0 80202780 0 0 0 0 80202710
[    2.200000] [ 4] [ ALERT]   R8: 0 0 0 0 0 10843d80 800039d5 10801425
[    2.200000] [ 4] [ ALERT] CPSR: 00000073

SVC SP is 0x80202708
USR SP is 0x80202710
SP overlap in SVC and USR mode

This commit change the default CPU mode to System and ensure the consistency of SP/LR in USR/SYS mode during syscall.

Signed-off-by: chao.an <anchao@xiaomi.com>
This commit is contained in:
chao.an
2022-03-14 10:34:51 +08:00
committed by Masayuki Ishikawa
parent 54e630e14d
commit 7c02432f0e
30 changed files with 264 additions and 1206 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/arm/arm_head.S
+2 -2
View File
@@ -220,9 +220,9 @@
.type __start, #function
__start:
/* Make sure that we are in SVC mode with all IRQs disabled */
/* Make sure that we are in SYS mode with all IRQs disabled */
mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
mov r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
msr cpsr_c, r0
/* Initialize DRAM using a macro provided by board-specific logic */
arch/arm/src/arm/arm_initialstate.c
+2 -2
View File
@@ -111,7 +111,7 @@ void up_initial_state(struct tcb_s *tcb)
{
/* It is a kernel thread.. set supervisor mode */
cpsr = PSR_MODE_SVC | PSR_F_BIT;
cpsr = PSR_MODE_SYS | PSR_F_BIT;
}
else
{
@@ -124,7 +124,7 @@ void up_initial_state(struct tcb_s *tcb)
* supervisor-mode.
*/
cpsr = PSR_MODE_SVC | PSR_F_BIT;
cpsr = PSR_MODE_SYS | PSR_F_BIT;
#endif
/* Enable or disable interrupts, based on user configuration */
arch/arm/src/arm/arm_nommuhead.S
+1 -1
View File
@@ -58,7 +58,7 @@ __start:
/* First, setup initial processor mode */
mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT )
mov r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT )
msr cpsr, r0
/* Setup system stack (and get the BSS range) */
arch/arm/src/arm/arm_schedulesigaction.c
+2 -2
View File
@@ -130,7 +130,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
CURRENT_REGS[REG_CPSR] = PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT;
CURRENT_REGS[REG_CPSR] = PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT;
/* And make sure that the saved context in the TCB
* is the same as the interrupt return context.
@@ -162,7 +162,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
tcb->xcp.regs[REG_CPSR] = PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT;
tcb->xcp.regs[REG_CPSR] = PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT;
}
}
}
arch/arm/src/arm/arm_vectors.S
+44 -330
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/armv7-a/arm_cpuhead.S
+15 -5
View File
@@ -90,6 +90,11 @@
.type __cpu1_start, #function
__cpu1_start:
/* Make sure that we are in SYS mode with IRQs and FIQs disabled */
mov r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
msr cpsr_c, r0
/* Set up the stack pointer and the CPU index */
ldr sp, .Lcpu1_stackpointer
@@ -108,6 +113,11 @@ __cpu1_start:
.type __cpu2_start, #function
__cpu2_start:
/* Make sure that we are in SYS mode with IRQs and FIQs disabled */
mov r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
msr cpsr_c, r0
/* Set up the stack pointer and the CPU index */
ldr sp, .Lcpu2_stackpointer
@@ -126,6 +136,11 @@ __cpu2_start:
.type __cpu3_start, #function
__cpu3_start:
/* Make sure that we are in SYS mode with IRQs and FIQs disabled */
mov r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
msr cpsr_c, r0
/* Set up the stack pointer and the CPU index */
ldr sp, .Lcpu3_stackpointer
@@ -162,11 +177,6 @@ __cpu3_start:
.type .Lcpu_start, #function
.Lcpu_start:
/* Make sure that we are in SVC mode with IRQs and FIQs disabled */
mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
msr cpsr_c, r0
/* The MMU and caches should be disabled */
mrc CP15_SCTLR(r0)
arch/arm/src/armv7-a/arm_head.S
+2 -2
View File
@@ -172,9 +172,9 @@
.type __start, #function
__start:
/* Make sure that we are in SVC mode with IRQs and FIQs disabled */
/* Make sure that we are in SYS mode with IRQs and FIQs disabled */
mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
mov r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
msr cpsr_c, r0
/* The MMU and caches should be disabled */
arch/arm/src/armv7-a/arm_initialstate.c
+1 -1
View File
@@ -109,7 +109,7 @@ void up_initial_state(struct tcb_s *tcb)
* privileges will be dropped before transitioning to user code.
*/
cpsr = PSR_MODE_SVC;
cpsr = PSR_MODE_SYS;
/* Enable or disable interrupts, based on user configuration */
arch/arm/src/armv7-a/arm_pghead.S
+2 -2
View File
@@ -201,9 +201,9 @@
.type __start, #function
__start:
/* Make sure that we are in SVC mode with IRQs and FIQs disabled */
/* Make sure that we are in SYS mode with IRQs and FIQs disabled */
mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
mov r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
msr cpsr_c, r0
/* Clear the 16K level 1 page table */
arch/arm/src/armv7-a/arm_schedulesigaction.c
+5 -5
View File
@@ -135,7 +135,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT |
CURRENT_REGS[REG_CPSR] = (PSR_MODE_SYS | PSR_I_BIT |
PSR_F_BIT);
#ifdef CONFIG_ARM_THUMB
CURRENT_REGS[REG_CPSR] |= PSR_T_BIT;
@@ -170,7 +170,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT);
#ifdef CONFIG_ARM_THUMB
tcb->xcp.regs[REG_CPSR] |= PSR_T_BIT;
#endif
@@ -257,7 +257,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT |
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SYS | PSR_I_BIT |
PSR_F_BIT);
#ifdef CONFIG_ARM_THUMB
tcb->xcp.regs[REG_CPSR] |= PSR_T_BIT;
@@ -283,7 +283,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT |
CURRENT_REGS[REG_CPSR] = (PSR_MODE_SYS | PSR_I_BIT |
PSR_F_BIT);
#ifdef CONFIG_ARM_THUMB
CURRENT_REGS[REG_CPSR] |= PSR_T_BIT;
@@ -347,7 +347,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT);
#ifdef CONFIG_ARM_THUMB
tcb->xcp.regs[REG_CPSR] |= PSR_T_BIT;
#endif
arch/arm/src/armv7-a/arm_syscall.c
+2 -2
View File
@@ -424,7 +424,7 @@ uint32_t *arm_syscall(uint32_t *regs)
regs[REG_PC] = rtcb->xcp.sigreturn;
cpsr = regs[REG_CPSR] & ~PSR_MODE_MASK;
regs[REG_CPSR] = cpsr | PSR_MODE_SVC;
regs[REG_CPSR] = cpsr | PSR_MODE_SYS;
rtcb->xcp.sigreturn = 0;
#ifdef CONFIG_ARCH_KERNEL_STACK
@@ -477,7 +477,7 @@ uint32_t *arm_syscall(uint32_t *regs)
regs[REG_PC] = (uint32_t)dispatch_syscall;
#ifdef CONFIG_BUILD_KERNEL
cpsr = regs[REG_CPSR] & ~PSR_MODE_MASK;
regs[REG_CPSR] = cpsr | PSR_MODE_SVC;
regs[REG_CPSR] = cpsr | PSR_MODE_SYS;
#endif
/* Offset R0 to account for the reserved values */
arch/arm/src/armv7-a/arm_vectors.S
+69 -402
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/armv7-r/arm_head.S
+2 -2
View File
@@ -134,9 +134,9 @@
.type __start, #function
__start:
/* Make sure that we are in SVC mode with IRQs and FIQs disabled */
/* Make sure that we are in SYS mode with IRQs and FIQs disabled */
mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
mov r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
msr cpsr_c, r0
/* Set up the stack pointer and clear the frame pointer. */
arch/arm/src/armv7-r/arm_initialstate.c
+1 -1
View File
@@ -109,7 +109,7 @@ void up_initial_state(struct tcb_s *tcb)
* privileges will be dropped before transitioning to user code.
*/
cpsr = PSR_MODE_SVC;
cpsr = PSR_MODE_SYS;
/* Enable or disable interrupts, based on user configuration */
arch/arm/src/armv7-r/arm_schedulesigaction.c
+2 -2
View File
@@ -130,7 +130,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT |
CURRENT_REGS[REG_CPSR] = (PSR_MODE_SYS | PSR_I_BIT |
PSR_F_BIT);
#ifdef CONFIG_ENDIAN_BIG
@@ -166,7 +166,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT |
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SYS | PSR_I_BIT |
PSR_F_BIT);
#ifdef CONFIG_ENDIAN_BIG
arch/arm/src/armv7-r/arm_syscall.c
+2 -2
View File
@@ -419,7 +419,7 @@ uint32_t *arm_syscall(uint32_t *regs)
regs[REG_PC] = rtcb->xcp.sigreturn;
cpsr = regs[REG_CPSR] & ~PSR_MODE_MASK;
regs[REG_CPSR] = cpsr | PSR_MODE_SVC;
regs[REG_CPSR] = cpsr | PSR_MODE_SYS;
rtcb->xcp.sigreturn = 0;
#ifdef CONFIG_ARCH_KERNEL_STACK
@@ -472,7 +472,7 @@ uint32_t *arm_syscall(uint32_t *regs)
regs[REG_PC] = (uint32_t)dispatch_syscall;
#ifdef CONFIG_BUILD_PROTECTED
cpsr = regs[REG_CPSR] & ~PSR_MODE_MASK;
regs[REG_CPSR] = cpsr | PSR_MODE_SVC;
regs[REG_CPSR] = cpsr | PSR_MODE_SYS;
#endif
/* Offset R0 to account for the reserved values */
arch/arm/src/armv7-r/arm_vectors.S
+69 -402
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/c5471/c5471_irq.c
+1 -1
View File
@@ -169,7 +169,7 @@ void up_irqinitialize(void)
/* And finally, enable interrupts */
#ifndef CONFIG_SUPPRESS_INTERRUPTS
up_irq_restore(PSR_MODE_SVC | PSR_F_BIT);
up_irq_restore(PSR_MODE_SYS | PSR_F_BIT);
#endif
}
arch/arm/src/c5471/c5471_vectors.S
+28 -28
View File
@@ -85,18 +85,18 @@ arm_vectorirq:
mrs lr, spsr
str lr, [r13, #4] /* Save spsr_IRQ */
/* Then switch back to SVC mode */
/* Then switch back to SYS mode */
bic lr, lr, #PSR_MODE_MASK /* Keep F and T bits */
orr lr, lr, #(PSR_MODE_SVC | PSR_I_BIT)
msr cpsr_c, lr /* Switch to SVC mode */
orr lr, lr, #(PSR_MODE_SYS | PSR_I_BIT)
msr cpsr_c, lr /* Switch to SYS mode */
/* Create a context structure. First set aside a stack frame
* and store r0-r12 into the frame.
*/
sub sp, sp, #XCPTCONTEXT_SIZE
stmia sp, {r0-r12} /* Save the SVC mode regs */
stmia sp, {r0-r12} /* Save the SYS mode regs */
/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
@@ -153,9 +153,9 @@ arm_vectorirq:
bl arm_doirq /* Call the handler */
#endif
/* Restore the CPSR, SVC mode registers and return */
/* Restore the CPSR, SYS mode registers and return */
.Lnoirqset:
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SYS mode SPSR */
msr spsr_cxsf, r0
ldmia sp, {r0-r15}^ /* Return */
@@ -171,7 +171,7 @@ arm_vectorirq:
* Function: arm_vectorsvc
*
* Description:
* SWI interrupt. We enter the SWI in SVC mode
* SWI interrupt. We enter the SWI in SYS mode
****************************************************************************/
.globl arm_vectorsvc
@@ -191,7 +191,7 @@ arm_vectorsvc:
*/
sub sp, sp, #XCPTCONTEXT_SIZE
stmia sp, {r0-r12} /* Save the SVC mode regs */
stmia sp, {r0-r12} /* Save the SYS mode regs */
/* Get the correct values of r13(sp), r14(lr), r15(pc)
* and CPSR in r1-r4 */
@@ -212,9 +212,9 @@ arm_vectorsvc:
mov r0, sp /* Get r0=xcp */
bl arm_syscall /* Call the handler */
/* Restore the CPSR, SVC mode registers and return */
/* Restore the CPSR, SYS mode registers and return */
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SYS mode SPSR */
msr spsr_cxsf, r0
ldmia sp, {r0-r15}^ /* Return */
@@ -243,18 +243,18 @@ arm_vectordata:
mrs lr, spsr /* Get SPSR */
str lr, [r13, #4] /* Save in temp storage */
/* Then switch back to SVC mode */
/* Then switch back to SYS mode */
bic lr, lr, #PSR_MODE_MASK /* Keep F and T bits */
orr lr, lr, #(PSR_MODE_SVC | PSR_I_BIT)
msr cpsr_c, lr /* Switch to SVC mode */
orr lr, lr, #(PSR_MODE_SYS | PSR_I_BIT)
msr cpsr_c, lr /* Switch to SYS mode */
/* Create a context structure. First set aside a stack frame
* and store r0-r12 into the frame.
*/
sub sp, sp, #XCPTCONTEXT_SIZE
stmia sp, {r0-r12} /* Save the SVC mode regs */
stmia sp, {r0-r12} /* Save the SYS mode regs */
/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
@@ -277,9 +277,9 @@ arm_vectordata:
mov r0, sp /* Get r0=xcp */
bl arm_dataabort /* Call the handler */
/* Restore the CPSR, SVC mode registers and return */
/* Restore the CPSR, SYS mode registers and return */
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SYS mode SPSR */
msr spsr_cxsf, r0
ldmia sp, {r0-r15}^ /* Return */
@@ -309,18 +309,18 @@ arm_vectorprefetch:
mrs lr, spsr /* Get SPSR */
str lr, [r13, #4] /* Save in temp storage */
/* Then switch back to SVC mode */
/* Then switch back to SYS mode */
bic lr, lr, #PSR_MODE_MASK /* Keep F and T bits */
orr lr, lr, #(PSR_MODE_SVC | PSR_I_BIT)
msr cpsr_c, lr /* Switch to SVC mode */
orr lr, lr, #(PSR_MODE_SYS | PSR_I_BIT)
msr cpsr_c, lr /* Switch to SYS mode */
/* Create a context structure. First set aside a stack frame
* and store r0-r12 into the frame.
*/
sub sp, sp, #XCPTCONTEXT_SIZE
stmia sp, {r0-r12} /* Save the SVC mode regs */
stmia sp, {r0-r12} /* Save the SYS mode regs */
/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
@@ -343,9 +343,9 @@ arm_vectorprefetch:
mov r0, sp /* Get r0=xcp */
bl arm_prefetchabort /* Call the handler */
/* Restore the CPSR, SVC mode registers and return */
/* Restore the CPSR, SYS mode registers and return */
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SYS mode SPSR */
msr spsr_cxsf, r0
ldmia sp, {r0-r15}^ /* Return */
@@ -375,18 +375,18 @@ arm_vectorundefinsn:
mrs lr, spsr /* Get SPSR */
str lr, [r13, #4] /* Save in temp storage */
/* Then switch back to SVC mode */
/* Then switch back to SYS mode */
bic lr, lr, #PSR_MODE_MASK /* Keep F and T bits */
orr lr, lr, #(PSR_MODE_SVC | PSR_I_BIT)
msr cpsr_c, lr /* Switch to SVC mode */
orr lr, lr, #(PSR_MODE_SYS | PSR_I_BIT)
msr cpsr_c, lr /* Switch to SYS mode */
/* Create a context structure. First set aside a stack frame
* and store r0-r12 into the frame.
*/
sub sp, sp, #XCPTCONTEXT_SIZE
stmia sp, {r0-r12} /* Save the SVC mode regs */
stmia sp, {r0-r12} /* Save the SYS mode regs */
/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
@@ -409,9 +409,9 @@ arm_vectorundefinsn:
mov r0, sp /* Get r0=xcp */
bl arm_undefinedinsn /* Call the handler */
/* Restore the CPSR, SVC mode registers and return */
/* Restore the CPSR, SYS mode registers and return */
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SYS mode SPSR */
msr spsr_cxsf, r0
ldmia sp, {r0-r15}^ /* Return */
arch/arm/src/dm320/dm320_irq.c
+1 -1
View File
@@ -105,7 +105,7 @@ void up_irqinitialize(void)
/* And finally, enable interrupts */
#ifndef CONFIG_SUPPRESS_INTERRUPTS
up_irq_restore(PSR_MODE_SVC | PSR_F_BIT);
up_irq_restore(PSR_MODE_SYS | PSR_F_BIT);
#endif
}
arch/arm/src/dm320/dm320_restart.S
+2 -2
View File
@@ -51,9 +51,9 @@
.globl up_restart
.type up_restart, %function
up_restart:
/* Make sure that we are in SVC mode with all IRQs disabled */
/* Make sure that we are in SYS mode with all IRQs disabled */
mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
mov r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
msr cpsr_c, r0
/* Create identity mapping for first MB section to support
arch/arm/src/imx1/imx_irq.c
+1 -1
View File
@@ -89,7 +89,7 @@ void up_irqinitialize(void)
/* And finally, enable interrupts */
up_irq_restore(PSR_MODE_SVC | PSR_F_BIT);
up_irq_restore(PSR_MODE_SYS | PSR_F_BIT);
#endif
}
arch/arm/src/lpc214x/lpc214x_head.S
+1 -1
View File
@@ -494,7 +494,7 @@ _vector_table:
__start:
/* Setup the initial processor mode */
mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT )
mov r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT )
msr cpsr, r0
/* Set up external memory mode (if so selected) */
arch/arm/src/lpc214x/lpc214x_irq.c
+1 -1
View File
@@ -100,7 +100,7 @@ void up_irqinitialize(void)
/* And finally, enable interrupts */
#ifndef CONFIG_SUPPRESS_INTERRUPTS
up_irq_restore(PSR_MODE_SVC | PSR_F_BIT);
up_irq_restore(PSR_MODE_SYS | PSR_F_BIT);
#endif
}
arch/arm/src/lpc2378/lpc23xx_head.S
+1 -1
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@@ -144,7 +144,7 @@ __start:
/* First, setup initial processor mode */
mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT )
mov r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT )
msr cpsr, r0
/* Configure the uart so that we can get debug output as soon
arch/arm/src/lpc2378/lpc23xx_irq.c
+1 -1
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@@ -117,7 +117,7 @@ void up_irqinitialize(void)
/* Enable global ARM interrupts */
#ifndef CONFIG_SUPPRESS_INTERRUPTS
up_irq_restore(PSR_MODE_SVC | PSR_F_BIT);
up_irq_restore(PSR_MODE_SYS | PSR_F_BIT);
#endif
}
arch/arm/src/lpc31xx/lpc31_irq.c
+1 -1
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@@ -113,7 +113,7 @@ void up_irqinitialize(void)
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts */
up_irq_restore(PSR_MODE_SVC | PSR_F_BIT);
up_irq_restore(PSR_MODE_SYS | PSR_F_BIT);
#endif
}
arch/arm/src/moxart/moxart_irq.c
+1 -1
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@@ -138,7 +138,7 @@ void up_irqinitialize(void)
getreg32(0x98800020));
#ifndef CONFIG_SUPPRESS_INTERRUPTS
up_irq_restore(PSR_MODE_SVC | PSR_F_BIT);
up_irq_restore(PSR_MODE_SYS | PSR_F_BIT);
#endif
}
arch/arm/src/str71x/str71x_head.S
+1 -1
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@@ -470,7 +470,7 @@ __flashstart:
/* Setup the initial processor mode */
mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT )
mov r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT )
msr cpsr, r0
/* Initialize the external memory interface (EMI) */
arch/arm/src/str71x/str71x_irq.c
+1 -1
View File
@@ -88,7 +88,7 @@ void up_irqinitialize(void)
/* Enable global ARM interrupts */
#ifndef CONFIG_SUPPRESS_INTERRUPTS
up_irq_restore(PSR_MODE_SVC | PSR_F_BIT);
up_irq_restore(PSR_MODE_SYS | PSR_F_BIT);
#endif
}