sched: replace up_cpu_index with this_cpu

Make this_cpu is arch independent and up_cpu_index do that.
In AMP mode, up_cpu_index() may return the index of the physical core.

Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>

arch/arm/src/armv6-m/arm_initialstate.c

@@ -157,7 +157,7 @@ void up_initial_state(struct tcb_s *tcb)
 
 noinline_function void arm_initialize_stack(void)
 {
-  uint32_t stack = up_get_intstackbase(up_cpu_index()) + INTSTACK_SIZE;
+  uint32_t stack = up_get_intstackbase(this_cpu()) + INTSTACK_SIZE;
   uint32_t tempa = 0;
   uint32_t tempb = 2;
 

arch/arm/src/armv7-a/smp.h

@@ -114,7 +114,7 @@ void __cpu3_start(void);
  *
  * Input Parameters:
  *   cpu - The CPU index.  This is the same value that would be obtained by
- *      calling up_cpu_index();
+ *      calling this_cpu();
  *
  * Returned Value:
  *   Does not return.

arch/arm/src/armv7-m/arm_initialstate.c

@@ -180,7 +180,7 @@ void up_initial_state(struct tcb_s *tcb)
 
 noinline_function void arm_initialize_stack(void)
 {
-  uint32_t stack = up_get_intstackbase(up_cpu_index()) + INTSTACK_SIZE;
+  uint32_t stack = up_get_intstackbase(this_cpu()) + INTSTACK_SIZE;
   uint32_t temp = 0;
 
   __asm__ __volatile__

arch/arm/src/armv7-r/smp.h

@@ -114,7 +114,7 @@ void __cpu3_start(void);
  *
  * Input Parameters:
  *   cpu - The CPU index.  This is the same value that would be obtained by
- *      calling up_cpu_index();
+ *      calling this_cpu();
  *
  * Returned Value:
  *   Does not return.

arch/arm/src/armv8-m/arm_doirq.c

@@ -140,7 +140,7 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
   board_autoled_off(LED_INIRQ);
 
 #ifdef CONFIG_ARMV8M_TRUSTZONE_HYBRID
-  if (((1 << up_cpu_index()) & CONFIG_ARMV8M_TRUSTZONE_CPU_BITMASK) == 0)
+  if (((1 << this_cpu()) & CONFIG_ARMV8M_TRUSTZONE_CPU_BITMASK) == 0)
     {
       regs[REG_EXC_RETURN] &=
         ~(EXC_RETURN_EXC_SECURE | EXC_RETURN_SECURE_STACK);

arch/arm/src/armv8-m/arm_initialstate.c

@@ -186,7 +186,7 @@ void up_initial_state(struct tcb_s *tcb)
 
 noinline_function void arm_initialize_stack(void)
 {
-  uint32_t stacklim = up_get_intstackbase(up_cpu_index());
+  uint32_t stacklim = up_get_intstackbase(this_cpu());
   uint32_t stack = stacklim + INTSTACK_SIZE;
   uint32_t temp = 0;
 

arch/arm/src/common/arm_backtrace_fp.c

@@ -125,7 +125,7 @@ int up_backtrace(struct tcb_s *tcb,
       if (up_interrupt_context())
         {
 #if CONFIG_ARCH_INTERRUPTSTACK > 7
-          void *istackbase = (void *)up_get_intstackbase(up_cpu_index());
+          void *istackbase = (void *)up_get_intstackbase(this_cpu());
 
           ret = backtrace(istackbase,
                           istackbase + INTSTACK_SIZE,

arch/arm/src/common/arm_backtrace_sp.c

@@ -266,7 +266,7 @@ int up_backtrace(struct tcb_s *tcb,
         {
           unsigned long top =
 #if CONFIG_ARCH_INTERRUPTSTACK > 7
-            up_get_intstackbase(up_cpu_index()) + INTSTACK_SIZE;
+            up_get_intstackbase(this_cpu()) + INTSTACK_SIZE;
 #else
             (unsigned long)rtcb->stack_base_ptr +
                            rtcb->adj_stack_size;

arch/arm/src/common/arm_backtrace_unwind.c

@@ -736,7 +736,7 @@ int up_backtrace(struct tcb_s *tcb,
       if (up_interrupt_context())
         {
 #if CONFIG_ARCH_INTERRUPTSTACK > 7
-          frame.stack_base = up_get_intstackbase(up_cpu_index());
+          frame.stack_base = up_get_intstackbase(this_cpu());
           frame.stack_top = frame.stack_base + INTSTACK_SIZE;
 #endif /* CONFIG_ARCH_INTERRUPTSTACK > 7 */
 

arch/arm/src/cxd56xx/cxd56_cpupause.c

@@ -315,7 +315,7 @@ int up_cpu_paused_restore(void)
 
 int arm_pause_handler(int irq, void *c, void *arg)
 {
-  int cpu = up_cpu_index();
+  int cpu = this_cpu();
   int ret = OK;
 
   DPRINTF("cpu%d will be paused\n", cpu);

arch/arm/src/cxd56xx/cxd56_cpustart.c

@@ -94,7 +94,7 @@ static void appdsp_boot(void)
 {
   int cpu;
 
-  cpu = up_cpu_index();
+  cpu = this_cpu();
   DPRINTF("cpu = %d\n", cpu);
 
 #if CONFIG_ARCH_INTERRUPTSTACK > 7

arch/arm/src/cxd56xx/cxd56_farapi.c

@@ -185,7 +185,7 @@ void farapi_main(int id, void *arg, struct modulelist_s *mlist)
   int ret;
 
 #ifdef CONFIG_SMP
-  int cpu = up_cpu_index();
+  int cpu = this_cpu();
   static cpu_set_t cpuset0;
 
   if (0 != cpu)

arch/arm/src/cxd56xx/cxd56_irq.c

@@ -413,7 +413,7 @@ void up_disable_irq(int irq)
 
       /* If a different cpu requested, send an irq request */
 
-      if (cpu != (int8_t)up_cpu_index())
+      if (cpu != (int8_t)this_cpu())
         {
           up_send_irqreq(1, irq, cpu);
           return;
@@ -462,7 +462,7 @@ void up_enable_irq(int irq)
   if (irq >= CXD56_IRQ_EXTINT)
     {
 #ifdef CONFIG_SMP
-      int cpu = up_cpu_index();
+      int cpu = this_cpu();
 
       /* Set the caller cpu for this irq */
 

arch/arm/src/cxd56xx/cxd56_testset.c

@@ -94,7 +94,7 @@ spinlock_t up_testset(volatile spinlock_t *lock)
 {
 #ifdef CONFIG_CXD56_TESTSET_WITH_HWSEM
   spinlock_t ret;
-  uint32_t sphlocked = ((up_cpu_index() + 2) << 16) | 0x1;
+  uint32_t sphlocked = ((this_cpu() + 2) << 16) | 0x1;
 
   /* Lock hardware semaphore */
 

arch/arm/src/imx6/imx_cpuboot.c

@@ -238,7 +238,7 @@ void imx_cpu_enable(void)
  *
  * Input Parameters:
  *   cpu - The CPU index.  This is the same value that would be obtained by
- *      calling up_cpu_index();
+ *      calling this_cpu();
  *
  * Returned Value:
  *   Does not return.

arch/arm/src/lc823450/lc823450_cpupause.c

@@ -236,7 +236,7 @@ int up_cpu_paused_restore(void)
 
 int lc823450_pause_handler(int irq, void *c, void *arg)
 {
-  int cpu = up_cpu_index();
+  int cpu = this_cpu();
 
   /* Clear : Pause IRQ */
 

arch/arm/src/lc823450/lc823450_cpustart.c

@@ -85,7 +85,7 @@ extern int lc823450_pause_handler(int irq, void *c, void *arg);
 
 static void cpu1_boot(void)
 {
-  int cpu = up_cpu_index();
+  int cpu = this_cpu();
 
   DPRINTF("cpu = %d\n", cpu);
 

arch/arm/src/lc823450/lc823450_dvfs2.c

@@ -433,7 +433,7 @@ void lc823450_dvfs_get_idletime(uint64_t idletime[])
   memcpy(idletime, g_idle_totaltime, sizeof(g_idle_totaltime));
 
 #if CONFIG_SMP_NCPUS == 2
-  int me = up_cpu_index();
+  int me = this_cpu();
 
   if (0 == _dvfs_another_cpu_state(me))
     {
@@ -504,7 +504,7 @@ void lc823450_dvfs_enter_idle(void)
 {
   irqstate_t flags = spin_lock_irqsave(NULL);
 
-  int me = up_cpu_index();
+  int me = this_cpu();
 
   /* Update my state first : 0 (idle) */
 
@@ -554,7 +554,7 @@ void lc823450_dvfs_exit_idle(int irq)
 {
   irqstate_t flags = spin_lock_irqsave(NULL);
 
-  int me = up_cpu_index();
+  int me = this_cpu();
   uint64_t d;
   uint64_t now;
 

arch/arm/src/lc823450/lc823450_idle.c

@@ -86,7 +86,7 @@ void up_idle(void)
   lc823450_dvfs_enter_idle();
 #endif
 
-  board_autoled_off(LED_CPU0 + up_cpu_index());
+  board_autoled_off(LED_CPU0 + this_cpu());
 
   up_irq_restore(flags);
 
@@ -94,7 +94,7 @@ void up_idle(void)
 
   asm("WFI");
 
-  g_idle_counter[up_cpu_index()]++;
+  g_idle_counter[this_cpu()]++;
 
 #endif
 }

arch/arm/src/lc823450/lc823450_irq.c

@@ -676,10 +676,10 @@ void arm_ack_irq(int irq)
   lc823450_dvfs_exit_idle(irq);
 #endif
 
-  board_autoled_on(LED_CPU0 + up_cpu_index());
+  board_autoled_on(LED_CPU0 + this_cpu());
 
 #ifdef CONFIG_SMP
-  if (irq > LC823450_IRQ_LPDSP0 && 1 == up_cpu_index())
+  if (irq > LC823450_IRQ_LPDSP0 && 1 == this_cpu())
     {
       /* IRQ should be handled on CPU0 */
 

arch/arm/src/lc823450/lc823450_testset.c

@@ -71,7 +71,7 @@ spinlock_t up_testset(volatile spinlock_t *lock)
 
   flags = up_irq_save();
 
-  val = (up_cpu_index() << 16) | 0x1;
+  val = (this_cpu() << 16) | 0x1;
 
   do
     {
@@ -90,7 +90,7 @@ spinlock_t up_testset(volatile spinlock_t *lock)
 
   SP_DMB();
 
-  val = (up_cpu_index() << 16) | 0x0;
+  val = (this_cpu() << 16) | 0x0;
   putreg32(val, MUTEX_REG_MUTEX0);
 
   up_irq_restore(flags);

arch/arm/src/qemu/qemu_cpuboot.c

@@ -111,7 +111,7 @@ void qemu_cpu_enable(void)
  *
  * Input Parameters:
  *   cpu - The CPU index.  This is the same value that would be obtained by
- *      calling up_cpu_index();
+ *      calling this_cpu();
  *
  * Returned Value:
  *   Does not return.

arch/arm/src/rp2040/rp2040_cpupause.c

@@ -86,7 +86,7 @@ static volatile spinlock_t g_cpu_resumed[CONFIG_SMP_NCPUS];
 
 static void rp2040_handle_irqreq(int irqreq)
 {
-  DEBUGASSERT(up_cpu_index() == 0);
+  DEBUGASSERT(this_cpu() == 0);
 
   /* Unlock the spinlock first */
 
@@ -276,7 +276,7 @@ int up_cpu_paused_restore(void)
 
 int arm_pause_handler(int irq, void *c, void *arg)
 {
-  int cpu = up_cpu_index();
+  int cpu = this_cpu();
   int irqreq;
   uint32_t stat;
 
@@ -379,7 +379,7 @@ int up_cpu_pause(int cpu)
   spin_lock(&g_cpu_wait[cpu]);
   spin_lock(&g_cpu_paused[cpu]);
 
-  DEBUGASSERT(cpu != up_cpu_index());
+  DEBUGASSERT(cpu != this_cpu());
 
   /* Generate IRQ for CPU(cpu) */
 

arch/arm/src/rp2040/rp2040_flash_mtd.c

@@ -93,7 +93,7 @@
                            / FLASH_SECTOR_SIZE
 
 #ifdef CONFIG_SMP
-#  define OTHER_CPU (up_cpu_index() == 0 ? 1 : 0)
+#  define OTHER_CPU (this_cpu() == 0 ? 1 : 0)
 #endif
 
 /****************************************************************************

arch/arm/src/rp2040/rp2040_irq.c

@@ -277,7 +277,7 @@ void up_disable_irq(int irq)
 
 #ifdef CONFIG_SMP
   if (irq >= RP2040_IRQ_EXTINT && irq != RP2040_SIO_IRQ_PROC1 &&
-      up_cpu_index() != 0)
+      this_cpu() != 0)
     {
       /* Must be handled by Core 0 */
 
@@ -325,7 +325,7 @@ void up_enable_irq(int irq)
 
 #ifdef CONFIG_SMP
   if (irq >= RP2040_IRQ_EXTINT && irq != RP2040_SIO_IRQ_PROC1 &&
-      up_cpu_index() != 0)
+      this_cpu() != 0)
     {
       /* Must be handled by Core 0 */
 

arch/arm/src/rp2040/rp2040_start.c

@@ -91,7 +91,7 @@ void __start(void)
 
   __asm__ __volatile__ ("\tmsr msp, %0\n" :: "r" (g_idle_topstack));
 
-  if (up_cpu_index() != 0)
+  if (this_cpu() != 0)
     {
       while (1)
         {

arch/arm/src/sam34/sam4cm_cpupause.c

@@ -238,7 +238,7 @@ int up_cpu_paused_restore(void)
 
 int arm_pause_handler(int irq, void *c, void *arg)
 {
-  int cpu = up_cpu_index();
+  int cpu = this_cpu();
 
   /* Clear : Pause IRQ */
 

arch/arm/src/sam34/sam4cm_cpustart.c

@@ -91,7 +91,7 @@ static void cpu1_boot(void)
   putreg32(0, 0x48018008);
   while ((getreg32(0x4801800c) & 0x01) != 0);
 
-  cpu = up_cpu_index();
+  cpu = this_cpu();
   DPRINTF("cpu = %d\n", cpu);
 
   if (cpu == 1)

arch/arm/src/tlsr82/tc32/tc32_backtrace.c

@@ -483,7 +483,7 @@ int up_backtrace(struct tcb_s *tcb, void **buffer, int size, int skip)
         {
 #if CONFIG_ARCH_INTERRUPTSTACK > 7
           ret = backtrace_push((void *)(INTSTACK_SIZE +
-                               up_get_intstackbase(up_cpu_index())),
+                               up_get_intstackbase(this_cpu())),
                                &sp, (void *)up_backtrace + 16,
                                buffer, size, &skip);
 #else

arch/arm64/src/common/arm64_backtrace.c

@@ -134,7 +134,7 @@ int up_backtrace(struct tcb_s *tcb,
       if (up_interrupt_context())
         {
 #if CONFIG_ARCH_INTERRUPTSTACK > 7
-          void *istackbase = (void *)up_get_intstackbase(up_cpu_index());
+          void *istackbase = (void *)up_get_intstackbase(this_cpu());
           ret = backtrace(istackbase,
                           istackbase + INTSTACK_SIZE,
                           (void *)__builtin_frame_address(0),

arch/arm64/src/common/arm64_smp.h

@@ -58,7 +58,7 @@
  *
  * Input Parameters:
  *   cpu - The CPU index.  This is the same value that would be obtained by
- *      calling up_cpu_index();
+ *      calling this_cpu();
  *
  * Returned Value:
  *   Does not return.

arch/risc-v/src/common/espressif/esp_gpio.c

@@ -124,7 +124,7 @@ static int gpio_interrupt(int irq, void *context, void *arg)
   int i;
   uint32_t status;
   uint32_t intr_bitmask;
-  int cpu = up_cpu_index();
+  int cpu = this_cpu();
 
   /* Read the lower GPIO interrupt status */
 
@@ -409,7 +409,7 @@ void esp_gpioirqenable(int irq, gpio_intrtype_t intrtype)
 
   /* Enable interrupt for this pin on the current core */
 
-  cpu = up_cpu_index();
+  cpu = this_cpu();
   gpio_hal_set_intr_type(&g_gpio_hal, pin, intrtype);
   gpio_hal_intr_enable_on_core(&g_gpio_hal, pin, cpu);
 

arch/risc-v/src/common/espressif/esp_rmt.c

@@ -1076,7 +1076,7 @@ static int rmt_isr_register(int (*fn)(int, void *, void *), void *arg,
 {
   int cpuint;
   int ret;
-  int cpu = up_cpu_index();
+  int cpu = this_cpu();
 
   DEBUGASSERT(fn);
   DEBUGASSERT(g_rmtdev_common.rmt_driver_channels == 0);

arch/risc-v/src/common/espressif/esp_spiflash.c

@@ -184,7 +184,7 @@ static IRAM_ATTR void spiflash_start(void)
 
   nxmutex_lock(&s_flash_op_mutex);
   flags = enter_critical_section();
-  cpu = up_cpu_index();
+  cpu = this_cpu();
   s_sched_suspended[cpu] = true;
 
   esp_intr_noniram_disable();
@@ -218,7 +218,7 @@ static IRAM_ATTR void spiflash_end(void)
 
   flags = enter_critical_section();
 
-  cpu = up_cpu_index();
+  cpu = this_cpu();
 
   cache_invalidate_icache_all();
   cache_resume_icache(s_flash_op_cache_state[cpu] >> 16);

arch/risc-v/src/common/riscv_cpupause.c

@@ -227,7 +227,7 @@ int up_cpu_paused_restore(void)
 
 int riscv_pause_handler(int irq, void *c, void *arg)
 {
-  int cpu = up_cpu_index();
+  int cpu = this_cpu();
 
   /* Clear IPI (Inter-Processor-Interrupt) */
 

arch/risc-v/src/qemu-rv/qemu_rv_irq.c

@@ -50,7 +50,7 @@ static int qemu_ipi_handler(int mcause, void *regs, void *args)
 {
   /* Clear IPI (Inter-Processor-Interrupt) */
 
-  riscv_ipi_clear(up_cpu_index());
+  riscv_ipi_clear(this_cpu());
 
 #ifdef CONFIG_SMP
   riscv_pause_handler(mcause, regs, args);

arch/sim/src/sim/sim_heap.c

@@ -86,11 +86,11 @@ static void mm_add_delaylist(struct mm_heap_s *heap, void *mem)
 
   flags = up_irq_save();
 
-  tmp->flink = heap->mm_delaylist[up_cpu_index()];
-  heap->mm_delaylist[up_cpu_index()] = tmp;
+  tmp->flink = heap->mm_delaylist[this_cpu()];
+  heap->mm_delaylist[this_cpu()] = tmp;
 
 #if CONFIG_MM_FREE_DELAYCOUNT_MAX > 0
-  heap->mm_delaycount[up_cpu_index()]++;
+  heap->mm_delaycount[this_cpu()]++;
 #endif
 
   up_irq_restore(flags);
@@ -108,20 +108,20 @@ static bool free_delaylist(struct mm_heap_s *heap, bool force)
 
   flags = up_irq_save();
 
-  tmp = heap->mm_delaylist[up_cpu_index()];
+  tmp = heap->mm_delaylist[this_cpu()];
 
 #if CONFIG_MM_FREE_DELAYCOUNT_MAX > 0
   if (tmp == NULL ||
       (!force &&
-        heap->mm_delaycount[up_cpu_index()] < CONFIG_MM_FREE_DELAYCOUNT_MAX))
+        heap->mm_delaycount[this_cpu()] < CONFIG_MM_FREE_DELAYCOUNT_MAX))
     {
       up_irq_restore(flags);
       return false;
     }
 
-  heap->mm_delaycount[up_cpu_index()] = 0;
+  heap->mm_delaycount[this_cpu()] = 0;
 #endif
-  heap->mm_delaylist[up_cpu_index()] = NULL;
+  heap->mm_delaylist[this_cpu()] = NULL;
 
   up_irq_restore(flags);
 

arch/sparc/src/s698pm/s698pm-irq.c

@@ -170,7 +170,7 @@ int s698pm_cpuint_initialize(void)
 #ifdef CONFIG_SMP
   /* Which CPU are we initializing */
 
-  cpu = up_cpu_index();
+  cpu = this_cpu();
   DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS);
 #endif
 

arch/sparc/src/s698pm/s698pm_cpupause.c

@@ -226,7 +226,7 @@ int up_cpu_paused_restore(void)
 
 int s698pm_pause_handler(int irq, void *c, void *arg)
 {
-  int cpu = up_cpu_index();
+  int cpu = this_cpu();
 
   /* Clear IPI (Inter-Processor-Interrupt) */
 

arch/x86_64/src/intel64/intel64_cpupause.c

@@ -234,7 +234,7 @@ int up_cpu_paused_restore(void)
 
 int up_pause_handler(int irq, void *c, void *arg)
 {
-  int cpu = up_cpu_index();
+  int cpu = this_cpu();
 
   /* Check for false alarms.  Such false could occur as a consequence of
    * some deadlock breaking logic that might have already serviced the SG2

arch/x86_64/src/intel64/intel64_irq.c

@@ -433,7 +433,7 @@ static inline void up_idtinit(void)
 
 void up_irqinitialize(void)
 {
-  int cpu = up_cpu_index();
+  int cpu = this_cpu();
 
   /* Initialize the TSS */
 
@@ -496,7 +496,7 @@ void up_disable_irq(int irq)
       g_irq_priv[irq].busy -= 1;
     }
 
-  CPU_CLR(up_cpu_index(), &g_irq_priv[irq].busy);
+  CPU_CLR(this_cpu(), &g_irq_priv[irq].busy);
 
   if (CPU_COUNT(&g_irq_priv[irq].busy) == 0)
     {
@@ -528,7 +528,7 @@ void up_enable_irq(int irq)
 #  ifndef CONFIG_IRQCHAIN
   /* Check if IRQ is free if we don't support IRQ chains */
 
-  if (CPU_ISSET(up_cpu_index(), &g_irq_priv[irq].busy))
+  if (CPU_ISSET(this_cpu(), &g_irq_priv[irq].busy))
     {
       ASSERT(0);
     }
@@ -551,7 +551,7 @@ void up_enable_irq(int irq)
         }
     }
 
-  CPU_SET(up_cpu_index(), &g_irq_priv[irq].busy);
+  CPU_SET(this_cpu(), &g_irq_priv[irq].busy);
 
   spin_unlock_irqrestore(&g_irq_spinlock, flags);
 #endif

arch/xtensa/src/common/espressif/esp_mcpwm.c

@@ -1635,7 +1635,7 @@ static int esp_mcpwm_isr_register(int (*fn)(int, void *, void *), void *arg)
 {
   int cpuint;
   int ret;
-  int cpu = up_cpu_index();
+  int cpu = this_cpu();
 
   DEBUGASSERT(fn);
 

arch/xtensa/src/common/espressif/esp_rmt.c

@@ -1123,7 +1123,7 @@ static int rmt_isr_register(int (*fn)(int, void *, void *), void *arg,
 {
   int cpuint;
   int ret;
-  int cpu = up_cpu_index();
+  int cpu = this_cpu();
 
   DEBUGASSERT(fn);
   DEBUGASSERT(g_rmtdev_common.rmt_driver_channels == 0);

arch/xtensa/src/common/xtensa_backtrace.c

@@ -242,7 +242,7 @@ int up_backtrace(struct tcb_s *tcb, void **buffer, int size, int skip)
       if (up_interrupt_context())
         {
 #if CONFIG_ARCH_INTERRUPTSTACK > 15
-          void *istackbase = (void *)up_get_intstackbase(up_cpu_index());
+          void *istackbase = (void *)up_get_intstackbase(this_cpu());
 
           xtensa_window_spill();
           ret = backtrace_stack(istackbase,

arch/xtensa/src/common/xtensa_cpupause.c

@@ -218,7 +218,7 @@ int up_cpu_paused_restore(void)
 
 void xtensa_pause_handler(void)
 {
-  int cpu = up_cpu_index();
+  int cpu = this_cpu();
 
   /* Check for false alarms.  Such false could occur as a consequence of
    * some deadlock breaking logic that might have already serviced the

arch/xtensa/src/esp32/esp32_cpustart.c

@@ -120,7 +120,7 @@ void IRAM_ATTR xtensa_appcpu_start(void)
                  XCPTCONTEXT_SIZE;
   __asm__ __volatile__("mov sp, %0\n" : : "r"(sp));
 
-  sinfo("CPU%d Started\n", up_cpu_index());
+  sinfo("CPU%d Started\n", this_cpu());
 
 #ifdef CONFIG_SCHED_INSTRUMENTATION
   /* Notify that this CPU has started */

arch/xtensa/src/esp32/esp32_emac.c

@@ -2042,7 +2042,7 @@ int esp32_emac_init(void)
 
   memset(priv, 0, sizeof(struct esp32_emac_s));
 
-  priv->cpu = up_cpu_index();
+  priv->cpu = this_cpu();
   priv->cpuint = esp32_setup_irq(priv->cpu, ESP32_PERIPH_EMAC,
                                  1, ESP32_CPUINT_LEVEL);
   if (priv->cpuint < 0)

arch/xtensa/src/esp32/esp32_gpio.c

@@ -469,7 +469,7 @@ void esp32_gpioirqenable(int irq, gpio_intrtype_t intrtype)
   uintptr_t regaddr;
   uint32_t regval;
   int pin;
-  int cpu = up_cpu_index();
+  int cpu = this_cpu();
 
   DEBUGASSERT(irq >= ESP32_FIRST_GPIOIRQ && irq <= ESP32_LAST_GPIOIRQ);
 
@@ -530,7 +530,7 @@ void esp32_gpioirqdisable(int irq)
   uintptr_t regaddr;
   uint32_t regval;
   int pin;
-  int cpu = up_cpu_index();
+  int cpu = this_cpu();
 
   DEBUGASSERT(irq >= ESP32_FIRST_GPIOIRQ && irq <= ESP32_LAST_GPIOIRQ);
 

arch/xtensa/src/esp32/esp32_i2c.c

@@ -1500,7 +1500,7 @@ struct i2c_master_s *esp32_i2cbus_initialize(int port)
 
   /* Set up to receive peripheral interrupts on the current CPU */
 
-  priv->cpu = up_cpu_index();
+  priv->cpu = this_cpu();
   priv->cpuint = esp32_setup_irq(priv->cpu, config->periph,
                                  1, ESP32_CPUINT_LEVEL);
   if (priv->cpuint < 0)

arch/xtensa/src/esp32/esp32_i2s.c

@@ -3002,7 +3002,7 @@ static int i2s_dma_setup(struct esp32_i2s_s *priv)
 
   /* Set up to receive peripheral interrupts on the current CPU */
 
-  priv->cpu = up_cpu_index();
+  priv->cpu = this_cpu();
   priv->cpuint = esp32_setup_irq(priv->cpu, priv->config->periph,
                                  1, ESP32_CPUINT_LEVEL);
   if (priv->cpuint < 0)