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Indent the define statement by two spaces

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follow the code style convention

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao
2023-05-20 06:32:34 +08:00
committed by Alan Carvalho de Assis
parent ae1fd83a46
commit 7990f90915
390 changed files with 4060 additions and 4063 deletions
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arch/arm/src/arm/arm_initialstate.c
+2 -2
View File
@@ -141,9 +141,9 @@ void up_initial_state(struct tcb_s *tcb)
/* Enable or disable interrupts, based on user configuration */
# ifdef CONFIG_SUPPRESS_INTERRUPTS
#ifdef CONFIG_SUPPRESS_INTERRUPTS
cpsr |= PSR_I_BIT;
# endif
#endif
#ifdef CONFIG_ARM_THUMB
cpsr |= PSR_T_BIT;
arch/arm/src/armv6-m/arm_hardfault.c
+4 -4
View File
@@ -39,15 +39,15 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_HARDFAULT_ALERT
# define hfalert(format, ...) _alert(format, ##__VA_ARGS__)
# define hfalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define hfalert(x...)
# define hfalert(x...)
#endif
#ifdef CONFIG_DEBUG_HARDFAULT_INFO
# define hfinfo(format, ...) _info(format, ##__VA_ARGS__)
# define hfinfo(format, ...) _info(format, ##__VA_ARGS__)
#else
# define hfinfo(x...)
# define hfinfo(x...)
#endif
#define INSN_SVC0 0xdf00 /* insn: svc 0 */
arch/arm/src/armv6-m/arm_svcall.c
+13 -13
View File
@@ -127,9 +127,9 @@ int arm_svcall(int irq, void *context, void *arg)
*/
#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# endif
# endif
{
svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
@@ -138,13 +138,13 @@ int arm_svcall(int irq, void *context, void *arg)
svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
# ifdef CONFIG_BUILD_PROTECTED
# ifdef CONFIG_BUILD_PROTECTED
svcinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
regs[REG_XPSR], regs[REG_PRIMASK], regs[REG_EXC_RETURN]);
# else
# else
svcinfo(" PSR: %08x PRIMASK: %08x\n",
regs[REG_XPSR], regs[REG_PRIMASK]);
# endif
# endif
}
#endif
@@ -429,11 +429,11 @@ int arm_svcall(int irq, void *context, void *arg)
*/
#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# else
# else
if (regs != CURRENT_REGS)
# endif
# endif
{
svcinfo("SVCall Return:\n");
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
@@ -446,21 +446,21 @@ int arm_svcall(int irq, void *context, void *arg)
CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
#ifdef CONFIG_BUILD_PROTECTED
# ifdef CONFIG_BUILD_PROTECTED
svcinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
CURRENT_REGS[REG_EXC_RETURN]);
#else
# else
svcinfo(" PSR: %08x PRIMASK: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
#endif
# endif
}
# ifdef CONFIG_DEBUG_SVCALL
# ifdef CONFIG_DEBUG_SVCALL
else
{
svcinfo("SVCall Return: %d\n", regs[REG_R0]);
}
# endif
# endif
#endif
return OK;
arch/arm/src/armv7-m/arm_busfault.c
+2 -2
View File
@@ -39,9 +39,9 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_BUSFAULT
# define bfalert(format, ...) _alert(format, ##__VA_ARGS__)
# define bfalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define bfalert(x...)
# define bfalert(x...)
#endif
/****************************************************************************
arch/arm/src/armv7-m/arm_hardfault.c
+4 -4
View File
@@ -45,15 +45,15 @@
*/
#ifdef CONFIG_DEBUG_HARDFAULT_ALERT
# define hfalert(format, ...) _alert(format, ##__VA_ARGS__)
# define hfalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define hfalert(x...)
# define hfalert(x...)
#endif
#ifdef CONFIG_DEBUG_HARDFAULT_INFO
# define hfinfo(format, ...) _info(format, ##__VA_ARGS__)
# define hfinfo(format, ...) _info(format, ##__VA_ARGS__)
#else
# define hfinfo(x...)
# define hfinfo(x...)
#endif
#define INSN_SVC0 0xdf00 /* insn: svc 0 */
arch/arm/src/armv7-m/arm_memfault.c
+2 -2
View File
@@ -38,9 +38,9 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_MEMFAULT
# define mfalert(format, ...) _alert(format, ##__VA_ARGS__)
# define mfalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define mfalert(x...)
# define mfalert(x...)
#endif
/****************************************************************************
arch/arm/src/armv7-m/arm_svcall.c
+13 -13
View File
@@ -135,9 +135,9 @@ int arm_svcall(int irq, void *context, void *arg)
*/
#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# endif
# endif
{
svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
@@ -146,12 +146,12 @@ int arm_svcall(int irq, void *context, void *arg)
svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
# ifdef REG_EXC_RETURN
# ifdef REG_EXC_RETURN
svcinfo(" PSR: %08x EXC_RETURN: %08x\n",
regs[REG_XPSR], regs[REG_EXC_RETURN]);
# else
# else
svcinfo(" PSR: %08x\n", regs[REG_XPSR]);
# endif
# endif
}
#endif
@@ -437,11 +437,11 @@ int arm_svcall(int irq, void *context, void *arg)
*/
#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# else
# else
if (regs != CURRENT_REGS)
# endif
# endif
{
svcinfo("SVCall Return:\n");
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
@@ -454,19 +454,19 @@ int arm_svcall(int irq, void *context, void *arg)
CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
# ifdef REG_EXC_RETURN
# ifdef REG_EXC_RETURN
svcinfo(" PSR: %08x EXC_RETURN: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_EXC_RETURN]);
# else
# else
svcinfo(" PSR: %08x\n", CURRENT_REGS[REG_XPSR]);
# endif
# endif
}
# ifdef CONFIG_DEBUG_SVCALL
# ifdef CONFIG_DEBUG_SVCALL
else
{
svcinfo("SVCall Return: %d\n", regs[REG_R0]);
}
# endif
# endif
#endif
return OK;
arch/arm/src/armv7-m/arm_usagefault.c
+2 -2
View File
@@ -39,9 +39,9 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_USAGEFAULT
# define ufalert(format, ...) _alert(format, ##__VA_ARGS__)
# define ufalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define ufalert(x...)
# define ufalert(x...)
#endif
/****************************************************************************
arch/arm/src/armv8-m/arm_busfault.c
+2 -2
View File
@@ -39,9 +39,9 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_BUSFAULT
# define bfalert(format, ...) _alert(format, ##__VA_ARGS__)
# define bfalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define bfalert(x...)
# define bfalert(x...)
#endif
/****************************************************************************
arch/arm/src/armv8-m/arm_hardfault.c
+4 -4
View File
@@ -45,15 +45,15 @@
*/
#ifdef CONFIG_DEBUG_HARDFAULT_ALERT
# define hfalert(format, ...) _alert(format, ##__VA_ARGS__)
# define hfalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define hfalert(x...)
# define hfalert(x...)
#endif
#ifdef CONFIG_DEBUG_HARDFAULT_INFO
# define hfinfo(format, ...) _info(format, ##__VA_ARGS__)
# define hfinfo(format, ...) _info(format, ##__VA_ARGS__)
#else
# define hfinfo(x...)
# define hfinfo(x...)
#endif
#define INSN_SVC0 0xdf00 /* insn: svc 0 */
arch/arm/src/armv8-m/arm_memfault.c
+2 -2
View File
@@ -38,9 +38,9 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_MEMFAULT
# define mfalert(format, ...) _alert(format, ##__VA_ARGS__)
# define mfalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define mfalert(x...)
# define mfalert(x...)
#endif
/****************************************************************************
arch/arm/src/armv8-m/arm_svcall.c
+13 -13
View File
@@ -134,9 +134,9 @@ int arm_svcall(int irq, void *context, void *arg)
*/
#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# endif
# endif
{
svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
@@ -145,12 +145,12 @@ int arm_svcall(int irq, void *context, void *arg)
svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
# ifdef REG_EXC_RETURN
# ifdef REG_EXC_RETURN
svcinfo(" PSR: %08x EXC_RETURN: %08x\n",
regs[REG_XPSR], regs[REG_EXC_RETURN]);
# else
# else
svcinfo(" PSR: %08x\n", regs[REG_XPSR]);
# endif
# endif
}
#endif
@@ -437,11 +437,11 @@ int arm_svcall(int irq, void *context, void *arg)
*/
#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# else
# else
if (regs != CURRENT_REGS)
# endif
# endif
{
svcinfo("SVCall Return:\n");
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
@@ -454,19 +454,19 @@ int arm_svcall(int irq, void *context, void *arg)
CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
# ifdef REG_EXC_RETURN
# ifdef REG_EXC_RETURN
svcinfo(" PSR: %08x EXC_RETURN: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_EXC_RETURN]);
# else
# else
svcinfo(" PSR: %08x\n", CURRENT_REGS[REG_XPSR]);
# endif
# endif
}
# ifdef CONFIG_DEBUG_SVCALL
# ifdef CONFIG_DEBUG_SVCALL
else
{
svcinfo("SVCall Return: %d\n", regs[REG_R0]);
}
# endif
# endif
#endif
return OK;
arch/arm/src/armv8-m/arm_usagefault.c
+2 -2
View File
@@ -39,9 +39,9 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_USAGEFAULT
# define ufalert(format, ...) _alert(format, ##__VA_ARGS__)
# define ufalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define ufalert(x...)
# define ufalert(x...)
#endif
/****************************************************************************
arch/arm/src/c5471/c5471_ethernet.c
+3 -3
View File
@@ -80,7 +80,7 @@
*/
#ifndef CONFIG_C5471_NET_NINTERFACES
# define CONFIG_C5471_NET_NINTERFACES 1
# define CONFIG_C5471_NET_NINTERFACES 1
#endif
/* CONFIG_C5471_NET_STATS will enabled collection of driver statistics.
@@ -99,7 +99,7 @@
# undef CONFIG_C5471_AUTONEGOTIATION
# undef CONFIG_C5471_BASET100
#else
# define CONFIG_C5471_AUTONEGOTIATION 1
# define CONFIG_C5471_AUTONEGOTIATION 1
# undef CONFIG_C5471_BASET100
# undef CONFIG_C5471_BASET10
#endif
@@ -435,7 +435,7 @@ static inline void c5471_dumpbuffer(const char *msg, const uint8_t *buffer,
ninfodumpbuffer(msg, buffer, nbytes);
}
#else
# define c5471_dumpbuffer(msg, buffer,nbytes)
# define c5471_dumpbuffer(msg, buffer,nbytes)
#endif
/****************************************************************************
arch/arm/src/c5471/c5471_serial.c
+7 -7
View File
@@ -48,7 +48,7 @@
#define BASE_BAUD 115200
#if defined(CONFIG_UART_IRDA_HWFLOWCONTROL) || defined(CONFIG_UART_MODEM_HWFLOWCONTROL)
# define CONFIG_UART_HWFLOWCONTROL
# define CONFIG_UART_HWFLOWCONTROL
#endif
/****************************************************************************
@@ -203,13 +203,13 @@ static uart_dev_t g_modemport =
/* Now, which one with be tty0/console and which tty1? */
#ifdef CONFIG_SERIAL_IRDA_CONSOLE
# define CONSOLE_DEV g_irdaport
# define TTYS0_DEV g_irdaport
# define TTYS1_DEV g_modemport
# define CONSOLE_DEV g_irdaport
# define TTYS0_DEV g_irdaport
# define TTYS1_DEV g_modemport
#else
# define CONSOLE_DEV g_modemport
# define TTYS0_DEV g_modemport
# define TTYS1_DEV g_irdaport
# define CONSOLE_DEV g_modemport
# define TTYS0_DEV g_modemport
# define TTYS1_DEV g_irdaport
#endif
/****************************************************************************
arch/arm/src/common/arm_internal.h
+6 -6
View File
@@ -356,7 +356,7 @@ uint32_t *arm_doirq(int irq, uint32_t *regs);
void arm_pginitialize(void);
uint32_t *arm_va2pte(uintptr_t vaddr);
#else /* CONFIG_PAGING */
# define arm_pginitialize()
# define arm_pginitialize()
#endif /* CONFIG_PAGING */
/* Exception Handlers */
@@ -382,7 +382,7 @@ void arm_pginitialize(void);
uint32_t *arm_va2pte(uintptr_t vaddr);
void arm_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr);
#else /* CONFIG_PAGING */
# define arm_pginitialize()
# define arm_pginitialize()
void arm_dataabort(uint32_t *regs);
#endif /* CONFIG_PAGING */
@@ -442,7 +442,7 @@ void arm_l2ccinitialize(void);
#if CONFIG_MM_REGIONS > 1
void arm_addregion(void);
#else
# define arm_addregion()
# define arm_addregion()
#endif
/* Networking ***************************************************************/
@@ -461,7 +461,7 @@ void arm_addregion(void);
#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT)
void arm_netinitialize(void);
#else
# define arm_netinitialize()
# define arm_netinitialize()
#endif
/* USB **********************************************************************/
@@ -470,8 +470,8 @@ void arm_netinitialize(void);
void arm_usbinitialize(void);
void arm_usbuninitialize(void);
#else
# define arm_usbinitialize()
# define arm_usbuninitialize()
# define arm_usbinitialize()
# define arm_usbuninitialize()
#endif
/* Debug ********************************************************************/
arch/arm/src/dm320/dm320_serial.c
+6 -6
View File
@@ -171,13 +171,13 @@ static uart_dev_t g_uart1port =
/* Now, which one with be tty0/console and which tty1? */
#ifdef CONFIG_SERIAL_IRDA_CONSOLE
# define CONSOLE_DEV g_uart1port
# define TTYS0_DEV g_uart1port
# define TTYS1_DEV g_uart0port
# define CONSOLE_DEV g_uart1port
# define TTYS0_DEV g_uart1port
# define TTYS1_DEV g_uart0port
#else
# define CONSOLE_DEV g_uart0port
# define TTYS0_DEV g_uart0port
# define TTYS1_DEV g_uart1port
# define CONSOLE_DEV g_uart0port
# define TTYS0_DEV g_uart0port
# define TTYS1_DEV g_uart1port
#endif
/****************************************************************************
arch/arm/src/dm320/dm320_timer.h
+4 -4
View File
@@ -60,9 +60,9 @@
#define DM320_TMR_MODE_TEST_MASK 0x00fc /* Bits 7:2=Test */
#define DM320_TMR_MODE_MODE_MASK 0x0003 /* Bits 1:0=timer mode */
# define DM320_TMR_MODE_STOP 0x0000 /* Stop Timer */
# define DM320_TMR_MODE_ONESHOT 0x0001 /* Start one-shot timer */
# define DM320_TMR_MODE_FREERUN 0x0002 /* Start free-running timer */
# define DM320_TMR_MODE_STOP 0x0000 /* Stop Timer */
# define DM320_TMR_MODE_ONESHOT 0x0001 /* Start one-shot timer */
# define DM320_TMR_MODE_FREERUN 0x0002 /* Start free-running timer */
/* Timer 0,1,2,3 Clock Select Register Bits: */
@@ -76,7 +76,7 @@
#define DM320_TMR_TMTRG_MASK 0x0001 /* Bit 0=One short trigger */
# define DM320_TMR_TMTRG_START 0x0001 /* 1 starts one shot timer */
# define DM320_TMR_TMTRG_START 0x0001 /* 1 starts one shot timer */
/* Timer 0,1,2,3 Timer Counter Register Bits: */
arch/arm/src/dm320/dm320_usbdev.c
+6 -6
View File
@@ -261,12 +261,12 @@ static void dm320_putreg8(uint8_t val, uint32_t addr);
static void dm320_putreg16(uint16_t val, uint32_t addr);
static void dm320_putreg32(uint32_t val, uint32_t addr);
#else
# define dm320_getreg8(addr) getreg8(addr)
# define dm320_getreg16(addr) getreg16(addr)
# define dm320_getreg32(addr) getreg32(addr)
# define dm320_putreg8(val,addr) putreg8(val,addr)
# define dm320_putreg16(val,addr) putreg16(val,addr)
# define dm320_putreg32(val,addr) putreg32(val,addr)
# define dm320_getreg8(addr) getreg8(addr)
# define dm320_getreg16(addr) getreg16(addr)
# define dm320_getreg32(addr) getreg32(addr)
# define dm320_putreg8(val,addr) putreg8(val,addr)
# define dm320_putreg16(val,addr) putreg16(val,addr)
# define dm320_putreg32(val,addr) putreg32(val,addr)
#endif
/* Request queue operations *************************************************/
arch/arm/src/efm32/efm32_usbdev.c
+2 -2
View File
@@ -465,8 +465,8 @@ struct efm32_usbdev_s
static uint32_t efm32_getreg(uint32_t addr);
static void efm32_putreg(uint32_t val, uint32_t addr);
#else
# define efm32_getreg(addr) getreg32(addr)
# define efm32_putreg(val,addr) putreg32(val,addr)
# define efm32_getreg(addr) getreg32(addr)
# define efm32_putreg(val,addr) putreg32(val,addr)
#endif
/* Request queue operations *************************************************/
arch/arm/src/efm32/efm32_usbhost.c
+2 -2
View File
@@ -284,8 +284,8 @@ static void efm32_checkreg(uint32_t addr, uint32_t val, bool iswrite);
static uint32_t efm32_getreg(uint32_t addr);
static void efm32_putreg(uint32_t addr, uint32_t value);
#else
# define efm32_getreg(addr) getreg32(addr)
# define efm32_putreg(addr,val) putreg32(val,addr)
# define efm32_getreg(addr) getreg32(addr)
# define efm32_putreg(addr,val) putreg32(val,addr)
#endif
static inline void efm32_modifyreg(uint32_t addr, uint32_t clrbits,
arch/arm/src/efm32/hardware/efm32gg_memorymap.h
+1 -1
View File
@@ -68,7 +68,7 @@
#define EFM32_FLASH_MEM_BASE 0x00000000 /* FLASH base address */
# define EFM32_FLASH_MEM_BITS 0x00000028 /* FLASH used bits */
#define EFM32_RAM_CODE_MEM_BASE 0x10000000 /* RAM_CODE base address */
# define EFM32_RAM_CODE_MEM_BITS 0x00000014 /* RAM_CODE used bits */
# define EFM32_RAM_CODE_MEM_BITS 0x00000014 /* RAM_CODE used bits */
#define EFM32_RAM_MEM_BASE 0x20000000 /* RAM base address */
# define EFM32_RAM_MEM_BITS 0x00000018 /* RAM used bits */
#define EFM32_PER_MEM_BASE 0x40000000 /* PER base address */
arch/arm/src/gd32f4/gd32f4xx_enet.c
+7 -7
View File
@@ -3295,7 +3295,7 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv)
* CK_PLLP clock (through a configurable prescaler) on PC9 pin."
*/
# if defined(CONFIG_GD32F4_MII_CKOUT0)
# if defined(CONFIG_GD32F4_MII_CKOUT0)
/* Configure CKOUT0 to drive the PHY. Board logic must provide
* CKOUT0 clocking info.
*/
@@ -3303,14 +3303,14 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv)
gd32_gpio_config(GPIO_CKOUT0);
gd32_rcu_ckout0_config(BOARD_CFG_CKOUT0_SOURCE, BOARD_CFG_CKOUT0_DIVIDER);
# elif defined(CONFIG_GD32F4_MII_CKOUT1)
# elif defined(CONFIG_GD32F4_MII_CKOUT1)
/* Configure CKOUT1 to drive the PHY. Board logic must provide
* CKOUT1 clocking info.
*/
gd32_gpio_config(GPIO_CKOUT1);
gd32_rcu_ckout1_config(BOARD_CFG_CKOUT1_SOURCE, BOARD_CFG_CKOUT1_DIVIDER);
# endif
# endif
/* MII interface pins (17):
*
@@ -3351,7 +3351,7 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv)
* CK_PLLP clock (through a configurable prescaler) on PC9 pin."
*/
# if defined(CONFIG_GD32F4_RMII_CKOUT0)
# if defined(CONFIG_GD32F4_RMII_CKOUT0)
/* Configure CKOUT0 to drive the PHY. Board logic must provide
* CKOUT0 clocking info.
*/
@@ -3359,7 +3359,7 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv)
gd32_gpio_config(GPIO_CKOUT0);
gd32_rcu_ckout0_config(BOARD_CFG_CKOUT0_SOURCE, BOARD_CFG_CKOUT0_DIV);
# elif defined(CONFIG_GD32F4_RMII_CKOUT1)
# elif defined(CONFIG_GD32F4_RMII_CKOUT1)
/* Configure CKOUT1 to drive the PHY. Board logic must provide
* CKOUT1 clocking info.
*/
@@ -3367,7 +3367,7 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv)
gd32_gpio_config(GPIO_CKOUT1);
gd32_rcu_ckout1_config(BOARD_CFG_CKOUT1_SOURCE, BOARD_CFG_CKOUT1_DIVIDER);
# endif
# endif
/* RMII interface pins (7):
*
@@ -3383,7 +3383,7 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv)
gd32_gpio_config(GPIO_ENET_RMII_TXD0);
gd32_gpio_config(GPIO_ENET_RMII_TXD1);
#endif
# endif
#endif
#ifdef CONFIG_GD32F4_ENET_PTP
arch/arm/src/gd32f4/gd32f4xx_i2c.c
+8 -8
View File
@@ -130,14 +130,14 @@
# error "Now I2C DMA has not ready"
# if defined(CONFIG_I2C_DMAPRIO)
# if (CONFIG_I2C_DMAPRIO & ~DMA_CHXCTL_PRIO_MASK) != 0
# error "Illegal value for CONFIG_I2C_DMAPRIO"
# endif
# define I2C_DMA_PRIO CONFIG_I2C_DMAPRIO
# else
# define I2C_DMA_PRIO DMA_PRIO_HIGH_SELECT
# endif
# if defined(CONFIG_I2C_DMAPRIO)
# if (CONFIG_I2C_DMAPRIO & ~DMA_CHXCTL_PRIO_MASK) != 0
# error "Illegal value for CONFIG_I2C_DMAPRIO"
# endif
# define I2C_DMA_PRIO CONFIG_I2C_DMAPRIO
# else
# define I2C_DMA_PRIO DMA_PRIO_HIGH_SELECT
# endif
#endif
/* Debug ********************************************************************/
arch/arm/src/gd32f4/gd32f4xx_serial.c
+16 -16
View File
@@ -356,65 +356,65 @@ static const struct uart_ops_s g_uart_ops_no_dma =
#ifdef CONFIG_GD32F4_USART0_SERIALDRIVER
static char g_usart0rxbuffer[CONFIG_USART0_RXBUFSIZE];
static char g_usart0txbuffer[CONFIG_USART0_TXBUFSIZE];
# ifdef CONFIG_GD32F4_USART0_RXDMA
# ifdef CONFIG_GD32F4_USART0_RXDMA
static char g_usart0rxfifo[RXDMA_BUFFER_SIZE];
# endif
# endif
#endif
#ifdef CONFIG_GD32F4_USART1_SERIALDRIVER
static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE];
static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE];
# ifdef CONFIG_GD32F4_USART1_RXDMA
# ifdef CONFIG_GD32F4_USART1_RXDMA
static char g_usart1rxfifo[RXDMA_BUFFER_SIZE];
# endif
# endif
#endif
#ifdef CONFIG_GD32F4_USART2_SERIALDRIVER
static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE];
static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE];
# ifdef CONFIG_GD32F4_USART2_RXDMA
# ifdef CONFIG_GD32F4_USART2_RXDMA
static char g_usart2rxfifo[RXDMA_BUFFER_SIZE];
# endif
# endif
#endif
#ifdef CONFIG_GD32F4_UART3_SERIALDRIVER
static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE];
static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE];
# ifdef CONFIG_GD32F4_UART3_RXDMA
# ifdef CONFIG_GD32F4_UART3_RXDMA
static char g_uart3rxfifo[RXDMA_BUFFER_SIZE];
# endif
# endif
#endif
#ifdef CONFIG_GD32F4_UART4_SERIALDRIVER
static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE];
static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE];
# ifdef CONFIG_GD32F4_UART4_RXDMA
# ifdef CONFIG_GD32F4_UART4_RXDMA
static char g_uart4rxfifo[RXDMA_BUFFER_SIZE];
# endif
# endif
#endif
#ifdef CONFIG_GD32F4_USART5_SERIALDRIVER
static char g_usart5rxbuffer[CONFIG_USART5_RXBUFSIZE];
static char g_usart5txbuffer[CONFIG_USART5_TXBUFSIZE];
# ifdef CONFIG_GD32F4_USART5_RXDMA
# ifdef CONFIG_GD32F4_USART5_RXDMA
static char g_usart5rxfifo[RXDMA_BUFFER_SIZE];
# endif
# endif
#endif
#ifdef CONFIG_GD32F4_UART6_SERIALDRIVER
static char g_uart6rxbuffer[CONFIG_UART6_RXBUFSIZE];
static char g_uart6txbuffer[CONFIG_UART6_TXBUFSIZE];
# ifdef CONFIG_GD32F4_UART6_RXDMA
# ifdef CONFIG_GD32F4_UART6_RXDMA
static char g_uart6rxfifo[RXDMA_BUFFER_SIZE];
# endif
# endif
#endif
#ifdef CONFIG_GD32F4_UART7_SERIALDRIVER
static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE];
static char g_uart7txbuffer[CONFIG_UART7_TXBUFSIZE];
# ifdef CONFIG_GD32F4_UART7_RXDMA
# ifdef CONFIG_GD32F4_UART7_RXDMA
static char g_uart7rxfifo[RXDMA_BUFFER_SIZE];
# endif
# endif
#endif
/* This describes the state of the GD32 USART0 ports. */
arch/arm/src/gd32f4/hardware/gd32f4xx_rcu.h
+2 -2
View File
@@ -236,7 +236,7 @@
#define RCU_CFG0_CKOUT0DIV_SHIFT (24) /* Bits 24-26: The CK_OUT0 divider */
#define RCU_CFG0_CKOUT0DIV_MASK (7 << RCU_CFG0_CKOUT0DIV_SHIFT)
# define RCU_CFG0_CKOUT0DIV(n) ((n) << RCU_CFG0_CKOUT0DIV_SHIFT)
# define RCU_CFG0_CKOUT0DIV(n) ((n) << RCU_CFG0_CKOUT0DIV_SHIFT)
# define RCU_CFG0_CKOUT0_DIV1 RCU_CFG0_CKOUT0DIV(0) /* CK_OUT0 is divided by 1, n=0..3 */
# define RCU_CFG0_CKOUT0_DIV2 RCU_CFG0_CKOUT0DIV(4) /* CK_OUT0 is divided by 2 */
# define RCU_CFG0_CKOUT0_DIV3 RCU_CFG0_CKOUT0DIV(5) /* CK_OUT0 is divided by 3 */
@@ -245,7 +245,7 @@
#define RCU_CFG0_CKOUT1DIV_SHIFT (27) /* Bits 27-29: The CK_OUT1 divider */
#define RCU_CFG0_CKOUT1DIV_MASK (7 << RCU_CFG0_CKOUT1DIV_SHIFT)
# define RCU_CFG0_CKOUT1DIV(n) ((n) << RCU_CFG0_CKOUT1DIV_SHIFT)
# define RCU_CFG0_CKOUT1DIV(n) ((n) << RCU_CFG0_CKOUT1DIV_SHIFT)
# define RCU_CFG0_CKOUT1_DIV1 RCU_CFG0_CKOUT1DIV(0) /* CK_OUT1 is divided by 1, n=0..3 */
# define RCU_CFG0_CKOUT1_DIV2 RCU_CFG0_CKOUT1DIV(4) /* CK_OUT1 is divided by 2 */
# define RCU_CFG0_CKOUT1_DIV3 RCU_CFG0_CKOUT1DIV(5) /* CK_OUT1 is divided by 3 */
arch/arm/src/imx1/imx_serial.c
+92 -92
View File
@@ -251,107 +251,107 @@ static struct uart_dev_s g_uart3port =
/* Now, which one with be tty0/console and which tty1 and tty2? */
#if defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_IMX1_UART1)
# define CONSOLE_DEV g_uart1port /* UART1 is /dev/console */
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# define TTYS0_DEV g_uart1port /* UART1 is /dev/ttyS0 */
# if defined(CONFIG_IMX1_UART2)
# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */
# if defined(CONFIG_IMX1_UART3)
# define TTYS2_DEV g_uart3port /* UART3 is /dev/ttyS2 */
# else
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART3)
# define TTYS1_DEV g_uart3port /* UART3 is /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# else
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_IMX1_UART2)
# define CONSOLE_DEV g_uart2port /* UART2 is /dev/console */
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# define TTYS0_DEV g_uart2port /* UART2 is /dev/ttyS0 */
# if defined(CONFIG_IMX1_UART1)
# define TTYS1_DEV g_uart1port /* UART1 is /dev/ttyS1 */
# if defined(CONFIG_IMX1_UART3)
# define TTYS2_DEV g_uart3port /* UART3 is /dev/ttyS2 */
# else
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART3)
# define TTYS1_DEV g_uart3port /* UART3 is /dev/ttyS1 */
# else
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_IMX1_UART3)
# define CONSOLE_DEV g_uart3port /* UART3 is /dev/console */
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# define TTYS0_DEV g_uart3port /* UART3 is /dev/ttyS0 */
# if defined(CONFIG_IMX1_UART1)
# define TTYS1_DEV g_uart1port /* UART1 is /dev/ttyS1 */
# if defined(CONFIG_IMX1_UART2)
# define TTYS2_DEV g_uart2port /* UART2 is /dev/ttyS2 */
# else
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART2)
# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# else
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
#else
# undef CONSOLE_DEV g_uart1port /* No /dev/console */
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# if defined(CONFIG_IMX1_UART1)
# define TTYS0_DEV g_uart1port /* UART1 is /dev/ttyS0 */
# define CONSOLE_DEV g_uart1port /* UART1 is /dev/console */
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# define TTYS0_DEV g_uart1port /* UART1 is /dev/ttyS0 */
# if defined(CONFIG_IMX1_UART2)
# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */
# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */
# if defined(CONFIG_IMX1_UART3)
# define TTYS2_DEV g_uart3port /* UART3 is /dev/ttyS2 */
# define TTYS2_DEV g_uart3port /* UART3 is /dev/ttyS2 */
# else
# undef TTYS2_DEV /* No /dev/ttyS2 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART3)
# define TTYS1_DEV g_uart3port /* UART3 is /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# define TTYS1_DEV g_uart3port /* UART3 is /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# else
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART2)
# define TTYS0_DEV g_uart2port /* UART2 is /dev/ttyS0 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# if defined(CONFIG_IMX1_UART3)
# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */
#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_IMX1_UART2)
# define CONSOLE_DEV g_uart2port /* UART2 is /dev/console */
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# define TTYS0_DEV g_uart2port /* UART2 is /dev/ttyS0 */
# if defined(CONFIG_IMX1_UART1)
# define TTYS1_DEV g_uart1port /* UART1 is /dev/ttyS1 */
# if defined(CONFIG_IMX1_UART3)
# define TTYS2_DEV g_uart3port /* UART3 is /dev/ttyS2 */
# else
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART3)
# define TTYS1_DEV g_uart3port /* UART3 is /dev/ttyS1 */
# else
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART3)
# define TTYS0_DEV g_uart3port /* UART3 is /dev/ttyS0 */
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_IMX1_UART3)
# define CONSOLE_DEV g_uart3port /* UART3 is /dev/console */
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# define TTYS0_DEV g_uart3port /* UART3 is /dev/ttyS0 */
# if defined(CONFIG_IMX1_UART1)
# define TTYS1_DEV g_uart1port /* UART1 is /dev/ttyS1 */
# if defined(CONFIG_IMX1_UART2)
# define TTYS2_DEV g_uart2port /* UART2 is /dev/ttyS2 */
# else
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART2)
# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# else
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# else
# error "No UARTs enabled"
# undef TTYS0_DEV /* No /dev/ttyS0 */
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
#else
# undef CONSOLE_DEV g_uart1port /* No /dev/console */
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# if defined(CONFIG_IMX1_UART1)
# define TTYS0_DEV g_uart1port /* UART1 is /dev/ttyS0 */
# if defined(CONFIG_IMX1_UART2)
# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */
# if defined(CONFIG_IMX1_UART3)
# define TTYS2_DEV g_uart3port /* UART3 is /dev/ttyS2 */
# else
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART3)
# define TTYS1_DEV g_uart3port /* UART3 is /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# else
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART2)
# define TTYS0_DEV g_uart2port /* UART2 is /dev/ttyS0 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# if defined(CONFIG_IMX1_UART3)
# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */
# else
# undef TTYS1_DEV /* No /dev/ttyS1 */
# endif
# elif defined(CONFIG_IMX1_UART3)
# define TTYS0_DEV g_uart3port /* UART3 is /dev/ttyS0 */
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# else
# error "No UARTs enabled"
# undef TTYS0_DEV /* No /dev/ttyS0 */
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
#endif
/****************************************************************************
@@ -1140,12 +1140,12 @@ void arm_serialinit(void)
#ifdef TTYS0_DEV
uart_register("/dev/ttyS0", &TTYS0_DEV);
# ifdef TTYS1_DEV
# ifdef TTYS1_DEV
uart_register("/dev/ttyS1", &TTYS1_DEV);
# ifdef TTYS2_DEV
# ifdef TTYS2_DEV
uart_register("/dev/ttyS2", &TTYS2_DEV);
# endif
# endif
# endif
#endif
}
arch/arm/src/imx6/hardware/imx_enet.h
+6 -6
View File
@@ -515,13 +515,13 @@
*/
#ifdef IMX_ENET_HAS_DBSWAP
# ifndef CONFIG_ENDIAN_BIG
# define IMX_USE_DBSWAP
# endif
# ifndef CONFIG_ENDIAN_BIG
# define IMX_USE_DBSWAP
# endif
#else
# ifndef CONFIG_ENDIAN_BIG
# define IMX_BUFFERS_SWAP
# endif
# ifndef CONFIG_ENDIAN_BIG
# define IMX_BUFFERS_SWAP
# endif
#endif
#ifndef IMX_BUFFERS_SWAP
arch/arm/src/imx6/imx_serial.c
+5 -5
View File
@@ -1090,18 +1090,18 @@ void arm_serialinit(void)
#ifdef TTYS0_DEV
uart_register("/dev/ttyS0", &TTYS0_DEV);
# ifdef TTYS1_DEV
# ifdef TTYS1_DEV
uart_register("/dev/ttyS1", &TTYS1_DEV);
# ifdef TTYS2_DEV
# ifdef TTYS2_DEV
uart_register("/dev/ttyS2", &TTYS2_DEV);
# ifdef TTYS3_DEV
# ifdef TTYS3_DEV
uart_register("/dev/ttyS3", &TTYS2_DEV);
# ifdef TTYS4_DEV
# ifdef TTYS4_DEV
uart_register("/dev/ttyS4", &TTYS2_DEV);
# endif
# endif
# endif
# endif
# endif
#endif
}
arch/arm/src/imxrt/hardware/imxrt_enet.h
+6 -6
View File
@@ -509,13 +509,13 @@
*/
#ifdef IMXRT_ENET_HAS_DBSWAP
# ifndef CONFIG_ENDIAN_BIG
# define IMXRT_USE_DBSWAP
# endif
# ifndef CONFIG_ENDIAN_BIG
# define IMXRT_USE_DBSWAP
# endif
#else
# ifndef CONFIG_ENDIAN_BIG
# define IMXRT_BUFFERS_SWAP
# endif
# ifndef CONFIG_ENDIAN_BIG
# define IMXRT_BUFFERS_SWAP
# endif
#endif
#ifndef IMXRT_BUFFERS_SWAP
arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h
+1 -1
View File
@@ -200,7 +200,7 @@
/* Bits 13-15: Reserved */
#define CCM_CBCDR_SEMC_PODF_SHIFT (16) /* Bits 16-18: Post divider for SEMC clock */
#define CCM_CBCDR_SEMC_PODF_MASK (0x7 << CCM_CBCDR_SEMC_PODF_SHIFT)
# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT)
# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT)
/* Bits 19-24: Reserved */
#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25) /* Bit 25: Selector for peripheral main clock */
#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (1 << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)
arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h
+1 -1
View File
@@ -1012,7 +1012,7 @@
#define GPR_GPR2_L2_MEM_FORCE_DEEPSLEEP (1 << 14)
#define GPR_GPR2_MQS_CLK_DIV_SHIFT (16)
#define GPR_GPR2_MQS_CLK_DIV_MASK (255 << GPR_GPR2_MQS_CLK_DIV_SHIFT)
# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT)
# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT)
#define GPR_GPR2_MQS_SW_RST_EN (1 << 24)
#define GPR_GPR2_MQS_EN (1 << 25)
#define GPR_GPR2_MQS_OVERSAMPLE32 (0 << 26)
arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h
+2 -2
View File
@@ -209,7 +209,7 @@
/* Bits 13-15: Reserved */
#define CCM_CBCDR_SEMC_PODF_SHIFT (16) /* Bits 16-18: Post divider for SEMC clock */
#define CCM_CBCDR_SEMC_PODF_MASK (0x3 << CCM_CBCDR_SEMC_PODF_SHIFT)
# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT)
# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT)
/* Bits 19-24: Reserved */
#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25) /* Bit 25: Selector for peripheral main clock */
#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (1 << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)
@@ -262,7 +262,7 @@
/* Bits 20-22: Reserved */
#define CCM_CBCMR_LCDIF_PODF_SHIFT (23) /* Bits 23-25: Post-divider for LCDIF clock */
#define CCM_CBCMR_LCDIF_PODF_MASK (0x7 << CCM_CBCMR_LCDIF_PODF_SHIFT)
# define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT)
# define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT)
#define CCM_CBCMR_LPSPI_PODF_SHIFT (26) /* Bits 26-28: Divider for LPSPI */
#define CCM_CBCMR_LPSPI_PODF_MASK (0x7 << CCM_CBCMR_LPSPI_PODF_SHIFT)
# define CCM_CBCMR_LPSPI_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_PODF_SHIFT)
arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h
+1 -1
View File
@@ -1288,7 +1288,7 @@
#define GPR_GPR2_L2_MEM_FORCE_DEEPSLEEP (1 << 14)
#define GPR_GPR2_MQS_CLK_DIV_SHIFT (16)
#define GPR_GPR2_MQS_CLK_DIV_MASK (255 << GPR_GPR2_MQS_CLK_DIV_SHIFT)
# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT)
# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT)
#define GPR_GPR2_MQS_SW_RST_EN (1 << 24)
#define GPR_GPR2_MQS_EN (1 << 25)
#define GPR_GPR2_MQS_OVERSAMPLE32 (0 << 26)
arch/arm/src/imxrt/hardware/rt106x/imxrt106x_ccm.h
+2 -2
View File
@@ -205,7 +205,7 @@
/* Bits 13-15: Reserved */
#define CCM_CBCDR_SEMC_PODF_SHIFT (16) /* Bits 16-18: Post divider for SEMC clock */
#define CCM_CBCDR_SEMC_PODF_MASK (0x3 << CCM_CBCDR_SEMC_PODF_SHIFT)
# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT)
# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT)
/* Bits 19-24: Reserved */
#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25) /* Bit 25: Selector for peripheral main clock */
#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (1 << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)
@@ -268,7 +268,7 @@
/* Bits 20-22: Reserved */
#define CCM_CBCMR_LCDIF_PODF_SHIFT (23) /* Bits 23-25: Post-divider for LCDIF clock */
#define CCM_CBCMR_LCDIF_PODF_MASK (0x7 << CCM_CBCMR_LCDIF_PODF_SHIFT)
# define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT)
# define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT)
#define CCM_CBCMR_LPSPI_PODF_SHIFT (26) /* Bits 26-28: Divider for LPSPI */
#define CCM_CBCMR_LPSPI_PODF_MASK (0x7 << CCM_CBCMR_LPSPI_PODF_SHIFT)
# define CCM_CBCMR_LPSPI_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_PODF_SHIFT)
arch/arm/src/imxrt/imxrt_allocateheap.c
+2 -2
View File
@@ -121,9 +121,9 @@
*/
#if defined(IMXRT_OCRAM2_BASE)
# define _IMXRT_OCRAM_BASE IMXRT_OCRAM2_BASE
# define _IMXRT_OCRAM_BASE IMXRT_OCRAM2_BASE
#else
# define _IMXRT_OCRAM_BASE IMXRT_OCRAM_BASE
# define _IMXRT_OCRAM_BASE IMXRT_OCRAM_BASE
#endif
#define CONFIG_ITCM_USED 0
arch/arm/src/imxrt/imxrt_enc.c
+12 -12
View File
@@ -77,7 +77,7 @@
#endif
#ifndef CONFIG_ENC1_HNE
# define CONFIG_ENC1_HNE 0
# define CONFIG_ENC1_HNE 0
#endif
#ifndef CONFIG_ENC1_XIE
@@ -89,7 +89,7 @@
#endif
#ifndef CONFIG_ENC1_XNE
# define CONFIG_ENC1_XNE 0
# define CONFIG_ENC1_XNE 0
#endif
#ifndef CONFIG_ENC1_MOD
@@ -97,7 +97,7 @@
#endif
#ifndef CONFIG_ENC1_MODULUS
# define CONFIG_ENC1_MODULUS 0
# define CONFIG_ENC1_MODULUS 0
#endif
#if defined(CONFIG_DEBUG_SENSORS)
@@ -122,7 +122,7 @@
#endif
#ifndef CONFIG_ENC2_HNE
# define CONFIG_ENC2_HNE 0
# define CONFIG_ENC2_HNE 0
#endif
#ifndef CONFIG_ENC2_XIE
@@ -134,7 +134,7 @@
#endif
#ifndef CONFIG_ENC2_XNE
# define CONFIG_ENC2_XNE 0
# define CONFIG_ENC2_XNE 0
#endif
#ifndef CONFIG_ENC2_MOD
@@ -142,7 +142,7 @@
#endif
#ifndef CONFIG_ENC2_MODULUS
# define CONFIG_ENC2_MODULUS 0
# define CONFIG_ENC2_MODULUS 0
#endif
#if defined(CONFIG_DEBUG_SENSORS)
@@ -167,7 +167,7 @@
#endif
#ifndef CONFIG_ENC3_HNE
# define CONFIG_ENC3_HNE 0
# define CONFIG_ENC3_HNE 0
#endif
#ifndef CONFIG_ENC3_XIE
@@ -179,7 +179,7 @@
#endif
#ifndef CONFIG_ENC3_XNE
# define CONFIG_ENC3_XNE 0
# define CONFIG_ENC3_XNE 0
#endif
#ifndef CONFIG_ENC3_MOD
@@ -187,7 +187,7 @@
#endif
#ifndef CONFIG_ENC3_MODULUS
# define CONFIG_ENC3_MODULUS 0
# define CONFIG_ENC3_MODULUS 0
#endif
#if defined(CONFIG_DEBUG_SENSORS)
@@ -212,7 +212,7 @@
#endif
#ifndef CONFIG_ENC4_HNE
# define CONFIG_ENC4_HNE 0
# define CONFIG_ENC4_HNE 0
#endif
#ifndef CONFIG_ENC4_XIE
@@ -224,7 +224,7 @@
#endif
#ifndef CONFIG_ENC4_XNE
# define CONFIG_ENC4_XNE 0
# define CONFIG_ENC4_XNE 0
#endif
#ifndef CONFIG_ENC4_MOD
@@ -232,7 +232,7 @@
#endif
#ifndef CONFIG_ENC4_MODULUS
# define CONFIG_ENC4_MODULUS 0
# define CONFIG_ENC4_MODULUS 0
#endif
#if defined(CONFIG_DEBUG_SENSORS)
arch/arm/src/imxrt/imxrt_flexcan.c
+2 -2
View File
@@ -821,10 +821,10 @@ static void imxrt_receive(struct imxrt_driver_s *priv,
uint32_t mbi;
uint32_t mbj;
struct mb_s *rf;
# ifdef CONFIG_NET_CAN_CANFD
#ifdef CONFIG_NET_CAN_CANFD
uint32_t *frame_data_word;
uint32_t i;
# endif
#endif
uint32_t f;
while ((f = flags) != 0)
arch/arm/src/imxrt/imxrt_flexpwm.c
+2 -2
View File
@@ -52,9 +52,9 @@
#ifdef CONFIG_IMXRT_FLEXPWM
#ifdef CONFIG_PWM_NCHANNELS
# define PWM_NCHANNELS CONFIG_PWM_NCHANNELS
# define PWM_NCHANNELS CONFIG_PWM_NCHANNELS
#else
# define PWM_NCHANNELS 1
# define PWM_NCHANNELS 1
#endif
#define MODULE_OFFSET 0x60
arch/arm/src/imxrt/imxrt_serial.c
+158 -158
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/imxrt/imxrt_usbdev.c
+2 -2
View File
@@ -408,8 +408,8 @@ struct imxrt_usbdev_s
static uint32_t imxrt_getreg(uint32_t addr);
static void imxrt_putreg(uint32_t val, uint32_t addr);
#else
# define imxrt_getreg(addr) getreg32(addr)
# define imxrt_putreg(val,addr) putreg32(val,addr)
# define imxrt_getreg(addr) getreg32(addr)
# define imxrt_putreg(val,addr) putreg32(val,addr)
#endif
static inline void imxrt_clrbits(uint32_t mask, uint32_t addr);
arch/arm/src/kinetis/hardware/kinetis_adc.h
+4 -4
View File
@@ -183,10 +183,10 @@
#define ADC_CFG1_MODE_SHIFT (2) /* Bits 2-3: Conversion mode selection */
#define ADC_CFG1_MODE_MASK (3 << ADC_CFG1_MODE_SHIFT)
# define ADC_CFG1_MODE_89BIT (0 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 8-bit; DIFF=1 9-bit */
# define ADC_CFG1_MODE_1213BIT (1 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 12-bit; DIFF=1 13-bit */
# define ADC_CFG1_MODE_1011BIT (2 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 10-bit; DIFF=1 11-bit */
# define ADC_CFG1_MODE_1616BIT (3 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 16-bit; DIFF=1 16-bit */
# define ADC_CFG1_MODE_89BIT (0 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 8-bit; DIFF=1 9-bit */
# define ADC_CFG1_MODE_1213BIT (1 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 12-bit; DIFF=1 13-bit */
# define ADC_CFG1_MODE_1011BIT (2 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 10-bit; DIFF=1 11-bit */
# define ADC_CFG1_MODE_1616BIT (3 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 16-bit; DIFF=1 16-bit */
#define ADC_CFG1_ADLSMP (1 << 4) /* Bit 4: Sample time configuration */
#define ADC_CFG1_ADIV_SHIFT (5) /* Bits 5-6: Clock divide select */
arch/arm/src/kinetis/hardware/kinetis_enet.h
+6 -6
View File
@@ -489,13 +489,13 @@
*/
#ifdef KINETIS_ENET_HAS_DBSWAP
# ifndef CONFIG_ENDIAN_BIG
# define KINETIS_USE_DBSWAP
# endif
# ifndef CONFIG_ENDIAN_BIG
# define KINETIS_USE_DBSWAP
# endif
#else
# ifndef CONFIG_ENDIAN_BIG
# define KINETIS_BUFFERS_SWAP
# endif
# ifndef CONFIG_ENDIAN_BIG
# define KINETIS_BUFFERS_SWAP
# endif
#endif
#ifndef KINETIS_BUFFERS_SWAP
arch/arm/src/kinetis/hardware/kinetis_flexbus.h
-2
View File
@@ -68,8 +68,6 @@
/* Register Addresses *******************************************************/
# define 0x4000c000 /* FlexBus */
#define KINETIS_FB_CS_BASE(n) (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CS_OFFSET(n))
#define KINETIS_FB_CSAR(n) (KINETIS_FB_CS_BASE(n)+KINETIS_FB_CSAR_OFFSET)
#define KINETIS_FB_CSMR(n) (KINETIS_FB_CS_BASE(n)+KINETIS_FB_CSMR_OFFSET)
arch/arm/src/kinetis/hardware/kinetis_k40memorymap.h
+2 -2
View File
@@ -46,10 +46,10 @@
#define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read-
* only data (Includes exception
* vectors in first 1024 bytes) */
# if !defined(KINETIS_FLEXMEM_SIZE)
#if !defined(KINETIS_FLEXMEM_SIZE)
# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */
# endif
#endif
#define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM
* (ICODE/DCODE) */
#define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
arch/arm/src/kinetis/hardware/kinetis_k64memorymap.h
+98 -98
View File
@@ -48,135 +48,135 @@
defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || \
defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12)
# define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read-
# define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read-
* only data (Includes exception
* vectors in first 1024 bytes) */
# if !defined(KINETIS_FLEXMEM_SIZE)
# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */
# endif
# define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM
# if !defined(KINETIS_FLEXMEM_SIZE)
# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */
# endif
# define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM
* (ICODE/DCODE) */
# define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
# define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
* region */
/* 0x20100000 * -0x21ffffff Reserved */
# define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */
# define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */
/* 0x24000000 * -0x3fffffff Reserved */
# define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral
# define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral
* bridge 0 (AIPS-Lite0) */
# define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral
# define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral
* bridge 1 (AIPS-Lite1) */
# define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general
# define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general
* purpose input/output (GPIO) */
/* 0x40100000 * -0x41ffffff Reserved */
# define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge
# define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge
* (AIPS-Lite) and general purpose
* input/output (GPIO) bitband */
/* 0x44000000 * -0x5fffffff Reserved */
# define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus */
# define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
# define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus */
# define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
/* 0xe0100000 * -0xffffffff Reserved */
/* Peripheral Bridge 0 Memory Map *******************************************/
# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
# define KINETIS_MPU_BASE 0x4000d000 /* MPU */
# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
# define KINETIS_FTFE_BASE 0x40020000 /* Flash memory */
# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel multiplexer 0 */
# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */
# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */
# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
# define KINETIS_CRC_BASE 0x40032000 /* CRC */
# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */
# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */
# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
# define KINETIS_LPTMR0_BASE 0x40040000 /* Low power timer 0 */
# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
# define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */
# define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */
# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */
# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
# define KINETIS_I2C2_BASE 0x400E6000 /* I2C 2 */
# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
# define KINETIS_MPU_BASE 0x4000d000 /* MPU */
# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
# define KINETIS_FTFE_BASE 0x40020000 /* Flash memory */
# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel multiplexer 0 */
# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */
# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */
# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
# define KINETIS_CRC_BASE 0x40032000 /* CRC */
# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */
# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */
# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
# define KINETIS_LPTMR0_BASE 0x40040000 /* Low power timer 0 */
# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
# define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */
# define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */
# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */
# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
# define KINETIS_I2C2_BASE 0x400E6000 /* I2C 2 */
# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
/* Peripheral Bridge 1 Memory Map *******************************************/
# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
# define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */
# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */
# define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */
# define KINETIS_FTM2_BASE 0x4003a000 /* FlexTimer 2 */
# define KINETIS_FTM3_BASE 0x400b9000 /* FlexTimer 3 */
# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */
# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
# define KINETIS_UART5_BASE 0x400eb000 /* UART5 */
# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
# define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */
# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */
# define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */
# define KINETIS_FTM2_BASE 0x4003a000 /* FlexTimer 2 */
# define KINETIS_FTM3_BASE 0x400b9000 /* FlexTimer 3 */
# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */
# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
# define KINETIS_UART5_BASE 0x400eb000 /* UART5 */
# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
* purpose input/output module that shares the
* crossbar switch slave port with the AIPS-Lite
* is accessed at this address. */
# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map **********************************/
# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */
# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */
# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
#else
/* The memory map for other parts is defined in other documents and may or
arch/arm/src/kinetis/hardware/kinetis_k66memorymap.h
+118 -118
View File
@@ -46,164 +46,164 @@
#if defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \
defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18)
# define KINETIS_FLASH_BASE 0x00000000 /* -0x07ffffff Program flash and read-
# define KINETIS_FLASH_BASE 0x00000000 /* -0x07ffffff Program flash and read-
* only data (Includes exception
* vectors in first 1024 bytes) */
# define KINETIS_SDRAMALIAS_BASE 0x08000000 /* -0x0fffffff SDRAM (Aliased area). mapped
# define KINETIS_SDRAMALIAS_BASE 0x08000000 /* -0x0fffffff SDRAM (Aliased area). mapped
* to same space of 0x88000000 -
* 0x8FFF_FFFF. See bit31 of
* SDRAMC */
# if defined(KINETIS_FLEXMEM_SIZE)
# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */
# else
# define KINETIS_PRGACCLRAM_BASE 0x14000000 /* -0x17ffffff For devices with program flash
# if defined(KINETIS_FLEXMEM_SIZE)
# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */
# else
# define KINETIS_PRGACCLRAM_BASE 0x14000000 /* -0x17ffffff For devices with program flash
* only: Programming acceleration
* RAM */
# endif
# define KINETIS_FBALIAS_BASE 0x18000000 /* -0x1bffffff FlexBus (Aliased Area). mapped
# endif
# define KINETIS_FBALIAS_BASE 0x18000000 /* -0x1bffffff FlexBus (Aliased Area). mapped
* to same space of 0x9800_0000 -
* 0x9BFF_FFFF. See bit31 of
* FlexBus chip select */
# define KINETIS_SRAML_BASE 0x1c000000 /* -0x1fffffff SRAM_L: Lower SRAM
# define KINETIS_SRAML_BASE 0x1c000000 /* -0x1fffffff SRAM_L: Lower SRAM
* (ICODE/DCODE) */
# define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
# define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
* region */
/* 0x20100000 * -0x21ffffff Reserved */
# define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */
# define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */
/* 0x24000000 * -0x2fffffff Reserved */
# define KINETIS_FDATALIAS_BASE 0x30000000 /* -0x33ffffff Flash Data Alias */
# define KINETIS_FLEXNVMCO_BASE 0x34000000 /* -0x3fffffff FlexNVM Cortex-M4 core only */
# define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral
# define KINETIS_FDATALIAS_BASE 0x30000000 /* -0x33ffffff Flash Data Alias */
# define KINETIS_FLEXNVMCO_BASE 0x34000000 /* -0x3fffffff FlexNVM Cortex-M4 core only */
# define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral
* bridge 0 (AIPS-Lite0) */
# define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral
# define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral
* bridge 1 (AIPS-Lite1) */
# define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general
# define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general
* purpose input/output (GPIO) */
/* 0x40100000 * -0x41ffffff Reserved */
# define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge
# define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge
* (AIPS-Lite) and general purpose
* input/output (GPIO) bitband */
/* 0x44000000 * -0x5fffffff Reserved */
# define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus (External Memory - Write-back) */
# define KINETIS_SDRAMWB_BASE 0x70000000 /* -0x7fffffff SDRAM (External RAM - Write-back) */
# define KINETIS_SDRAMWT_BASE 0x80000000 /* -0x8fffffff SDRAM (External RAM - Write-through) */
# define KINETIS_FLEXBUSWT_BASE 0x90000000 /* -0x9fffffff FlexBus (External RAM - Write-through) */
# define KINETIS_FLEXBUSEP_BASE 0xa0000000 /* -0xdfffffff FlexBus External Peripheral - Not executable)*/
# define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
# define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus (External Memory - Write-back) */
# define KINETIS_SDRAMWB_BASE 0x70000000 /* -0x7fffffff SDRAM (External RAM - Write-back) */
# define KINETIS_SDRAMWT_BASE 0x80000000 /* -0x8fffffff SDRAM (External RAM - Write-through) */
# define KINETIS_FLEXBUSWT_BASE 0x90000000 /* -0x9fffffff FlexBus (External RAM - Write-through) */
# define KINETIS_FLEXBUSEP_BASE 0xa0000000 /* -0xdfffffff FlexBus External Peripheral - Not executable)*/
# define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
/* 0xe0100000 * -0xffffffff Reserved */
/* Peripheral Bridge 0 Memory Map *******************************************/
# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
# define KINETIS_MPU_BASE 0x4000d000 /* MPU */
# define KINETIS_SDRAMC_BASE 0x4000f000 /* SDRAMC */
# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
# define KINETIS_FTFE_BASE 0x40020000 /* Flash memory */
# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel multiplexer 0 */
# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
# define KINETIS_RNGA_BASE 0x40029000 /* Random Number Generator (RNGA) */
# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */
# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */
# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
# define KINETIS_CRC_BASE 0x40032000 /* CRC */
# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */
# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */
# define KINETIS_FTM2_BASE 0x4003a000 /* FlexTimer (FTM) 2 */
# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
# define KINETIS_DAC0_BASE 0x4003f000 /* DAC0 */
# define KINETIS_LPTMR0_BASE 0x40040000 /* Low power timer 0 */
# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */
# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
# define KINETIS_RCM_BASE 0x4007f000 /* Reset Control Module (RCM) */
# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
# define KINETIS_MPU_BASE 0x4000d000 /* MPU */
# define KINETIS_SDRAMC_BASE 0x4000f000 /* SDRAMC */
# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
# define KINETIS_FTFE_BASE 0x40020000 /* Flash memory */
# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel multiplexer 0 */
# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
# define KINETIS_RNGA_BASE 0x40029000 /* Random Number Generator (RNGA) */
# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */
# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */
# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
# define KINETIS_CRC_BASE 0x40032000 /* CRC */
# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */
# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */
# define KINETIS_FTM2_BASE 0x4003a000 /* FlexTimer (FTM) 2 */
# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
# define KINETIS_DAC0_BASE 0x4003f000 /* DAC0 */
# define KINETIS_LPTMR0_BASE 0x40040000 /* Low power timer 0 */
# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */
# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
# define KINETIS_RCM_BASE 0x4007f000 /* Reset Control Module (RCM) */
/* Peripheral Bridge 1 Memory Map *******************************************/
# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
# define KINETIS_RNGA_ALT_BASE 0x400a0000 /* Alternate address Random number generator (RNGA) */
# define KINETIS_USBHS_BASE 0x400a1000 /* USB OTG HS/FS/LS */
# define KINETIS_USBHSPHY_BASE 0x400a2000 /* USBHS PHY */
# define KINETIS_USBHSDCD_BASE 0x400a3000 /* USBHS DCD */
# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */
# define KINETIS_SDHC_BASE 0x400b1000 /* eSDHC */
# define KINETIS_FTM2_ALT_BASE 0x400b8000 /* Alternate address FlexTimer 2 */
# define KINETIS_FTM3_BASE 0x400b9000 /* FlexTimer 3 */
# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */
# define KINETIS_LPUART0_BASE 0x400c4000 /* LPUART0 */
# define KINETIS_TPM1_BASE 0x400c9000 /* TPM1 */
# define KINETIS_TPM2_BASE 0x400ca000 /* TPM2 */
# define KINETIS_DAC0_ALT_BASE 0x400cc000 /* Alternate address 12-bit digital-to-analog converter (DAC) 0 */
# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
# define KINETIS_I2C2_BASE 0x400e6000 /* I2C 2 */
# define KINETIS_I2C3_BASE 0x400e7000 /* I2C 3 */
# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
# define KINETIS_RNGA_ALT_BASE 0x400a0000 /* Alternate address Random number generator (RNGA) */
# define KINETIS_USBHS_BASE 0x400a1000 /* USB OTG HS/FS/LS */
# define KINETIS_USBHSPHY_BASE 0x400a2000 /* USBHS PHY */
# define KINETIS_USBHSDCD_BASE 0x400a3000 /* USBHS DCD */
# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */
# define KINETIS_SDHC_BASE 0x400b1000 /* eSDHC */
# define KINETIS_FTM2_ALT_BASE 0x400b8000 /* Alternate address FlexTimer 2 */
# define KINETIS_FTM3_BASE 0x400b9000 /* FlexTimer 3 */
# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */
# define KINETIS_LPUART0_BASE 0x400c4000 /* LPUART0 */
# define KINETIS_TPM1_BASE 0x400c9000 /* TPM1 */
# define KINETIS_TPM2_BASE 0x400ca000 /* TPM2 */
# define KINETIS_DAC0_ALT_BASE 0x400cc000 /* Alternate address 12-bit digital-to-analog converter (DAC) 0 */
# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
# define KINETIS_I2C2_BASE 0x400e6000 /* I2C 2 */
# define KINETIS_I2C3_BASE 0x400e7000 /* I2C 3 */
# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
* purpose input/output module that shares the
* crossbar switch slave port with the AIPS-Lite
* is accessed at this address. */
# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map **********************************/
# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */
# define KINETIS_CACHECTL_BASE 0xe0082000 /* Cache Controller */
# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */
# define KINETIS_CACHECTL_BASE 0xe0082000 /* Cache Controller */
# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
#else
/* The memory map for other parts is defined in other documents and may or
arch/arm/src/kinetis/hardware/kinetis_kx6tpm.h
+32 -32
View File
@@ -81,20 +81,20 @@
#define TPM_SC_PS_SHIFT 0 /* Bits 0-2: Prescale Factor Selection */
#define TPM_SC_PS_MASK (7 << TPM_SC_PS_SHIFT)
# define TPM_SC_PS_DIV1 (0 << TPM_SC_PS_SHIFT) /* Divide Clock by 1 */
# define TPM_SC_PS_DIV2 (1 << TPM_SC_PS_SHIFT) /* Divide Clock by 2 */
# define TPM_SC_PS_DIV4 (2 << TPM_SC_PS_SHIFT) /* Divide Clock by 4 */
# define TPM_SC_PS_DIV8 (3 << TPM_SC_PS_SHIFT) /* Divide Clock by 8 */
# define TPM_SC_PS_DIV16 (4 << TPM_SC_PS_SHIFT) /* Divide Clock by 16 */
# define TPM_SC_PS_DIV32 (5 << TPM_SC_PS_SHIFT) /* Divide Clock by 32 */
# define TPM_SC_PS_DIV64 (6 << TPM_SC_PS_SHIFT) /* Divide Clock by 64 */
# define TPM_SC_PS_DIV128 (7 << TPM_SC_PS_SHIFT) /* Divide Clock by 128 */
# define TPM_SC_PS_DIV1 (0 << TPM_SC_PS_SHIFT) /* Divide Clock by 1 */
# define TPM_SC_PS_DIV2 (1 << TPM_SC_PS_SHIFT) /* Divide Clock by 2 */
# define TPM_SC_PS_DIV4 (2 << TPM_SC_PS_SHIFT) /* Divide Clock by 4 */
# define TPM_SC_PS_DIV8 (3 << TPM_SC_PS_SHIFT) /* Divide Clock by 8 */
# define TPM_SC_PS_DIV16 (4 << TPM_SC_PS_SHIFT) /* Divide Clock by 16 */
# define TPM_SC_PS_DIV32 (5 << TPM_SC_PS_SHIFT) /* Divide Clock by 32 */
# define TPM_SC_PS_DIV64 (6 << TPM_SC_PS_SHIFT) /* Divide Clock by 64 */
# define TPM_SC_PS_DIV128 (7 << TPM_SC_PS_SHIFT) /* Divide Clock by 128 */
#define TPM_SC_CMOD_SHIFT 3 /* Bits 3-4: Clock Mode Selection */
#define TPM_SC_CMOD_MASK (3 << TPM_SC_CMOD_SHIFT)
# define TPM_SC_CMOD_DIS (0 << TPM_SC_CMOD_SHIFT) /* TPM counter is disabled */
# define TPM_SC_CMOD_LPTPM_CLK (1 << TPM_SC_CMOD_SHIFT) /* TPM increments on every counter clock */
# define TPM_SC_CMOD_LPTPM_EXTCLK (2 << TPM_SC_CMOD_SHIFT) /* TPM increments on rising edge of EXTCLK */
# define TPM_SC_CMOD_DIS (0 << TPM_SC_CMOD_SHIFT) /* TPM counter is disabled */
# define TPM_SC_CMOD_LPTPM_CLK (1 << TPM_SC_CMOD_SHIFT) /* TPM increments on every counter clock */
# define TPM_SC_CMOD_LPTPM_EXTCLK (2 << TPM_SC_CMOD_SHIFT) /* TPM increments on rising edge of EXTCLK */
#define TPM_SC_CPWMS (1 << 5) /* Bit 5: Center-aligned PWM Select */
#define TPM_SC_TOIE (1 << 6) /* Bit 6: Timer Overflow Interrupt Enable */
@@ -162,8 +162,8 @@
#define TPM_CONF_DBGMODE_SHIFT 6 /* Bits 6-7: Debug Mode */
#define TPM_CONF_DBGMODE_MASK (3 << TPM_CONF_DBGMODE_SHIFT)
# define TPM_CONF_DBGMODE_PAUSE (0 << TPM_CONF_DBGMODE_SHIFT) /* TPM counter will pause during DEBUG mode */
# define TPM_CONF_DBGMODE_CONT (3 << TPM_CONF_DBGMODE_SHIFT) /* TPM counter continue working in DEBUG mode */
# define TPM_CONF_DBGMODE_PAUSE (0 << TPM_CONF_DBGMODE_SHIFT) /* TPM counter will pause during DEBUG mode */
# define TPM_CONF_DBGMODE_CONT (3 << TPM_CONF_DBGMODE_SHIFT) /* TPM counter continue working in DEBUG mode */
#define TPM_CONF_GTBSYNC (1 << 8) /* Bit 8: Global Time Base Synchronization */
#define TPM_CONF_GTBEEN (1 << 9) /* Bit 9: Global Time Base Enable */
@@ -179,25 +179,25 @@
#define TPM_CONF_TRGSEL_SHIFT 24 /* Bits 24-27: Trigger Select */
#define TPM_CONF_TRGSEL_MASK (0xf << TPM_CONF_TRGSEL_SHIFT)
/* Internal TPM_CONF_TRGSRC set */
# define TPM_CONF_TRGSEL_INTC0 (0 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 0 pin input capture */
# define TPM_CONF_TRGSEL_INTC1 (2 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 1 pin input capture */
# define TPM_CONF_TRGSEL_INTC01 (3 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 0 or 1 pin input capture */
# define TPM_CONF_TRGSEL_INTC0 (0 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 0 pin input capture */
# define TPM_CONF_TRGSEL_INTC1 (2 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 1 pin input capture */
# define TPM_CONF_TRGSEL_INTC01 (3 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 0 or 1 pin input capture */
# define TPM_CONF_TRGSEL_EXTRG_IN (0 << TPM_CONF_TRGSEL_SHIFT) /* External trigger pin input */
# define TPM_CONF_TRGSEL_CMP0 (1 << TPM_CONF_TRGSEL_SHIFT) /* CPM0 output */
# define TPM_CONF_TRGSEL_CMP1 (2 << TPM_CONF_TRGSEL_SHIFT) /* CPM1 output */
# define TPM_CONF_TRGSEL_CMP2 (3 << TPM_CONF_TRGSEL_SHIFT) /* CPM2 output */
# define TPM_CONF_TRGSEL_PIT0 (4 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 0 */
# define TPM_CONF_TRGSEL_PIT1 (5 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 1 */
# define TPM_CONF_TRGSEL_PIT2 (6 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 2 */
# define TPM_CONF_TRGSEL_PIT3 (7 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 3 */
# define TPM_CONF_TRGSEL_FTM0 (8 << TPM_CONF_TRGSEL_SHIFT) /* FTM0 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_FTM1 (9 << TPM_CONF_TRGSEL_SHIFT) /* FTM1 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_FTM2 (10 << TPM_CONF_TRGSEL_SHIFT) /* FTM2 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_FTM3 (11 << TPM_CONF_TRGSEL_SHIFT) /* FTM3 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_RTC_ALRM (12 << TPM_CONF_TRGSEL_SHIFT) /* RTC Alarm */
# define TPM_CONF_TRGSEL_RTC_SECS (13 << TPM_CONF_TRGSEL_SHIFT) /* RTC Seconds */
# define TPM_CONF_TRGSEL_LPTMR (14 << TPM_CONF_TRGSEL_SHIFT) /* LPTMR trigger */
# define TPM_CONF_TRGSEL_SW (15 << TPM_CONF_TRGSEL_SHIFT) /* Software Trigger */
# define TPM_CONF_TRGSEL_EXTRG_IN (0 << TPM_CONF_TRGSEL_SHIFT) /* External trigger pin input */
# define TPM_CONF_TRGSEL_CMP0 (1 << TPM_CONF_TRGSEL_SHIFT) /* CPM0 output */
# define TPM_CONF_TRGSEL_CMP1 (2 << TPM_CONF_TRGSEL_SHIFT) /* CPM1 output */
# define TPM_CONF_TRGSEL_CMP2 (3 << TPM_CONF_TRGSEL_SHIFT) /* CPM2 output */
# define TPM_CONF_TRGSEL_PIT0 (4 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 0 */
# define TPM_CONF_TRGSEL_PIT1 (5 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 1 */
# define TPM_CONF_TRGSEL_PIT2 (6 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 2 */
# define TPM_CONF_TRGSEL_PIT3 (7 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 3 */
# define TPM_CONF_TRGSEL_FTM0 (8 << TPM_CONF_TRGSEL_SHIFT) /* FTM0 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_FTM1 (9 << TPM_CONF_TRGSEL_SHIFT) /* FTM1 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_FTM2 (10 << TPM_CONF_TRGSEL_SHIFT) /* FTM2 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_FTM3 (11 << TPM_CONF_TRGSEL_SHIFT) /* FTM3 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_RTC_ALRM (12 << TPM_CONF_TRGSEL_SHIFT) /* RTC Alarm */
# define TPM_CONF_TRGSEL_RTC_SECS (13 << TPM_CONF_TRGSEL_SHIFT) /* RTC Seconds */
# define TPM_CONF_TRGSEL_LPTMR (14 << TPM_CONF_TRGSEL_SHIFT) /* LPTMR trigger */
# define TPM_CONF_TRGSEL_SW (15 << TPM_CONF_TRGSEL_SHIFT) /* Software Trigger */
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_KX6TPM_H */
arch/arm/src/kinetis/hardware/kinetis_sim.h
+1 -1
View File
@@ -639,7 +639,7 @@
#endif
/* Bits 13-14: Reserved */
#if defined(KINETIS_SIM_SOPT7_ADC1ALTTRGEN)
# define SIM_SOPT7_ADC1ALTTRGEN (1 << 15) /* Bit 15: ADC1 alternate trigger enable */
# define SIM_SOPT7_ADC1ALTTRGEN (1 << 15) /* Bit 15: ADC1 alternate trigger enable */
#endif
/* Bits 16-31: Reserved */
#if defined(KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL)
arch/arm/src/kinetis/kinetis_clockconfig.c
+11 -11
View File
@@ -68,15 +68,15 @@
/* A board may provide BOARD_EXTAL_LP to not choose MCG_C2_HGO */
# if defined(BOARD_EXTAL_LP)
# define BOARD_MGC_C2_HGO 0 /* Do not use MCG_C2_HGO */
# else
# if !defined(KINETIS_MCG_HAS_C2_HGO)
# error BOARD_EXTAL_LP is not defined and MCG_C2_HGO is not supported on this SoC!
# else
# define BOARD_MGC_C2_HGO MCG_C2_HGO
# endif
# endif
# if defined(BOARD_EXTAL_LP)
# define BOARD_MGC_C2_HGO 0 /* Do not use MCG_C2_HGO */
# else
# if !defined(KINETIS_MCG_HAS_C2_HGO)
# error BOARD_EXTAL_LP is not defined and MCG_C2_HGO is not supported on this SoC!
# else
# define BOARD_MGC_C2_HGO MCG_C2_HGO
# endif
# endif
/* A board must provide BOARD_MCG_C2_FCFTRIM when SoC has the setting */
@@ -97,11 +97,11 @@
/* A board must provide BOARD_MCG_C2_LOCRE0 when SoC has the setting */
# if defined(KINETIS_MCG_HAS_C2_LOCRE0) && !defined(BOARD_MCG_C2_LOCRE0)
# error MCG_C2_LOCRE0 is supported on this SoC and BOARD_MCG_C2_LOCRE0 is not defined!
# error MCG_C2_LOCRE0 is supported on this SoC and BOARD_MCG_C2_LOCRE0 is not defined!
# endif
# if !defined(KINETIS_MCG_HAS_C2_LOCRE0) && defined(BOARD_MCG_C2_LOCRE0)
# error BOARD_MCG_C2_LOCRE0 is defined but MCG_C2_LOCRE0 is not supported on this SoC!
# error BOARD_MCG_C2_LOCRE0 is defined but MCG_C2_LOCRE0 is not supported on this SoC!
# endif
/* Provide the 0 default */

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