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Fix style problems noted by nxstyle for this PR

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NOTES:
- arch/arm/src/sama5/sam_can.c:  Generates several "Mixed case identifier" complaints because definitions provided by header files that are not part of the change.
- arch/arm/src/sama5/sam_pmecc.c:  Has two cases of "Mixed case identifies" result within commented out code.  There are references to undefined types that might be provided by Atmel logic (Pmecc and Pmerrloc) if it were ever integrated.
This commit is contained in:
Gregory Nutt
2020-04-05 07:41:41 -06:00
committed by Alan Carvalho de Assis
parent d95d641597
commit 7837eec33f
4 changed files with 368 additions and 228 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/sama5/sam_can.c
+51 -29
View File
@@ -65,17 +65,18 @@
#include "up_internal.h"
#include "up_arch.h"
#include "hardware/sam_pinmap.h"
#include "sam_periphclks.h"
#include "sam_pio.h"
#include "sam_can.h"
#if defined(CONFIG_CAN) && (defined(CONFIG_SAMA5_CAN0) || defined(CONFIG_SAMA5_CAN1))
#if defined(CONFIG_CAN) && (defined(CONFIG_SAMA5_CAN0) || \
defined(CONFIG_SAMA5_CAN1))
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Common definitions *******************************************************/
#ifndef MIN
@@ -99,6 +100,7 @@
#endif
/* Interrupts ***************************************************************/
/* If debug is enabled, then print some diagnostic info if any of these
* events occur:
*
@@ -114,7 +116,8 @@
*
* CAN_INT_CERR YES Bit 24: Mailbox CRC Error
* CAN_INT_SERR YES Bit 25: Mailbox Stuffing Error
* CAN_INT_AERR NO Bit 26: Acknowledgment Error (uusally means no CAN bus)
* CAN_INT_AERR NO Bit 26: Acknowledgment Error (usally means no
* CAN bus)
* CAN_INT_FERR YES Bit 27: Form Error
*
* CAN_INT_BERR YES Bit 28: Bit Error
@@ -130,6 +133,7 @@
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure describes receive mailbox filtering */
struct sam_filter_s
@@ -164,7 +168,10 @@ struct sam_config_s
struct sam_can_s
{
const struct sam_config_s *config; /* The constant configuration */
/* The constant configuration */
const struct sam_config_s *config;
bool initialized; /* TRUE: Device has been initialized */
uint8_t freemb; /* Rhe set of unalloated mailboxes */
uint8_t rxmbset; /* The set of mailboxes configured for receive */
@@ -187,9 +194,11 @@ struct sam_can_s
/* CAN Register access */
static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset);
static void can_putreg(FAR struct sam_can_s *priv, int offset, uint32_t regval);
static void can_putreg(FAR struct sam_can_s *priv, int offset,
uint32_t regval);
#ifdef CONFIG_SAMA5_CAN_REGDEBUG
static void can_dumpctrlregs(FAR struct sam_can_s *priv, FAR const char *msg);
static void can_dumpctrlregs(FAR struct sam_can_s *priv,
FAR const char *msg);
static void can_dumpmbregs(FAR struct sam_can_s *priv, FAR const char *msg);
#else
# define can_dumpctrlregs(priv,msg)
@@ -421,7 +430,8 @@ static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset)
****************************************************************************/
#ifdef CONFIG_SAMA5_CAN_REGDEBUG
static void can_putreg(FAR struct sam_can_s *priv, int offset, uint32_t regval)
static void can_putreg(FAR struct sam_can_s *priv, int offset,
uint32_t regval)
{
FAR const struct sam_config_s *config = priv->config;
uintptr_t regaddr = config->base + offset;
@@ -436,7 +446,8 @@ static void can_putreg(FAR struct sam_can_s *priv, int offset, uint32_t regval)
}
#else
static void can_putreg(FAR struct sam_can_s *priv, int offset, uint32_t regval)
static void can_putreg(FAR struct sam_can_s *priv, int offset,
uint32_t regval)
{
FAR const struct sam_config_s *config = priv->config;
putreg32(regval, config->base + offset);
@@ -830,7 +841,8 @@ static int can_setup(FAR struct can_dev_s *dev)
ret = can_hwinitialize(priv);
if (ret < 0)
{
canerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret);
canerr("ERROR: CAN%d H/W initialization failed: %d\n",
config->port, ret);
return ret;
}
@@ -842,7 +854,8 @@ static int can_setup(FAR struct can_dev_s *dev)
ret = irq_attach(config->pid, can_interrupt, dev);
if (ret < 0)
{
canerr("ERROR: Failed to attach CAN%d IRQ (%d)", config->port, config->pid);
canerr("ERROR: Failed to attach CAN%d IRQ (%d)",
config->port, config->pid);
return ret;
}
@@ -851,7 +864,8 @@ static int can_setup(FAR struct can_dev_s *dev)
ret = can_recvsetup(priv);
if (ret < 0)
{
canerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret);
canerr("ERROR: CAN%d H/W initialization failed: %d\n",
config->port, ret);
return ret;
}
@@ -1100,10 +1114,12 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
#ifdef CONFIG_CAN_EXTID
DEBUGASSERT(msg->cm_hdr.ch_extid);
DEBUGASSERT(msg->cm_hdr.ch_id < (1 << 29));
can_putreg(priv, SAM_CAN_MnID_OFFSET(mbndx), CAN_MID_EXTID(msg->cm_hdr.ch_id));
can_putreg(priv, SAM_CAN_MnID_OFFSET(mbndx),
CAN_MID_EXTID(msg->cm_hdr.ch_id));
#else
DEBUGASSERT(msg->cm_hdr.ch_id < (1 << 11));
can_putreg(priv, SAM_CAN_MnID_OFFSET(mbndx), CAN_MID_STDID(msg->cm_hdr.ch_id));
can_putreg(priv, SAM_CAN_MnID_OFFSET(mbndx),
CAN_MID_STDID(msg->cm_hdr.ch_id));
#endif
/* Enable transmit mode */
@@ -1118,7 +1134,8 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
* message data length in the CAN_MCRx register.
*/
DEBUGASSERT((can_getreg(priv, SAM_CAN_MnSR_OFFSET(mbndx)) & CAN_MSR_MRDY) != 0);
DEBUGASSERT((can_getreg(priv, SAM_CAN_MnSR_OFFSET(mbndx)) &
CAN_MSR_MRDY) != 0);
/* Bytes are received/sent on the bus in the following order:
*
@@ -1139,10 +1156,12 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
/* The message buffer is probably not properaly aligned for 32-bit accesses */
ptr = msg->cm_data;
regval = CAN_MDL0(ptr[0]) | CAN_MDL1(ptr[1]) | CAN_MDL2(ptr[2]) | CAN_MDL3(ptr[3]);
regval = CAN_MDL0(ptr[0]) | CAN_MDL1(ptr[1]) | CAN_MDL2(ptr[2]) |
CAN_MDL3(ptr[3]);
can_putreg(priv, SAM_CAN_MnDL_OFFSET(mbndx), regval);
regval = CAN_MDH4(ptr[4]) | CAN_MDH5(ptr[5]) | CAN_MDH6(ptr[6]) | CAN_MDH7(ptr[7]);
regval = CAN_MDH4(ptr[4]) | CAN_MDH5(ptr[5]) | CAN_MDH6(ptr[6]) |
CAN_MDH7(ptr[7]);
can_putreg(priv, SAM_CAN_MnDH_OFFSET(mbndx), regval);
/* Set the DLC value in the CAN_MCRx register. Set the MTCR register
@@ -1270,10 +1289,10 @@ static inline void can_rxinterrupt(FAR struct can_dev_s *dev, int mbndx,
md[0] = can_getreg(priv, SAM_CAN_MnDH_OFFSET(mbndx));
md[1] = can_getreg(priv, SAM_CAN_MnDL_OFFSET(mbndx));
/* Get the ID associated with the newly received message: )nce a new message
* is received, its ID is masked with the CAN_MAMx value and compared
* with the CAN_MIDx value. If accepted, the message ID is copied to the
* CAN_MIDx register.
/* Get the ID associated with the newly received message: )nce a new
* message is received, its ID is masked with the CAN_MAMx value and
* compared with the CAN_MIDx value. If accepted, the message ID is
* copied to the CAN_MIDx register.
*/
mid = can_getreg(priv, SAM_CAN_MnID_OFFSET(mbndx));
@@ -1401,7 +1420,8 @@ static inline void can_mbinterrupt(FAR struct can_dev_s *dev, int mbndx)
case CAN_MMR_MOT_CONSUMER: /* Consumer Mailbox */
case CAN_MMR_MOT_PRODUCER: /* Producer Mailbox */
case CAN_MMR_MOT_DISABLED: /* Mailbox is disabled */
canerr("ERROR: CAN%d MB%d: Unsupported or invalid mailbox type\n",
canerr("ERROR: CAN%d MB%d: Unsupported or "
"invalid mailbox type\n",
priv->config->port, mbndx);
canerr(" MSR: %08x MMR: %08x\n", msr, mmr);
break;
@@ -1438,8 +1458,9 @@ static void can_interrupt(int irq, void *context, FAR void *arg)
/* Get the set of pending interrupts.
*
* All interrupts are cleared by clearing the interrupt source except for
* the internal timer counter overflow interrupt and the timestamp interrupt.
* These interrupts are cleared by reading the CAN_SR register.
* the internal timer counter overflow interrupt and the timestamp
* interrupt. * These interrupts are cleared by reading the CAN_SR
* register.
*/
sr = can_getreg(priv, SAM_CAN_SR_OFFSET);
@@ -1677,7 +1698,8 @@ static int can_bittiming(struct sam_can_s *priv)
if ((propag + phase1 + phase2) != (uint32_t)(tq - 4))
{
canerr("CAN%d ERROR: Could not realize baud %d\n", config->port, config->baud);
canerr("CAN%d ERROR: Could not realize baud %d\n",
config->port, config->baud);
return -EINVAL;
}
@@ -1730,11 +1752,11 @@ static int can_autobaud(struct sam_can_s *priv)
#warning Missing Logic
/* Autobaud Mode. The autobaud feature is enabled by setting the ABM
* field in the CAN_MR register. In this mode, the CAN controller is only
* listening to the line without acknowledging the received messages. It
* can not send any message. The errors flags are updated. The bit timing
* can be adjusted until no error occurs (good configuration found). In
* this mode, the error counters are frozen.
* field in the CAN_MR register. In this mode, the CAN controller is
* only listening to the line without acknowledging the received
* messages. It can not send any message. The errors flags are
* updated. The bit timing can be adjusted until no error occurs (good
* configuration found). In this mode, the error counters are frozen.
*/
regval = can_getreg(priv, SAM_CAN_MR_OFFSET);
arch/arm/src/sama5/sam_nand.c
+77 -47
View File
@@ -137,6 +137,7 @@
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Low-level HSMC Helpers */
#if NAND_NBANKS > 1
@@ -265,6 +266,7 @@ static void nand_reset(struct sam_nandcs_s *priv);
/****************************************************************************
* Private Data
****************************************************************************/
/* These pre-allocated structures hold the state of the MTD driver for NAND
* on CS0..3 as configured.
*/
@@ -648,8 +650,10 @@ static void nand_nfc_cleale(struct sam_nandcs_s *priv, uint8_t mode,
}
cmd = (rw | regval | NFCADDR_CMD_CSID(priv->cs) | acycle |
(((mode & HSMC_CLE_VCMD2_EN) == HSMC_CLE_VCMD2_EN) ? NFCADDR_CMD_VCMD2 : 0) |
(cmd1 << NFCADDR_CMD_CMD1_SHIFT) | (cmd2 << NFCADDR_CMD_CMD2_SHIFT));
(((mode & HSMC_CLE_VCMD2_EN) == HSMC_CLE_VCMD2_EN) ?
NFCADDR_CMD_VCMD2 : 0) |
(cmd1 << NFCADDR_CMD_CMD1_SHIFT) |
(cmd2 << NFCADDR_CMD_CMD2_SHIFT));
nand_nfc_cmdsend(priv, cmd, acycle1234, acycle0);
}
@@ -974,10 +978,6 @@ static uint32_t nand_nfc_poll(void)
sr = nand_getreg(SAM_HSMC_SR);
#ifndef CONFIG_SAMA5_NAND_REGDEBUG
// finfo("sr=%08x\n", sr);
#endif
/* When set to one, this XFRDONE indicates that the NFC has terminated
* the data transfer. This flag is reset after the status read.
*/
@@ -1000,10 +1000,10 @@ static uint32_t nand_nfc_poll(void)
g_nand.cmddone = true;
}
/* If set to one, the RBEDGE0 flag indicates that an edge has been detected
* on the Ready/Busy Line x. Depending on the EDGE CTRL field located in the
* SMC_CFG register, only rising or falling edge is detected. This flag is
* reset after the status read.
/* If set to one, the RBEDGE0 flag indicates that an edge has been
* detected on the Ready/Busy Line x. Depending on the EDGE CTRL field
* located in the SMC_CFG register, only rising or falling edge is
* detected. This flag is reset after the status read.
*/
if ((sr & HSMC_NFCINT_RBEDGE0) != 0)
@@ -1074,10 +1074,10 @@ static int hsmc_interrupt(int irq, void *context, FAR void *arg)
nand_putreg(SAM_HSMC_IDR, HSMC_NFCINT_CMDDONE);
}
/* If set to one, the RBEDGE0 flag indicates that an edge has been detected
* on the Ready/Busy Line x. Depending on the EDGE CTRL field located in the
* SMC_CFG register, only rising or falling edge is detected. This flag is
* reset after the status read.
/* If set to one, the RBEDGE0 flag indicates that an edge has been
* detected on the Ready/Busy Line x. Depending on the EDGE CTRL field
* located in the SMC_CFG register, only rising or falling edge is
* detected. This flag is reset after the status read.
*/
if (g_nand.rbedge && (imr & HSMC_NFCINT_RBEDGE0) != 0)
@@ -1146,17 +1146,21 @@ static void nand_dma_sampledone(struct sam_nandcs_s *priv, int result)
sam_dmasample(priv->dma, &priv->dmaregs[DMA_END_TRANSFER]);
/* Then dump the sampled DMA registers */
/* Initial register values */
sam_dmadump(priv->dma, &priv->dmaregs[DMA_INITIAL], "Initial Registers");
sam_dmadump(priv->dma, &priv->dmaregs[DMA_INITIAL],
"Initial Registers");
/* Register values after DMA setup */
sam_dmadump(priv->dma, &priv->dmaregs[DMA_AFTER_SETUP], "After DMA Setup");
sam_dmadump(priv->dma, &priv->dmaregs[DMA_AFTER_SETUP],
"After DMA Setup");
/* Register values after DMA start */
sam_dmadump(priv->dma, &priv->dmaregs[DMA_AFTER_START], "After DMA Start");
sam_dmadump(priv->dma, &priv->dmaregs[DMA_AFTER_START],
"After DMA Start");
/* Register values at the time of the TX and RX DMA callbacks
* -OR- DMA timeout.
@@ -1169,15 +1173,18 @@ static void nand_dma_sampledone(struct sam_nandcs_s *priv, int result)
#if 0 /* No timeout */
if (result == -ETIMEDOUT || result == -EINTR)
{
sam_dmadump(priv->dma, &priv->dmaregs[DMA_TIMEOUT], "At DMA timeout");
sam_dmadump(priv->dma, &priv->dmaregs[DMA_TIMEOUT],
"At DMA timeout");
}
else
#endif
{
sam_dmadump(priv->dma, &priv->dmaregs[DMA_CALLBACK], "At DMA callback");
sam_dmadump(priv->dma, &priv->dmaregs[DMA_CALLBACK],
"At DMA callback");
}
sam_dmadump(priv->dma, &priv->dmaregs[DMA_END_TRANSFER], "At End-of-Transfer");
sam_dmadump(priv->dma, &priv->dmaregs[DMA_END_TRANSFER],
"At End-of-Transfer");
}
#endif
@@ -1372,9 +1379,10 @@ static int nand_dma_write(struct sam_nandcs_s *priv,
sam_dmaconfig(priv->dma, dmaflags);
/* Setup the Memory-to-Memory DMA. The semantics of the DMA module are
* awkward here. We will treat the NAND (dest) as the peripheral destination
* and memory as the source. Internally, the DMA module will realize that
* this is a memory to memory transfer and should do the right thing.
* awkward here. We will treat the NAND (dest) as the peripheral
* destination and memory as the source. Internally, the DMA module will
* realize that this is a memory to memory transfer and should do the
* right thing.
*/
ret = sam_dmatxsetup(priv->dma, pdest, psrc, nbytes);
@@ -1452,7 +1460,8 @@ static int nand_nfcsram_read(struct sam_nandcs_s *priv, uint8_t *buffer,
/* Transfer using DMA */
ret = nand_dma_read(priv, src, (uintptr_t)buffer, buflen, NFCSRAM_DMA_FLAGS);
ret = nand_dma_read(priv, src, (uintptr_t)buffer, buflen,
NFCSRAM_DMA_FLAGS);
}
else
#endif
@@ -1479,8 +1488,9 @@ static int nand_nfcsram_read(struct sam_nandcs_s *priv, uint8_t *buffer,
* Name: nand_read
*
* Description:
* Read data directly from the NAND data address. Currently this only used
* by the PMECC logic which I could not get working if I read from NFC SRAM.
* Read data directly from the NAND data address. Currently this only
* used by the PMECC logic which I could not get working if I read from
* NFC SRAM.
*
* Input Parameters:
* priv - Lower-half, private NAND FLASH device state
@@ -1536,7 +1546,8 @@ static int nand_read(struct sam_nandcs_s *priv, uint8_t *buffer,
remaining = buflen;
if (buswidth == 16)
{
volatile uint16_t *src16 = (volatile uint16_t *)priv->raw.dataaddr;
volatile uint16_t *src16 =
(volatile uint16_t *)priv->raw.dataaddr;
uint16_t *dest16 = (uint16_t *)buffer;
DEBUGASSERT(((uintptr_t)buffer & 1) == 0);
@@ -1659,7 +1670,8 @@ static int nand_read_pmecc(struct sam_nandcs_s *priv, off_t block,
#if 0 /* Don't use NFC SRAM */
nand_nfc_cleale(priv,
HSMC_ALE_COL_EN | HSMC_ALE_ROW_EN | HSMC_CLE_VCMD2_EN | HSMC_CLE_DATA_EN,
HSMC_ALE_COL_EN | HSMC_ALE_ROW_EN | HSMC_CLE_VCMD2_EN |
HSMC_CLE_DATA_EN,
COMMAND_READ_1, COMMAND_READ_2, 0, rowaddr);
#else
nand_setup_rbedge(priv);
@@ -1751,11 +1763,13 @@ static int nand_nfcsram_write(struct sam_nandcs_s *priv, uint8_t *buffer,
if (priv->dma && buflen > CONFIG_SAMA5_NAND_DMA_THRESHOLD)
{
DEBUGASSERT(((uintptr_t)buffer & 3) == 0 && ((uintptr_t)dest & 3) == 0);
DEBUGASSERT(((uintptr_t)buffer & 3) == 0 &&
((uintptr_t)dest & 3) == 0);
/* Transfer using DMA */
ret = nand_dma_write(priv, (uintptr_t)buffer, dest, buflen, NFCSRAM_DMA_FLAGS);
ret = nand_dma_write(priv, (uintptr_t)buffer, dest, buflen,
NFCSRAM_DMA_FLAGS);
}
else
#endif
@@ -1894,7 +1908,8 @@ static int nand_readpage_noecc(struct sam_nandcs_s *priv, off_t block,
off_t coladdr;
int ret;
finfo("block=%d page=%d data=%p spare=%p\n", (int)block, page, data, spare);
finfo("block=%d page=%d data=%p spare=%p\n",
(int)block, page, data, spare);
DEBUGASSERT(priv && (data || spare));
/* Get page and spare sizes */
@@ -1933,8 +1948,9 @@ static int nand_readpage_noecc(struct sam_nandcs_s *priv, off_t block,
/* Configure the SMC */
regval |= (HSMC_CFG_RBEDGE | HSMC_CFG_DTOCYC(15) | HSMC_CFG_DTOMUL_1048576 |
HSMC_CFG_NFCSPARESIZE((sparesize - 1) >> 2));
regval |= HSMC_CFG_RBEDGE | HSMC_CFG_DTOCYC(15) |
HSMC_CFG_DTOMUL_1048576 |
HSMC_CFG_NFCSPARESIZE((sparesize - 1) >> 2);
nand_putreg(SAM_HSMC_CFG, regval);
/* Calculate actual address of the page */
@@ -1946,7 +1962,8 @@ static int nand_readpage_noecc(struct sam_nandcs_s *priv, off_t block,
nand_setup_xfrdone(priv);
nand_nfc_cleale(priv,
HSMC_ALE_COL_EN | HSMC_ALE_ROW_EN | HSMC_CLE_VCMD2_EN | HSMC_CLE_DATA_EN,
HSMC_ALE_COL_EN | HSMC_ALE_ROW_EN | HSMC_CLE_VCMD2_EN |
HSMC_CLE_DATA_EN,
COMMAND_READ_1, COMMAND_READ_2, coladdr, rowaddr);
nand_wait_xfrdone(priv);
@@ -1973,7 +1990,8 @@ static int nand_readpage_noecc(struct sam_nandcs_s *priv, off_t block,
ret = nand_nfcsram_read(priv, (uint8_t *)spare, sparesize, offset);
if (ret < 0)
{
ferr("ERROR: nand_nfcsram_read for spare region failed: %d\n", ret);
ferr("ERROR: nand_nfcsram_read for spare region failed: %d\n",
ret);
return ret;
}
}
@@ -2041,6 +2059,7 @@ static int nand_readpage_pmecc(struct sam_nandcs_s *priv, off_t block,
if (regval)
{
/* Bad sectors. Check if this is because spare area has been erased */
/* First, re-read the spare area. REVISIT: Is this necessary? */
ret = nand_readpage_noecc(priv, block, page, NULL, priv->raw.spare);
@@ -2129,7 +2148,8 @@ static int nand_writepage_noecc(struct sam_nandcs_s *priv, off_t block,
off_t rowaddr;
int ret = OK;
finfo("block=%d page=%d data=%p spare=%p\n", (int)block, page, data, spare);
finfo("block=%d page=%d data=%p spare=%p\n",
(int)block, page, data, spare);
/* Get page and spare sizes */
@@ -2167,8 +2187,9 @@ static int nand_writepage_noecc(struct sam_nandcs_s *priv, off_t block,
/* Configure the SMC */
regval |= (HSMC_CFG_RBEDGE | HSMC_CFG_DTOCYC(15) | HSMC_CFG_DTOMUL_1048576 |
HSMC_CFG_NFCSPARESIZE((sparesize - 1) >> 2));
regval |= HSMC_CFG_RBEDGE | HSMC_CFG_DTOCYC(15) |
HSMC_CFG_DTOMUL_1048576 |
HSMC_CFG_NFCSPARESIZE((sparesize - 1) >> 2);
if (spare)
{
@@ -2190,16 +2211,19 @@ static int nand_writepage_noecc(struct sam_nandcs_s *priv, off_t block,
ret = nand_nfcsram_write(priv, (uint8_t *)data, pagesize, 0);
if (ret < 0)
{
ferr("ERROR: nand_nfcsram_write for data region failed: %d\n", ret);
ferr("ERROR: nand_nfcsram_write for data region failed: %d\n",
ret);
return ret;
}
if (spare)
{
ret = nand_nfcsram_write(priv, (uint8_t *)spare, sparesize, pagesize);
ret = nand_nfcsram_write(priv, (uint8_t *)spare, sparesize,
pagesize);
if (ret < 0)
{
ferr("ERROR: nand_nfcsram_write for data region failed: %d\n", ret);
ferr("ERROR: nand_nfcsram_write for data region failed: %d\n",
ret);
return ret;
}
}
@@ -2322,7 +2346,8 @@ static int nand_writepage_pmecc(struct sam_nandcs_s *priv, off_t block,
ret = nand_nfcsram_write(priv, (uint8_t *)data, pagesize, 0);
if (ret < 0)
{
ferr("ERROR: Block %d page %d nand_nfcsram_write for data region failed: %d\n",
ferr("ERROR: Block %d page %d nand_nfcsram_write for data region "
"failed: %d\n",
block, page, ret);
goto errout;
}
@@ -2444,7 +2469,8 @@ static int nand_writepage_pmecc(struct sam_nandcs_s *priv, off_t block,
ret = nand_write(priv, (uint8_t *)g_nand.ecctab, eccsize, 0);
if (ret < 0)
{
ferr("ERROR: Block %d page %d nand_write for spare region failed: %d\n",
ferr("ERROR: Block %d page %d nand_write for spare region "
"failed: %d\n",
block, page, ret);
goto errout;
}
@@ -2968,6 +2994,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
return NULL;
}
#endif
/* Disable all interrupts at the HSMC */
nand_putreg(SAM_HSMC_IDR, HSMC_NFCINT_ALL);
@@ -2981,14 +3008,16 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
}
/* Initialize the NAND hardware for this CS */
/* Perform board-specific SMC initialization for this CS. This should include:
/* Perform board-specific SMC initialization for this CS. This should
* include:
*
* 1. Enabling of clocking to the HSMC
* 2. Configuration of timing for the HSMC NAND CS
* 3. Configuration of PIO pins
*
* Other than enabling the HSMC, these are all things that the board-cognizant
* logic is best prepared to handle.
* Other than enabling the HSMC, these are all things that the board-
* cognizant logic is best prepared to handle.
*/
ret = board_nandflash_config(cs);
@@ -3037,7 +3066,8 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
* Name: nand_checkreg
*
* Description:
* Check if the current HSMC register access is a duplicate of the preceding.
* Check if the current HSMC register access is a duplicate of the
* preceding.
*
* Input Parameters:
* regval - The value to be written
arch/arm/src/sama5/sam_pmecc.c
+91 -47
View File
@@ -72,6 +72,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Number of bits of correction. These much match the (unshifted) values
* in the SMC_PMECCFG register BCH_ERR field.
*/
@@ -89,6 +90,7 @@
/****************************************************************************
* Private Types
****************************************************************************/
/* This is the form of the PMECC descriptor that is passed to the ECC
* detection correction algorithm in ROM. The binary for of this structure
* cannot be altered!
@@ -118,7 +120,8 @@ struct pmecc_desc_s
/* 468-: Sigma table */
int16_t smu[PMECC_MAX_CORRECTABILITY + 2][2 * PMECC_MAX_CORRECTABILITY + 1];
int16_t smu[PMECC_MAX_CORRECTABILITY + 2]
[2 * PMECC_MAX_CORRECTABILITY + 1];
/* Polynomial order */
@@ -142,7 +145,7 @@ struct sam_pmecc_s
/* This is the type of the ROM detection/correction function
*
* REVISIT: Whare are the types Pmecc and Pmerrloc?
* REVISIT: Where are the types Pmecc and Pmerrloc?
*/
#ifdef CONFIG_SAMA5_PMECC_EMBEDDEDALGO
@@ -165,13 +168,19 @@ static uint32_t pmecc_correctionalgo(uint32_t isr, uintptr_t data);
/****************************************************************************
* Private Data
****************************************************************************/
/* PMECC state data */
static struct sam_pmecc_s g_pmecc;
/* Maps BCH_ERR correctability register value to number of errors per sector */
/* Maps BCH_ERR correctability register value to number of errors per
* sector.
*/
static const uint8_t g_correctability[5] = {2, 4, 8, 12, 24};
static const uint8_t g_correctability[5] =
{
2, 4, 8, 12, 24
};
/****************************************************************************
* Private Functions
@@ -243,6 +252,7 @@ static uint32_t pmecc_substitute(void)
}
/* Computation 2t syndromes based on S(x) */
/* Odd syndromes */
for (i = 1; i <= 2 * g_pmecc.desc.tt - 1; i = i + 2)
@@ -298,9 +308,9 @@ static uint32_t pmecc_getsigma(void)
int16_t *lmu = g_pmecc.desc.lmu;
int16_t *si = g_pmecc.desc.si;
int16_t tt = g_pmecc.desc.tt;
int32_t mu[PMECC_MAX_CORRECTABILITY+1]; /* Mu */
int32_t dmu[PMECC_MAX_CORRECTABILITY+1]; /* Discrepancy */
int32_t delta[PMECC_MAX_CORRECTABILITY+1]; /* Delta order */
int32_t mu[PMECC_MAX_CORRECTABILITY + 1]; /* Mu */
int32_t dmu[PMECC_MAX_CORRECTABILITY + 1]; /* Discrepancy */
int32_t delta[PMECC_MAX_CORRECTABILITY + 1]; /* Delta order */
int32_t largest;
int32_t diff;
int ro; /* Index of largest delta */
@@ -311,6 +321,7 @@ static uint32_t pmecc_getsigma(void)
dmu0count = 0;
/* First Row */
/* Mu */
mu[0] = -1; /* Actually -1/2 */
@@ -337,6 +348,7 @@ static uint32_t pmecc_getsigma(void)
delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
/* Second row */
/* Mu */
mu[1] = 0;
@@ -371,10 +383,11 @@ static uint32_t pmecc_getsigma(void)
for (i = 1; i <= tt; i++)
{
mu[i+1] = i << 1;
mu[i + 1] = i << 1;
/* Compute Sigma (Mu+1) and L(mu). */
/* check if discrepancy is set to 0 */
/* Check if discrepancy is set to 0 */
if (dmu[i] == 0)
{
@@ -385,8 +398,9 @@ static uint32_t pmecc_getsigma(void)
{
for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
{
g_pmecc.desc.smu[tt+1][j] = g_pmecc.desc.smu[i][j];
g_pmecc.desc.smu[tt + 1][j] = g_pmecc.desc.smu[i][j];
}
lmu[tt + 1] = lmu[i];
return 0;
}
@@ -399,6 +413,7 @@ static uint32_t pmecc_getsigma(void)
{
g_pmecc.desc.smu[tt + 1][j] = g_pmecc.desc.smu[i][j];
}
lmu[tt + 1] = lmu[i];
return 0;
}
@@ -451,9 +466,9 @@ static uint32_t pmecc_getsigma(void)
/* Init smu[i+1] with 0 */
for (k = 0; k < (2 * PMECC_MAX_CORRECTABILITY+1); k ++)
for (k = 0; k < (2 * PMECC_MAX_CORRECTABILITY + 1); k ++)
{
g_pmecc.desc.smu[i+1][k] = 0;
g_pmecc.desc.smu[i + 1][k] = 0;
}
/* Compute smu[i+1] */
@@ -465,17 +480,19 @@ static uint32_t pmecc_getsigma(void)
g_pmecc.desc.smu[i + 1][k + diff] =
g_pmecc.desc.alphato[(g_pmecc.desc.indexof[dmu[i]] +
(g_pmecc.desc.nn - g_pmecc.desc.indexof[dmu[ro]]) +
g_pmecc.desc.indexof[g_pmecc.desc.smu[ro][k]]) % g_pmecc.desc.nn];
g_pmecc.desc.indexof[g_pmecc.desc.smu[ro][k]]) %
g_pmecc.desc.nn];
}
}
for (k = 0; k <= lmu[i] >> 1; k++)
{
g_pmecc.desc.smu[i+1][k] ^= g_pmecc.desc.smu[i][k];
g_pmecc.desc.smu[i + 1][k] ^= g_pmecc.desc.smu[i][k];
}
}
/* End Compute Sigma (Mu+1) and L(mu) */
/* In either case compute delta */
delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
@@ -491,13 +508,18 @@ static uint32_t pmecc_getsigma(void)
dmu[i + 1] = si[2 * (i - 1) + 3];
}
/* Check if one operand of the multiplier is null, its index is -1 */
/* Check if one operand of the multiplier is null, its index
* is -1
*/
else if (g_pmecc.desc.smu[i + 1][k] && si[2 * (i - 1) + 3 - k])
else if (g_pmecc.desc.smu[i + 1][k] &&
si[2 * (i - 1) + 3 - k])
{
dmu[i + 1] =
g_pmecc.desc.alphato[(g_pmecc.desc.indexof[g_pmecc.desc.smu[i + 1][k]] +
g_pmecc.desc.indexof[si[2 * (i - 1) + 3 - k]]) % g_pmecc.desc.nn] ^ dmu[i + 1];
g_pmecc.desc.alphato[
(g_pmecc.desc.indexof[g_pmecc.desc.smu[i + 1][k]] +
g_pmecc.desc.indexof[si[2 * (i - 1) + 3 - k]]) %
g_pmecc.desc.nn] ^ dmu[i + 1];
}
}
}
@@ -637,22 +659,27 @@ static uint32_t pmecc_errorcorrection(uintptr_t sectorbase,
if (*(uint8_t *)(sectorbase + bytepos) & (1 << bitpos))
{
*(uint8_t *)(sectorbase + bytepos) &= (0xff ^ (1 << bitpos));
*(uint8_t *)(sectorbase + bytepos) &=
(0xff ^ (1 << bitpos));
}
else
{
*(uint8_t *)(sectorbase + bytepos) |= (1 << bitpos);
*(uint8_t *)(sectorbase + bytepos) |=
(1 << bitpos);
}
}
else
{
if (*(uint8_t *)(sectorbase + bytepos + eccsize) & (1 << bitpos))
if (*(uint8_t *)(sectorbase + bytepos + eccsize) &
(1 << bitpos))
{
*(uint8_t *)(sectorbase + bytepos + eccsize) &= (0xff ^ (1 << bitpos));
*(uint8_t *)(sectorbase + bytepos + eccsize) &=
(0xff ^ (1 << bitpos));
}
else
{
*(uint8_t *)(sectorbase + bytepos + eccsize) |= (1 << bitpos);
*(uint8_t *)(sectorbase + bytepos + eccsize) |=
(1 << bitpos);
}
}
}
@@ -721,7 +748,8 @@ static uint32_t pmecc_correctionalgo(uint32_t isr, uintptr_t data)
/* Number of bits of the sector + ecc */
nerrors = pmecc_errorlocation((sectorsz * 8) + (g_pmecc.desc.tt * mm));
nerrors = pmecc_errorlocation((sectorsz * 8) +
(g_pmecc.desc.tt * mm));
if (nerrors == -1)
{
return 1;
@@ -850,7 +878,7 @@ static int pmecc_bcherr1k(uint8_t nsectors, uint16_t eccsize)
static int pmecc_pagelayout(uint16_t datasize, uint16_t eccsize)
{
uint16_t correctability512;
uint16_t correctability1K;
uint16_t correctability1k;
uint8_t nsectors512;
uint8_t nsectors1k;
uint8_t bcherr;
@@ -922,11 +950,11 @@ static int pmecc_pagelayout(uint16_t datasize, uint16_t eccsize)
case 3: /* Both 512B and 1KB sectors possible */
{
correctability512 = nsectors512 * g_correctability[bcherr512];
correctability1K = nsectors1k * g_correctability[bcherr1k];
correctability1k = nsectors1k * g_correctability[bcherr1k];
/* Use 512B sectors unless we can do better with 1K sectors */
if (correctability512 >= correctability1K)
if (correctability512 >= correctability1k)
{
g_pmecc.sector1k = false;
g_pmecc.nsectors = nsectors512;
@@ -1072,12 +1100,18 @@ int pmecc_configure(struct sam_nandcs_s *priv, bool protected)
g_pmecc.desc.sectorsz = HSMC_PMECCFG_SECTORSZ_1024;
sectorsperpage = (priv->raw.model.pagesize >> 10);
g_pmecc.desc.mm = 14;
#if defined (CONFIG_SAMA5_PMECC_GALOIS_TABLE1024_ROMADDR) && defined (CONFIG_SAMA5_PMECC_GALOIS_ROMTABLES)
g_pmecc.desc.alphato = (int16_t *)&(pmecc_gf1024[PMECC_GF_SIZEOF_1024]);
g_pmecc.desc.indexof = (int16_t *)&(pmecc_gf1024[0]);
#if defined (CONFIG_SAMA5_PMECC_GALOIS_TABLE1024_ROMADDR) && \
defined (CONFIG_SAMA5_PMECC_GALOIS_ROMTABLES)
g_pmecc.desc.alphato =
(int16_t *)&(pmecc_gf1024[PMECC_GF_SIZEOF_1024]);
g_pmecc.desc.indexof =
(int16_t *)&(pmecc_gf1024[0]);
#else
g_pmecc.desc.alphato = (int16_t *)&(pmecc_gf1024[PMECC_GF_ALPHA_TO]);
g_pmecc.desc.indexof = (int16_t *)&(pmecc_gf1024[PMECC_GF_INDEX_OF]);
g_pmecc.desc.alphato =
(int16_t *)&(pmecc_gf1024[PMECC_GF_ALPHA_TO]);
g_pmecc.desc.indexof =
(int16_t *)&(pmecc_gf1024[PMECC_GF_INDEX_OF]);
#endif
}
else
@@ -1087,12 +1121,18 @@ int pmecc_configure(struct sam_nandcs_s *priv, bool protected)
g_pmecc.desc.sectorsz = HSMC_PMECCFG_SECTORSZ_512;
sectorsperpage = (priv->raw.model.pagesize >> 9);
g_pmecc.desc.mm = 13;
#if defined (CONFIG_SAMA5_PMECC_GALOIS_TABLE512_ROMADDR) && defined (CONFIG_SAMA5_PMECC_GALOIS_ROMTABLES)
g_pmecc.desc.alphato = (int16_t *)&(pmecc_gf512[PMECC_GF_SIZEOF_512]);
g_pmecc.desc.indexof = (int16_t *)&(pmecc_gf512[0]);
#if defined (CONFIG_SAMA5_PMECC_GALOIS_TABLE512_ROMADDR) && \
defined (CONFIG_SAMA5_PMECC_GALOIS_ROMTABLES)
g_pmecc.desc.alphato =
(int16_t *)&(pmecc_gf512[PMECC_GF_SIZEOF_512]);
g_pmecc.desc.indexof =
(int16_t *)&(pmecc_gf512[0]);
#else
g_pmecc.desc.alphato = (int16_t *)&(pmecc_gf512[PMECC_GF_ALPHA_TO]);
g_pmecc.desc.indexof = (int16_t *)&(pmecc_gf512[PMECC_GF_INDEX_OF]);
g_pmecc.desc.alphato =
(int16_t *)&(pmecc_gf512[PMECC_GF_ALPHA_TO]);
g_pmecc.desc.indexof =
(int16_t *)&(pmecc_gf512[PMECC_GF_INDEX_OF]);
#endif
}
@@ -1133,7 +1173,8 @@ int pmecc_configure(struct sam_nandcs_s *priv, bool protected)
else
{
g_pmecc.desc.eccsize =
(((g_pmecc.desc.mm * g_pmecc.correctability) >> 3) + 1) * sectorsperpage;
(((g_pmecc.desc.mm * g_pmecc.correctability) >> 3) + 1) *
sectorsperpage;
}
finfo("mm=%d correctability=%d eccsize=%d\n",
@@ -1162,8 +1203,11 @@ int pmecc_configure(struct sam_nandcs_s *priv, bool protected)
g_pmecc.desc.sparesize = priv->raw.model.sparesize;
//g_pmecc.desc.nandwr = PMECC_CFG_NANDWR; /* NAND write access */
g_pmecc.desc.nandwr = 0; /* NAND Read access */
#if 0
g_pmecc.desc.nandwr = PMECC_CFG_NANDWR; /* NAND write access */
#else
g_pmecc.desc.nandwr = 0; /* NAND Read access */
#endif
if (protected)
{
g_pmecc.desc.sparena = HSMC_PMECCFG_SPARE_ENABLE;
@@ -1185,7 +1229,7 @@ int pmecc_configure(struct sam_nandcs_s *priv, bool protected)
g_pmecc.desc.clkctrl = 2;
g_pmecc.desc.interrupt = 0;
/* Disable ECC module */
/* Disable ECC module */
nand_putreg(SAM_HSMC_PMECCTRL, HSMC_PMECCTRL_DISABLE);
@@ -1283,8 +1327,9 @@ void pmecc_unlock(void)
int pmecc_correction(uint32_t isr, uintptr_t data)
{
#ifdef CONFIG_SAMA5_PMECC_EMBEDDEDALGO
/* REVISIT: Whare are the types Pmecc and Pmerrloc? */
/* REVISIT: Check returned value */
/* REVISIT: Whare are the types Pmecc and Pmerrloc?
* REVISIT: Check returned value
*/
return pmecc_correctionalgo(??, ??, &g_pmecc, isr, data);
#else
@@ -1458,22 +1503,21 @@ void pmecc_buildgf(uint32_t mm, int16_t *indexof, int16_t *alphato)
{
/* Check if the msb bit of the lfsr is set */
if (alphato[i-1] & mask)
if (alphato[i - 1] & mask)
{
/* Feedback loop is set */
alphato[i] = alphato[mm] ^ ((alphato[i-1] ^ mask) << 1);
alphato[i] = alphato[mm] ^ ((alphato[i - 1] ^ mask) << 1);
}
else
{
/* Only shift is enabled */
alphato[i] = alphato[i-1] << 1;
alphato[i] = alphato[i - 1] << 1;
}
/* lookup table */
//indexof[alphato[i]] = i;
indexof[alphato[i]] = i % nn;
}
arch/arm/src/samv7/sam_mcan.c
+149 -105
View File
File diff suppressed because it is too large Load Diff