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Add initial ESP32S2 Xtensa support

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This commit is contained in:
Alan C. Assis
2021-05-20 17:07:54 -03:00
committed by Alin Jerpelea
parent 85f9b893b2
commit 7767acd24a
58 changed files with 52163 additions and 3 deletions
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arch/xtensa/Kconfig
+39
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@@ -37,6 +37,32 @@ config ARCH_CHIP_ESP32
"application"), however for most purposes the two CPUs are
interchangeable.
config ARCH_CHIP_ESP32S2
bool "Espressif ESP32-S2"
select ARCH_FAMILY_LX7
select XTENSA_HAVE_INTERRUPTS
select ARCH_HAVE_MODULE_TEXT
select ARCH_HAVE_SDRAM
select ARCH_HAVE_RESET
select ARCH_TOOLCHAIN_GNU
select ARCH_VECNOTIRQ
select LIBC_ARCH_MEMCPY
select LIBC_ARCH_MEMCHR
select LIBC_ARCH_MEMCMP
select LIBC_ARCH_MEMCCMP
select LIBC_ARCH_MEMMOVE
select LIBC_ARCH_MEMSET
select LIBC_ARCH_STRCHR
select LIBC_ARCH_STRCMP
select LIBC_ARCH_STRCPY
select LIBC_ARCH_STRLCPY
select LIBC_ARCH_STRNCPY
select LIBC_ARCH_STRLEN
select LIBC_ARCH_STRNLEN
---help---
The ESP32-S2 is a dual-core system from Espressif with a
Harvard architecture Xtensa LX7 CPU.
config ARCH_CHIP_XTENSA_CUSTOM
bool "Custom XTENSA chip"
select ARCH_CHIP_CUSTOM
@@ -53,9 +79,17 @@ config ARCH_FAMILY_LX6
Cadence® Tensilica® Xtensa® LX6 data plane processing unit (DPU).
The LX6 is a configurable and extensible processor core.
config ARCH_FAMILY_LX7
bool
default n
---help---
Cadence® Tensilica® Xtensa® LX7 data plane processing unit (DPU).
The LX7 is a configurable and extensible processor core.
config ARCH_CHIP
string
default "esp32" if ARCH_CHIP_ESP32
default "esp32s2" if ARCH_CHIP_ESP32S2
config XTENSA_CP_LAZY
bool "Lazy co-processor state restoration"
@@ -143,4 +177,9 @@ if ARCH_CHIP_ESP32
source arch/xtensa/src/esp32/Kconfig
endif
source arch/xtensa/src/lx7/Kconfig
if ARCH_CHIP_ESP32S2
source arch/xtensa/src/esp32s2/Kconfig
endif
endif # ARCH_XTENSA
arch/xtensa/include/esp32s2/chip.h
+74
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@@ -0,0 +1,74 @@
/****************************************************************************
* arch/xtensa/include/esp32s2/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_INCLUDE_ESP32S2_CHIP_H
#define __ARCH_XTENSA_INCLUDE_ESP32S2_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Characterize each supported ESP32S2 part */
#define ESP32S2_NDAC 2 /* DAC0-1 */
#define ESP32S2_NI2C 1 /* I2C0 */
#define ESP32S2_NI2S 1 /* I2S0 */
#define ESP32S2_NLCD 1 /* LCD0 */
#define ESP32S2_NSPI 4 /* SPI0-3 */
#define ESP32S2_NUARTS 2 /* UART0-1 */
#define ESP32S2_NUSBOTG 1 /* USB OTG */
#define ESP32S2_NGPIOS 46 /* GPIO0-45 */
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_INCLUDE_ESP32S2_CHIP_H */
arch/xtensa/include/esp32s2/core-isa.h
+738
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File diff suppressed because it is too large Load Diff
arch/xtensa/include/esp32s2/irq.h
+495
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@@ -0,0 +1,495 @@
/****************************************************************************
* arch/xtensa/include/esp32s2/irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_XTENSA_INCLUDE_ESP32S2_IRQ_H
#define __ARCH_XTENSA_INCLUDE_ESP32S2_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch/esp32s2/chip.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Interrupt Matrix
*
* Features
* - Accepts 95 peripheral interrupt sources as input.
* - Generates 26 peripheral interrupt sources as output.
* - CPU NMI Interrupt Mask.
* - Queries current interrupt status of peripheral interrupt sources.
*
* Peripheral Interrupt Source
*
* ESP32S2 has 95 peripheral interrupt sources in total. 67 of 71 ESP32S2
* peripheral interrupt sources can be allocated to either CPU. The four
* remaining peripheral interrupt sources are CPU-specific, two per CPU.
*
* - GPIO_INTERRUPT_PRO and GPIO_INTERRUPT_PRO_NMI can only be allocated to
* PRO_CPU.
* - GPIO_INTERRUPT_APP and GPIO_INTERRUPT_APP_NMI can only be allocated to
* APP_CPU.
*
* As a result, PRO_CPU and APP_CPU each have 69 peripheral interrupt
* sources.
*/
/* PRO_INTR_STATUS_REG_0 */
#define ESP32S2_PERI_MAC 0 /* INTR_STATUS_REG_0, bit 0 */
#define ESP32S2_PERI_MAC_NMI 1 /* INTR_STATUS_REG_0, bit 1 */
#define ESP32S2_PERI_PWR 2 /* INTR_STATUS_REG_0, bit 2 */
#define ESP32S2_PERI_BB 3 /* INTR_STATUS_REG_0, bit 3 */
#define ESP32S2_PERI_BT_MAC 4 /* INTR_STATUS_REG_0, bit 4 */
#define ESP32S2_PERI_BT_BB 5 /* INTR_STATUS_REG_0, bit 5 */
#define ESP32S2_PERI_BT_BB_NMI 6 /* INTR_STATUS_REG_0, bit 6 */
#define ESP32S2_PERI_RWBT 7 /* INTR_STATUS_REG_0, bit 7 */
#define ESP32S2_PERI_RWBLE 8 /* INTR_STATUS_REG_0, bit 8 */
#define ESP32S2_PERI_RWBT_NMI 9 /* INTR_STATUS_REG_0, bit 9 */
#define ESP32S2_PERI_RWBLE_NMI 10 /* INTR_STATUS_REG_0, bit 10 */
#define ESP32S2_PERI_SLC0 11 /* INTR_STATUS_REG_0, bit 11 */
#define ESP32S2_PERI_SLC1 12 /* INTR_STATUS_REG_0, bit 12 */
#define ESP32S2_PERI_UHCI0 13 /* INTR_STATUS_REG_0, bit 13 */
#define ESP32S2_PERI_UHCI1 14 /* INTR_STATUS_REG_0, bit 14 */
#define ESP32S2_PERI_TG_T0_LEVEL 15 /* INTR_STATUS_REG_0, bit 15 */
#define ESP32S2_PERI_TG_T1_LEVEL 16 /* INTR_STATUS_REG_0, bit 16 */
#define ESP32S2_PERI_TG_WDT_LEVEL 17 /* INTR_STATUS_REG_0, bit 17 */
#define ESP32S2_PERI_TG_LACT_LEVEL 18 /* INTR_STATUS_REG_0, bit 18 */
#define ESP32S2_PERI_TG1_T0_LEVEL 19 /* INTR_STATUS_REG_0, bit 19 */
#define ESP32S2_PERI_TG1_T1_LEVEL 20 /* INTR_STATUS_REG_0, bit 20 */
#define ESP32S2_PERI_TG1_WDT_LEVEL 21 /* INTR_STATUS_REG_0, bit 21 */
#define ESP32S2_PERI_TG1_LACT_LEVEL 22 /* INTR_STATUS_REG_0, bit 22 */
#define ESP32S2_PERI_GPIO_INT_PRO 23 /* INTR_STATUS_REG_0, bit 23 */
#define ESP32S2_PERI_GPIO_INT_PRO_NMI 24 /* INTR_STATUS_REG_0, bit 24 */
#define ESP32S2_PERI_GPIO_INT_APP 25 /* INTR_STATUS_REG_0, bit 25 */
#define ESP32S2_PERI_GPIO_INT_APP_NMI 26 /* INTR_STATUS_REG_0, bit 26 */
#define ESP32S2_PERI_DEDICATED_GPIO_IN 27 /* INTR_STATUS_REG_0, bit 27 */
#define ESP32S2_PERI_INT_FROM_CPU0 28 /* INTR_STATUS_REG_0, bit 28 */
#define ESP32S2_PERI_INT_FROM_CPU1 29 /* INTR_STATUS_REG_0, bit 29 */
#define ESP32S2_PERI_INT_FROM_CPU2 30 /* INTR_STATUS_REG_0, bit 30 */
#define ESP32S2_PERI_INT_FROM_CPU3 31 /* INTR_STATUS_REG_0, bit 31 */
/* PRO_INTR_STATUS_REG_1 */
#define ESP32S2_PERI_SPI1 32 /* INTR_STATUS_REG_1, bit 0 */
#define ESP32S2_PERI_SPI2 33 /* INTR_STATUS_REG_1, bit 1 */
#define ESP32S2_PERI_SPI3 34 /* INTR_STATUS_REG_1, bit 2 */
#define ESP32S2_PERI_I2S0 35 /* INTR_STATUS_REG_1, bit 3 */
#define ESP32S2_PERI_I2S1 36 /* INTR_STATUS_REG_1, bit 4 */
#define ESP32S2_PERI_UART 37 /* INTR_STATUS_REG_1, bit 5 */
#define ESP32S2_PERI_UART1 38 /* INTR_STATUS_REG_1, bit 6 */
#define ESP32S2_PERI_UART2 39 /* INTR_STATUS_REG_1, bit 7 */
#define ESP32S2_PERI_SDIO_HOST 40 /* INTR_STATUS_REG_1, bit 8 */
#define ESP32S2_PERI_PWM0 41 /* INTR_STATUS_REG_1, bit 9 */
#define ESP32S2_PERI_PWM1 42 /* INTR_STATUS_REG_1, bit 10 */
#define ESP32S2_PERI_PWM2 43 /* INTR_STATUS_REG_1, bit 11 */
#define ESP32S2_PERI_PWM3 44 /* INTR_STATUS_REG_1, bit 12 */
#define ESP32S2_PERI_LEDC 45 /* INTR_STATUS_REG_1, bit 13 */
#define ESP32S2_PERI_EFUSE 46 /* INTR_STATUS_REG_1, bit 14 */
#define ESP32S2_PERI_CAN 47 /* INTR_STATUS_REG_1, bit 15 */
#define ESP32S2_PERI_USB 48 /* INTR_STATUS_REG_1, bit 16 */
#define ESP32S2_PERI_RTC_CORE 49 /* INTR_STATUS_REG_1, bit 17 */
#define ESP32S2_PERI_RMT 50 /* INTR_STATUS_REG_1, bit 18 */
#define ESP32S2_PERI_PCNT 51 /* INTR_STATUS_REG_1, bit 19 */
#define ESP32S2_PERI_I2C_EXT0 52 /* INTR_STATUS_REG_1, bit 20 */
#define ESP32S2_PERI_I2C_EXT1 53 /* INTR_STATUS_REG_1, bit 21 */
#define ESP32S2_PERI_RSA 54 /* INTR_STATUS_REG_1, bit 22 */
#define ESP32S2_PERI_SHA 55 /* INTR_STATUS_REG_1, bit 23 */
#define ESP32S2_PERI_AES 56 /* INTR_STATUS_REG_1, bit 24 */
#define ESP32S2_PERI_SPI2_DMA 57 /* INTR_STATUS_REG_1, bit 25 */
#define ESP32S2_PERI_SPI3_DMA 58 /* INTR_STATUS_REG_1, bit 26 */
#define ESP32S2_PERI_WDG 59 /* INTR_STATUS_REG_1, bit 27 */
#define ESP32S2_PERI_TIMER 60 /* INTR_STATUS_REG_1, bit 28 */
#define ESP32S2_PERI_TIMER_INT2 61 /* INTR_STATUS_REG_1, bit 29 */
#define ESP32S2_PERI_TG_T0_EDGE 62 /* INTR_STATUS_REG_1, bit 30 */
#define ESP32S2_PERI_TG_T1_EDGE 63 /* INTR_STATUS_REG_1, bit 31 */
/* PRO_INTR_STATUS_REG_2 */
#define ESP32S2_PERI_TG_WDT_EDGE 64 /* INTR_STATUS_REG_2, bit 0 */
#define ESP32S2_PERI_TG_LACT_EDGE 65 /* INTR_STATUS_REG_2, bit 1 */
#define ESP32S2_PERI_TG1_T0_EDGE 66 /* INTR_STATUS_REG_2, bit 2 */
#define ESP32S2_PERI_TG1_T1_EDGE 67 /* INTR_STATUS_REG_2, bit 3 */
#define ESP32S2_PERI_TG1_WDT_EDGE 68 /* INTR_STATUS_REG_2, bit 4 */
#define ESP32S2_PERI_TG1_LACT_EDGE 69 /* INTR_STATUS_REG_2, bit 5 */
#define ESP32S2_PERI_CACHE_IA 70 /* INTR_STATUS_REG_2, bit 6 */
#define ESP32S2_PERI_SYSTIMER_TARGET0 71 /* INTR_STATUS_REG_2, bit 7 */
#define ESP32S2_PERI_SYSTIMER_TARGET1 72 /* INTR_STATUS_REG_2, bit 8 */
#define ESP32S2_PERI_SYSTIMER_TARGET2 73 /* INTR_STATUS_REG_2, bit 9 */
#define ESP32S2_PERI_ASSIST_DEBUG 74 /* INTR_STATUS_REG_2, bit 10 */
#define ESP32S2_PERI_PMS_PRO_IRAM0_ILG 75 /* INTR_STATUS_REG_2, bit 11 */
#define ESP32S2_PERI_PMS_PRO_DRAM0_ILG 76 /* INTR_STATUS_REG_2, bit 12 */
#define ESP32S2_PERI_PMS_PRO_DPORT_ILG 77 /* INTR_STATUS_REG_2, bit 13 */
#define ESP32S2_PERI_PMS_PRO_AHB_ILG 78 /* INTR_STATUS_REG_2, bit 14 */
#define ESP32S2_PERI_PMS_PRO_CACHE_ILG 79 /* INTR_STATUS_REG_2, bit 15 */
#define ESP32S2_PERI_PMS_DMA_APB_I_ILG 80 /* INTR_STATUS_REG_2, bit 16 */
#define ESP32S2_PERI_PMS_DMA_RX_I_ILG 81 /* INTR_STATUS_REG_2, bit 17 */
#define ESP32S2_PERI_PMS_DMA_TX_I_ILG 82 /* INTR_STATUS_REG_2, bit 18 */
#define ESP32S2_PERI_SPI_MEM_REJECT 83 /* INTR_STATUS_REG_2, bit 19 */
#define ESP32S2_PERI_DMA_COPY 84 /* INTR_STATUS_REG_2, bit 20 */
#define ESP32S2_PERI_SPI4_DMA 85 /* INTR_STATUS_REG_2, bit 21 */
#define ESP32S2_PERI_SPI4 86 /* INTR_STATUS_REG_2, bit 22 */
#define ESP32S2_PERI_DCACHE_PRELOAD 87 /* INTR_STATUS_REG_2, bit 23 */
#define ESP32S2_PERI_ICACHE_PRELOAD 88 /* INTR_STATUS_REG_2, bit 24 */
#define ESP32S2_PERI_APB_ADC 89 /* INTR_STATUS_REG_2, bit 25 */
#define ESP32S2_PERI_CRYPTO_DMA 90 /* INTR_STATUS_REG_2, bit 26 */
#define ESP32S2_PERI_CPU_PERI_ERR 91 /* INTR_STATUS_REG_2, bit 27 */
#define ESP32S2_PERI_APB_PERI_ERR 92 /* INTR_STATUS_REG_2, bit 28 */
#define ESP32S2_PERI_DCACHE_SYNC 93 /* INTR_STATUS_REG_2, bit 29 */
#define ESP32S2_PERI_ICACHE_SYNC 94 /* INTR_STATUS_REG_2, bit 29 */
/* Total number of peripherals */
#define ESP32S2_NPERIPHERALS 95
/* Exceptions
*
* IRAM Offset Description
* 0x0000 Windows
* 0x0180 Level 2 interrupt
* 0x01c0 Level 3 interrupt
* 0x0200 Level 4 interrupt
* 0x0240 Level 5 interrupt
* 0x0280 Debug exception
* 0x02c0 NMI exception
* 0x0300 Kernel exception
* 0x0340 User exception
* 0x03c0 Double exception
*
* REVISIT: In more architectures supported by NuttX, exception errors
* tie into the normal interrupt handling via special IRQ numbers.
* It is still to be determined what will be done for the ESP32S2.
*
*/
/* IRQ numbers for internal interrupts that are dispatched like peripheral
* interrupts
*/
#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_NIRQ_INTERNAL 4 /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_FIRSTPERI 4 /* First peripheral IRQ number */
/* IRQ numbers for peripheral interrupts coming through the Interrupt
* Matrix.
*/
#define ESP32S2_IRQ2PERIPH(irq) ((irq)-XTENSA_IRQ_FIRSTPERI)
/* PRO_INTR_STATUS_REG_0 */
#define ESP32S2_IRQ_MAC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_MAC)
#define ESP32S2_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_MAC_NMI)
#define ESP32S2_IRQ_PWR (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWR)
#define ESP32S2_IRQ_BB (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_BB)
#define ESP32S2_IRQ_BT_MAC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_BT_MAC)
#define ESP32S2_IRQ_BT_BB (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_BB)
#define ESP32S2_IRQ_BT_BB_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_BB_NMI)
#define ESP32S2_IRQ_RWBT (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RWBT)
#define ESP32S2_IRQ_RWBLE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RWBLE)
#define ESP32S2_IRQ_RWBT_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RWBT_NMI)
#define ESP32S2_IRQ_RWBLE_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RWBLE_NMI)
#define ESP32S2_IRQ_SLC0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SLC0)
#define ESP32S2_IRQ_SLC1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SLC1)
#define ESP32S2_IRQ_UHCI0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UHCI0)
#define ESP32S2_IRQ_UHCI1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UHCI1)
#define ESP32S2_IRQ_TG_T0_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_T0_LEVEL)
#define ESP32S2_IRQ_TG_T1_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_T1_LEVEL)
#define ESP32S2_IRQ_TG_WDT_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_WDT_LEVEL)
#define ESP32S2_IRQ_TG_LACT_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_LACT_LEVEL)
#define ESP32S2_IRQ_TG1_T0_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_T0_LEVEL)
#define ESP32S2_IRQ_TG1_T1_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_T1_LEVEL)
#define ESP32S2_IRQ_TG1_WDT_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_WDT_LEVEL)
#define ESP32S2_IRQ_TG1_LACT_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_LACT_LEVEL)
#define ESP32S2_IRQ_GPIO_INT_PRO (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_GPIO_INT_PRO)
#define ESP32S2_IRQ_GPIO_INT_PRO_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_GPIO_INT_PRO_NMI)
#define ESP32S2_IRQ_GPIO_INT_APP (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_GPIO_INT_APP)
#define ESP32S2_IRQ_GPIO_INT_APP_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_GPIO_INT_APP_NMI)
#define ESP32S2_IRQ_DEDICATED_GPIO_IN (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_DEDICATED_GPIO_IN)
#define ESP32S2_IRQ_INT_FROM_CPU0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_INT_FROM_CPU0
#define ESP32S2_IRQ_INT_FROM_CPU1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_INT_FROM_CPU1)
#define ESP32S2_IRQ_INT_FROM_CPU2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_INT_FROM_CPU2)
#define ESP32S2_IRQ_INT_FROM_CPU3 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_INT_FROM_CPU3)
#define ESP32_IRQ_SREG0 ESP32S2_IRQ_MAC
#define ESP32_NIRQS_SREG0 32
/* PRO_INTR_STATUS_REG_1 */
#define ESP32S2_IRQ_SPI1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI1)
#define ESP32S2_IRQ_SPI2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI2)
#define ESP32S2_IRQ_SPI3 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI3)
#define ESP32S2_IRQ_I2S0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_I2S0)
#define ESP32S2_IRQ_I2S1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_I2S1)
#define ESP32S2_IRQ_UART (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UART)
#define ESP32S2_IRQ_UART1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UART1)
#define ESP32S2_IRQ_UART2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UART2)
#define ESP32S2_IRQ_SDIO_HOST (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SDIO_HOST)
#define ESP32S2_IRQ_PWM0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWM0)
#define ESP32S2_IRQ_PWM1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWM1)
#define ESP32S2_IRQ_PWM2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWM2)
#define ESP32S2_IRQ_PWM3 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWM3)
#define ESP32S2_IRQ_LEDC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_LEDC)
#define ESP32S2_IRQ_EFUSE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_EFUSE)
#define ESP32S2_IRQ_CAN (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_CAN)
#define ESP32S2_IRQ_USB (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_USB)
#define ESP32S2_IRQ_RTC_CORE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RTC_CORE)
#define ESP32S2_IRQ_RMT (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RMT)
#define ESP32S2_IRQ_PCNT (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PCNT)
#define ESP32S2_IRQ_I2C_EXT0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_I2C_EXT0)
#define ESP32S2_IRQ_I2C_EXT1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_I2C_EXT1)
#define ESP32S2_IRQ_RSA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RSA)
#define ESP32S2_IRQ_SHA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SHA)
#define ESP32S2_IRQ_AES (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_AES)
#define ESP32S2_IRQ_SPI2_DMA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI2_DMA)
#define ESP32S2_IRQ_SPI3_DMA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI3_DMA)
#define ESP32S2_IRQ_WDG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_WDG)
#define ESP32S2_IRQ_TIMER (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TIMER)
#define ESP32S2_IRQ_TIMER_INT2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TIMER_INT2)
#define ESP32S2_IRQ_TG_T0_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_T0_EDGE)
#define ESP32S2_IRQ_TG_T1_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_T1_EDGE)
#define ESP32S2_IRQ_SREG1 ESP32S2_IRQ_SPI1
#define ESP32S2_NIRQS_SREG1 32
/* PRO_INTR_STATUS_REG_2 */
#define ESP32S2_IRQ_TG_WDT_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_WDT_EDGE)
#define ESP32S2_IRQ_TG_LACT_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_LACT_EDGE)
#define ESP32S2_IRQ_TG1_T0_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_T0_EDGE)
#define ESP32S2_IRQ_TG1_T1_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_T1_EDGE)
#define ESP32S2_IRQ_TG1_WDT_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_WDT_EDGE)
#define ESP32S2_IRQ_TG1_LACT_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_LACT_EDGE)
#define ESP32S2_IRQ_CACHE_IA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_CACHE_IA)
#define ESP32S2_IRQ_SYSTIMER_TARGET0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SYSTIMER_TARGET0)
#define ESP32S2_IRQ_SYSTIMER_TARGET1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SYSTIMER_TARGET1)
#define ESP32S2_IRQ_SYSTIMER_TARGET2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SYSTIMER_TARGET2)
#define ESP32S2_IRQ_ASSIST_DEBUG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_ASSIST_DEBUG)
#define ESP32S2_IRQ_PMS_PRO_IRAM0_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_IRAM0_ILG)
#define ESP32S2_IRQ_PMS_PRO_DRAM0_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_DRAM0_ILG)
#define ESP32S2_IRQ_PMS_PRO_DPORT_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_DPORT_ILG)
#define ESP32S2_IRQ_PMS_PRO_AHB_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_AHB_ILG)
#define ESP32S2_IRQ_PMS_PRO_CACHE_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_CACHE_ILG)
#define ESP32S2_IRQ_PMS_DMA_APB_I_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_DMA_APB_I_ILG)
#define ESP32S2_IRQ_PMS_DMA_RX_I_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_DMA_RX_I_ILG)
#define ESP32S2_IRQ_PMS_DMA_TX_I_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_DMA_TX_I_ILG)
#define ESP32S2_IRQ_SPI_MEM_REJECT (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI_MEM_REJECT)
#define ESP32S2_IRQ_DMA_COPY (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_DMA_COPY)
#define ESP32S2_IRQ_SPI4_DMA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI4_DMA)
#define ESP32S2_IRQ_SPI4 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI4)
#define ESP32S2_IRQ_DCACHE_PRELOAD (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_DCACHE_PRELOAD)
#define ESP32S2_IRQ_ICACHE_PRELOAD (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_ICACHE_PRELOAD)
#define ESP32S2_IRQ_APB_ADC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_APB_ADC)
#define ESP32S2_IRQ_CRYPTO_DMA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_CRYPTO_DMA)
#define ESP32S2_IRQ_CPU_PERI_ERR (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_CPU_PERI_ERR)
#define ESP32S2_IRQ_APB_PERI_ERE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_APB_PERI_ERR)
#define ESP32S2_IRQ_DCACHE_SYNC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_DCACHE_SYNC)
#define ESP32S2_IRQ_ICACHE_SYNC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_ICACHE_SYNC)
#define ESP32S2_IRQ_SREG2 ESP32S2_IRQ_TG_WDT_EDGE
#define ESP32S2_NIRQS_SREG2 32
/* PRO_INTR_STATUS_REG_2 / APP_INTR_STATUS_REG_2 */
#define ESP32S2_IRQ_SREG2 ESP32S2_IRQ_TG1_WDT_EDGE
#define ESP32S2_NIRQS_SREG2 5
#define ESP32S2_NIRQ_PERIPH ESP32S2_NPERIPHERALS
/* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched
* as a second level of decoding: The first level dispatches to the GPIO
* interrupt handler. The second to the decoded GPIO interrupt handler.
*/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
# define ESP32S2_NIRQ_GPIO 40
# define ESP32S2_FIRST_GPIOIRQ (XTENSA_NIRQ_INTERNAL+ESP32S2_NIRQ_PERIPH)
# define ESP32S2_LAST_GPIOIRQ (ESP32S2_FIRST_GPIOIRQ+ESP32S2_NIRQ_GPIO-1)
# define ESP32S2_PIN2IRQ(p) ((p) + ESP32S2_FIRST_GPIOIRQ)
# define ESP32S2_IRQ2PIN(i) ((i) - ESP32S2_FIRST_GPIOIRQ)
#else
# define ESP32S2_NIRQ_GPIO 0
#endif
/* Total number of interrupts */
#define NR_IRQS (XTENSA_NIRQ_INTERNAL+ESP32S2_NIRQ_PERIPH+ESP32S2_NIRQ_GPIO)
/* Xtensa CPU Interrupts.
*
* Each of the two CPUs (PRO and APP) have 32 interrupts each, of which
* 26 can be mapped to peripheral interrupts:
*
* Level triggered peripherals (21 total):
* 0-5, 8-9, 12-13, 17-18 - Priority 1
* 19-21 - Priority 2
* 23, 27 - Priority 3
* 24-25 - Priority 4
* 26, 31 - Priority 5
* Edge triggered peripherals (4 total):
* 10 - Priority 1
* 22 - Priority 3
* 28, 30 - Priority 4
* NMI (1 total):
* 14 - NMI
*
* CPU peripheral interrupts can be a assigned to a CPU interrupt using the
* PRO_*_MAP_REG or APP_*_MAP_REG. There are a pair of these registers for
* each peripheral source. Multiple peripheral interrupt sources can be
* mapped to the same CPU interrupt.
*
* The remaining, six, internal CPU interrupts are:
*
* 6 Timer0 - Priority 1
* 7 Software - Priority 1
* 11 Profiling - Priority 3
* 15 Timer1 - Priority 3
* 16 Timer2 - Priority 5
* 29 Software - Priority 3
*
* A peripheral interrupt can be disabled
*/
#define ESP32S2_CPUINT_LEVELPERIPH_0 0
#define ESP32S2_CPUINT_LEVELPERIPH_1 1
#define ESP32S2_CPUINT_LEVELPERIPH_2 2
#define ESP32S2_CPUINT_LEVELPERIPH_3 3
#define ESP32S2_CPUINT_LEVELPERIPH_4 4
#define ESP32S2_CPUINT_LEVELPERIPH_5 5
#define ESP32S2_CPUINT_LEVELPERIPH_6 8
#define ESP32S2_CPUINT_LEVELPERIPH_7 9
#define ESP32S2_CPUINT_LEVELPERIPH_8 12
#define ESP32S2_CPUINT_LEVELPERIPH_9 13
#define ESP32S2_CPUINT_LEVELPERIPH_10 17
#define ESP32S2_CPUINT_LEVELPERIPH_11 18
#define ESP32S2_CPUINT_LEVELPERIPH_12 19
#define ESP32S2_CPUINT_LEVELPERIPH_13 20
#define ESP32S2_CPUINT_LEVELPERIPH_14 21
#define ESP32S2_CPUINT_LEVELPERIPH_15 23
#define ESP32S2_CPUINT_LEVELPERIPH_16 24
#define ESP32S2_CPUINT_LEVELPERIPH_17 25
#define ESP32S2_CPUINT_LEVELPERIPH_18 26
#define ESP32S2_CPUINT_LEVELPERIPH_19 27
#define ESP32S2_CPUINT_LEVELPERIPH_20 31
#define ESP32S2_CPUINT_NLEVELPERIPHS 21
#define EPS32_CPUINT_LEVELSET 0x8fbe333f
#define ESP32S2_CPUINT_EDGEPERIPH_0 10
#define ESP32S2_CPUINT_EDGEPERIPH_1 22
#define ESP32S2_CPUINT_EDGEPERIPH_2 28
#define ESP32S2_CPUINT_EDGEPERIPH_3 30
#define ESP32S2_CPUINT_NEDGEPERIPHS 4
#define EPS32_CPUINT_EDGESET 0x50400400
#define ESP32S2_CPUINT_NNMIPERIPHS 1
#define EPS32_CPUINT_NMISET 0x00004000
#define ESP32S2_CPUINT_MAC 0
#define ESP32S2_CPUINT_TIMER0 6
#define ESP32S2_CPUINT_SOFTWARE0 7
#define ESP32S2_CPUINT_PROFILING 11
#define ESP32S2_CPUINT_TIMER1 15
#define ESP32S2_CPUINT_TIMER2 16
#define ESP32S2_CPUINT_SOFTWARE1 29
#define ESP32S2_CPUINT_NINTERNAL 6
#define ESP32S2_NCPUINTS 32
#define ESP32S2_CPUINT_MAX (ESP32S2_NCPUINTS - 1)
#define ESP32_CPUINT_PERIPHSET 0xdffe773f
#define EPS32_CPUINT_INTERNALSET 0x200188c0
/* Priority 1: 0-10, 12-13, 17-18 (15)
* Priority 2: 19-21 (3)
* Priority 3: 11, 15, 22-23, 27, 29 (6)
* Priority 4: 24-25, 28, 30 (4)
* Priority 5: 16, 26, 31 (3)
* Priority NMI: 14 (1)
*/
#define ESP32S2_INTPRI1_MASK 0x000637ff
#define ESP32S2_INTPRI2_MASK 0x00380000
#define ESP32S2_INTPRI3_MASK 0x28c08800
#define ESP32S2_INTPRI4_MASK 0x53000000
#define ESP32S2_INTPRI5_MASK 0x84010000
#define ESP32S2_INTNMI_MASK 0x00004000
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_INCLUDE_ESP32S2_IRQ_H */
arch/xtensa/include/esp32s2/memory_layout.h
+139
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/****************************************************************************
* arch/xtensa/include/esp32s2/memory_layout.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The heap overview:
*
* CONFIG_HEAP2_BASE eg. 3f80 0000
* :
* : g_mmheap (CONFIG_ESP32_SPIRAM)
* :
* CONFIG_HEAP2_BASE + CONFIG_HEAP2_SIZE eg. 3fc0 0000
*
* HEAP_REGION0_START 3ffa e6f0
* :
* : g_mmheap region0
* :
* HEAP_REGION0_END 3ffa fff0
* :
* _sheap eg. 3ffc 8c6c
* :
* : g_mmheap region1
* :
* HEAP_REGION1_END 3ffd fff0
* :
* : ROM data
* :
*---------------------------------------------------------------------
*
* HEAP_REGION2_START 3ffe 0450
* :
* : g_iheap (CONFIG_XTENSA_IMEM_USE_SEPARATE_HEAP)
* :
* HEAP_REGION2_START + CONFIG_XTENSA_IMEM_REGION_SIZE
* :
* : g_mmheap region2
* :
*---------------------------------------------------------------------
* _eheap 4000 0000
*/
/* This region is supposed to be part of the ROM data. However, the ROM
* isn't using the last 6KB, so we get it as heap. It's called REGION0
* because it starts before _sheap.
* Although this region is adjacent to 0x3ffb0000 (start of static memory)
* we don't add it to static memory but we add it as heap. The reason is the
* Bluetooth controller uses a fixed 64KB region at the start of 0x3ffb0000.
* It's cleaner, from a source code perspective, to start static memory at
* 0x3ffb0000 and get what's before that as heap.
*/
#define HEAP_REGION0_START 0x3ffae6f0
#define HEAP_REGION0_END 0x3ffafff0
/* Region 1 of the heap is the area from the end of the .data section to the
* beginning of the ROM data. The start address is defined from the linker
* script as "_sheap". The end is defined here, as follows:
*/
#define HEAP_REGION1_END 0x3ffdfff0
/* Region 2 of the heap is the area from the end of the ROM data to the end
* of DRAM. The linker script has already set "_eheap" as the end of DRAM,
* the following defines the start of region2.
* N.B: That ROM data consists of 2 regions, one per CPU. If SMP is not
* enabled include APP's region with the heap.
*
* When an internal heap is enabled this region starts at an offset equal to
* the size of the internal heap.
*
* The QEMU bootloader image is slightly different than the chip's one.
* The ROM on PRO and APP CPUs uses different regions for static data.
* In QEMU, however, we load only one ROM binary, taken from the PRO CPU,
* and it is used by both CPUs. So, in QEMU, if we allocate PRO CPUs region
* early, it will be clobbered once the APP CPU starts.
* We can delay the allocation to when everything has started through the
* board_late_initiliaze hook, as is done for the APP data, however this
* should be fixed from QEMU side. The following macros, then, just skip
* PRO CPU's regions when a QEMU image generation is enabled with SMP.
*/
#if defined(CONFIG_ESP32_QEMU_IMAGE) && defined(CONFIG_SMP)
# define HEAP_REGION2_START 0x3ffe7e40
#else
# define HEAP_REGION2_START 0x3ffe0450
#endif
#ifdef CONFIG_SMP
# define HEAP_REGION2_END 0x3ffe3f10
# define HEAP_REGION3_START 0x3ffe5240
#endif
#ifdef CONFIG_XTENSA_IMEM_USE_SEPARATE_HEAP
# define XTENSA_IMEM_REGION_SIZE CONFIG_XTENSA_IMEM_REGION_SIZE
#else
# define XTENSA_IMEM_REGION_SIZE 0
#endif
/* Internal heap starts at the end of the ROM data.
* This is either the start of region2 if SMP is disabled or start of region3
* if SMP is enabled.
*/
#ifndef CONFIG_SMP
# define ESP32_IMEM_START HEAP_REGION2_START
#else
# define ESP32_IMEM_START HEAP_REGION3_START
#endif
/* Region of unused ROM App data */
#define HEAP_REGION_ROMAPP_START 0x3ffe4360
#define HEAP_REGION_ROMAPP_END 0x3ffe5230
arch/xtensa/include/esp32s2/tie-asm.h
+150
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/****************************************************************************
* arch/xtensa/include/esp32s2/tie-asm.h
* Compile-time assembler definitions dependent on CORE & TIE
*
* This header file contains assembly-language definitions (assembly
* macros, etc.) for this specific Xtensa processor's TIE extensions
* and options. It is customized to this Xtensa processor configuration.
*
* Customer ID=11657; Build=0x5fe96;
* Copyright (c) 1999-2016 Cadence Design Systems Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_INCLUDE_ESP32S2_TIE_ASM_H
#define __ARCH_XTENSA_INCLUDE_ESP32S2_TIE_ASM_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Selection parameter values for save-area save/restore macros: */
#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
/* Whether used automatically by compiler: */
#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
/* ABI handling across function calls: */
#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
/* Misc */
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
| ((ccuse) & XTHAL_SAS_ANYCC) \
| ((abi) & XTHAL_SAS_ANYABI) )
/* Macro to store all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first
* XCHAL_NCP_NUM_ATMPS registers are clobbered, the
* remaining are unused).
* Optional parameters:
* continue If macro invoked as part of a larger store sequence,
* set to 1 if this is not the first in the sequence.
* Defaults to 0.
* ofs Offset from start of larger sequence (from value of first
* ptr in sequence) at which to store. Defaults to next
* available space (or 0 if <continue> is 0).
* select Select what category(ies) of registers to store, as a
* bitmask (see XTHAL_SAS_xxx constants). Defaults to all
* registers.
* alloc Select what category(ies) of registers to allocate; if
* any category is selected here that is not in <select>,
* space for the corresponding registers is skipped without
* doing any store.
*/
.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
/* Optional global registers used by default by the compiler: */
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4
rur.THREADPTR \at1 /* threadptr option */
s32i \at1, \ptr, .Lxchal_ofs_+0
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1016, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
.endm /* xchal_ncp_store */
/* Macro to load all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first
* XCHAL_NCP_NUM_ATMPS registers are clobbered, the
* remaining are unused).
* Optional parameters:
* continue If macro invoked as part of a larger load sequence, set
* to 1 if this is not the first in the sequence. Defaults
* to 0.
* ofs Offset from start of larger sequence (from value of first
* ptr in sequence) at which to load. Defaults to next
* available space (or 0 if <continue> is 0).
* select Select what category(ies) of registers to load, as a
* bitmask (see XTHAL_SAS_xxx constants). Defaults to all
* registers.
* alloc Select what category(ies) of registers to allocate; if
* any category is selected here that is not in <select>,
* space for the corresponding registers is skipped without
* doing any load.
*/
.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
/* Optional global registers used by default by the compiler: */
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wur.THREADPTR \at1 /* threadptr option */
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1016, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
.endm /* xchal_ncp_load */
#define XCHAL_NCP_NUM_ATMPS 1
#define XCHAL_SA_NUM_ATMPS 1
#endif /* __ARCH_XTENSA_INCLUDE_ESP32S2_TIE_ASM_H */
arch/xtensa/include/esp32s2/tie.h
+194
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/****************************************************************************
* arch/xtensa/include/esp32s2/tie.h
* Compile-time HAL definitions dependent on CORE & TIE configuration
*
* NOTE: This header file is not meant to be included directly.
*
* This header file describes this specific Xtensa processor's TIE extensions
* that extend basic Xtensa core functionality. It is customized to this
* Xtensa processor configuration.
*
* Customer ID=11657; Build=0x5fe96;
* Copyright (c) 1999-2016 Cadence Design Systems Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
****************************************************************************/
#ifndef _ARCH_XTENSA_INCLUDE_ESP32S2_TIE_H
#define _ARCH_XTENSA_INCLUDE_ESP32S2_TIE_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define XCHAL_CP_NUM 1 /* number of coprocessors */
#define XCHAL_CP_MAX 1 /* max CP ID + 1 (0 if none) */
#define XCHAL_CP_MASK 0x01 /* bitmask of all CPs by ID */
#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
/* Basic parameters of each coprocessor: */
#define XCHAL_CP0_NAME "FPU"
#define XCHAL_CP0_IDENT FPU
#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */
#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */
#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
/* Filler info for unassigned coprocessors, to simplify arrays etc: */
#define XCHAL_CP1_SA_SIZE 0
#define XCHAL_CP1_SA_ALIGN 1
#define XCHAL_CP2_SA_SIZE 0
#define XCHAL_CP2_SA_ALIGN 1
#define XCHAL_CP3_SA_SIZE 0
#define XCHAL_CP3_SA_ALIGN 1
#define XCHAL_CP4_SA_SIZE 0
#define XCHAL_CP4_SA_ALIGN 1
#define XCHAL_CP5_SA_SIZE 0
#define XCHAL_CP5_SA_ALIGN 1
#define XCHAL_CP6_SA_SIZE 0
#define XCHAL_CP6_SA_ALIGN 1
#define XCHAL_CP7_SA_SIZE 0
#define XCHAL_CP7_SA_ALIGN 1
/* Save area for non-coprocessor optional and custom (TIE) state: */
#define XCHAL_NCP_SA_SIZE 48
#define XCHAL_NCP_SA_ALIGN 4
/* Total save area for optional and custom state (NCP + CPn): */
#define XCHAL_TOTAL_SA_SIZE 128 /* With 16-byte align padding */
#define XCHAL_TOTAL_SA_ALIGN 4 /* Actual minimum alignment */
/* Detailed contents of save areas.
* NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
* before expanding the XCHAL_xxx_SA_LIST() macros.
*
* XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
* dbnum,base,regnum,bitsz,gapsz,reset,x...)
*
* s = passed from XCHAL_*_LIST(s), eg. to select how to expand
* ccused = set if used by compiler without special options or code
* abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
* kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
* opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
* name = lowercase reg name (no quotes)
* galign = group byte alignment (power of 2) (galign >= align)
* align = register byte alignment (power of 2)
* asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
* (not including any pad bytes required to galign this or next reg)
* dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
* base = reg shortname w/o index (or sr=special, ur=TIE user reg)
* regnum = reg index in regfile, or special/TIE-user reg number
* bitsz = number of significant bits (regfile width, or ur/sr mask bits)
* gapsz = intervening bits, if bitsz bits not stored contiguously
* (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
* reset = register reset value (or 0 if undefined at reset)
* x = reserved for future use (0 until then)
*
* To filter out certain registers, e.g. to expand only the non-global
* registers used by the compiler, you can do something like this:
*
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
* #define SELCC0(p...)
* #define SELCC1(abikind,p...) SELAK##abikind(p)
* #define SELAK0(p...) REG(p)
* #define SELAK1(p...) REG(p)
* #define SELAK2(p...)
* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
* ...what you want to expand...
*/
#define XCHAL_NCP_SA_NUM 12
#define XCHAL_NCP_SA_LIST(s) \
XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, f64r_lo, 4, 4, 4,0x03EA, ur,234, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, f64r_hi, 4, 4, 4,0x03EB, ur,235, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, f64s, 4, 4, 4,0x03EC, ur,236, 32,0,0,0)
#define XCHAL_CP0_SA_NUM 18
#define XCHAL_CP0_SA_LIST(s) \
XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0)
#define XCHAL_CP1_SA_NUM 0
#define XCHAL_CP1_SA_LIST(s) /* empty */
#define XCHAL_CP2_SA_NUM 0
#define XCHAL_CP2_SA_LIST(s) /* empty */
#define XCHAL_CP3_SA_NUM 0
#define XCHAL_CP3_SA_LIST(s) /* empty */
#define XCHAL_CP4_SA_NUM 0
#define XCHAL_CP4_SA_LIST(s) /* empty */
#define XCHAL_CP5_SA_NUM 0
#define XCHAL_CP5_SA_LIST(s) /* empty */
#define XCHAL_CP6_SA_NUM 0
#define XCHAL_CP6_SA_LIST(s) /* empty */
#define XCHAL_CP7_SA_NUM 0
#define XCHAL_CP7_SA_LIST(s) /* empty */
/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
/* Byte length of instruction from its first byte, per FLIX. */
#define XCHAL_BYTE0_FORMAT_LENGTHS \
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
#endif /* _ARCH_XTENSA_INCLUDE_ESP32S2_TIE_H */
arch/xtensa/include/irq.h
+11
View File
@@ -55,6 +55,17 @@
# error Unknown LX6 implementation
# endif
#elif CONFIG_ARCH_FAMILY_LX7
# include <arch/lx7/irq.h>
/* Include implementation-specific IRQ definitions (including IRQ numbers) */
# ifdef CONFIG_ARCH_CHIP_ESP32S2
# include <arch/esp32s2/irq.h>
# else
# error Unknown LX7 implementation
# endif
#else
# error Unknown XTENSA architecture
#endif
arch/xtensa/include/lx7/irq.h
+68
View File
@@ -0,0 +1,68 @@
/****************************************************************************
* arch/xtensa/include/lx7/irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_XTENSA_INCLUDE_LX7_IRQ_H
#define __ARCH_XTENSA_INCLUDE_LX7_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_INCLUDE_LX7_IRQ_H */
arch/xtensa/include/xtensa/xtensa_coproc.h
+1 -1
View File
@@ -38,7 +38,7 @@
* Included Files
****************************************************************************/
#include <arch/esp32/core-isa.h>
#include <arch/chip/core-isa.h>
/****************************************************************************
* Pre-processor Definitions
arch/xtensa/src/Makefile
+4
View File
@@ -25,6 +25,10 @@ ifeq ($(CONFIG_ARCH_FAMILY_LX6),y)
ARCH_SUBDIR = lx6
endif
ifeq ($(CONFIG_ARCH_FAMILY_LX7),y)
ARCH_SUBDIR = lx7
endif
ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip}
arch/xtensa/src/common/xtensa_coproc.S
+2 -2
View File
@@ -128,7 +128,7 @@ _xtensa_coproc_savestate:
bbci.l a2, 0, 2f /* CP 0 not enabled */
l32i a14, a13, 0 /* a14 = _xtensa_coproc_saoffsets[0] */
add a3, a14, a15 /* a3 = save area for CP 0 */
xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
xchal_ncp_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
@@ -327,7 +327,7 @@ _xtensa_coproc_restorestate:
bbci.l a2, 0, 2f /* CP 0 not enabled */
l32i a14, a13, 0 /* a14 = _xtensa_coproc_saoffsets[0] */
add a3, a14, a15 /* a3 = save area for CP 0 */
xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
xchal_ncp_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
arch/xtensa/src/esp32s2/Kconfig
+911
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32s2/Make.defs
+87
View File
@@ -0,0 +1,87 @@
############################################################################
# arch/xtensa/src/esp32s2/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
# The start-up, "head", file. May be either a .S or a .c file.
HEAD_ASRC = xtensa_vectors.S xtensa_window_vector.S xtensa_windowspill.S
HEAD_ASRC += xtensa_int_handlers.S xtensa_user_handler.S
HEAD_CSRC = esp32s2_start.c
# Common XTENSA files (arch/xtensa/src/common)
CMN_ASRCS = xtensa_context.S xtensa_coproc.S xtensa_cpuint.S xtensa_panic.S
CMN_ASRCS += xtensa_sigtramp.S
CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c
CMN_CSRCS += xtensa_cpenable.c xtensa_createstack.c xtensa_exit.c
CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c xtensa_interruptcontext.c
CMN_CSRCS += xtensa_irqdispatch.c xtensa_lowputs.c xtensa_mdelay.c
CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c
CMN_CSRCS += xtensa_puts.c xtensa_releasepending.c xtensa_releasestack.c
CMN_CSRCS += xtensa_reprioritizertr.c xtensa_schedsigaction.c
CMN_CSRCS += xtensa_sigdeliver.c xtensa_stackframe.c xtensa_udelay.c
CMN_CSRCS += xtensa_unblocktask.c xtensa_usestack.c
CMN_CSRCS += esp32s2_systemreset.c
# Configuration-dependent common XTENSA files
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += esp32s2_idle.c
endif
ifeq ($(CONFIG_DEBUG_ALERT),y)
CMN_CSRCS += xtensa_dumpstate.c
endif
ifeq ($(CONFIG_XTENSA_DUMPBT_ON_ASSERT),y)
CMN_ASRCS += xtensa_backtrace.S
endif
ifeq ($(CONFIG_SPINLOCK),y)
CMN_CSRCS += xtensa_testset.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += xtensa_checkstack.c
endif
ifeq ($(CONFIG_FS_HOSTFS),y)
CMN_ASRCS += xtensa_simcall.S
CMN_CSRCS += xtensa_hostfs.c
endif
# Required ESP32S2 files (arch/xtensa/src/lx7)
CHIP_CSRCS = esp32s2_allocateheap.c esp32s2_clockconfig.c esp32s2_cpuint.c
CHIP_CSRCS += esp32s2_gpio.c esp32s2_intdecode.c esp32s2_irq.c esp32s2_region.c
CHIP_CSRCS += esp32s2_timerisr.c esp32s2_user.c esp32s2_rtc.c
CHIP_CSRCS += esp32s2_lowputc.c
# Configuration-dependent ESP32S2 files
ifeq ($(CONFIG_ESP32S2_UART),y)
CMN_CSRCS += esp32s2_serial.c
endif
ifeq ($(CONFIG_ARCH_USE_MODULE_TEXT),y)
CHIP_CSRCS += esp32s2_modtext.c
CMN_ASRCS += xtensa_loadstore.S
endif
arch/xtensa/src/esp32s2/chip_macros.h
+107
View File
@@ -0,0 +1,107 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/chip_macros.h
*
* Adapted from use in NuttX by:
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Derives from logic originally provided by Cadence Design Systems Inc.
*
* Copyright (c) 2006-2015 Cadence Design Systems Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_CHIP_MACROS_H
#define __ARCH_XTENSA_SRC_ESP32S2_CHIP_MACROS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* This is the name of the section containing the Xtensa low level handlers
* that is used by the board linker scripts.
*/
#define HANDLER_SECTION .iram1
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef __ASSEMBLY__
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Assembly Language Macros
****************************************************************************/
#ifdef __ASSEMBLY__
/* Macro to get the current core ID. Only uses the reg given as an argument.
* Reading PRID on the ESP108 architecture gives us 0xcdcd on the PRO
* processor and 0xabab on the APP CPU. We distinguish between the two by
* simply checking bit 1: it's 1 on the APP and 0 on the PRO processor.
*/
.macro getcoreid reg
rsr.prid \reg
bbci \reg, 1, 1f
movi \reg, 1
j 2f
1:
movi \reg, 0
2:
.endm
#endif /* __ASSEMBLY */
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S2_CHIP_MACROS_H */
arch/xtensa/src/esp32s2/chip_memory.h
+68
View File
@@ -0,0 +1,68 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/chip_memory.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_CHIP_MEMORY_H
#define __ARCH_XTENSA_SRC_ESP32S2_CHIP_MEMORY_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/esp32s2_soc.h"
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: xtensa_sp_sane
****************************************************************************/
static inline bool xtensa_sp_sane(uint32_t sp)
{
return (esp32s2_sp_dram(sp) && ((sp & 0x0f) == 0));
}
/****************************************************************************
* Name: xtensa_ptr_extram
****************************************************************************/
static inline bool xtensa_ptr_exec(const void *p)
{
return esp32s2_ptr_exec(p);
}
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S2_CHIP_MEMORY_H */
arch/xtensa/src/esp32s2/esp32s2_allocateheap.c
+83
View File
@@ -0,0 +1,83 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_allocateheap.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/mm/mm.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include <arch/esp32s2/memory_layout.h>
#include "xtensa.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_allocate_heap
*
* Description:
* This function will be called to dynamically set aside the heap region.
*
* For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
* size of the unprotected, user-space heap.
*
* If a protected kernel-space heap is provided, the kernel heap must be
* allocated (and protected) by an analogous up_allocate_kheap().
*
****************************************************************************/
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)&_sheap;
DEBUGASSERT(HEAP_REGION1_END > (uintptr_t)*heap_start);
*heap_size = (size_t)(HEAP_REGION1_END - (uintptr_t)*heap_start);
}
/****************************************************************************
* Name: xtensa_add_region
*
* Description:
* Memory may be added in non-contiguous chunks. Additional chunks are
* added by calling this function.
*
****************************************************************************/
#if CONFIG_MM_REGIONS > 1
void xtensa_add_region(void)
{
}
#endif
arch/xtensa/src/esp32s2/esp32s2_clockconfig.c
+325
View File
@@ -0,0 +1,325 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_clockconfig.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "hardware/esp32s2_soc.h"
#include "hardware/esp32s2_uart.h"
#include "hardware/esp32s2_rtccntl.h"
#include "hardware/esp32s2_system.h"
#include "esp32s2_rtc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef MIN
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#ifndef CONFIG_ESP_CONSOLE_UART_NUM
#define CONFIG_ESP_CONSOLE_UART_NUM 0
#endif
#define DEFAULT_CPU_FREQ 80
/****************************************************************************
* Private Types
****************************************************************************/
enum cpu_freq_e
{
CPU_80M = 0,
CPU_160M = 1,
CPU_240M = 2,
};
enum cpu_clksrc_e
{
XTAL_CLK,
PLL_CLK,
RTC8M_CLK,
APLL_CLK
};
enum pll_freq_e
{
PLL_320,
PLL_480
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s2_cpuclksrc
*
* Description:
* Select a clock source for CPU clock.
*
* Input Parameters:
* src - Any source from cpu_clksrc_e.
*
* Returned Value:
* None
*
****************************************************************************/
static inline void esp32s2_cpuclksrc(enum cpu_clksrc_e src)
{
uint32_t value;
value = VALUE_TO_FIELD(src, SYSTEM_SOC_CLK_SEL);
modifyreg32(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL_M, value);
}
/****************************************************************************
* Name: esp32s2_cpudiv
*
* Description:
* Select a divider for the CPU clk.
* NOTE: The divider is not necessarily the real divisor. See TRM for the
* equivalences.
*
* Input Parameters:
* divider - A value between 0 to 2.
*
* Returned Value:
* None
*
****************************************************************************/
static inline void esp32s2_cpudiv(uint8_t divider)
{
uint32_t value;
value = VALUE_TO_FIELD(divider, SYSTEM_CPUPERIOD_SEL);
modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL_M, value);
}
/****************************************************************************
* Name: esp32s2_pllfreqsel
*
* Description:
* Select the PLL frequency.
*
* Input Parameters:
* freq - Any clock from enum pll_freq_e
*
* Returned Value:
* None
****************************************************************************/
static inline void esp32s2_pllfreqsel(enum pll_freq_e freq)
{
uint32_t value;
value = VALUE_TO_FIELD(freq, SYSTEM_PLL_FREQ_SEL);
modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL_M, value);
}
/****************************************************************************
* Name: esp32s2_uart_tx_wait_idle
*
* Description:
* Wait until uart tx full empty and the last char send ok.
*
* Input Parameters:
* uart_no - 0 for UART0, 1 for UART1, 2 for UART2
*
* Returned Value:
* None
*
****************************************************************************/
static inline void esp32s2_uart_tx_wait_idle(uint8_t uart_no)
{
uint32_t status;
do
{
status = getreg32(UART_STATUS_REG(uart_no));
/* tx count is non-zero */
}
while ((status & UART_TXFIFO_CNT_M) != 0);
}
/****************************************************************************
* Public Functions
****************************************************************************/
extern uint32_t g_ticks_per_us;
/****************************************************************************
* Name: esp32s2_update_cpu_freq
*
* Description:
* Set the real CPU ticks per us to the ets, so that ets_delay_us
* will be accurate. Call this function when CPU frequency is changed.
*
* Input Parameters:
* ticks_per_us - CPU ticks per us
*
* Returned Value:
* None
*
****************************************************************************/
void IRAM_ATTR esp32s2_update_cpu_freq(uint32_t ticks_per_us)
{
/* Update scale factors used by esp_rom_delay_us */
g_ticks_per_us = ticks_per_us;
}
/****************************************************************************
* Name: esp32s2_set_cpu_freq
*
* Description:
* Switch to one of PLL-based frequencies.
*
* Input Parameters:
* cpu_freq_mhz - Target CPU frequency
*
* Returned Value:
* None
*
****************************************************************************/
void IRAM_ATTR esp32s2_set_cpu_freq(int cpu_freq_mhz)
{
uint32_t dbias;
uint32_t value;
switch (cpu_freq_mhz)
{
case 80:
/* 80 MHz is obtained from the 480 MHz PLL.
* In this case CPU_CLK = PLL_CLK / 6. Config the PLL as 480 MHz
* with a 6 divider and set the source clock as PLL_CLK.
*/
dbias = DIG_DBIAS_80M_160M;
esp32s2_cpudiv(0);
break;
case 160:
/* 160 MHz is obtained from the 480 MHz PLL.
* In this case CPU_CLK = PLL_CLK / 3. Config the PLL as 480 MHz
* with a 3 divider and set the source clock as PLL_CLK.
*/
dbias = DIG_DBIAS_80M_160M;
esp32s2_cpudiv(1);
break;
case 240:
/* 160 MHz is obtained from the 480 MHz PLL.
* In this case CPU_CLK = PLL_CLK / 2. Config the PLL as 480 MHz
* with a 2 divider and set the source clock as PLL_CLK.
*/
dbias = DIG_DBIAS_240M;
esp32s2_cpudiv(2);
break;
default:
/* Unsupported clock config. */
return;
}
value = (((80 * MHZ) >> 12) & UINT16_MAX) |
((((80 * MHZ) >> 12) & UINT16_MAX) << 16);
esp32s2_pllfreqsel(PLL_480);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias);
esp32s2_cpuclksrc(PLL_CLK);
putreg32(value, RTC_APB_FREQ_REG);
esp32s2_update_cpu_freq(cpu_freq_mhz);
}
/****************************************************************************
* Name: esp32s2_clockconfig
*
* Description:
* Called to initialize the ESP32S2. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
* clocking using the settings in board.h.
*
****************************************************************************/
void esp32s2_clockconfig(void)
{
/* Wait for the TX FIFO to unload data */
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
esp32s2_uart_tx_wait_idle(0);
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
esp32s2_uart_tx_wait_idle(1);
#endif
/* Configure the CPU frequency */
esp32s2_set_cpu_freq(CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ);
}
/****************************************************************************
* Name: esp_clk_cpu_freq
*
* Description:
* Get CPU frequency
*
* Input Parameters:
* None
*
* Returned Value:
* CPU frequency
*
****************************************************************************/
int IRAM_ATTR esp_clk_cpu_freq(void)
{
return g_ticks_per_us * MHZ;
}
/****************************************************************************
* Name: esp_clk_apb_freq
*
* Description:
* Return current APB clock frequency.
*
* Input Parameters:
* None
*
* Returned Value:
* APB clock frequency, in Hz
*
****************************************************************************/
int IRAM_ATTR esp_clk_apb_freq(void)
{
return MIN(g_ticks_per_us, 80) * MHZ;
}
arch/xtensa/src/esp32s2/esp32s2_clockconfig.h
+112
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/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_clockconfig.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CLOCKCONFIG_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CLOCKCONFIG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s2_update_cpu_freq
*
* Description:
* Set the real CPU ticks per us to the ets, so that ets_delay_us
* will be accurate. Call this function when CPU frequency is changed.
*
* Input Parameters:
* ticks_per_us - CPU ticks per us
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_update_cpu_freq(uint32_t ticks_per_us);
/****************************************************************************
* Name: esp32s2_set_cpu_freq
*
* Description:
* Switch to one of PLL-based frequencies.
* Current frequency can be XTAL or PLL.
*
* Input Parameters:
* cpu_freq_mhz - new CPU frequency
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_set_cpu_freq(int cpu_freq_mhz);
/****************************************************************************
* Name: esp32s2_clockconfig
*
* Description:
* Called to initialize the ESP32S2. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
* clocking using the settings in board.h.
*
****************************************************************************/
void esp32s2_clockconfig(void);
/****************************************************************************
* Name: esp_clk_cpu_freq
*
* Description:
* Get CPU frequency
*
* Input Parameters:
* None
*
* Returned Value:
* CPU frequency
*
****************************************************************************/
int esp_clk_cpu_freq(void);
/****************************************************************************
* Name: esp_clk_apb_freq
*
* Description:
* Return current APB clock frequency.
*
* Input Parameters:
* None
*
* Returned Value:
* APB clock frequency, in Hz
*
****************************************************************************/
int esp_clk_apb_freq(void);
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CLOCKCONFIG_H */
arch/xtensa/src/esp32s2/esp32s2_config.h
+84
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/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_config.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CONFIG_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CONFIG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/chip/chip.h>
#include <arch/board/board.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* UARTs ********************************************************************/
/* Are any UARTs enabled? */
#undef HAVE_UART_DEVICE
#ifdef CONFIG_ESP32S2_UART
# define HAVE_UART_DEVICE 1
#endif
/* Serial Console ***********************************************************/
/* Is there a serial console? There should be no more than one defined. It
* could be on any UARTn. n E {0,1}
*/
#undef HAVE_SERIAL_CONSOLE
#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_ESP32S2_UART0)
# undef CONFIG_UART1_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_ESP32S2_UART1)
# undef CONFIG_UART0_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#else
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
#endif
/* SPI **********************************************************************/
/* Don't enable SPI peripherals not supported by the chip. */
#if ESP32S2_NSPI < 1
# undef CONFIG_ESP32S2_SPI0
# undef CONFIG_ESP32S2_SPI1
# undef CONFIG_ESP32S2_SPI2
# undef CONFIG_ESP32S2_SPI3
#elif ESP32S2_NSPI < 2
# undef CONFIG_ESP32S2_SPI1
# undef CONFIG_ESP32S2_SPI2
# undef CONFIG_ESP32S2_SPI3
#elif ESP32S2_NSPI < 3
# undef CONFIG_ESP32S2_SPI2
# undef CONFIG_ESP32S2_SPI3
#elif ESP32S2_NSPI < 4
# undef CONFIG_ESP32S2_SPI3
#endif
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CONFIG_H */
arch/xtensa/src/esp32s2/esp32s2_cpuint.c
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arch/xtensa/src/esp32s2/esp32s2_cpuint.h
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/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_cpuint.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CPUINT_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CPUINT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/irq.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* No peripheral assigned to this CPU interrupt */
#define CPUINT_UNASSIGNED 0xff
/* A low priority definition to be used by drivers */
#define ESP32S2_INT_PRIO_DEF 1
/****************************************************************************
* Public Data
****************************************************************************/
/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */
extern uint8_t g_cpu0_intmap[ESP32S2_NCPUINTS];
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s2_cpuint_initialize
*
* Description:
* Initialize CPU interrupts.
*
* Input Parameters:
* None
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned on
* any failure.
*
****************************************************************************/
int esp32s2_cpuint_initialize(void);
/****************************************************************************
* Name: esp32s2_alloc_levelint
*
* Description:
* Allocate a level CPU interrupt
*
* Input Parameters:
* priority - Priority of the CPU interrupt (1-5)
*
* Returned Value:
* On success, the allocated level-sensitive, CPU interrupt number is
* returned. A negated errno is returned on failure. The only possible
* failure is that all level-sensitive CPU interrupts have already been
* allocated.
*
****************************************************************************/
int esp32s2_alloc_levelint(int priority);
/****************************************************************************
* Name: esp32s2_alloc_edgeint
*
* Description:
* Allocate an edge CPU interrupt
*
* Input Parameters:
* priority - Priority of the CPU interrupt (1-5)
*
* Returned Value:
* On success, the allocated edge-sensitive, CPU interrupt number is
* returned. A negated errno is returned on failure. The only possible
* failure is that all edge-sensitive CPU interrupts have already been
* allocated.
*
****************************************************************************/
int esp32s2_alloc_edgeint(int priority);
/****************************************************************************
* Name: esp32s2_free_cpuint
*
* Description:
* Free a previously allocated CPU interrupt by making it available in the
* g_cpu0_freeints.
*
* Input Parameters:
* cpuint - The CPU interrupt number to be freed.
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_free_cpuint(int cpuint);
/****************************************************************************
* Name: esp32s2_attach_peripheral
*
* Description:
* Attach a peripheral interrupt to a CPU interrupt.
* This function may be called after esp32s2_alloc_edgeint or
* esp32s2_alloc_levelint
*
* Input Parameters:
* periphid - The peripheral number from irq.h to be assigned to
* a CPU interrupt.
* cpuint - The CPU interrupt to receive the peripheral interrupt
* assignment. This value is returned by
* esp32s2_alloc_edgeint or esp32s2_alloc_levelint.
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_attach_peripheral(int periphid, int cpuint);
/****************************************************************************
* Name: esp32s2_detach_peripheral
*
* Description:
* Detach a peripheral interrupt from a CPU interrupt.
*
* Input Parameters:
* periphid - The peripheral number from irq.h to be detached from the
* CPU interrupt.
* cpuint - The CPU interrupt from which the peripheral interrupt will
* be detached.
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_detach_peripheral(int periphid, int cpuint);
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CPUINT_H */
arch/xtensa/src/esp32s2/esp32s2_gpio.c
+474
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/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <arch/irq.h>
#include "xtensa.h"
#include "hardware/esp32s2_iomux.h"
#include "hardware/esp32s2_gpio.h"
#include "esp32s2_cpuint.h"
#include "esp32s2_gpio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define NGPIO_HPINS (ESP32S2_NIRQ_GPIO - 32)
#define NGPIO_HMASK ((1ul << NGPIO_HPINS) - 1)
#define _NA_ 0xff
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
static int g_gpio_cpuint;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: gpio_dispatch
*
* Description:
* Second level dispatch for GPIO interrupt handling.
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
static void gpio_dispatch(int irq, uint32_t status, uint32_t *regs)
{
uint32_t mask;
int i;
/* Check each bit in the status register */
for (i = 0; i < 32 && status != 0; i++)
{
/* Check if there is an interrupt pending for this pin */
mask = (1ul << i);
if ((status & mask) != 0)
{
/* Yes... perform the second level dispatch */
irq_dispatch(irq + i, regs);
/* Clear the bit in the status so that we might execute this loop
* sooner.
*/
status &= ~mask;
}
}
}
#endif
/****************************************************************************
* Name: gpio_interrupt
*
* Description:
* GPIO interrupt handler.
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
static int gpio_interrupt(int irq, FAR void *context, FAR void *arg)
{
uint32_t status;
/* Read and clear the lower GPIO interrupt status */
status = getreg32(GPIO_STATUS_REG);
putreg32(status, GPIO_STATUS_W1TC_REG);
/* Dispatch pending interrupts in the lower GPIO status register */
gpio_dispatch(ESP32S2_FIRST_GPIOIRQ, status, (uint32_t *)context);
/* Read and clear the upper GPIO interrupt status */
status = getreg32(GPIO_STATUS1_REG) & NGPIO_HMASK;
putreg32(status, GPIO_STATUS1_W1TC_REG);
/* Dispatch pending interrupts in the lower GPIO status register */
gpio_dispatch(ESP32S2_FIRST_GPIOIRQ + 32, status, (uint32_t *)context);
return OK;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s2_configgpio
*
* Description:
* Configure a GPIO pin based on encoded pin attributes.
*
****************************************************************************/
int esp32s2_configgpio(int pin, gpio_pinattr_t attr)
{
uintptr_t regaddr;
uint32_t func;
uint32_t cntrl;
uint32_t pin2func;
DEBUGASSERT(pin >= 0 && pin <= ESP32S2_NGPIOS);
/* Handle input pins */
func = 0;
cntrl = 0;
if ((attr & INPUT) != 0)
{
if (pin < 32)
{
putreg32((1ul << pin), GPIO_ENABLE_W1TC_REG);
}
else
{
putreg32((1ul << (pin - 32)), GPIO_ENABLE1_W1TC_REG);
}
/* Input enable */
func |= FUN_IE;
if ((attr & PULLUP) != 0)
{
func |= FUN_PU;
}
else if (attr & PULLDOWN)
{
func |= FUN_PD;
}
}
/* Handle output pins */
if ((attr & OUTPUT) != 0)
{
if (pin < 32)
{
putreg32((1ul << pin), GPIO_ENABLE_W1TS_REG);
}
else
{
putreg32((1ul << (pin - 32)), GPIO_ENABLE1_W1TS_REG);
}
}
/* Add drivers */
func |= (uint32_t)(2ul << FUN_DRV_S);
/* Select the pad's function. If no function was given, consider it a
* normal input or output (i.e. function3).
*/
if ((attr & FUNCTION_MASK) != 0)
{
func |= (uint32_t)(((attr >> FUNCTION_SHIFT) - 1) << MCU_SEL_S);
}
else
{
func |= (uint32_t)(PIN_FUNC_GPIO << MCU_SEL_S);
}
if ((attr & OPEN_DRAIN) != 0)
{
cntrl |= (1 << GPIO_PIN_PAD_DRIVER_S);
}
pin2func = (pin + 1) * 4;
regaddr = DR_REG_IO_MUX_BASE + pin2func;
putreg32(func, regaddr);
regaddr = GPIO_REG(pin);
putreg32(cntrl, regaddr);
return OK;
}
/****************************************************************************
* Name: esp32s2_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void esp32s2_gpiowrite(int pin, bool value)
{
DEBUGASSERT(pin >= 0 && pin <= ESP32S2_NGPIOS);
if (value)
{
if (pin < 32)
{
putreg32((uint32_t)(1ul << pin), GPIO_OUT_W1TS_REG);
}
else
{
putreg32((uint32_t)(1ul << (pin - 32)), GPIO_OUT1_W1TS_REG);
}
}
else
{
if (pin < 32)
{
putreg32((uint32_t)(1ul << pin), GPIO_OUT_W1TC_REG);
}
else
{
putreg32((uint32_t)(1ul << (pin - 32)), GPIO_OUT1_W1TC_REG);
}
}
}
/****************************************************************************
* Name: esp32s2_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool esp32s2_gpioread(int pin)
{
uint32_t regval;
DEBUGASSERT(pin >= 0 && pin <= ESP32S2_NGPIOS);
if (pin < 32)
{
regval = getreg32(GPIO_IN_REG);
return ((regval >> pin) & 1) != 0;
}
else
{
regval = getreg32(GPIO_IN1_REG);
return ((regval >> (pin - 32)) & 1) != 0;
}
}
/****************************************************************************
* Name: esp32s2_gpioirqinitialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
void esp32s2_gpioirqinitialize(void)
{
/* Allocate a level-sensitive, priority 1 CPU interrupt */
g_gpio_cpuint = esp32s2_alloc_levelint(1);
DEBUGASSERT(g_gpio_cpuint >= 0);
/* Attach the GPIO peripheral to the allocated CPU interrupt */
up_disable_irq(g_gpio_cpuint);
esp32s2_attach_peripheral(ESP32S2_PERI_GPIO_INT_PRO, g_gpio_cpuint);
/* Attach and enable the interrupt handler */
DEBUGVERIFY(irq_attach(ESP32S2_PERI_GPIO_INT_PRO, gpio_interrupt, NULL));
up_enable_irq(g_gpio_cpuint);
}
#endif
/****************************************************************************
* Name: esp32s2_gpioirqenable
*
* Description:
* Enable the COPY interrupt for specified GPIO IRQ
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
void esp32s2_gpioirqenable(int irq, gpio_intrtype_t intrtype)
{
uintptr_t regaddr;
uint32_t regval;
int pin;
DEBUGASSERT(irq >= ESP32S2_FIRST_GPIOIRQ && irq <= ESP32S2_LAST_GPIOIRQ);
/* Convert the IRQ number to a pin number */
pin = ESP32S2_IRQ2PIN(irq);
/* Get the address of the GPIO PIN register for this pin */
up_disable_irq(g_gpio_cpuint);
regaddr = GPIO_REG(pin);
regval = getreg32(regaddr);
regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M);
/* Set the pin ENA field:
*
* Bit 0: APP CPU interrupt enable
* Bit 1: APP CPU non-maskable interrupt enable
* Bit 3: PRO CPU interrupt enable
* Bit 4: PRO CPU non-maskable interrupt enable
* Bit 5: SDIO's extent interrupt enable.
*/
/* PRO_CPU */
regval |= ((1 << 2) << GPIO_PIN_INT_ENA_S);
regval |= (intrtype << GPIO_PIN_INT_TYPE_S);
putreg32(regval, regaddr);
up_enable_irq(g_gpio_cpuint);
}
#endif
/****************************************************************************
* Name: esp32s2_gpioirqdisable
*
* Description:
* Disable the interrupt for specified GPIO IRQ
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
void esp32s2_gpioirqdisable(int irq)
{
uintptr_t regaddr;
uint32_t regval;
int pin;
DEBUGASSERT(irq >= ESP32S2_FIRST_GPIOIRQ && irq <= ESP32S2_LAST_GPIOIRQ);
/* Convert the IRQ number to a pin number */
pin = ESP32S2_IRQ2PIN(irq);
/* Get the address of the GPIO PIN register for this pin */
up_disable_irq(g_gpio_cpuint);
regaddr = GPIO_REG(pin);
regval = getreg32(regaddr);
regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M);
putreg32(regval, regaddr);
up_enable_irq(g_gpio_cpuint);
}
#endif
/****************************************************************************
* Name: esp32s2_gpio_matrix_in
*
* Description:
* Set gpio input to a signal
* NOTE: one gpio can input to several signals
* If gpio == 0x30, cancel input to the signal, input 0 to signal
* If gpio == 0x38, cancel input to the signal, input 1 to signal,
* for I2C pad
*
****************************************************************************/
void esp32s2_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv)
{
uint32_t regaddr = GPIO_FUNC0_IN_SEL_CFG_REG + (signal_idx * 4);
uint32_t regval = (gpio << GPIO_FUNC0_IN_SEL_S);
if (inv)
{
regval |= GPIO_FUNC0_IN_INV_SEL;
}
if (gpio != 0x34)
{
regval |= GPIO_SIG0_IN_SEL;
}
putreg32(regval, regaddr);
}
/****************************************************************************
* Name: esp32s2_gpio_matrix_out
*
* Description:
* Set signal output to gpio
* NOTE: one signal can output to several gpios
* If signal_idx == 0x100, cancel output put to the gpio
*
****************************************************************************/
void esp32s2_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx,
bool out_inv, bool oen_inv)
{
uint32_t regaddr = GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio * 4);
uint32_t regval = signal_idx << GPIO_FUNC0_OUT_SEL_S;
if (gpio >= GPIO_PIN_COUNT)
{
return;
}
if (gpio < 32)
{
putreg32((1ul << gpio), GPIO_ENABLE_W1TS_REG);
}
else
{
putreg32((1ul << (gpio - 32)), GPIO_ENABLE1_W1TS_REG);
}
if (out_inv)
{
regval |= GPIO_FUNC0_OUT_INV_SEL;
}
if (oen_inv)
{
regval |= GPIO_FUNC0_OEN_INV_SEL;
}
putreg32(regval, regaddr);
}
arch/xtensa/src/esp32s2/esp32s2_gpio.h
+235
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/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_GPIO_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */
#define MATRIX_DETACH_IN_LOW_PIN 0x30 /* Detach non-inverted INPUT sig */
#define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */
/* Bit-encoded input to esp32s2_configgpio() ********************************/
/* Encoded pin attributes used with esp32s2_configgpio()
*
* 8 7 6 5 4 3 2 1 0
* -- -- -- -- -- -- -- -- --
* FN FN FN OD PD PU F O I
*/
#define PINMODE_SHIFT 0
#define PINMODE_MASK (7 << PINMODE_SHIFT)
# define INPUT (1 << 0)
# define OUTPUT (1 << 1)
# define FUNCTION (1 << 2)
#define PULLUP (1 << 3)
#define PULLDOWN (1 << 4)
#define OPEN_DRAIN (1 << 5)
#define FUNCTION_SHIFT 6
#define FUNCTION_MASK (7 << FUNCTION_SHIFT)
# define FUNCTION_1 (1 << FUNCTION_SHIFT)
# define FUNCTION_2 (2 << FUNCTION_SHIFT)
# define FUNCTION_3 (3 << FUNCTION_SHIFT)
# define FUNCTION_4 (4 << FUNCTION_SHIFT)
# define FUNCTION_5 (5 << FUNCTION_SHIFT)
# define FUNCTION_6 (6 << FUNCTION_SHIFT)
#define INPUT_PULLUP (INPUT | PULLUP)
#define INPUT_PULLDOWN (INPUT | PULLDOWN)
#define OUTPUT_OPEN_DRAIN (OUTPUT | OPEN_DRAIN)
#define INPUT_FUNCTION (INPUT | FUNCTION)
# define INPUT_FUNCTION_1 (INPUT_FUNCTION | FUNCTION_1)
# define INPUT_FUNCTION_2 (INPUT_FUNCTION | FUNCTION_2)
# define INPUT_FUNCTION_3 (INPUT_FUNCTION | FUNCTION_3)
# define INPUT_FUNCTION_4 (INPUT_FUNCTION | FUNCTION_4)
# define INPUT_FUNCTION_5 (INPUT_FUNCTION | FUNCTION_5)
# define INPUT_FUNCTION_6 (INPUT_FUNCTION | FUNCTION_6)
#define OUTPUT_FUNCTION (OUTPUT | FUNCTION)
# define OUTPUT_FUNCTION_1 (OUTPUT_FUNCTION | FUNCTION_1)
# define OUTPUT_FUNCTION_2 (OUTPUT_FUNCTION | FUNCTION_2)
# define OUTPUT_FUNCTION_3 (OUTPUT_FUNCTION | FUNCTION_3)
# define OUTPUT_FUNCTION_4 (OUTPUT_FUNCTION | FUNCTION_4)
# define OUTPUT_FUNCTION_5 (OUTPUT_FUNCTION | FUNCTION_5)
# define OUTPUT_FUNCTION_6 (OUTPUT_FUNCTION | FUNCTION_6)
/* Interrupt type used with esp32s2_gpioirqenable() */
#define DISABLED 0x00
#define RISING 0x01
#define FALLING 0x02
#define CHANGE 0x03
#define ONLOW 0x04
#define ONHIGH 0x05
#define ONLOW_WE 0x0c
#define ONHIGH_WE 0x0d
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/* Must be big enough to hold the above encodings */
typedef uint16_t gpio_pinattr_t;
typedef uint8_t gpio_intrtype_t;
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s2_gpioirqinitialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
void esp32s2_gpioirqinitialize(void);
#else
# define esp32s2_gpioirqinitialize()
#endif
/****************************************************************************
* Name: esp32s2_configgpio
*
* Description:
* Configure a GPIO pin based on encoded pin attributes.
*
****************************************************************************/
int esp32s2_configgpio(int pin, gpio_pinattr_t attr);
/****************************************************************************
* Name: esp32s2_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void esp32s2_gpiowrite(int pin, bool value);
/****************************************************************************
* Name: esp32s2_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool esp32s2_gpioread(int pin);
/****************************************************************************
* Name: esp32s2_gpioirqenable
*
* Description:
* Enable the interrupt for specified GPIO IRQ
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
void esp32s2_gpioirqenable(int irq, gpio_intrtype_t intrtype);
#else
# define esp32s2_gpioirqenable(irq,intrtype)
#endif
/****************************************************************************
* Name: esp32s2_gpioirqdisable
*
* Description:
* Disable the interrupt for specified GPIO IRQ
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
void esp32s2_gpioirqdisable(int irq);
#else
# define esp32s2_gpioirqdisable(irq)
#endif
/****************************************************************************
* Name: esp32s2_gpio_matrix_in
*
* Description:
* Set gpio input to a signal
* NOTE: one gpio can input to several signals
* If gpio == 0x30, cancel input to the signal, input 0 to signal
* If gpio == 0x38, cancel input to the signal, input 1 to signal,
* for I2C pad
*
****************************************************************************/
void esp32s2_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
/****************************************************************************
* Name: esp32s2_gpio_matrix_out
*
* Description:
* Set signal output to gpio
* NOTE: one signal can output to several gpios
* If signal_idx == 0x100, cancel output put to the gpio
*
****************************************************************************/
void esp32s2_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx,
bool out_inv, bool oen_inv);
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_GPIO_H */
arch/xtensa/src/esp32s2/esp32s2_idle.c
+206
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/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_idle.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/power/pm.h>
#include "esp32s2_pm.h"
#include "xtensa.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Values for the RTC Alarm to wake up from the PM_STANDBY mode
* (which corresponds to ESP32S2 stop mode). If this alarm expires,
* the logic in this file will wakeup from PM_STANDBY mode and
* transition to PM_SLEEP mode (ESP32S2 standby mode).
*/
#ifdef CONFIG_PM
#ifndef CONFIG_PM_ALARM_SEC
# define CONFIG_PM_ALARM_SEC 15
#endif
#ifndef CONFIG_PM_ALARM_NSEC
# define CONFIG_PM_ALARM_NSEC 0
#endif
#ifndef CONFIG_PM_SLEEP_WAKEUP_SEC
# define CONFIG_PM_SLEEP_WAKEUP_SEC 20
#endif
#ifndef CONFIG_PM_SLEEP_WAKEUP_NSEC
# define CONFIG_PM_SLEEP_WAKEUP_NSEC 0
#endif
#define PM_IDLE_DOMAIN 0 /* Revisit */
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_idlepm
*
* Description:
* Perform IDLE state power management.
*
****************************************************************************/
#ifdef CONFIG_PM
static void up_idlepm(void)
{
static enum pm_state_e oldstate = PM_NORMAL;
enum pm_state_e newstate;
irqstate_t flags;
int ret;
/* Decide, which power saving level can be obtained */
newstate = pm_checkstate(PM_IDLE_DOMAIN);
/* Check for state changes */
if (newstate != oldstate)
{
flags = spin_lock_irqsave(NULL);
/* Perform board-specific, state-dependent logic here */
_info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
ret = pm_changestate(PM_IDLE_DOMAIN, newstate);
if (ret < 0)
{
/* The new state change failed, revert to the preceding state */
pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
/* Save the new state */
oldstate = newstate;
}
spin_unlock_irqrestore(NULL, flags);
/* MCU-specific power management logic */
switch (newstate)
{
case PM_NORMAL:
break;
case PM_IDLE:
break;
case PM_STANDBY:
{
/* Enter Force-sleep mode */
esp32s2_pmstandby(CONFIG_PM_ALARM_SEC * 1000000 +
CONFIG_PM_ALARM_NSEC / 1000);
}
break;
case PM_SLEEP:
{
/* Enter Deep-sleep mode */
esp32s2_pmsleep(CONFIG_PM_SLEEP_WAKEUP_SEC * 1000000 +
CONFIG_PM_SLEEP_WAKEUP_NSEC / 1000);
}
break;
default:
break;
}
}
else
{
if (oldstate == PM_NORMAL)
{
/* Relax normal operation */
pm_relax(PM_IDLE_DOMAIN, PM_NORMAL);
}
#ifdef CONFIG_WATCHDOG
/* Announce the power management state change to feed watchdog */
pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL);
#endif
}
}
#else
# define up_idlepm()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when their is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
nxsched_process_timer();
#else
/* Perform IDLE mode power management */
up_idlepm();
/* This would be an appropriate place to put some MCU-specific logic to
* sleep in a reduced power mode until an interrupt occurs to save power
*/
#if XCHAL_HAVE_INTERRUPTS
__asm__ __volatile__ ("waiti 0");
#endif
#endif
}
arch/xtensa/src/esp32s2/esp32s2_intdecode.c
+122
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@@ -0,0 +1,122 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_intdecode.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include "xtensa.h"
#include "esp32s2_cpuint.h"
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: xtensa_intclear
****************************************************************************/
static inline void xtensa_intclear(uint32_t mask)
{
__asm__ __volatile__
(
"wsr %0, INTCLEAR\n"
: "=r"(mask) : :
);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xtensa_int_decode
*
* Description:
* Determine the peripheral that generated the interrupt and dispatch
* handling to the registered interrupt handler via xtensa_irq_dispatch().
*
* Input Parameters:
* cpuints - Set of pending interrupts valid for this level
* regs - Saves processor state on the stack
*
* Returned Value:
* Normally the same value as regs is returned. But, in the event of an
* interrupt level context switch, the returned value will, instead point
* to the saved processor state in the TCB of the newly started task.
*
****************************************************************************/
uint32_t *xtensa_int_decode(uint32_t cpuints, uint32_t *regs)
{
uint8_t *intmap;
uint32_t mask;
int bit;
intmap = g_cpu0_intmap;
/* Skip over zero bits, eight at a time */
for (bit = 0, mask = 0xff;
bit < ESP32S2_NCPUINTS && (cpuints & mask) == 0;
bit += 8, mask <<= 8);
/* Process each pending CPU interrupt */
for (; bit < ESP32S2_NCPUINTS && cpuints != 0; bit++)
{
mask = (1 << bit);
if ((cpuints & mask) != 0)
{
/* Extract the IRQ number from the mapping table */
uint8_t irq = intmap[bit];
DEBUGASSERT(irq != CPUINT_UNASSIGNED);
/* Clear software or edge-triggered interrupt */
xtensa_intclear(mask);
/* Dispatch the CPU interrupt.
*
* NOTE that regs may be altered in the case of an interrupt
* level context switch.
*/
regs = xtensa_irq_dispatch((int)irq, regs);
/* Clear the bit in the pending interrupt so that perhaps
* we can exit the look early.
*/
cpuints &= ~mask;
}
}
return regs;
}
arch/xtensa/src/esp32s2/esp32s2_irq.c
+109
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@@ -0,0 +1,109 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_irq.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include "xtensa.h"
#include "esp32s2_cpuint.h"
#include "esp32s2_gpio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/* g_current_regs[] holds a reference to the current interrupt level
* register storage structure. It is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
volatile uint32_t *g_current_regs[1];
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s2_irq_dump
*
* Description:
* Dump some interesting NVIC registers
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void esp32s2_irq_dump(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
#warning Missing logic
leave_critical_section(flags);
}
#else
# define esp32s2_irq_dump(msg, irq)
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void)
{
/* Initialize CPU interrupts */
esp32s2_cpuint_initialize();
/* Attach and enable internal interrupts */
esp32s2_irq_dump("initial", NR_IRQS);
#ifdef CONFIG_ESP32S2_GPIO_IRQ
/* Initialize GPIO interrupt support */
esp32s2_gpioirqinitialize();
#endif
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts. Also clears PS.EXCM */
up_irq_enable();
#endif
}
arch/xtensa/src/esp32s2/esp32s2_lowputc.c
+656
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arch/xtensa/src/esp32s2/esp32s2_lowputc.h
+391
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@@ -0,0 +1,391 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_lowputc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_LOWPUTC_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_LOWPUTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <debug.h>
#include "hardware/esp32s2_uart.h"
#include "hardware/esp32s2_gpio_sigmap.h"
#include "esp32s2_cpuint.h"
/****************************************************************************
* Public Types
****************************************************************************/
enum uart_sclk
{
REF_TICK,
APB_CLK = 1, /* 80 MHz */
};
enum uart_parity
{
UART_PARITY_DISABLE,
UART_PARITY_ODD,
UART_PARITY_EVEN
};
enum uart_data_length
{
UART_DATA_5_BITS,
UART_DATA_6_BITS,
UART_DATA_7_BITS,
UART_DATA_8_BITS
};
enum uart_stop_length
{
UART_STOP_BITS_1 = 0x1, /* Stop bit: 1 bit */
UART_STOP_BITS_2 = 0x3, /* Stop bit: 2 bits */
};
/* Default FIFOs size */
#define UART_TX_FIFO_SIZE 128
#define UART_RX_FIFO_SIZE 128
/* Struct used to store uart driver information and to
* manipulate uart driver
*/
struct esp32s2_uart_s
{
uint8_t periph; /* UART peripheral ID */
int cpuint; /* CPU interrupt assigned to this UART */
uint8_t id; /* UART ID */
uint8_t irq; /* IRQ associated with this UART */
uint32_t baud; /* Configured baud rate */
uint8_t bits; /* Data length (5 to 8 bits). */
uint8_t parity; /* 0=no parity, 1=odd parity, 2=even parity */
uint8_t stop_b2; /* Use 2 stop bits? 0 = no (use 1) 1 = yes (use 2) */
uint8_t int_pri; /* UART Interrupt Priority */
uint8_t txpin; /* TX pin */
uint8_t txsig; /* TX signal */
uint8_t rxpin; /* RX pin */
uint8_t rxsig; /* RX signal */
};
extern struct esp32s2_uart_s g_uart0_config;
extern struct esp32s2_uart_s g_uart1_config;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s2_lowputc_enable_sysclk
*
* Description:
* Enable clock for the UART using the System register.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_enable_sysclk(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_enable_memclk
*
* Description:
* Enable memory clock gate enable signal.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_enable_memclk(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_disable_sysclk
*
* Description:
* Disable clock for the UART using the System register.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_disable_sysclk(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_disable_memclk
*
* Description:
* Disable memory clock gate enable signal.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_disable_memclk(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_set_sclk
*
* Description:
* Set a source clock for UART.
*
* Parameters:
* priv - Pointer to the private driver struct.
* source - REF_TICK = 0
* APB_CLK = 1 80 MHz
*
****************************************************************************/
void esp32s2_lowputc_set_sclk(const struct esp32s2_uart_s *priv,
enum uart_sclk source);
/****************************************************************************
* Name: esp32s2_lowputc_get_sclk
*
* Description:
* Get the source clock for UART.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
* Returned Value:
* The frequency of the clock in Hz.
*
****************************************************************************/
uint32_t esp32s2_lowputc_get_sclk(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_baud
*
* Description:
* Set the baud rate according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_baud(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_normal_mode
*
* Description:
* Set the UART to operate in normal mode, i.e., disable the RS485 mode and
* IRDA mode.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_normal_mode(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_parity
*
* Description:
* Set the parity, according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_parity(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_data_length
*
* Description:
* Set the data bits length, according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
int esp32s2_lowputc_data_length(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_stop_length
*
* Description:
* Set the stop bits length, according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_stop_length(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_send_byte
*
* Description:
* Send one byte.
*
* Parameters:
* priv - Pointer to the private driver struct.
* byte - Byte to be sent.
*
****************************************************************************/
void esp32s2_lowputc_send_byte(const struct esp32s2_uart_s *priv,
char byte);
/****************************************************************************
* Name: esp32s2_lowputc_is_tx_fifo_full
*
* Description:
* Verify if TX FIFO is full.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
* Returned Value:
* True if it is full, otherwise false.
*
****************************************************************************/
bool esp32s2_lowputc_is_tx_fifo_full(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_rst_peripheral
*
* Description:
* Reset the UART peripheral by using System reg.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_rst_peripheral(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_rst_txfifo
*
* Description:
* Reset TX FIFO.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_rst_txfifo(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_rst_rxfifo
*
* Description:
* Reset RX FIFO.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_rst_rxfifo(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_disable_all_uart_int
*
* Description:
* Disable all UART interrupts.
*
* Parameters:
* priv - Pointer to the private driver struct.
* current_status - Pointer to a variable to store the current status of
* the interrupt enable register before disabling
* UART interrupts.
*
****************************************************************************/
void esp32s2_lowputc_disable_all_uart_int(const struct esp32s2_uart_s *priv,
uint32_t *current_status);
/****************************************************************************
* Name: esp32s2_lowputc_restore_all_uart_int
*
* Description:
* Restore all UART interrupts.
*
* Parameters:
* priv - Pointer to the private driver struct.
* last_status - Pointer to a variable that stored the last state of the
* interrupt enable register.
*
****************************************************************************/
void esp32s2_lowputc_restore_all_uart_int(const struct esp32s2_uart_s *priv,
uint32_t * last_status);
/****************************************************************************
* Name: esp32s2_lowputc_config_pins
*
* Description:
* Configure TX and RX UART pins.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_config_pins(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowsetup
*
* Description:
* This performs basic initialization of the UART used for the serial
* console. Its purpose is to get the console output available as soon
* as possible.
*
****************************************************************************/
void esp32s2_lowsetup(void);
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_LOWPUTC_H */
arch/xtensa/src/esp32s2/esp32s2_pm.h
+218
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@@ -0,0 +1,218 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_pm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_PMSLEEP_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_PMSLEEP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#ifdef CONFIG_PM
/****************************************************************************
* Public Types
****************************************************************************/
/* Sleep wakeup cause */
enum esp32s2_sleep_source_e
{
/* In case of deep sleep, reset was not caused by exit from deep sleep */
ESP_SLEEP_WAKEUP_UNDEFINED,
/* Not a wakeup cause, used to disable all wakeup sources with
* esp_sleep_disable_wakeup_source
*/
ESP_SLEEP_WAKEUP_ALL,
/* Wakeup caused by external signal using RTC_IO */
ESP_SLEEP_WAKEUP_EXT0,
/* Wakeup caused by external signal using RTC_CNTL */
ESP_SLEEP_WAKEUP_EXT1,
/* Wakeup caused by timer */
ESP_SLEEP_WAKEUP_TIMER,
/* Wakeup caused by touchpad */
ESP_SLEEP_WAKEUP_TOUCHPAD,
/* Wakeup caused by ULP program */
ESP_SLEEP_WAKEUP_ULP,
/* Wakeup caused by GPIO (light sleep only) */
ESP_SLEEP_WAKEUP_GPIO,
/* Wakeup caused by UART (light sleep only) */
ESP_SLEEP_WAKEUP_UART,
};
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s2_sleep_enable_timer_wakeup
*
* Description:
* Configure wake-up interval
*
* Input Parameters:
* time_in_us - Configure wake-up time interval
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_sleep_enable_timer_wakeup(uint64_t time_in_us);
/****************************************************************************
* Name: esp32s2_light_sleep_start
*
* Description:
* Enter sleep mode
*
* Input Parameters:
* None
*
* Returned Value:
* 0 is returned on success or a negated errno value is returned
*
****************************************************************************/
int esp32s2_light_sleep_start(void);
/****************************************************************************
* Name: esp32s2_pminit
*
* Description:
* Initialize force sleep parameters.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_pminit(void);
/****************************************************************************
* Name: esp32s2_pmstandby
*
* Description:
* Enter force sleep time interval.
*
* Input Parameters:
* time_in_us - force sleep time interval
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_pmstandby(uint64_t time_in_us);
/****************************************************************************
* Name: esp32s2_sleep_get_wakeup_cause
*
* Description:
* Get the wakeup source which caused wakeup from sleep.
*
* Input Parameters:
* None
*
* Returned Value:
* enum esp32s2_sleep_source_e - Cause of wake up from last sleep.
*
****************************************************************************/
enum esp32s2_sleep_source_e esp32s2_sleep_get_wakeup_cause(void);
/****************************************************************************
* Name: esp32s2_deep_sleep_start
*
* Description:
* Enter deep sleep mode
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_deep_sleep_start(void);
/****************************************************************************
* Name: esp32s2_pmsleep
*
* Description:
* Enter deep sleep.
*
* Input Parameters:
* time_in_us - deep sleep time interval
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_pmsleep(uint64_t time_in_us);
#endif /* CONFIG_PM */
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_PMSLEEP_H */
arch/xtensa/src/esp32s2/esp32s2_region.c
+102
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/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_region.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
/****************************************************************************
* Private Data
****************************************************************************/
static const uint32_t g_protected_pages[] =
{
0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000
};
#define NPROTECTED_PAGES (sizeof(g_protected_pages)/sizeof(uint32_t))
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: xtensa_write_dtlb and xtensa_write_itlb
*
* Description:
* Functions to set page attributes for Region Protection option in the
* CPU. See Xtensa ISA Reference manual for explanation of arguments
* (section 4.6.3.2).
*
****************************************************************************/
static inline void xtensa_write_dtlb(uint32_t vpn, unsigned int attr)
{
__asm__ __volatile__
(
"wdtlb %1, %0\n"
"dsync\n"
: : "r" (vpn), "r" (attr)
);
}
static inline void xtensa_write_itlb(unsigned vpn, unsigned int attr)
{
__asm__ __volatile__
(
"witlb %1, %0\n"
"isync\n"
: : "r" (vpn), "r" (attr)
);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s2_region_protection
*
* Description:
* Make page 0 access raise an exception. Also protect some other unused
* pages so we can catch weirdness.
*
* Useful attribute values:
* 0 — cached, RW
* 2 — bypass cache, RWX (default value after CPU reset)
* 15 — no access, raise exception
*
****************************************************************************/
void esp32s2_region_protection(void)
{
int i;
for (i = 0; i < NPROTECTED_PAGES; ++i)
{
xtensa_write_dtlb(g_protected_pages[i], 0xf);
xtensa_write_itlb(g_protected_pages[i], 0xf);
}
xtensa_write_dtlb(0x20000000, 0);
xtensa_write_itlb(0x20000000, 0);
}
arch/xtensa/src/esp32s2/esp32s2_region.h
+52
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@@ -0,0 +1,52 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_region.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_REGION_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_REGION_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Name: esp32s2_region_protection
*
* Description:
* Make page 0 access raise an exception. Also protect some other unused
* pages so we can catch weirdness.
*
* Useful attribute values:
* 0 — cached, RW
* 2 — bypass cache, RWX (default value after CPU reset)
* 15 — no access, raise exception
*
****************************************************************************/
void esp32s2_region_protection(void);
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_REGION_H */
arch/xtensa/src/esp32s2/esp32s2_rtc.c
+562
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arch/xtensa/src/esp32s2/esp32s2_rtc.h
+358
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@@ -0,0 +1,358 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_rtc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/esp32s2_soc.h"
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Number of cycles to wait from the 32k XTAL oscillator to
* consider it running. Larger values increase startup delay.
* Smaller values may cause false positive detection
* (i.e. oscillator runs for a few cycles and then stops).
*/
#define SLOW_CLK_CAL_CYCLES 1024
/* Indicates that 32k oscillator gets input from external oscillator
* instead of a crystal.
*/
#define EXT_OSC_FLAG BIT(3)
/****************************************************************************
* Public Types
****************************************************************************/
/* Possible main XTAL frequency values.
* Enum values should be equal to frequency in MHz.
*/
enum esp32s2_rtc_xtal_freq_e
{
RTC_XTAL_FREQ_AUTO = 0, /* Automatic XTAL frequency detection */
RTC_XTAL_FREQ_40M = 40, /* 40 MHz XTAL */
RTC_XTAL_FREQ_26M = 26, /* 26 MHz XTAL */
RTC_XTAL_FREQ_24M = 24, /* 24 MHz XTAL */
};
/* RTC SLOW_CLK frequency values */
enum esp32s2_rtc_slow_freq_e
{
RTC_SLOW_FREQ_RTC = 0, /* Internal 150 kHz RC oscillator */
RTC_SLOW_FREQ_32K_XTAL = 1, /* External 32 kHz XTAL */
RTC_SLOW_FREQ_8MD256 = 2, /* Internal 8 MHz RC oscillator, divided by 256 */
};
/* RTC FAST_CLK frequency values */
enum esp32s2_rtc_fast_freq_e
{
RTC_FAST_FREQ_XTALD4 = 0, /* Main XTAL, divided by 4 */
RTC_FAST_FREQ_8M = 1, /* Internal 8 MHz RC oscillator */
};
/* This is almost the same as esp32s2_rtc_slow_freq_e, except that we define
* an extra enum member for the external 32k oscillator. For convenience,
* lower 2 bits should correspond to esp32s2_rtc_slow_freq_e values.
*/
enum esp32s2_slow_clk_sel_e
{
/* Internal 150 kHz RC oscillator */
SLOW_CLK_150K = RTC_SLOW_FREQ_RTC,
/* External 32 kHz XTAL */
SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL,
/* Internal 8 MHz RC oscillator, divided by 256 */
SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256,
/* External 32k oscillator connected to 32K_XP pin */
SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG
};
/* Clock source to be calibrated using rtc_clk_cal function */
enum esp32s2_rtc_cal_sel_e
{
RTC_CAL_RTC_MUX = 0, /* Currently selected RTC SLOW_CLK */
RTC_CAL_8MD256 = 1, /* Internal 8 MHz RC oscillator, divided by 256 */
RTC_CAL_32K_XTAL = 2 /* External 32 kHz XTAL */
};
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s2_rtc_get_slow_clk_rtc
*
* Description:
* Get slow_clk_rtc source.
*
* Input Parameters:
* None
*
* Returned Value:
* The clock source:
* - SLOW_CK
* - CK_XTAL_32K
* - CK8M_D256_OUT
*
****************************************************************************/
enum esp32s2_rtc_slow_freq_e esp32s2_rtc_get_slow_clk(void);
/****************************************************************************
* Name: esp32s2_rtc_clk_cal
*
* Description:
* Measure RTC slow clock's period, based on main XTAL frequency
*
* Input Parameters:
* cal_clk - clock to be measured
* slowclk_cycles - number of slow clock cycles to average
*
* Returned Value:
* Average slow clock period in microseconds, Q13.19 fixed point format
* or 0 if calibration has timed out
*
****************************************************************************/
uint32_t esp32s2_rtc_clk_cal(enum esp32s2_rtc_cal_sel_e cal_clk,
uint32_t slowclk_cycles);
/****************************************************************************
* Name: esp32s2_rtc_clk_xtal_freq_get
*
* Description:
* Get main XTAL frequency
*
* Input Parameters:
* None
*
* Returned Value:
* XTAL frequency (one of enum esp32s2_rtc_xtal_freq_e values)
*
****************************************************************************/
enum esp32s2_rtc_xtal_freq_e esp32s2_rtc_clk_xtal_freq_get(void);
/****************************************************************************
* Name: esp32s2_rtc_update_to_xtal
*
* Description:
* Switch to XTAL frequency, does not disable the PLL
*
* Input Parameters:
* freq - XTAL frequency
* div - REF_TICK divider
*
* Returned Value:
* none
*
****************************************************************************/
void esp32s2_rtc_update_to_xtal(int freq, int div);
/****************************************************************************
* Name: esp32s2_rtc_bbpll_enable
*
* Description:
* Reset BBPLL configuration.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_rtc_bbpll_enable(void);
/****************************************************************************
* Name: esp32s2_rtc_bbpll_configure
*
* Description:
* Configure main XTAL frequency values according to pll_freq.
*
* Input Parameters:
* xtal_freq - XTAL frequency values
* pll_freq - PLL frequency values
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_rtc_bbpll_configure(
enum esp32s2_rtc_xtal_freq_e xtal_freq, int pll_freq);
/****************************************************************************
* Name: esp32s2_rtc_clk_set
*
* Description:
* Set RTC CLK frequency.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_rtc_clk_set(void);
/****************************************************************************
* Name: esp32s2_rtc_init
*
* Description:
* Initialize RTC clock and power control related functions.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_rtc_init(void);
/****************************************************************************
* Name: esp32s2_rtc_time_get
*
* Description:
* Get current value of RTC counter.
*
* Input Parameters:
* None
*
* Returned Value:
* current value of RTC counter
*
****************************************************************************/
uint64_t esp32s2_rtc_time_get(void);
/****************************************************************************
* Name: esp32s2_rtc_wait_for_slow_cycle
*
* Description:
* Busy loop until next RTC_SLOW_CLK cycle.
*
* Input Parameters:
* None
*
* Returned Value:
* none
*
****************************************************************************/
void esp32s2_rtc_wait_for_slow_cycle(void);
/****************************************************************************
* Name: esp_rtc_clk_get_cpu_freq
*
* Description:
* Get the currently used CPU frequency configuration.
*
* Input Parameters:
* None
*
* Returned Value:
* CPU frequency
*
****************************************************************************/
int esp_rtc_clk_get_cpu_freq(void);
/****************************************************************************
* Name: esp32s2_rtc_sleep_init
*
* Description:
* Prepare the chip to enter sleep mode
*
* Input Parameters:
* flags - sleep mode configuration
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_rtc_sleep_init(uint32_t flags);
/****************************************************************************
* Name: esp32s2_rtc_sleep_start
*
* Description:
* Enter force sleep mode.
*
* Input Parameters:
* wakeup_opt - bit mask wake up reasons to enable
* reject_opt - bit mask of sleep reject reasons.
*
* Returned Value:
* non-zero if sleep was rejected by hardware
*
****************************************************************************/
int esp32s2_rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_H */
arch/xtensa/src/esp32s2/esp32s2_serial.c
+1031
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arch/xtensa/src/esp32s2/esp32s2_start.c
+169
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/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_start.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <string.h>
#include <nuttx/init.h>
#include <nuttx/irq.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "hardware/esp32s2_rtccntl.h"
#include "esp32s2_clockconfig.h"
#include "esp32s2_region.h"
#include "esp32s2_start.h"
#include "esp32s2_lowputc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) up_lowputc(c)
#else
# define showprogress(c)
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* Address of the CPU0 IDLE thread */
uint32_t g_idlestack[IDLETHREAD_STACKWORDS]
__attribute__((aligned(16), section(".noinit")));
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: __start
*
* Description:
* We arrive here after the bootloader finished loading the program from
* flash. The hardware is mostly uninitialized, and the app CPU is in
* reset. We do have a stack, so we can do the initialization in C.
*
****************************************************************************/
void IRAM_ATTR __start(void)
{
uint32_t *dest;
uint32_t regval;
uint32_t sp;
/* Kill the watchdog timer */
regval = getreg32(RTC_CNTL_WDTCONFIG0_REG);
regval &= ~RTC_CNTL_WDT_FLASHBOOT_MOD_EN;
putreg32(regval, RTC_CNTL_WDTCONFIG0_REG);
regval = getreg32(DR_REG_BB_BASE + 0x48); /* DR_REG_BB_BASE+48 */
regval &= ~(1 << 14);
putreg32(regval, DR_REG_BB_BASE + 0x48);
/* Make sure that normal interrupts are disabled. This is really only an
* issue when we are started in un-usual ways (such as from IRAM). In this
* case, we can at least defer some unexpected interrupts left over from
* the last program execution.
*/
up_irq_disable();
/* Set CPU frequency configured in board.h */
esp32s2_clockconfig();
esp32s2_lowsetup();
#ifdef USE_EARLYSERIALINIT
/* Perform early serial initialization */
xtensa_earlyserialinit();
#endif
#ifdef CONFIG_STACK_COLORATION
{
register uint32_t *ptr;
register int i;
/* If stack debug is enabled, then fill the stack with a recognizable
* value that we can use later to test for high water marks.
*/
for (i = 0, ptr = g_idlestack; i < IDLETHREAD_STACKWORDS; i++)
{
*ptr++ = STACK_COLOR;
}
}
#endif
/* Move the stack to a known location. Although we were given a stack
* pointer at start-up, we don't know where that stack pointer is
* positioned with respect to our memory map. The only safe option is to
* switch to a well-known IDLE thread stack.
*/
sp = (uint32_t)g_idlestack + IDLETHREAD_STACKSIZE;
__asm__ __volatile__("mov sp, %0\n" : : "r"(sp));
/* Make page 0 access raise an exception */
esp32s2_region_protection();
/* Move CPU0 exception vectors to IRAM */
__asm__ __volatile__ ("wsr %0, vecbase\n"::"r" (&_init_start));
showprogress('A');
/* Set .bss to zero */
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
* certain that there are no issues with the state of global variables.
*/
for (dest = &_sbss; dest < &_ebss; dest++)
{
*dest = 0;
}
showprogress('B');
/* Initialize onboard resources */
esp32s2_board_initialize();
showprogress('C');
/* Bring up NuttX */
nx_start();
for (; ; ); /* Should not return */
}
arch/xtensa/src/esp32s2/esp32s2_start.h
+54
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@@ -0,0 +1,54 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_start.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_START_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_START_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Name: esp32s2_board_initialize
*
* Description:
* Board-specific logic is initialized by calling this function. This
* entry point is called early in the initialization -- after all memory
* has been configured but before any devices have been initialized.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_board_initialize(void);
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_START_H */
arch/xtensa/src/esp32s2/esp32s2_systemreset.c
+54
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@@ -0,0 +1,54 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_systemreset.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include "xtensa.h"
#include "hardware/esp32s2_rtccntl.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_systemreset
*
* Description:
* Internal reset logic.
*
****************************************************************************/
void up_systemreset(void)
{
putreg32(RTC_CNTL_SW_SYS_RST, RTC_CNTL_OPTIONS0_REG);
/* Wait for the reset */
for (; ; );
}
arch/xtensa/src/esp32s2/esp32s2_timerisr.c
+185
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@@ -0,0 +1,185 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_timerisr.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <arch/xtensa/xtensa_specregs.h>
#include <arch/board/board.h>
#include "clock/clock.h"
#include "xtensa_timer.h"
#include "xtensa.h"
/****************************************************************************
* Private data
****************************************************************************/
static uint32_t g_tick_divisor;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: xtensa_getcount, xtensa_getcompare, and xtensa_setcompare
*
* Description:
* Lower level operations on Xtensa special registers.
*
****************************************************************************/
/* Return the current value of the cycle count register */
static inline uint32_t xtensa_getcount(void)
{
uint32_t count;
__asm__ __volatile__
(
"rsr %0, CCOUNT" : "=r"(count)
);
return count;
}
/* Return the old value of the compare register */
static inline uint32_t xtensa_getcompare(void)
{
uint32_t compare;
__asm__ __volatile__
(
"rsr %0, %1" : "=r"(compare) : "I"(XT_CCOMPARE)
);
return compare;
}
/* Set the value of the compare register */
static inline void xtensa_setcompare(uint32_t compare)
{
__asm__ __volatile__
(
"wsr %0, %1" : : "r"(compare), "I"(XT_CCOMPARE)
);
}
/****************************************************************************
* Function: esp32s2_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
* of the systems.
*
* Xtensa timers work by comparing a cycle counter with a preset value.
* Once the match occurs an interrupt is generated, and the handler has to
* set a new cycle count into the comparator. To avoid clock drift due to
* interrupt latency, the new cycle count is computed from the old, not the
* time the interrupt was serviced. However if a timer interrupt is ever
* serviced more than one tick late, it is necessary to process multiple
* ticks until the new cycle count is in the future, otherwise the next
* timer interrupt would not occur until after the cycle counter had
* wrapped (2^32 cycles later).
*
****************************************************************************/
static int esp32s2_timerisr(int irq, uint32_t *regs, FAR void *arg)
{
uint32_t divisor;
uint32_t compare;
uint32_t diff;
divisor = g_tick_divisor;
do
{
/* Increment the compare register for the next tick */
compare = xtensa_getcompare();
xtensa_setcompare(compare + divisor);
/* Process one timer tick */
nxsched_process_timer();
/* Check if we are falling behind and need to process multiple timer
* interrupts.
*/
diff = xtensa_getcount() - compare;
}
while (diff >= divisor);
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: up_timer_initialize
*
* Description:
* This function is called during start-up to initialize
* the timer interrupt.
*
****************************************************************************/
void up_timer_initialize(void)
{
uint32_t divisor;
uint32_t count;
/* Configured the timer0 as the system timer.
*
* divisor = BOARD_CLOCK_FREQUENCY / ticks_per_sec
*/
divisor = BOARD_CLOCK_FREQUENCY / CLOCKS_PER_SEC;
g_tick_divisor = divisor;
/* Set up periodic timer */
count = xtensa_getcount();
xtensa_setcompare(count + divisor);
/* NOTE: Timer 0 is an internal interrupt source so we do not need to
* attach any peripheral ID to the dedicated CPU interrupt.
*/
/* Attach the timer interrupt */
irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32s2_timerisr, NULL);
/* Enable the timer 0 CPU interrupt. */
up_enable_irq(ESP32S2_CPUINT_TIMER0);
}
arch/xtensa/src/esp32s2/esp32s2_user.c
+395
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@@ -0,0 +1,395 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_user.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <arch/loadstore.h>
#include <arch/xtensa/core.h>
#include <sys/types.h>
#include <debug.h>
#include "xtensa.h"
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef CONFIG_ARCH_USE_MODULE_TEXT
extern uint32_t _smodtext;
extern uint32_t _emodtext;
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
#ifdef CONFIG_ARCH_USE_MODULE_TEXT
#ifdef CONFIG_ENDIAN_BIG
#error not implemented
#endif
#ifndef CONFIG_BUILD_FLAT
#error permission check not implemented
#endif
/****************************************************************************
* Name: load_uint8
*
* Description:
* Fetch a byte using 32-bit aligned access.
*
****************************************************************************/
static uint8_t load_uint8(const uint8_t *p)
{
const uint32_t *aligned;
uint32_t value;
unsigned int offset;
aligned = (const uint32_t *)(((uintptr_t)p) & ~3);
value = l32i(aligned);
offset = ((uintptr_t)p) & 3;
switch (offset)
{
case 0:
return value & 0xff;
case 1:
return (value >> 8) & 0xff;
case 2:
return (value >> 16) & 0xff;
case 3:
return (value >> 24) & 0xff;
}
/* not reached */
PANIC();
}
/****************************************************************************
* Name: store_uint8
*
* Description:
* Store a byte using 32-bit aligned access.
*
****************************************************************************/
static void store_uint8(uint8_t *p, uint8_t v)
{
uint32_t *aligned;
uint32_t value;
unsigned int offset;
aligned = (uint32_t *)(((uintptr_t)p) & ~3);
value = l32i(aligned);
offset = ((uintptr_t)p) & 3;
switch (offset)
{
case 0:
value = (value & 0xffffff00) | v;
break;
case 1:
value = (value & 0xffff00ff) | (v << 8);
break;
case 2:
value = (value & 0xff00ffff) | (v << 16);
break;
case 3:
value = (value & 0x00ffffff) | (v << 24);
break;
}
s32i(aligned, value);
}
/****************************************************************************
* Name: decode_s8i
*
* Description:
* Decode S8I instruction using 32-bit aligned access.
* Return non-zero on successful decoding.
*
****************************************************************************/
static int decode_s8i(const uint8_t *p, uint8_t *imm8, uint8_t *s,
uint8_t *t)
{
/* 23 16 15 12 11 8 7 4 3 0
* | imm8 |0 1 0 0| s | t |0 0 1 0|
*/
uint8_t b0 = load_uint8(p);
uint8_t b1 = load_uint8(p + 1);
if ((b0 & 0xf) == 2 && (b1 & 0xf0) == 0x40)
{
*t = b0 >> 4;
*s = b1 & 0xf;
*imm8 = load_uint8(p + 2);
return 1;
}
return 0;
}
/****************************************************************************
* Name: decode_s16i
*
* Description:
* Decode S16I instruction using 32-bit aligned access.
* Return non-zero on successful decoding.
*
****************************************************************************/
static int decode_s16i(const uint8_t *p, uint8_t *imm8, uint8_t *s,
uint8_t *t)
{
/* 23 16 15 12 11 8 7 4 3 0
* | imm8 |0 1 0 1| s | t |0 0 1 0|
*/
uint8_t b0 = load_uint8(p);
uint8_t b1 = load_uint8(p + 1);
if ((b0 & 0xf) == 2 && (b1 & 0xf0) == 0x50)
{
*t = b0 >> 4;
*s = b1 & 0xf;
*imm8 = load_uint8(p + 2);
return 1;
}
return 0;
}
/****************************************************************************
* Name: decode_l8ui
*
* Description:
* Decode L8UI instruction using 32-bit aligned access.
* Return non-zero on successful decoding.
*
****************************************************************************/
static int decode_l8ui(const uint8_t *p, uint8_t *imm8, uint8_t *s,
uint8_t *t)
{
/* 23 16 15 12 11 8 7 4 3 0
* | imm8 |0 0 0 0| s | t |0 0 1 0|
*/
uint8_t b0 = load_uint8(p);
uint8_t b1 = load_uint8(p + 1);
if ((b0 & 0xf) == 2 && (b1 & 0xf0) == 0)
{
*t = b0 >> 4;
*s = b1 & 0xf;
*imm8 = load_uint8(p + 2);
return 1;
}
return 0;
}
/****************************************************************************
* Name: decode_l16ui
*
* Description:
* Decode L16UI instruction using 32-bit aligned access.
* Return non-zero on successful decoding.
*
****************************************************************************/
static int decode_l16ui(const uint8_t *p, uint8_t *imm8, uint8_t *s,
uint8_t *t)
{
/* 23 16 15 12 11 8 7 4 3 0
* | imm8 |0 0 0 1| s | t |0 0 1 0|
*/
uint8_t b0 = load_uint8(p);
uint8_t b1 = load_uint8(p + 1);
if ((b0 & 0xf) == 2 && (b1 & 0xf0) == 0x10)
{
*t = b0 >> 4;
*s = b1 & 0xf;
*imm8 = load_uint8(p + 2);
return 1;
}
return 0;
}
/****************************************************************************
* Name: advance_pc
*
* Description:
* Advance PC register by the given value.
*
****************************************************************************/
static void advance_pc(uint32_t *regs, int diff)
{
uint32_t nextpc;
/* Advance to the next instruction. */
nextpc = regs[REG_PC] + diff;
#if XCHAL_HAVE_LOOPS
/* See Xtensa ISA 4.3.2.4 Loopback Semantics */
if (regs[REG_LCOUNT] != 0 && nextpc == regs[REG_LEND])
{
regs[REG_LCOUNT]--;
nextpc = regs[REG_LBEG];
}
#endif
regs[REG_PC] = nextpc;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xtensa_user
*
* Description:
* ESP32S2-specific user exception handler.
*
****************************************************************************/
uint32_t *xtensa_user(int exccause, uint32_t *regs)
{
#ifdef CONFIG_ARCH_USE_MODULE_TEXT
/* Emulate byte access for module text.
*
* ESP32S2 only allows word-aligned accesses to the instruction memory
* regions. A non-aligned access raises a LoadStoreErrorCause exception.
* We catch those exception and emulate byte access here because it's
* necessary in a few places during dynamic code loading:
*
* - memcpy as a part of read(2) when loading code from a file system.
* - relocation needs to inspect and modify text.
*
* (thus binfo() is used below)
*/
if (exccause == XCHAL_EXCCAUSE_LOAD_STORE_ERROR &&
(uintptr_t)&_smodtext <= regs[REG_EXCVADDR] &&
(uintptr_t)&_emodtext > regs[REG_EXCVADDR])
{
uint8_t *pc = (uint8_t *)regs[REG_PC];
uint8_t imm8;
uint8_t s;
uint8_t t;
binfo("XCHAL_EXCCAUSE_LOAD_STORE_ERROR at %p, pc=%p\n",
(FAR void *)regs[REG_EXCVADDR],
pc);
if (decode_s8i(pc, &imm8, &s, &t))
{
binfo("Emulating S8I imm8=%u, s=%u (%p), t=%u (%p)\n",
(unsigned int)imm8,
(unsigned int)s,
(void *)regs[REG_A0 + s],
(unsigned int)t,
(void *)regs[REG_A0 + t]);
DEBUGASSERT(regs[REG_A0 + s] + imm8 == regs[REG_EXCVADDR]);
store_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8,
regs[REG_A0 + t]);
advance_pc(regs, 3);
return regs;
}
else if (decode_s16i(pc, &imm8, &s, &t))
{
binfo("Emulating S16I imm8=%u, s=%u (%p), t=%u (%p)\n",
(unsigned int)imm8,
(unsigned int)s,
(void *)regs[REG_A0 + s],
(unsigned int)t,
(void *)regs[REG_A0 + t]);
DEBUGASSERT(regs[REG_A0 + s] + imm8 == regs[REG_EXCVADDR]);
store_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8,
regs[REG_A0 + t]);
store_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8 + 1,
regs[REG_A0 + t] >> 8);
advance_pc(regs, 3);
return regs;
}
else if (decode_l8ui(pc, &imm8, &s, &t))
{
binfo("Emulating L8UI imm8=%u, s=%u (%p), t=%u (%p)\n",
(unsigned int)imm8,
(unsigned int)s,
(void *)regs[REG_A0 + s],
(unsigned int)t,
(void *)regs[REG_A0 + t]);
DEBUGASSERT(regs[REG_A0 + s] + imm8 == regs[REG_EXCVADDR]);
regs[REG_A0 + t] = load_uint8(((uint8_t *)regs[REG_A0 + s]) +
imm8);
advance_pc(regs, 3);
return regs;
}
else if (decode_l16ui(pc, &imm8, &s, &t))
{
binfo("Emulating L16UI imm8=%u, s=%u (%p), t=%u (%p)\n",
(unsigned int)imm8,
(unsigned int)s,
(void *)regs[REG_A0 + s],
(unsigned int)t,
(void *)regs[REG_A0 + t]);
DEBUGASSERT(regs[REG_A0 + s] + imm8 == regs[REG_EXCVADDR]);
uint8_t lo = load_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8);
uint8_t hi = load_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8 + 1);
regs[REG_A0 + t] = (hi << 8) | lo;
advance_pc(regs, 3);
return regs;
}
}
#endif
/* xtensa_user_panic never returns. */
xtensa_user_panic(exccause, regs);
while (1)
{
}
}
arch/xtensa/src/esp32s2/hardware/esp32s2_aes.h
+780
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File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h
+3282
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File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32s2/hardware/esp32s2_gpio.h
+16494
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File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32s2/hardware/esp32s2_gpio_sigmap.h
+327
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@@ -0,0 +1,327 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/hardware/esp32s2_gpio_sigmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_SIGMAP_H
#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_SIGMAP_H
#define SPICLK_OUT_IDX SPICLK_OUT_MUX_IDX
#define CLK_I2S_IDX CLK_I2S_MUX_IDX
#define FSPICLK_OUT_IDX FSPICLK_OUT_MUX_IDX
#define SPIQ_IN_IDX 0
#define SPIQ_OUT_IDX 0
#define SPID_IN_IDX 1
#define SPID_OUT_IDX 1
#define SPIHD_IN_IDX 2
#define SPIHD_OUT_IDX 2
#define SPIWP_IN_IDX 3
#define SPIWP_OUT_IDX 3
#define SPICLK_OUT_MUX_IDX 4
#define SPICS0_OUT_IDX 5
#define SPICS1_OUT_IDX 6
#define SPID4_IN_IDX 7
#define SPID4_OUT_IDX 7
#define SPID5_IN_IDX 8
#define SPID5_OUT_IDX 8
#define SPID6_IN_IDX 9
#define SPID6_OUT_IDX 9
#define SPID7_IN_IDX 10
#define SPID7_OUT_IDX 10
#define SPIDQS_IN_IDX 11
#define SPIDQS_OUT_IDX 11
#define U0RXD_IN_IDX 14
#define U0TXD_OUT_IDX 14
#define U0CTS_IN_IDX 15
#define U0RTS_OUT_IDX 15
#define U0DSR_IN_IDX 16
#define U0DTR_OUT_IDX 16
#define U1RXD_IN_IDX 17
#define U1TXD_OUT_IDX 17
#define U1CTS_IN_IDX 18
#define U1RTS_OUT_IDX 18
#define U1DSR_IN_IDX 21
#define U1DTR_OUT_IDX 21
#define I2S0O_BCK_IN_IDX 23
#define I2S0O_BCK_OUT_IDX 23
#define I2S0O_WS_IN_IDX 25
#define I2S0O_WS_OUT_IDX 25
#define I2S0I_BCK_IN_IDX 27
#define I2S0I_BCK_OUT_IDX 27
#define I2S0I_WS_IN_IDX 28
#define I2S0I_WS_OUT_IDX 28
#define I2CEXT0_SCL_IN_IDX 29
#define I2CEXT0_SCL_OUT_IDX 29
#define I2CEXT0_SDA_IN_IDX 30
#define I2CEXT0_SDA_OUT_IDX 30
#define SDIO_TOHOST_INT_OUT_IDX 31
#define GPIO_BT_ACTIVE_IDX 37
#define GPIO_BT_PRIORITY_IDX 38
#define PCNT_SIG_CH0_IN0_IDX 39
#define GPIO_WLAN_PRIO_IDX 39
#define PCNT_SIG_CH1_IN0_IDX 40
#define GPIO_WLAN_ACTIVE_IDX 40
#define PCNT_CTRL_CH0_IN0_IDX 41
#define BB_DIAG0_IDX 41
#define PCNT_CTRL_CH1_IN0_IDX 42
#define BB_DIAG1_IDX 42
#define PCNT_SIG_CH0_IN1_IDX 43
#define BB_DIAG2_IDX 43
#define PCNT_SIG_CH1_IN1_IDX 44
#define BB_DIAG3_IDX 44
#define PCNT_CTRL_CH0_IN1_IDX 45
#define BB_DIAG4_IDX 45
#define PCNT_CTRL_CH1_IN1_IDX 46
#define BB_DIAG5_IDX 46
#define PCNT_SIG_CH0_IN2_IDX 47
#define BB_DIAG6_IDX 47
#define PCNT_SIG_CH1_IN2_IDX 48
#define BB_DIAG7_IDX 48
#define PCNT_CTRL_CH0_IN2_IDX 49
#define BB_DIAG8_IDX 49
#define PCNT_CTRL_CH1_IN2_IDX 50
#define BB_DIAG9_IDX 50
#define PCNT_SIG_CH0_IN3_IDX 51
#define BB_DIAG10_IDX 51
#define PCNT_SIG_CH1_IN3_IDX 52
#define BB_DIAG11_IDX 52
#define PCNT_CTRL_CH0_IN3_IDX 53
#define BB_DIAG12_IDX 53
#define PCNT_CTRL_CH1_IN3_IDX 54
#define BB_DIAG13_IDX 54
#define BB_DIAG14_IDX 55
#define BB_DIAG15_IDX 56
#define BB_DIAG16_IDX 57
#define BB_DIAG17_IDX 58
#define BB_DIAG18_IDX 59
#define BB_DIAG19_IDX 60
#define USB_EXTPHY_VP_IDX 61
#define USB_EXTPHY_OEN_IDX 61
#define USB_EXTPHY_VM_IDX 62
#define USB_EXTPHY_SPEED_IDX 62
#define USB_EXTPHY_RCV_IDX 63
#define USB_EXTPHY_VPO_IDX 63
#define USB_OTG_IDDIG_IN_IDX 64
#define USB_EXTPHY_VMO_IDX 64
#define USB_OTG_AVALID_IN_IDX 65
#define USB_EXTPHY_SUSPND_IDX 65
#define USB_SRP_BVALID_IN_IDX 66
#define USB_OTG_IDPULLUP_IDX 66
#define USB_OTG_VBUSVALID_IN_IDX 67
#define USB_OTG_DPPULLDOWN_IDX 67
#define USB_SRP_SESSEND_IN_IDX 68
#define USB_OTG_DMPULLDOWN_IDX 68
#define USB_OTG_DRVVBUS_IDX 69
#define USB_SRP_CHRGVBUS_IDX 70
#define USB_SRP_DISCHRGVBUS_IDX 71
#define SPI3_CLK_IN_IDX 72
#define SPI3_CLK_OUT_MUX_IDX 72
#define SPI3_Q_IN_IDX 73
#define SPI3_Q_OUT_IDX 73
#define SPI3_D_IN_IDX 74
#define SPI3_D_OUT_IDX 74
#define SPI3_HD_IN_IDX 75
#define SPI3_HD_OUT_IDX 75
#define SPI3_CS0_IN_IDX 76
#define SPI3_CS0_OUT_IDX 76
#define SPI3_CS1_OUT_IDX 77
#define SPI3_CS2_OUT_IDX 78
#define LEDC_LS_SIG_OUT0_IDX 79
#define LEDC_LS_SIG_OUT1_IDX 80
#define LEDC_LS_SIG_OUT2_IDX 81
#define LEDC_LS_SIG_OUT3_IDX 82
#define RMT_SIG_IN0_IDX 83
#define LEDC_LS_SIG_OUT4_IDX 83
#define RMT_SIG_IN1_IDX 84
#define LEDC_LS_SIG_OUT5_IDX 84
#define RMT_SIG_IN2_IDX 85
#define LEDC_LS_SIG_OUT6_IDX 85
#define RMT_SIG_IN3_IDX 86
#define LEDC_LS_SIG_OUT7_IDX 86
#define RMT_SIG_OUT0_IDX 87
#define RMT_SIG_OUT1_IDX 88
#define RMT_SIG_OUT2_IDX 89
#define RMT_SIG_OUT3_IDX 90
#define EXT_ADC_START_IDX 93
#define I2CEXT1_SCL_IN_IDX 95
#define I2CEXT1_SCL_OUT_IDX 95
#define I2CEXT1_SDA_IN_IDX 96
#define I2CEXT1_SDA_OUT_IDX 96
#define GPIO_SD0_OUT_IDX 100
#define GPIO_SD1_OUT_IDX 101
#define GPIO_SD2_OUT_IDX 102
#define GPIO_SD3_OUT_IDX 103
#define GPIO_SD4_OUT_IDX 104
#define GPIO_SD5_OUT_IDX 105
#define GPIO_SD6_OUT_IDX 106
#define GPIO_SD7_OUT_IDX 107
#define FSPICLK_IN_IDX 108
#define FSPICLK_OUT_MUX_IDX 108
#define FSPIQ_IN_IDX 109
#define FSPIQ_OUT_IDX 109
#define FSPID_IN_IDX 110
#define FSPID_OUT_IDX 110
#define FSPIHD_IN_IDX 111
#define FSPIHD_OUT_IDX 111
#define FSPIWP_IN_IDX 112
#define FSPIWP_OUT_IDX 112
#define FSPIIO4_IN_IDX 113
#define FSPIIO4_OUT_IDX 113
#define FSPIIO5_IN_IDX 114
#define FSPIIO5_OUT_IDX 114
#define FSPIIO6_IN_IDX 115
#define FSPIIO6_OUT_IDX 115
#define FSPIIO7_IN_IDX 116
#define FSPIIO7_OUT_IDX 116
#define FSPICS0_IN_IDX 117
#define FSPICS0_OUT_IDX 117
#define FSPICS1_OUT_IDX 118
#define FSPICS2_OUT_IDX 119
#define FSPICS3_OUT_IDX 120
#define FSPICS4_OUT_IDX 121
#define FSPICS5_OUT_IDX 122
#define TWAI_RX_IDX 123
#define TWAI_TX_IDX 123
#define TWAI_BUS_OFF_ON_IDX 124
#define TWAI_CLKOUT_IDX 125
#define SUBSPICLK_OUT_MUX_IDX 126
#define SUBSPIQ_IN_IDX 127
#define SUBSPIQ_OUT_IDX 127
#define SUBSPID_IN_IDX 128
#define SUBSPID_OUT_IDX 128
#define SUBSPIHD_IN_IDX 129
#define SUBSPIHD_OUT_IDX 129
#define SUBSPIWP_IN_IDX 130
#define SUBSPIWP_OUT_IDX 130
#define SUBSPICS0_OUT_IDX 131
#define SUBSPICS1_OUT_IDX 132
#define FSPIDQS_OUT_IDX 133
#define FSPI_HSYNC_OUT_IDX 134
#define FSPI_VSYNC_OUT_IDX 135
#define FSPI_DE_OUT_IDX 136
#define FSPICD_OUT_IDX 137
#define SPI3_CD_OUT_IDX 139
#define SPI3_DQS_OUT_IDX 140
#define I2S0I_DATA_IN0_IDX 143
#define I2S0O_DATA_OUT0_IDX 143
#define I2S0I_DATA_IN1_IDX 144
#define I2S0O_DATA_OUT1_IDX 144
#define I2S0I_DATA_IN2_IDX 145
#define I2S0O_DATA_OUT2_IDX 145
#define I2S0I_DATA_IN3_IDX 146
#define I2S0O_DATA_OUT3_IDX 146
#define I2S0I_DATA_IN4_IDX 147
#define I2S0O_DATA_OUT4_IDX 147
#define I2S0I_DATA_IN5_IDX 148
#define I2S0O_DATA_OUT5_IDX 148
#define I2S0I_DATA_IN6_IDX 149
#define I2S0O_DATA_OUT6_IDX 149
#define I2S0I_DATA_IN7_IDX 150
#define I2S0O_DATA_OUT7_IDX 150
#define I2S0I_DATA_IN8_IDX 151
#define I2S0O_DATA_OUT8_IDX 151
#define I2S0I_DATA_IN9_IDX 152
#define I2S0O_DATA_OUT9_IDX 152
#define I2S0I_DATA_IN10_IDX 153
#define I2S0O_DATA_OUT10_IDX 153
#define I2S0I_DATA_IN11_IDX 154
#define I2S0O_DATA_OUT11_IDX 154
#define I2S0I_DATA_IN12_IDX 155
#define I2S0O_DATA_OUT12_IDX 155
#define I2S0I_DATA_IN13_IDX 156
#define I2S0O_DATA_OUT13_IDX 156
#define I2S0I_DATA_IN14_IDX 157
#define I2S0O_DATA_OUT14_IDX 157
#define I2S0I_DATA_IN15_IDX 158
#define I2S0O_DATA_OUT15_IDX 158
#define I2S0O_DATA_OUT16_IDX 159
#define I2S0O_DATA_OUT17_IDX 160
#define I2S0O_DATA_OUT18_IDX 161
#define I2S0O_DATA_OUT19_IDX 162
#define I2S0O_DATA_OUT20_IDX 163
#define I2S0O_DATA_OUT21_IDX 164
#define I2S0O_DATA_OUT22_IDX 165
#define I2S0O_DATA_OUT23_IDX 166
#define SUBSPID4_IN_IDX 167
#define SUBSPID4_OUT_IDX 167
#define SUBSPID5_IN_IDX 168
#define SUBSPID5_OUT_IDX 168
#define SUBSPID6_IN_IDX 169
#define SUBSPID6_OUT_IDX 169
#define SUBSPID7_IN_IDX 170
#define SUBSPID7_OUT_IDX 170
#define SUBSPIDQS_IN_IDX 171
#define SUBSPIDQS_OUT_IDX 171
#define I2S0I_H_SYNC_IDX 193
#define I2S0I_V_SYNC_IDX 194
#define I2S0I_H_ENABLE_IDX 195
#define PCMFSYNC_IN_IDX 203
#define BT_AUDIO0_IRQ_IDX 203
#define PCMCLK_IN_IDX 204
#define BT_AUDIO1_IRQ_IDX 204
#define PCMDIN_IDX 205
#define BT_AUDIO2_IRQ_IDX 205
#define RW_WAKEUP_REQ_IDX 206
#define BLE_AUDIO0_IRQ_IDX 206
#define BLE_AUDIO1_IRQ_IDX 207
#define BLE_AUDIO2_IRQ_IDX 208
#define PCMFSYNC_OUT_IDX 209
#define PCMCLK_OUT_IDX 210
#define PCMDOUT_IDX 211
#define BLE_AUDIO_SYNC0_P_IDX 212
#define BLE_AUDIO_SYNC1_P_IDX 213
#define BLE_AUDIO_SYNC2_P_IDX 214
#define ANT_SEL0_IDX 215
#define ANT_SEL1_IDX 216
#define ANT_SEL2_IDX 217
#define ANT_SEL3_IDX 218
#define ANT_SEL4_IDX 219
#define ANT_SEL5_IDX 220
#define ANT_SEL6_IDX 221
#define ANT_SEL7_IDX 222
#define SIG_IN_FUNC_223_IDX 223
#define SIG_IN_FUNC223_IDX 223
#define SIG_IN_FUNC_224_IDX 224
#define SIG_IN_FUNC224_IDX 224
#define SIG_IN_FUNC_225_IDX 225
#define SIG_IN_FUNC225_IDX 225
#define SIG_IN_FUNC_226_IDX 226
#define SIG_IN_FUNC226_IDX 226
#define SIG_IN_FUNC_227_IDX 227
#define SIG_IN_FUNC227_IDX 227
#define PRO_ALONEGPIO_IN0_IDX 235
#define PRO_ALONEGPIO_OUT0_IDX 235
#define PRO_ALONEGPIO_IN1_IDX 236
#define PRO_ALONEGPIO_OUT1_IDX 236
#define PRO_ALONEGPIO_IN2_IDX 237
#define PRO_ALONEGPIO_OUT2_IDX 237
#define PRO_ALONEGPIO_IN3_IDX 238
#define PRO_ALONEGPIO_OUT3_IDX 238
#define PRO_ALONEGPIO_IN4_IDX 239
#define PRO_ALONEGPIO_OUT4_IDX 239
#define PRO_ALONEGPIO_IN5_IDX 240
#define PRO_ALONEGPIO_OUT5_IDX 240
#define PRO_ALONEGPIO_IN6_IDX 241
#define PRO_ALONEGPIO_OUT6_IDX 241
#define PRO_ALONEGPIO_IN7_IDX 242
#define PRO_ALONEGPIO_OUT7_IDX 242
#define CLK_I2S_MUX_IDX 251
#define SIG_GPIO_OUT_IDX 256
#define GPIO_MAP_DATE_IDX 0x1904100
#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_SIGMAP_H */
arch/xtensa/src/esp32s2/hardware/esp32s2_i2cbbpll.h
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/****************************************************************************
* arch/xtensa/src/esp32s2/hardware/esp32s2_i2cbbpll.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2CBBPLL_H
#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2CBBPLL_H
/**
* Register definitions for digital PLL (BBPLL)
*
* This file lists register fields of BBPLL, located on an internal
* configuration bus. These definitions are used via macros defined in
* regi2c_ctrl.h, by rtc_clk_cpu_freq_set function in rtc_clk.c.
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 1
#define I2C_BBPLL_IR_CAL_DELAY 0
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
#define I2C_BBPLL_IR_CAL_CK_DIV 0
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4
#define I2C_BBPLL_IR_CAL_EXT_CAP 1
#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3
#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0
#define I2C_BBPLL_IR_CAL_ENX_CAP 1
#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4
#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4
#define I2C_BBPLL_IR_CAL_RSTB 1
#define I2C_BBPLL_IR_CAL_RSTB_MSB 5
#define I2C_BBPLL_IR_CAL_RSTB_LSB 5
#define I2C_BBPLL_IR_CAL_START 1
#define I2C_BBPLL_IR_CAL_START_MSB 6
#define I2C_BBPLL_IR_CAL_START_LSB 6
#define I2C_BBPLL_IR_CAL_UNSTOP 1
#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7
#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7
#define I2C_BBPLL_OC_REF_DIV 2
#define I2C_BBPLL_OC_REF_DIV_MSB 3
#define I2C_BBPLL_OC_REF_DIV_LSB 0
#define I2C_BBPLL_OC_DCHGP 2
#define I2C_BBPLL_OC_DCHGP_MSB 6
#define I2C_BBPLL_OC_DCHGP_LSB 4
#define I2C_BBPLL_OC_ENB_FCAL 2
#define I2C_BBPLL_OC_ENB_FCAL_MSB 7
#define I2C_BBPLL_OC_ENB_FCAL_LSB 7
#define I2C_BBPLL_OC_DIV_7_0 3
#define I2C_BBPLL_OC_DIV_7_0_MSB 7
#define I2C_BBPLL_OC_DIV_7_0_LSB 0
#define I2C_BBPLL_RSTB_DIV_ADC 4
#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0
#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0
#define I2C_BBPLL_MODE_HF 4
#define I2C_BBPLL_MODE_HF_MSB 1
#define I2C_BBPLL_MODE_HF_LSB 1
#define I2C_BBPLL_DIV_ADC 4
#define I2C_BBPLL_DIV_ADC_MSB 3
#define I2C_BBPLL_DIV_ADC_LSB 2
#define I2C_BBPLL_DIV_DAC 4
#define I2C_BBPLL_DIV_DAC_MSB 4
#define I2C_BBPLL_DIV_DAC_LSB 4
#define I2C_BBPLL_DIV_CPU 4
#define I2C_BBPLL_DIV_CPU_MSB 5
#define I2C_BBPLL_DIV_CPU_LSB 5
#define I2C_BBPLL_OC_ENB_VCON 4
#define I2C_BBPLL_OC_ENB_VCON_MSB 6
#define I2C_BBPLL_OC_ENB_VCON_LSB 6
#define I2C_BBPLL_OC_TSCHGP 4
#define I2C_BBPLL_OC_TSCHGP_MSB 7
#define I2C_BBPLL_OC_TSCHGP_LSB 7
#define I2C_BBPLL_OC_DR1 5
#define I2C_BBPLL_OC_DR1_MSB 2
#define I2C_BBPLL_OC_DR1_LSB 0
#define I2C_BBPLL_OC_DR3 5
#define I2C_BBPLL_OC_DR3_MSB 6
#define I2C_BBPLL_OC_DR3_LSB 4
#define I2C_BBPLL_EN_USB 5
#define I2C_BBPLL_EN_USB_MSB 7
#define I2C_BBPLL_EN_USB_LSB 7
#define I2C_BBPLL_OC_DCUR 6
#define I2C_BBPLL_OC_DCUR_MSB 2
#define I2C_BBPLL_OC_DCUR_LSB 0
#define I2C_BBPLL_INC_CUR 6
#define I2C_BBPLL_INC_CUR_MSB 3
#define I2C_BBPLL_INC_CUR_LSB 3
#define I2C_BBPLL_OC_DHREF_SEL 6
#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
#define I2C_BBPLL_OC_DLREF_SEL 6
#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
#define I2C_BBPLL_OR_CAL_CAP 8
#define I2C_BBPLL_OR_CAL_CAP_MSB 3
#define I2C_BBPLL_OR_CAL_CAP_LSB 0
#define I2C_BBPLL_OR_CAL_UDF 8
#define I2C_BBPLL_OR_CAL_UDF_MSB 4
#define I2C_BBPLL_OR_CAL_UDF_LSB 4
#define I2C_BBPLL_OR_CAL_OVF 8
#define I2C_BBPLL_OR_CAL_OVF_MSB 5
#define I2C_BBPLL_OR_CAL_OVF_LSB 5
#define I2C_BBPLL_OR_CAL_END 8
#define I2C_BBPLL_OR_CAL_END_MSB 6
#define I2C_BBPLL_OR_CAL_END_LSB 6
#define I2C_BBPLL_OR_LOCK 8
#define I2C_BBPLL_OR_LOCK_MSB 7
#define I2C_BBPLL_OR_LOCK_LSB 7
#define I2C_BBPLL_BBADC_DELAY1 9
#define I2C_BBPLL_BBADC_DELAY1_MSB 1
#define I2C_BBPLL_BBADC_DELAY1_LSB 0
#define I2C_BBPLL_BBADC_DELAY2 9
#define I2C_BBPLL_BBADC_DELAY2_MSB 3
#define I2C_BBPLL_BBADC_DELAY2_LSB 2
#define I2C_BBPLL_BBADC_DVDD 9
#define I2C_BBPLL_BBADC_DVDD_MSB 5
#define I2C_BBPLL_BBADC_DVDD_LSB 4
#define I2C_BBPLL_BBADC_DREF 9
#define I2C_BBPLL_BBADC_DREF_MSB 7
#define I2C_BBPLL_BBADC_DREF_LSB 6
#define I2C_BBPLL_BBADC_DCUR 10
#define I2C_BBPLL_BBADC_DCUR_MSB 1
#define I2C_BBPLL_BBADC_DCUR_LSB 0
#define I2C_BBPLL_BBADC_INPUT_SHORT 10
#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2
#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2
#define I2C_BBPLL_ENT_PLL 10
#define I2C_BBPLL_ENT_PLL_MSB 3
#define I2C_BBPLL_ENT_PLL_LSB 3
#define I2C_BBPLL_DTEST 10
#define I2C_BBPLL_DTEST_MSB 5
#define I2C_BBPLL_DTEST_LSB 4
#define I2C_BBPLL_ENT_ADC 10
#define I2C_BBPLL_ENT_ADC_MSB 7
#define I2C_BBPLL_ENT_ADC_LSB 6
#endif
arch/xtensa/src/esp32s2/hardware/esp32s2_i2s.h
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arch/xtensa/src/esp32s2/hardware/esp32s2_interrupt.h
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arch/xtensa/src/esp32s2/hardware/esp32s2_iomux.h
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/****************************************************************************
* arch/xtensa/src/esp32s2/hardware/esp32s2_iomux.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_IOMUM_H
#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_IOMUM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "esp32s2_soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers
* Output enable in sleep mode
*/
#define SLP_OE (BIT(0))
#define SLP_OE_M (BIT(0))
#define SLP_OE_V 1
#define SLP_OE_S 0
/* Pin used for wakeup from sleep */
#define SLP_SEL (BIT(1))
#define SLP_SEL_M (BIT(1))
#define SLP_SEL_V 1
#define SLP_SEL_S 1
/* Pulldown enable in sleep mode */
#define SLP_PD (BIT(2))
#define SLP_PD_M (BIT(2))
#define SLP_PD_V 1
#define SLP_PD_S 2
/* Pullup enable in sleep mode */
#define SLP_PU (BIT(3))
#define SLP_PU_M (BIT(3))
#define SLP_PU_V 1
#define SLP_PU_S 3
/* Input enable in sleep mode */
#define SLP_IE (BIT(4))
#define SLP_IE_M (BIT(4))
#define SLP_IE_V 1
#define SLP_IE_S 4
/* Drive strength in sleep mode */
#define SLP_DRV 0x3
#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
#define SLP_DRV_V 0x3
#define SLP_DRV_S 5
/* Pulldown enable */
#define FUN_PD (BIT(7))
#define FUN_PD_M (BIT(7))
#define FUN_PD_V 1
#define FUN_PD_S 7
/* Pullup enable */
#define FUN_PU (BIT(8))
#define FUN_PU_M (BIT(8))
#define FUN_PU_V 1
#define FUN_PU_S 8
/* Input enable */
#define FUN_IE (BIT(9))
#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
#define FUN_IE_V 1
#define FUN_IE_S 9
/* Drive strength */
#define FUN_DRV 0x3
#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
#define FUN_DRV_V 0x3
#define FUN_DRV_S 10
/* Function select (possible values are defined for each pin as
* FUNC_pinname_function below)
*/
#define MCU_SEL 0x7
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
#define MCU_SEL_V 0x7
#define MCU_SEL_S 12
#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_GPIO4_U
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_GPIO5_U
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_GPIO6_U
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_GPIO11_U
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_GPIO13_U
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_GPIO14_U
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_XTAL_32K_P_U
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_XTAL_32K_N_U
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_DAC_1_U
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_DAC_2_U
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_GPIO20_U
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_GPIO21_U
#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_SPICS1_U
#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_SPIHD_U
#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_SPIWP_U
#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_SPICS0_U
#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_SPICLK_U
#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_SPIQ_U
#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_SPID_U
#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U
#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U
#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U
#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U
#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U
#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U
#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_MTCK_U
#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_MTDO_U
#define IO_MUX_GPIO41_REG PERIPHS_IO_MUX_MTDI_U
#define IO_MUX_GPIO42_REG PERIPHS_IO_MUX_MTMS_U
#define IO_MUX_GPIO43_REG PERIPHS_IO_MUX_U0TXD_U
#define IO_MUX_GPIO44_REG PERIPHS_IO_MUX_U0RXD_U
#define IO_MUX_GPIO45_REG PERIPHS_IO_MUX_GPIO45_U
#define IO_MUX_GPIO46_REG PERIPHS_IO_MUX_GPIO46_U
#define FUNC_GPIO_GPIO 1
#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define U1RXD_GPIO_NUM 18
#define U1TXD_GPIO_NUM 17
#define U0RXD_GPIO_NUM 44
#define U0TXD_GPIO_NUM 43
#define SPI_CS1_GPIO_NUM 26
#define SPI_HD_GPIO_NUM 27
#define SPI_WP_GPIO_NUM 28
#define SPI_CS0_GPIO_NUM 29
#define SPI_CLK_GPIO_NUM 30
#define SPI_Q_GPIO_NUM 31
#define SPI_D_GPIO_NUM 32
#define SPI_D4_GPIO_NUM 33
#define SPI_D5_GPIO_NUM 34
#define SPI_D6_GPIO_NUM 35
#define SPI_D7_GPIO_NUM 36
#define SPI_DQS_GPIO_NUM 37
#define MAX_RTC_GPIO_NUM 21
#define MAX_PAD_GPIO_NUM 46
#define MAX_GPIO_NUM 53
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
#define PAD_POWER_SEL_V 0x1
#define PAD_POWER_SEL_M BIT(15)
#define PAD_POWER_SEL_S 15
#define PAD_POWER_SWITCH_DELAY 0x7
#define PAD_POWER_SWITCH_DELAY_V 0x7
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
#define PAD_POWER_SWITCH_DELAY_S 12
#define CLK_OUT3 0xf
#define CLK_OUT3_V CLK_OUT3
#define CLK_OUT3_S 8
#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S)
#define CLK_OUT2 0xf
#define CLK_OUT2_V CLK_OUT2
#define CLK_OUT2_S 4
#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S)
#define CLK_OUT1 0xf
#define CLK_OUT1_V CLK_OUT1
#define CLK_OUT1_S 0
#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S)
#define PERIPHS_IO_MUX_GPIO0_U (REG_IO_MUX_BASE +0x04)
#define FUNC_GPIO0_GPIO0 1
#define FUNC_GPIO0_GPIO0_0 0
#define PERIPHS_IO_MUX_GPIO1_U (REG_IO_MUX_BASE +0x08)
#define FUNC_GPIO1_GPIO1 1
#define FUNC_GPIO1_GPIO1_0 0
#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE +0x0c)
#define FUNC_GPIO2_GPIO2 1
#define FUNC_GPIO2_GPIO2_0 0
#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE +0x10)
#define FUNC_GPIO3_GPIO3 1
#define FUNC_GPIO3_GPIO3_0 0
#define PERIPHS_IO_MUX_GPIO4_U (REG_IO_MUX_BASE +0x14)
#define FUNC_GPIO4_GPIO4 1
#define FUNC_GPIO4_GPIO4_0 0
#define PERIPHS_IO_MUX_GPIO5_U (REG_IO_MUX_BASE +0x18)
#define FUNC_GPIO5_GPIO5 1
#define FUNC_GPIO5_GPIO5_0 0
#define PERIPHS_IO_MUX_GPIO6_U (REG_IO_MUX_BASE +0x1c)
#define FUNC_GPIO6_GPIO6 1
#define FUNC_GPIO6_GPIO6_0 0
#define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE +0x20)
#define FUNC_GPIO7_GPIO7 1
#define FUNC_GPIO7_GPIO7_0 0
#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE +0x24)
#define FUNC_GPIO8_SUBSPICS1 3
#define FUNC_GPIO8_GPIO8 1
#define FUNC_GPIO8_GPIO8_0 0
#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE +0x28)
#define FUNC_GPIO9_FSPIHD 4
#define FUNC_GPIO9_SUBSPIHD 3
#define FUNC_GPIO9_GPIO9 1
#define FUNC_GPIO9_GPIO9_0 0
#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE +0x2c)
#define FUNC_GPIO10_FSPICS0 4
#define FUNC_GPIO10_SUBSPICS0 3
#define FUNC_GPIO10_FSPIIO4 2
#define FUNC_GPIO10_GPIO10 1
#define FUNC_GPIO10_GPIO10_0 0
#define PERIPHS_IO_MUX_GPIO11_U (REG_IO_MUX_BASE +0x30)
#define FUNC_GPIO11_FSPID 4
#define FUNC_GPIO11_SUBSPID 3
#define FUNC_GPIO11_FSPIIO5 2
#define FUNC_GPIO11_GPIO11 1
#define FUNC_GPIO11_GPIO11_0 0
#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE +0x34)
#define FUNC_GPIO12_FSPICLK 4
#define FUNC_GPIO12_SUBSPICLK 3
#define FUNC_GPIO12_FSPIIO6 2
#define FUNC_GPIO12_GPIO12 1
#define FUNC_GPIO12_GPIO12_0 0
#define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE +0x38)
#define FUNC_GPIO13_FSPIQ 4
#define FUNC_GPIO13_SUBSPIQ 3
#define FUNC_GPIO13_FSPIIO7 2
#define FUNC_GPIO13_GPIO13 1
#define FUNC_GPIO13_GPIO13_0 0
#define PERIPHS_IO_MUX_GPIO14_U (REG_IO_MUX_BASE +0x3c)
#define FUNC_GPIO14_FSPIWP 4
#define FUNC_GPIO14_SUBSPIWP 3
#define FUNC_GPIO14_FSPIDQS 2
#define FUNC_GPIO14_GPIO14 1
#define FUNC_GPIO14_GPIO14_0 0
#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE +0x40)
#define FUNC_XTAL_32K_P_U0RTS 2
#define FUNC_XTAL_32K_P_GPIO15 1
#define FUNC_XTAL_32K_P_GPIO15_0 0
#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE +0x44)
#define FUNC_XTAL_32K_N_U0CTS 2
#define FUNC_XTAL_32K_N_GPIO16 1
#define FUNC_XTAL_32K_N_GPIO16_0 0
#define PERIPHS_IO_MUX_DAC_1_U (REG_IO_MUX_BASE +0x48)
#define FUNC_DAC_1_U1TXD 2
#define FUNC_DAC_1_GPIO17 1
#define FUNC_DAC_1_GPIO17_0 0
#define PERIPHS_IO_MUX_DAC_2_U (REG_IO_MUX_BASE +0x4c)
#define FUNC_DAC_2_CLK_OUT3 3
#define FUNC_DAC_2_U1RXD 2
#define FUNC_DAC_2_GPIO18 1
#define FUNC_DAC_2_GPIO18_0 0
#define PERIPHS_IO_MUX_GPIO19_U (REG_IO_MUX_BASE +0x50)
#define FUNC_GPIO19_CLK_OUT2 3
#define FUNC_GPIO19_U1RTS 2
#define FUNC_GPIO19_GPIO19 1
#define FUNC_GPIO19_GPIO19_0 0
#define PERIPHS_IO_MUX_GPIO20_U (REG_IO_MUX_BASE +0x54)
#define FUNC_GPIO20_CLK_OUT1 3
#define FUNC_GPIO20_U1CTS 2
#define FUNC_GPIO20_GPIO20 1
#define FUNC_GPIO20_GPIO20_0 0
#define PERIPHS_IO_MUX_GPIO21_U (REG_IO_MUX_BASE +0x58)
#define FUNC_GPIO21_GPIO21 1
#define FUNC_GPIO21_GPIO21_0 0
#define PERIPHS_IO_MUX_SPICS1_U (REG_IO_MUX_BASE +0x6c)
#define FUNC_SPICS1_GPIO26 1
#define FUNC_SPICS1_SPICS1 0
#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE +0x70)
#define FUNC_SPIHD_GPIO27 1
#define FUNC_SPIHD_SPIHD 0
#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE +0x74)
#define FUNC_SPIWP_GPIO28 1
#define FUNC_SPIWP_SPIWP 0
#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE +0x78)
#define FUNC_SPICS0_GPIO29 1
#define FUNC_SPICS0_SPICS0 0
#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE +0x7c)
#define FUNC_SPICLK_GPIO30 1
#define FUNC_SPICLK_SPICLK 0
#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE +0x80)
#define FUNC_SPIQ_GPIO31 1
#define FUNC_SPIQ_SPIQ 0
#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE +0x84)
#define FUNC_SPID_GPIO32 1
#define FUNC_SPID_SPID 0
#define PERIPHS_IO_MUX_GPIO33_U (REG_IO_MUX_BASE +0x88)
#define FUNC_GPIO33_SPIIO4 4
#define FUNC_GPIO33_SUBSPIHD 3
#define FUNC_GPIO33_FSPIHD 2
#define FUNC_GPIO33_GPIO33 1
#define FUNC_GPIO33_GPIO33_0 0
#define PERIPHS_IO_MUX_GPIO34_U (REG_IO_MUX_BASE +0x8c)
#define FUNC_GPIO34_SPIIO5 4
#define FUNC_GPIO34_SUBSPICS0 3
#define FUNC_GPIO34_FSPICS0 2
#define FUNC_GPIO34_GPIO34 1
#define FUNC_GPIO34_GPIO34_0 0
#define PERIPHS_IO_MUX_GPIO35_U (REG_IO_MUX_BASE +0x90)
#define FUNC_GPIO35_SPIIO6 4
#define FUNC_GPIO35_SUBSPID 3
#define FUNC_GPIO35_FSPID 2
#define FUNC_GPIO35_GPIO35 1
#define FUNC_GPIO35_GPIO35_0 0
#define PERIPHS_IO_MUX_GPIO36_U (REG_IO_MUX_BASE +0x94)
#define FUNC_GPIO36_SPIIO7 4
#define FUNC_GPIO36_SUBSPICLK 3
#define FUNC_GPIO36_FSPICLK 2
#define FUNC_GPIO36_GPIO36 1
#define FUNC_GPIO36_GPIO36_0 0
#define PERIPHS_IO_MUX_GPIO37_U (REG_IO_MUX_BASE +0x98)
#define FUNC_GPIO37_SPIDQS 4
#define FUNC_GPIO37_SUBSPIQ 3
#define FUNC_GPIO37_FSPIQ 2
#define FUNC_GPIO37_GPIO37 1
#define FUNC_GPIO37_GPIO37_0 0
#define PERIPHS_IO_MUX_GPIO38_U (REG_IO_MUX_BASE +0x9c)
#define FUNC_GPIO38_SUBSPIWP 3
#define FUNC_GPIO38_FSPIWP 2
#define FUNC_GPIO38_GPIO38 1
#define FUNC_GPIO38_GPIO38_0 0
#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE +0xa0)
#define FUNC_MTCK_SUBSPICS1 3
#define FUNC_MTCK_CLK_OUT3 2
#define FUNC_MTCK_GPIO39 1
#define FUNC_MTCK_MTCK 0
#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE +0xa4)
#define FUNC_MTDO_CLK_OUT2 2
#define FUNC_MTDO_GPIO40 1
#define FUNC_MTDO_MTDO 0
#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE +0xa8)
#define FUNC_MTDI_CLK_OUT1 2
#define FUNC_MTDI_GPIO41 1
#define FUNC_MTDI_MTDI 0
#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE +0xac)
#define FUNC_MTMS_GPIO42 1
#define FUNC_MTMS_MTMS 0
#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE +0xb0)
#define FUNC_U0TXD_CLK_OUT1 2
#define FUNC_U0TXD_GPIO43 1
#define FUNC_U0TXD_U0TXD 0
#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE +0xb4)
#define FUNC_U0RXD_CLK_OUT2 2
#define FUNC_U0RXD_GPIO44 1
#define FUNC_U0RXD_U0RXD 0
#define PERIPHS_IO_MUX_GPIO45_U (REG_IO_MUX_BASE +0xb8)
#define FUNC_GPIO45_GPIO45 1
#define FUNC_GPIO45_GPIO45_0 0
#define PERIPHS_IO_MUX_GPIO46_U (REG_IO_MUX_BASE +0xbc)
#define FUNC_GPIO46_GPIO46 1
#define FUNC_GPIO46_GPIO46_0 0
#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
#define IO_MUX_DATE 0xFFFFFFFF
#define IO_MUX_DATE_S 0
#define IO_MUX_DATE_VERSION 0x1907160
#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2CBBPLL_H */
arch/xtensa/src/esp32s2/hardware/esp32s2_rsa.h
+233
View File
@@ -0,0 +1,233 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/hardware/esp32s2_rsa.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RSA_H
#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RSA_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "esp32s2_soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* RSA_M_PRIME_REG register
* Register to store M'
*/
#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800)
/* RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0;
* Stores M'
*/
#define RSA_M_PRIME 0xFFFFFFFF
#define RSA_M_PRIME_M (RSA_M_PRIME_V << RSA_M_PRIME_S)
#define RSA_M_PRIME_V 0xFFFFFFFF
#define RSA_M_PRIME_S 0
/* RSA_MODE_REG register
* RSA length mode
*/
#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804)
/* RSA_MODE : R/W; bitpos: [6:0]; default: 0;
* Stores the mode of modular exponentiation.
*/
#define RSA_MODE 0x0000007F
#define RSA_MODE_M (RSA_MODE_V << RSA_MODE_S)
#define RSA_MODE_V 0x0000007F
#define RSA_MODE_S 0
/* RSA_CLEAN_REG register
* RSA clean register
*/
#define RSA_CLEAN_REG (DR_REG_RSA_BASE + 0x808)
/* RSA_CLEAN : RO; bitpos: [0]; default: 0;
* The content of this bit is 1 when memories complete initialization.
*/
#define RSA_CLEAN (BIT(0))
#define RSA_CLEAN_M (RSA_CLEAN_V << RSA_CLEAN_S)
#define RSA_CLEAN_V 0x00000001
#define RSA_CLEAN_S 0
/* RSA_MODEXP_START_REG register
* Modular exponentiation starting bit
*/
#define RSA_MODEXP_START_REG (DR_REG_RSA_BASE + 0x80c)
/* RSA_MODEXP_START : WO; bitpos: [0]; default: 0;
* Set this bit to 1 to start the modular exponentiation.
*/
#define RSA_MODEXP_START (BIT(0))
#define RSA_MODEXP_START_M (RSA_MODEXP_START_V << RSA_MODEXP_START_S)
#define RSA_MODEXP_START_V 0x00000001
#define RSA_MODEXP_START_S 0
/* RSA_MODMULT_START_REG register
* Modular multiplication starting bit
*/
#define RSA_MODMULT_START_REG (DR_REG_RSA_BASE + 0x810)
/* RSA_MODMULT_START : WO; bitpos: [0]; default: 0;
* Set this bit to 1 to start the modular multiplication.
*/
#define RSA_MODMULT_START (BIT(0))
#define RSA_MODMULT_START_M (RSA_MODMULT_START_V << RSA_MODMULT_START_S)
#define RSA_MODMULT_START_V 0x00000001
#define RSA_MODMULT_START_S 0
/* RSA_MULT_START_REG register
* Normal multiplicaiton starting bit
*/
#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x814)
/* RSA_MULT_START : WO; bitpos: [0]; default: 0;
* Set this bit to 1 to start the multiplication.
*/
#define RSA_MULT_START (BIT(0))
#define RSA_MULT_START_M (RSA_MULT_START_V << RSA_MULT_START_S)
#define RSA_MULT_START_V 0x00000001
#define RSA_MULT_START_S 0
/* RSA_IDLE_REG register
* RSA idle register
*/
#define RSA_IDLE_REG (DR_REG_RSA_BASE + 0x818)
/* RSA_IDLE : RO; bitpos: [0]; default: 0;
* The content of this bit is 1 when the RSA accelerator is idle.
*/
#define RSA_IDLE (BIT(0))
#define RSA_IDLE_M (RSA_IDLE_V << RSA_IDLE_S)
#define RSA_IDLE_V 0x00000001
#define RSA_IDLE_S 0
/* RSA_CLEAR_INTERRUPT_REG register
* RSA clear interrupt register
*/
#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81c)
/* RSA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
* Set this bit to 1 to clear the RSA interrupts.
*/
#define RSA_CLEAR_INTERRUPT (BIT(0))
#define RSA_CLEAR_INTERRUPT_M (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S)
#define RSA_CLEAR_INTERRUPT_V 0x00000001
#define RSA_CLEAR_INTERRUPT_S 0
/* RSA_CONSTANT_TIME_REG register
* The constant_time option
*/
#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820)
/* RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1;
* Set this bit to 0 to enable the acceleration option of constant_time for
* modular exponentiation. Set to 1 to disable the acceleration (by default).
*/
#define RSA_CONSTANT_TIME (BIT(0))
#define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S)
#define RSA_CONSTANT_TIME_V 0x00000001
#define RSA_CONSTANT_TIME_S 0
/* RSA_SEARCH_ENABLE_REG register
* The search option
*/
#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824)
/* RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0;
* Set this bit to 1 to enable the acceleration option of search for modular
* exponentiation. Set to 0 to disable the acceleration (by default).
*/
#define RSA_SEARCH_ENABLE (BIT(0))
#define RSA_SEARCH_ENABLE_M (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S)
#define RSA_SEARCH_ENABLE_V 0x00000001
#define RSA_SEARCH_ENABLE_S 0
/* RSA_SEARCH_POS_REG register
* The search position
*/
#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828)
/* RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0;
* Is used to configure the starting address when the acceleration option of
* search is used.
*/
#define RSA_SEARCH_POS 0x00000FFF
#define RSA_SEARCH_POS_M (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S)
#define RSA_SEARCH_POS_V 0x00000FFF
#define RSA_SEARCH_POS_S 0
/* RSA_INTERRUPT_ENA_REG register
* RSA interrupt enable register
*/
#define RSA_INTERRUPT_ENA_REG (DR_REG_RSA_BASE + 0x82c)
/* RSA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
* Set this bit to 1 to enable the RSA interrupt. This option is enabled by
* default.
*/
#define RSA_INTERRUPT_ENA (BIT(0))
#define RSA_INTERRUPT_ENA_M (RSA_INTERRUPT_ENA_V << RSA_INTERRUPT_ENA_S)
#define RSA_INTERRUPT_ENA_V 0x00000001
#define RSA_INTERRUPT_ENA_S 0
/* RSA_DATE_REG register
* Version control register
*/
#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830)
/* RSA_DATE : R/W; bitpos: [29:0]; default: 538510373;
* Version control register
*/
#define RSA_DATE 0x3FFFFFFF
#define RSA_DATE_M (RSA_DATE_V << RSA_DATE_S)
#define RSA_DATE_V 0x3FFFFFFF
#define RSA_DATE_S 0
#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RSA_H */
arch/xtensa/src/esp32s2/hardware/esp32s2_rtc_io.h
+3704
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