SAML21 DMA: Add logic to set up base and writeback table addresses

arch/arm/src/samdl/Kconfig

@@ -241,7 +241,7 @@ config ARCH_FAMILY_SAMD20J
 config ARCH_FAMILY_SAML21
 	bool
 	default n
-	selest SAMDL_HAVE_DMAC
+	select SAMDL_HAVE_DMAC
 
 config ARCH_FAMILY_SAML21E
 	bool
@@ -420,9 +420,18 @@ config SAMDL_SERCOM0_ISUSART
 endchoice
 
 config SAMDL_DMAC_NDESC
-	int "Number of DMA Descriptors"
-	default 64
+	int "Number of additional DMA Descriptors"
+	default 0
 	depends on SAMDL_DMAC
+	---help---
+		This provides the number of additional DMA descriptors that can be
+		use to support multi-linked DMA transfers.  A minimum of 16
+		descriptors will always be allocated (16 for the base descriptor which
+		overlap the writeback descriptors).  If this value is set to zero,
+		then only single block DMA transfers can be supported.
+
+		Each additional DMA descriptor will require 16-bytes for LPRAM
+		memory.
 
 choice
 	prompt "SERCOM1 mode"

arch/arm/src/samdl/chip/saml_dmac.h

@@ -174,7 +174,7 @@
 #  define DMAC_QOSCTRL_DQOS_MEDIUM       (2 << DMAC_QOSCTRL_DQOS_SHIFT) /* Sensitive latency */
 #  define DMAC_QOSCTRL_DQOS_HIGH         (3 << DMAC_QOSCTRL_DQOS_SHIFT) /* Critical latency */
             
-/* Common bit defintions for: Software Trigger Control Register, Interrupt Status Register,
+/* Common bit definitions for: Software Trigger Control Register, Interrupt Status Register,
  * Busy Channels Register, and Pending Channels Register 
  */