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STM32L4 ADC: Change the way that hardware trigger configuration word for regular and injected channels are done.
This commit is contained in:
Daniel P. Carvalho
committed by
Alan Carvalho de Assis
Alan Carvalho de Assis
parent
23a2e27ffc
commit
7518beee2e
+162
-60
@@ -5287,53 +5287,6 @@ config STM32L4_ADC3_DMA_CFG
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---help---
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0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode
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config STM32L4_ADC1_OUTPUT_DFSDM
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bool "ADC1 output to DFSDM"
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depends on STM32L4_ADC1 && STM32L4_DFSDM1 && (STM32L4_STM32L496XX || STM32L4_STM32L4XR)
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default n
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---help---
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Route ADC1 output directly to DFSDM parallel inputs.
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config STM32L4_ADC2_OUTPUT_DFSDM
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bool "ADC2 output to DFSDM"
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depends on STM32L4_ADC2 && STM32L4_DFSDM1 && STM32L4_STM32L496XX
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default n
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---help---
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Route ADC2 output directly to DFSDM parallel inputs.
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config STM32L4_ADC3_OUTPUT_DFSDM
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bool "ADC3 output to DFSDM"
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depends on STM32L4_ADC3 && STM32L4_DFSDM1 && STM32L4_STM32L496XX
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default n
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---help---
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Route ADC3 output directly to DFSDM parallel inputs.
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menu "STM32L4 ADCx triggering Configuration"
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config STM32L4_ADC1_TIMTRIG
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int "ADC1 regular channel trigger"
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default 0
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range 0 4
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depends on STM32L4_HAVE_ADC1_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
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config STM32L4_ADC2_TIMTRIG
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int "ADC2 Timer Trigger"
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default 0
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range 0 4
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depends on STM32L4_HAVE_ADC2_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
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config STM32L4_ADC3_TIMTRIG
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int "ADC3 Timer Trigger"
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default 0
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range 0 4
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depends on STM32L4_HAVE_ADC3_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
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config STM32L4_ADC1_INJ_CHAN
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int "ADC1 configured injected channels"
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depends on STM32L4_ADC1
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@@ -5358,39 +5311,188 @@ config STM32L4_ADC3_INJ_CHAN
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---help---
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Number of configured ADC3 injected channels.
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config STM32L4_ADC1_OUTPUT_DFSDM
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bool "ADC1 output to DFSDM"
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depends on STM32L4_ADC1 && STM32L4_DFSDM1 && (STM32L4_STM32L496XX || STM32L4_STM32L4XR)
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default n
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---help---
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Route ADC1 output directly to DFSDM parallel inputs.
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config STM32L4_ADC2_OUTPUT_DFSDM
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bool "ADC2 output to DFSDM"
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depends on STM32L4_ADC2 && STM32L4_DFSDM1 && STM32L4_STM32L496XX
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default n
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---help---
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Route ADC2 output directly to DFSDM parallel inputs.
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config STM32L4_ADC3_OUTPUT_DFSDM
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bool "ADC3 output to DFSDM"
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depends on STM32L4_ADC3 && STM32L4_DFSDM1 && STM32L4_STM32L496XX
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default n
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---help---
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Route ADC3 output directly to DFSDM parallel inputs.
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menu "STM32L4 ADCx triggering Configuration"
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config STM32L4_ADC1_EXTTRIG
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int "ADC1 External trigger configuration for regular channels"
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default 0
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range 0 4
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depends on STM32L4_ADC1
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---help---
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Values 0: Hardware trigger detection disabled
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1: Hardware trigger detection on the rising edge
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2: Hardware trigger detection on the falling edge
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3: Hardware trigger detection on the rising and falling edges
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if STM32L4_ADC1_EXTTRIG > 0
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config STM32L4_ADC1_EXTSEL
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int "ADC1 External trigger selection for regular group"
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default 0
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range 0 15
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depends on STM32L4_ADC1
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---help---
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Select the external event used to trigger the start of conversion of
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a regular group. See Reference Manual for mor information.
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endif
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config STM32L4_ADC2_EXTTRIG
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int "ADC2 External trigger configuration for regular channels"
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default 0
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range 0 4
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depends on STM32L4_ADC2
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---help---
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Values 0: Hardware trigger detection disabled
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1: Hardware trigger detection on the rising edge
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2: Hardware trigger detection on the falling edge
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3: Hardware trigger detection on the rising and falling edges
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if STM32L4_ADC2_EXTTRIG > 0
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config STM32L4_ADC2_EXTSEL
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int "ADC2 External trigger selection for regular group"
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default 0
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range 0 15
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depends on STM32L4_ADC2
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---help---
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Select the external event used to trigger the start of conversion of
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a regular group. See Reference Manual for mor information.
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endif
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config STM32L4_ADC3_EXTTRIG
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int "ADC3 External trigger configuration for regular channels"
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default 0
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range 0 4
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depends on STM32L4_ADC3
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---help---
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Values 0: Hardware trigger detection disabled
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1: Hardware trigger detection on the rising edge
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2: Hardware trigger detection on the falling edge
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3: Hardware trigger detection on the rising and falling edges
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if STM32L4_ADC3_EXTTRIG > 0
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config STM32L4_ADC3_EXTSEL
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int "ADC3 External trigger selection for regular group"
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default 0
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range 0 15
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depends on STM32L4_ADC3
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---help---
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Select the external event used to trigger the start of conversion of
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a regular group. See Reference Manual for mor information.
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endif
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if STM32L4_ADC1_INJ_CHAN > 0
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config STM32L4_ADC1_JTIMTRIG
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int "ADC1 external trigger for injected channels"
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config STM32L4_ADC1_JEXTTRIG
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int "ADC1 External Trigger Enable and Polarity Selection for injected channels"
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default 0
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range 0 5
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depends on STM32L4_HAVE_ADC1_TIMER
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range 0 4
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depends on STM32L4_ADC1
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2
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Values 0: Hardware and software trigger detection disabled, JQDIS=0
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(queue enabled)
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0: Hardware trigger detection disabled, JQDIS=1 (queue disabled)
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1: Hardware trigger detection on the rising edge
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2: Hardware trigger detection on the falling edge
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3: Hardware trigger detection on the rising and falling edges
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if STM32L4_ADC1_JEXTTRIG > 0
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config STM32L4_ADC1_JEXTSEL
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int "ADC1 External Trigger Selection for injected group"
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default 0
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range 0 15
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depends on STM32L4_ADC1
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---help---
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Select the external event used to trigger the start of conversion of an
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injected group
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endif
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endif
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if STM32L4_ADC2_INJ_CHAN > 0
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config STM32L4_ADC2_JTIMTRIG
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int "ADC2 external trigger for injected channels"
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config STM32L4_ADC2_JEXTTRIG
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int "ADC2 External Trigger Enable and Polarity Selection for injected channels"
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default 0
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range 0 4
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depends on STM32L4_ADC2
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---help---
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Values 0: Hardware and software trigger detection disabled, JQDIS=0
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(queue enabled)
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0: Hardware trigger detection disabled, JQDIS=1 (queue disabled)
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1: Hardware trigger detection on the rising edge
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2: Hardware trigger detection on the falling edge
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3: Hardware trigger detection on the rising and falling edges
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if STM32L4_ADC2_JEXTTRIG > 0
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config STM32L4_ADC2_JEXTSEL
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int "ADC2 External Trigger Selection for injected group"
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default 0
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range 0 5
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depends on STM32L4_HAVE_ADC2_TIMER
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depends on STM32L4_ADC2
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2
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Select the external event used to trigger the start of conversion of an
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injected group
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endif
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endif
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if STM32L4_ADC3_INJ_CHAN > 0
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config STM32L4_ADC3_JTIMTRIG
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int "ADC3 external trigger for injected channels"
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config STM32L4_ADC3_JEXTTRIG
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int "ADC3 External Trigger Enable and Polarity Selection for injected channels"
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default 0
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range 0 4
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depends on STM32L4_ADC3
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---help---
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Values 0: Hardware and software trigger detection disabled, JQDIS=0
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(queue enabled)
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0: Hardware trigger detection disabled, JQDIS=1 (queue disabled)
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1: Hardware trigger detection on the rising edge
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2: Hardware trigger detection on the falling edge
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3: Hardware trigger detection on the rising and falling edges
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if STM32L4_ADC3_JEXTTRIG > 0
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config STM32L4_ADC3_JEXTSEL
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int "ADC3 External Trigger Selection for injected group"
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default 0
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range 0 5
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depends on STM32L4_HAVE_ADC3_TIMER
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depends on STM32L4_ADC3
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2
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Select the external event used to trigger the start of conversion of an
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injected group
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endif
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endif
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@@ -245,6 +245,7 @@
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# endif
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#define ADC_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */
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#define ADC_CFGR_EXTEN_MASK (3 << ADC_CFGR_EXTEN_SHIFT)
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# define ADC_CFGR_EXTEN(pol) ((pol) << ADC_CFGR_EXTEN_SHIFT) /* Trigger polarity = 0..3 */
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# define ADC_CFGR_EXTEN_NONE (0 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection disabled */
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# define ADC_CFGR_EXTEN_RISING (1 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the rising edge */
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# define ADC_CFGR_EXTEN_FALLING (2 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the falling edge */
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@@ -463,6 +464,8 @@
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# define ADC_JEXTSEL_T15TRGO ADC_JSQR_JEXTSEL(15) /* 1111 TIM15_TRGO */
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#define ADC_JSQR_JEXTEN_SHIFT (6) /* Bits 6-7: External trigger selection for injected greoup */
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#define ADC_JSQR_JEXTEN_MASK (3 << ADC_JSQR_JEXTEN_SHIFT)
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# define ADC_JSQR_JEXTEN(pol) ((pol) << ADC_JSQR_JEXTEN_SHIFT)
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/* Trigger polarity = 0..3 */
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# define ADC_JSQR_JEXTEN_NONE (0 << ADC_JSQR_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
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# define ADC_JSQR_JEXTEN_RISING (1 << ADC_JSQR_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
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# define ADC_JSQR_JEXTEN_FALLING (2 << ADC_JSQR_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
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@@ -1690,7 +1690,7 @@ static int adc_jextsel_set(struct stm32_dev_s *priv, uint32_t jextcfg)
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setbits = (jexten | jextsel);
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clrbits = (ADC_JSQR_JEXTEN_MASK | ADC_JSQR_JEXTSEL_MASK);
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ainfo("Initializing jextsel = 0x%08x\n", jextsel);
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ainfo("Initializing jextsel = 0x%08" PRIx32 "\n", jextsel);
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/* Write register */
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