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Merged in alinjerpelea/nuttx/code_style (pull request #887)

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Code style fixes

* arch: arm: cxd56xx: cxd56_cpufifo fix codestyle

    Only codestyle fix

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* arch: arm: cxd56xx: cxd56_clock fix codestyle

    Only codestyle fix

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* arch: arm: cxd56xx: cxd56_gpio fix codestyle

    Only codestyle fix

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* arch: arm: cxd56xx: cxd56_gpioint fix codestyle

    Only codestyle fix

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* arch: arm: cxd56xx: cxd56_irq fix codestyle

    Only codestyle fix

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* arch: arm: cxd56xx: cxd56_pinconfig fix codestyle

    Only codestyle fix

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* arch: arm: cxd56xx: cxd56_pmic fix codestyle

    Only codestyle fix

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* arch: arm: cxd56xx: cxd56_sdhci fix codestyle

    Only codestyle fix

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* arch: arm: cxd56xx: cxd56_start fix codestyle

    Only codestyle fix

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* arch: arm: cxd56xx: cxd56_usbdev fix codestyle

    Only codestyle fix

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
Alin Jerpelea
2019-06-10 13:00:57 +00:00
committed by Gregory Nutt
parent e923c7683b
commit 750e45ad6e
16 changed files with 587 additions and 379 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/cxd56xx/cxd56_clock.c
+106 -55
View File
@@ -97,10 +97,9 @@
#ifndef CONFIG_CXD56_UART2_BASE_CLOCK_DIVIDER
#define CONFIG_CXD56_UART2_BASE_CLOCK_DIVIDER 4
#endif /* CONFIG_CXD56_UART2_BASE_CLOCK_DIVIDER */
#endif
/*
* Flags for IMG device active
/* Flags for IMG device active
*
* This flags for fixed clock devices.
*/
@@ -139,10 +138,14 @@ struct power_domain
static void cxd56_img_clock_enable(void);
static void cxd56_img_clock_disable(void);
static void cxd56_scu_clock_ctrl(uint32_t block, uint32_t intr, int on);
static void cxd56_scu_peri_clock_enable(FAR const struct scu_peripheral *p) __unused;
static void cxd56_scu_peri_clock_disable(FAR const struct scu_peripheral *p) __unused;
static void cxd56_scu_peri_clock_gating(FAR const struct scu_peripheral *p, int enable) __unused;
static void cxd56_scu_clock_ctrl(\
uint32_t block, uint32_t intr, int on);
static void cxd56_scu_peri_clock_enable(\
FAR const struct scu_peripheral *p) __unused;
static void cxd56_scu_peri_clock_disable(\
FAR const struct scu_peripheral *p) __unused;
static void cxd56_scu_peri_clock_gating(\
FAR const struct scu_peripheral *p, int enable) __unused;
/****************************************************************************
* Public Data
@@ -286,7 +289,7 @@ static inline void release_pwd_reset(uint32_t domain)
{
/* Release power domain reset */
putreg32(domain | domain <<16, CXD56_TOPREG_PWD_RESET0);
putreg32(domain | domain << 16, CXD56_TOPREG_PWD_RESET0);
}
}
@@ -298,7 +301,7 @@ static void enable_pwd(int pdid)
stat = getreg32(CXD56_TOPREG_PWD_STAT);
if ((stat & domain) != domain)
{
putreg32((domain|(domain<<16)), CXD56_TOPREG_PWD_CTL);
putreg32((domain | (domain << 16)), CXD56_TOPREG_PWD_CTL);
do_power_control();
release_pwd_reset(domain);
}
@@ -316,7 +319,7 @@ static void disable_pwd(int pdid)
g_digital.refs[pdid]--;
if (g_digital.refs[pdid] == 0)
{
putreg32(domain<<16, CXD56_TOPREG_PWD_CTL);
putreg32(domain << 16, CXD56_TOPREG_PWD_CTL);
do_power_control();
}
}
@@ -330,7 +333,7 @@ static void enable_apwd(int apdid)
stat = getreg32(CXD56_TOPREG_ANA_PW_STAT);
if ((stat & domain) != domain)
{
putreg32(domain|(domain<<16), CXD56_TOPREG_ANA_PW_CTL);
putreg32(domain | (domain << 16), CXD56_TOPREG_ANA_PW_CTL);
do_power_control();
}
g_analog.refs[apdid]++;
@@ -347,7 +350,7 @@ static void disable_apwd(int apdid)
g_analog.refs[apdid]--;
if (g_analog.refs[apdid] == 0)
{
putreg32(domain<<16, CXD56_TOPREG_ANA_PW_CTL);
putreg32(domain << 16, CXD56_TOPREG_ANA_PW_CTL);
do_power_control();
}
}
@@ -419,7 +422,8 @@ void cxd56_xosc_disable(void)
void cxd56_spif_clock_enable(void)
{
uint32_t val, rst;
uint32_t val;
uint32_t rst;
val = getreg32(CXD56_TOPREG_SYSIOP_SUB_CKEN);
if (val & CK_SFC)
@@ -446,7 +450,8 @@ void cxd56_spif_clock_enable(void)
void cxd56_spif_clock_disable(void)
{
uint32_t val, rst;
uint32_t val;
uint32_t rst;
val = getreg32(CXD56_TOPREG_SYSIOP_SUB_CKEN);
if (!(val & CK_SFC))
@@ -470,7 +475,8 @@ void cxd56_spif_clock_disable(void)
uint32_t cxd56_get_cpu_baseclk(void)
{
uint32_t val;
int n, m;
int n;
int m;
val = getreg32(CXD56_CRG_GEAR_AHB);
n = (val >> 16) & 0x7f;
@@ -507,7 +513,8 @@ void cxd56_cpu_clock_enable(int cpu)
void cxd56_cpulist_clock_enable(uint32_t cpus)
{
uint32_t c, bits = (cpus & 0x3f) << 16;
uint32_t c;
uint32_t bits = (cpus & 0x3f) << 16;
c = getreg32(CXD56_CRG_CK_GATE_AHB);
putreg32(c | bits, CXD56_CRG_CK_GATE_AHB);
@@ -534,7 +541,8 @@ void cxd56_cpu_clock_disable(int cpu)
void cxd56_cpulist_clock_disable(uint32_t cpus)
{
uint32_t c, bits = (cpus & 0x3f) << 16;
uint32_t c;
uint32_t bits = (cpus & 0x3f) << 16;
c = getreg32(CXD56_CRG_CK_GATE_AHB);
putreg32(c & ~bits, CXD56_CRG_CK_GATE_AHB);
@@ -561,7 +569,9 @@ void cxd56_cpu_reset(int cpu)
void cxd56_cpulist_reset(uint32_t cpus)
{
uint32_t c, r, bits = (cpus & 0x3f) << 16;
uint32_t c;
uint32_t r;
uint32_t bits = (cpus & 0x3f) << 16;
/* Reset assert */
@@ -589,7 +599,8 @@ void cxd56_cpulist_reset(uint32_t cpus)
void cxd56_usb_clock_enable(void)
{
uint32_t c, r;
uint32_t c;
uint32_t r;
enable_pwd(PDID_APP_SUB);
@@ -615,7 +626,8 @@ void cxd56_usb_clock_enable(void)
void cxd56_usb_clock_disable(void)
{
uint32_t c, r;
uint32_t c;
uint32_t r;
c = getreg32(CXD56_CRG_CK_GATE_AHB);
if (c & CK_GATE_USB)
@@ -639,7 +651,9 @@ void cxd56_usb_clock_disable(void)
void cxd56_emmc_clock_enable(uint32_t div, uint32_t driver, uint32_t sample)
{
uint32_t c, r, g;
uint32_t c;
uint32_t r;
uint32_t g;
enable_pwd(PDID_APP_SUB);
@@ -686,7 +700,9 @@ void cxd56_emmc_clock_enable(uint32_t div, uint32_t driver, uint32_t sample)
void cxd56_emmc_clock_disable(void)
{
uint32_t c, r, g;
uint32_t c;
uint32_t r;
uint32_t g;
c = getreg32(CXD56_CRG_CKEN_EMMC);
if (c != 7)
@@ -699,7 +715,7 @@ void cxd56_emmc_clock_disable(void)
putreg32(0, CXD56_CRG_CKEN_EMMC);
r = getreg32(CXD56_CRG_RESET);
putreg32(r & ~(XRS_MMC|XRS_MMC_CRG), CXD56_CRG_RESET);
putreg32(r & ~(XRS_MMC | XRS_MMC_CRG), CXD56_CRG_RESET);
disable_pwd(PDID_APP_SUB);
}
@@ -713,7 +729,8 @@ void cxd56_emmc_clock_disable(void)
void cxd56_sdio_clock_enable(void)
{
uint32_t c, r;
uint32_t c;
uint32_t r;
enable_pwd(PDID_APP_SUB);
@@ -738,7 +755,8 @@ void cxd56_sdio_clock_enable(void)
void cxd56_sdio_clock_disable(void)
{
uint32_t c, r;
uint32_t c;
uint32_t r;
c = getreg32(CXD56_CRG_CK_GATE_AHB);
if (c & CK_GATE_SDIO)
@@ -814,7 +832,8 @@ bool cxd56_audio_clock_is_enabled(void)
static void cxd56_spim_clock_enable(void)
{
uint32_t val, rst;
uint32_t val;
uint32_t rst;
val = getreg32(CXD56_TOPREG_SYSIOP_SUB_CKEN);
if (val & CK_SPIM)
@@ -822,14 +841,16 @@ static void cxd56_spim_clock_enable(void)
return;
}
putreg32(val | CK_SPIM | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
putreg32(val | CK_SPIM | CK_COM_BRG |
CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
busy_wait(10);
putreg32(val | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
rst = getreg32(CXD56_TOPREG_SWRESET_BUS);
putreg32(rst | XRST_SPIM, CXD56_TOPREG_SWRESET_BUS);
putreg32(val | CK_SPIM | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
putreg32(val | CK_SPIM | CK_COM_BRG |
CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
}
/****************************************************************************
@@ -842,7 +863,9 @@ static void cxd56_spim_clock_enable(void)
static void cxd56_spim_clock_disable(void)
{
uint32_t val, rst, mask;
uint32_t val;
uint32_t rst;
uint32_t mask;
val = getreg32(CXD56_TOPREG_SYSIOP_SUB_CKEN);
if (!(val & CK_SPIM))
@@ -1095,7 +1118,8 @@ void cxd56_spi_clock_gear_adjust(int port, uint32_t maxfreq)
static void cxd56_i2cm_clock_enable(void)
{
uint32_t val, rst;
uint32_t val;
uint32_t rst;
val = getreg32(CXD56_TOPREG_SYSIOP_SUB_CKEN);
if (val & CK_I2CM)
@@ -1103,14 +1127,16 @@ static void cxd56_i2cm_clock_enable(void)
return;
}
putreg32(val | CK_I2CM | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
putreg32(val | CK_I2CM | CK_COM_BRG |
CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
busy_wait(10);
putreg32(val | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
rst = getreg32(CXD56_TOPREG_SWRESET_BUS);
putreg32(rst | XRST_I2CM, CXD56_TOPREG_SWRESET_BUS);
putreg32(val | CK_I2CM | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
putreg32(val | CK_I2CM | CK_COM_BRG |
CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
}
/****************************************************************************
@@ -1122,7 +1148,9 @@ static void cxd56_i2cm_clock_enable(void)
static void cxd56_i2cm_clock_disable(void)
{
uint32_t val, rst, mask;
uint32_t val;
uint32_t rst;
uint32_t mask;
val = getreg32(CXD56_TOPREG_SYSIOP_SUB_CKEN);
if (!(val & CK_I2CM))
@@ -1249,7 +1277,8 @@ void cxd56_i2c_clock_gate_disable(int port)
uint32_t cxd56_get_img_uart_baseclock(void)
{
uint32_t val;
int n, m;
int n;
int m;
val = getreg32(CXD56_CRG_GEAR_IMG_UART);
n = (val >> 16) & 1;
@@ -1412,7 +1441,9 @@ static uint32_t cxd56_get_clock(enum clock_source cs)
return CONFIG_CXD56_XOSC_CLOCK;
case SYSPLL:
{
uint32_t ctrl, rc, fb;
uint32_t ctrl;
uint32_t rc;
uint32_t fb;
ctrl = getreg32(CXD56_TOPREG_SYS_PLL_CTRL2);
rc = ctrl >> 30;
@@ -1466,7 +1497,7 @@ uint32_t cxd56_get_sys_baseclock(void)
{
uint32_t div = ((val >> 10) & 0x3) + 1;
if (div == 4 && (val & (1<<2)))
if (div == 4 && (val & (1 << 2)))
{
div = 5;
}
@@ -1525,7 +1556,7 @@ uint32_t cxd56_get_appsmp_baseclock(void)
{
uint32_t div = ((val >> 10) & 0x3) + 1;
if (div == 4 && (val & (1<<7)))
if (div == 4 && (val & (1 << 7)))
{
div = 5;
}
@@ -1554,7 +1585,8 @@ uint32_t cxd56_get_com_baseclock(void)
uint32_t cxd56_get_sdio_baseclock(void)
{
uint32_t val;
int n, m;
int n;
int m;
val = getreg32(CXD56_CRG_GEAR_PER_SDIO);
n = (val >> 16) & 1;
@@ -1573,7 +1605,8 @@ uint32_t cxd56_get_sdio_baseclock(void)
uint32_t cxd56_get_img_spi_baseclock(void)
{
uint32_t val;
int n, m;
int n;
int m;
val = getreg32(CXD56_CRG_GEAR_IMG_SPI);
n = (val >> 16) & 1;
@@ -1592,7 +1625,8 @@ uint32_t cxd56_get_img_spi_baseclock(void)
uint32_t cxd56_get_img_wspi_baseclock(void)
{
uint32_t val;
int n, m;
int n;
int m;
val = getreg32(CXD56_CRG_GEAR_IMG_WSPI);
n = (val >> 16) & 1;
@@ -1704,7 +1738,8 @@ static void cxd56_img_clock_disable(void)
static void cxd56_scu_clock_ctrl(uint32_t block, uint32_t intr, int on)
{
uint32_t val, stat;
uint32_t val;
uint32_t stat;
int retry = 10000;
putreg32(0xffffffff, CXD56_TOPREG_CRG_INT_CLR0);
@@ -1743,7 +1778,8 @@ static void cxd56_scu_clock_ctrl(uint32_t block, uint32_t intr, int on)
static void cxd56_scu_clock_enable(void)
{
uint32_t val, stat;
uint32_t val;
uint32_t stat;
int retry = 1000;
val = getreg32(CXD56_TOPREG_SYSIOP_CKEN);
@@ -1797,7 +1833,8 @@ static void cxd56_scu_clock_enable(void)
void cxd56_scu_clock_disable(void)
{
uint32_t val, stat;
uint32_t val;
uint32_t stat;
int retry = 1000;
val = getreg32(CXD56_TOPREG_SYSIOP_CKEN);
@@ -1823,7 +1860,8 @@ void cxd56_scu_clock_disable(void)
/* Enable each blocks in SCU */
val = getreg32(CXD56_TOPREG_SCU_CKEN);
putreg32(val & ~(SCU_SCU | SCU_SC | SCU_32K | SCU_SEQ), CXD56_TOPREG_SCU_CKEN);
putreg32(val & ~(SCU_SCU | SCU_SC | SCU_32K | SCU_SEQ),
CXD56_TOPREG_SCU_CKEN);
do
{
@@ -1904,7 +1942,8 @@ void cxd56_scuseq_clock_disable(void)
static void cxd56_scu_peri_clock_enable(FAR const struct scu_peripheral *p)
{
uint32_t val, rst;
uint32_t val;
uint32_t rst;
uint32_t cken = 1u << p->cken;
uint32_t crgintmask = 1u << p->crgintmask;
uint32_t swreset = 1u << p->swreset;
@@ -1932,7 +1971,8 @@ static void cxd56_scu_peri_clock_enable(FAR const struct scu_peripheral *p)
static void cxd56_scu_peri_clock_disable(FAR const struct scu_peripheral *p)
{
uint32_t val, rst;
uint32_t val;
uint32_t rst;
uint32_t cken = 1u << p->cken;
uint32_t crgintmask = 1u << p->crgintmask;
uint32_t swreset = 1u << p->swreset;
@@ -1953,7 +1993,8 @@ static void cxd56_scu_peri_clock_disable(FAR const struct scu_peripheral *p)
disable_pwd(PDID_SCU);
}
static void cxd56_scu_peri_clock_gating(FAR const struct scu_peripheral *p, int enable)
static void cxd56_scu_peri_clock_gating(\
FAR const struct scu_peripheral *p, int enable)
{
uint32_t cken = 1u << p->cken;
@@ -2086,7 +2127,8 @@ uint32_t cxd56_get_syspll_clock(void)
uint32_t cxd56_get_sys_ahb_baseclock(void)
{
uint32_t bus, ahb;
uint32_t bus;
uint32_t ahb;
bus = getreg32(CXD56_TOPREG_CKDIV_CPU_DSP_BUS);
ahb = 1 << ((bus >> 16) & 0x7);
@@ -2095,7 +2137,8 @@ uint32_t cxd56_get_sys_ahb_baseclock(void)
uint32_t cxd56_get_sys_apb_baseclock(void)
{
uint32_t bus, apb;
uint32_t bus;
uint32_t apb;
bus = getreg32(CXD56_TOPREG_CKDIV_CPU_DSP_BUS);
apb = 1 << ((bus >> 24) & 0x3);
@@ -2104,7 +2147,8 @@ uint32_t cxd56_get_sys_apb_baseclock(void)
uint32_t cxd56_get_sys_sfc_baseclock(void)
{
uint32_t bus, sfchclk;
uint32_t bus;
uint32_t sfchclk;
bus = getreg32(CXD56_TOPREG_CKDIV_CPU_DSP_BUS);
sfchclk = ((bus >> 28) & 0xf);
@@ -2191,7 +2235,8 @@ uint32_t cxd56_get_gps_ahb_baseclock(void)
uint32_t cxd56_get_usb_baseclock(void)
{
uint32_t val;
int n, m;
int n;
int m;
val = getreg32(CXD56_CRG_GEAR_PER_USB);
n = (val >> 16) & 1;
@@ -2209,7 +2254,8 @@ uint32_t cxd56_get_usb_baseclock(void)
uint32_t cxd56_get_img_vsync_baseclock(void)
{
int n, m;
int n;
int m;
n = getreg32(CXD56_CRG_GEAR_N_IMG_VENB);
m = getreg32(CXD56_CRG_GEAR_M_IMG_VENB);
@@ -2226,9 +2272,13 @@ uint32_t cxd56_get_img_vsync_baseclock(void)
int up_pmramctrl(int cmd, uintptr_t addr, size_t size)
{
int startidx, endidx;
int startidx;
int endidx;
int i;
uint32_t mode, mask, ctrl, stat;
uint32_t mode;
uint32_t mask;
uint32_t ctrl;
uint32_t stat;
uint32_t val;
int changed = 0;
@@ -2317,7 +2367,8 @@ int up_pmramctrl(int cmd, uintptr_t addr, size_t size)
void up_pmstatdump(void)
{
uint32_t stat0, stat1;
uint32_t stat0;
uint32_t stat1;
const char statch[] = " -?+"; /* OFF, retention, invalid, ON */
const char gatech[] = "| "; /* clock on, clock off */
arch/arm/src/cxd56xx/cxd56_cpufifo.c
+1
View File
@@ -80,6 +80,7 @@ static void cpufifo_reserve(uint32_t data[2]);
/****************************************************************************
* Private Data
****************************************************************************/
/* Only for SYS, GNSS CPUs */
static sq_queue_t g_pushqueue;
arch/arm/src/cxd56xx/cxd56_gpio.c
+2 -2
View File
@@ -259,7 +259,7 @@ bool cxd56_gpio_read(uint32_t pin)
return ((regval & (1 << shift)) != 0);
}
/********************************************************************************************
/************************************************************
* Name: cxd56_gpio_status
*
* Description:
@@ -268,7 +268,7 @@ bool cxd56_gpio_read(uint32_t pin)
* Returned Value:
* OK on success; A negated errno value on failure.
*
********************************************************************************************/
*************************************************************/
int cxd56_gpio_status(uint32_t pin, cxd56_gpio_status_t *stat)
{
arch/arm/src/cxd56xx/cxd56_gpio.h
+20 -20
View File
@@ -39,9 +39,9 @@
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_GPIO_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_GPIO_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -50,13 +50,13 @@
#include "cxd56_pinconfig.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
struct cxd56_gpio_status_s
{
@@ -66,9 +66,9 @@ struct cxd56_gpio_status_s
typedef struct cxd56_gpio_status_s cxd56_gpio_status_t;
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@@ -79,11 +79,11 @@ extern "C"
#define EXTERN extern
#endif
/********************************************************************************************
/****************************************************************************
* Public Functions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Name: cxd56_gpio_config
*
* Description:
@@ -93,11 +93,11 @@ extern "C"
* Returned Value:
* OK on success; A negated errno value on failure.
*
********************************************************************************************/
****************************************************************************/
int cxd56_gpio_config(uint32_t pin, bool input_enable);
/********************************************************************************************
/****************************************************************************
* Name: cxd56_gpio_write
*
* Description:
@@ -106,11 +106,11 @@ int cxd56_gpio_config(uint32_t pin, bool input_enable);
* Returned Value:
* None
*
********************************************************************************************/
****************************************************************************/
void cxd56_gpio_write(uint32_t pin, bool value);
/********************************************************************************************
/****************************************************************************
* Name: cxd56_gpio_write_hiz
*
* Description:
@@ -119,11 +119,11 @@ void cxd56_gpio_write(uint32_t pin, bool value);
* Returned Value:
* None
*
********************************************************************************************/
****************************************************************************/
void cxd56_gpio_write_hiz(uint32_t pin);
/********************************************************************************************
/****************************************************************************
* Name: cxd56_gpio_read
*
* Description:
@@ -132,11 +132,11 @@ void cxd56_gpio_write_hiz(uint32_t pin);
* Returned Value:
* The boolean state of the input pin
*
********************************************************************************************/
****************************************************************************/
bool cxd56_gpio_read(uint32_t pin);
/********************************************************************************************
/****************************************************************************
* Name: cxd56_gpio_status
*
* Description:
@@ -145,7 +145,7 @@ bool cxd56_gpio_read(uint32_t pin);
* Returned Value:
* OK on success; A negated errno value on failure.
*
********************************************************************************************/
****************************************************************************/
int cxd56_gpio_status(uint32_t pin, cxd56_gpio_status_t *stat);
arch/arm/src/cxd56xx/cxd56_gpioint.c
+8 -5
View File
@@ -450,9 +450,9 @@ int cxd56_gpioint_config(uint32_t pin, uint32_t gpiocfg, xcpt_t isr)
/* set GPIO interrupt configuration */
if (gpiocfg & GPIOINT_TOGGLE_BOTH_MASK) {
/* set GPIO pseudo both edge interrupt */
if (gpiocfg & GPIOINT_TOGGLE_BOTH_MASK)
{
/* set GPIO pseudo both edge interrupt */
flags = enter_critical_section();
g_bothedge |= (1 << slot);
@@ -460,9 +460,12 @@ int cxd56_gpioint_config(uint32_t pin, uint32_t gpiocfg, xcpt_t isr)
/* detect the change from the current signal */
if (true == cxd56_gpio_read(pin)) {
if (true == cxd56_gpio_read(pin))
{
gpiocfg |= GPIOINT_SET_POLARITY(GPIOINT_LEVEL_LOW);
} else {
}
else
{
gpiocfg |= GPIOINT_SET_POLARITY(GPIOINT_LEVEL_HIGH);
}
}
arch/arm/src/cxd56xx/cxd56_gpioint.h
+6 -4
View File
@@ -65,8 +65,8 @@
/* GPIO Interrupt Polarity Definitions */
//#define GPIOINT_INSTANT_HIGH (0) /* Not supported */
//#define GPIOINT_INSTANT_LOW (1) /* Not supported */
/* #define GPIOINT_INSTANT_HIGH (0) */ /* Not supported */
/* #define GPIOINT_INSTANT_LOW (1) */ /* Not supported */
#define GPIOINT_LEVEL_HIGH (2) /* High Level */
#define GPIOINT_LEVEL_LOW (3) /* Low Level */
#define GPIOINT_EDGE_RISE (4) /* Rising Edge */
@@ -75,9 +75,11 @@
#define GPIOINT_PSEUDO_EDGE_RISE (GPIOINT_LEVEL_HIGH | \
GPIOINT_TOGGLE_MODE_MASK)
/* Rising Edge without clear */
#define GPIOINT_PSEUDO_EDGE_FALL (GPIOINT_LEVEL_LOW | \
GPIOINT_TOGGLE_MODE_MASK)
/* Falling Edge without clear */
#define GPIOINT_PSEUDO_EDGE_BOTH (GPIOINT_TOGGLE_MODE_MASK | \
GPIOINT_TOGGLE_BOTH_MASK)
/* Both Edge without clear */
@@ -209,7 +211,7 @@ void cxd56_gpioint_disable(uint32_t pin);
void cxd56_gpioint_invert(uint32_t pin);
/********************************************************************************************
/****************************************************************************
* Name: cxd56_gpioint_status
*
* Description:
@@ -218,7 +220,7 @@ void cxd56_gpioint_invert(uint32_t pin);
* Returned Value:
* OK on success; A negated errno value on failure.
*
********************************************************************************************/
****************************************************************************/
int cxd56_gpioint_status(uint32_t pin, cxd56_gpioint_status_t *stat);
arch/arm/src/cxd56xx/cxd56_irq.c
+1 -7
View File
@@ -123,13 +123,6 @@ static void cxd56_dumpnvic(const char *msg, int irq)
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n", getreg32(NVIC_INTCTRL),
getreg32(NVIC_VECTAB));
# if 0
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA),
getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA),
getreg32(NVIC_SYSTICK_CTRL_ENABLE));
# endif
irqinfo(" IRQ ENABLE: %08x %08x\n", getreg32(NVIC_IRQ0_31_ENABLE),
getreg32(NVIC_IRQ32_63_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
@@ -360,6 +353,7 @@ void up_irqinitialize(void)
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(CXD56_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
cxd56_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
#endif
arch/arm/src/cxd56xx/cxd56_pinconfig.c
+4 -3
View File
@@ -390,7 +390,8 @@ int cxd56_pin_configs(uint32_t pinconfs[], size_t n)
if (((PIN_I2S0_BCK == pin) || (PIN_I2S1_BCK == pin)) &&
(PINCONF_MODE1 == mode))
{
set_i2s_output_config(pin, mode, PINCONF_INPUT_ENABLED(pinconfs[i]));
set_i2s_output_config(pin, mode,
PINCONF_INPUT_ENABLED(pinconfs[i]));
}
ret = get_mode_regaddr(pin, &modereg, &shift);
@@ -408,7 +409,7 @@ int cxd56_pin_configs(uint32_t pinconfs[], size_t n)
return 0;
}
/********************************************************************************************
/****************************************************************************
* Name: cxd56_pin_status
*
* Description:
@@ -417,7 +418,7 @@ int cxd56_pin_configs(uint32_t pinconfs[], size_t n)
* Returned Value:
* OK on success; A negated errno value on failure.
*
********************************************************************************************/
****************************************************************************/
int cxd56_pin_status(uint32_t pin, cxd56_pin_status_t *stat)
{
arch/arm/src/cxd56xx/cxd56_pinconfig.h
+16 -16
View File
@@ -39,9 +39,9 @@
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_PINCONFIG_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_PINCONFIG_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -52,9 +52,9 @@
#include <arch/chip/pin.h>
#include "hardware/cxd5602_pinconfig.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* 32-bit encoded pinconf value
*
@@ -140,9 +140,9 @@
cxd56_pin_configs((p), sizeof(p) / sizeof((p)[0])); \
} while (0)
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
struct cxd56_pin_status_s
{
@@ -154,9 +154,9 @@ struct cxd56_pin_status_s
typedef struct cxd56_pin_status_s cxd56_pin_status_t;
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@@ -167,11 +167,11 @@ extern "C"
#define EXTERN extern
#endif
/********************************************************************************************
/****************************************************************************
* Public Functions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Name: cxd56_pin_config
*
* Description:
@@ -183,11 +183,11 @@ extern "C"
* Returned Value:
* OK on success; A negated errno value on failure.
*
********************************************************************************************/
****************************************************************************/
int cxd56_pin_config(uint32_t pinconf);
/********************************************************************************************
/****************************************************************************
* Name: cxd56_pin_configs
*
* Description:
@@ -200,11 +200,11 @@ int cxd56_pin_config(uint32_t pinconf);
* Returned Value:
* OK on success; A negated errno value on failure.
*
********************************************************************************************/
****************************************************************************/
int cxd56_pin_configs(uint32_t pinconfs[], size_t n);
/********************************************************************************************
/****************************************************************************
* Name: cxd56_pin_status
*
* Description:
@@ -213,7 +213,7 @@ int cxd56_pin_configs(uint32_t pinconfs[], size_t n);
* Returned Value:
* OK on success; A negated errno value on failure.
*
********************************************************************************************/
****************************************************************************/
int cxd56_pin_status(uint32_t pin, cxd56_pin_status_t *stat);
arch/arm/src/cxd56xx/cxd56_pmic.c
+20 -12
View File
@@ -62,6 +62,7 @@
enum pmic_cmd_type_e
{
/* basic */
PMIC_CMD_READ = 0x00,
PMIC_CMD_WRITE,
PMIC_CMD_GPO,
@@ -72,7 +73,9 @@ enum pmic_cmd_type_e
PMIC_CMD_GETPREVSYS,
PMIC_CMD_SETVSYS,
PMIC_CMD_GETVSYS,
/* charger */
PMIC_CMD_GAUGE = 0x10,
PMIC_CMD_GET_USB_PORT_TYPE,
PMIC_CMD_GET_CHG_STATE,
@@ -90,7 +93,9 @@ enum pmic_cmd_type_e
PMIC_CMD_CHG_PAUSE,
PMIC_CMD_CHG_ENABLE,
PMIC_CMD_CHG_DISABLE,
/* power monitor */
PMIC_CMD_POWER_MONITOR_ENABLE = 0x30,
PMIC_CMD_POWER_MONITOR_STATUS,
PMIC_CMD_POWER_MONITOR_SET,
@@ -142,6 +147,7 @@ enum pmic_cmd_type_e
/****************************************************************************
* Private Types
****************************************************************************/
/* FarAPI interface structures */
struct pmic_afe_s
@@ -173,13 +179,13 @@ static struct work_s g_irqwork;
****************************************************************************/
#ifdef CONFIG_CXD56_PMIC_INT
/************************************************************************************
/****************************************************************************
* Name: is_notify_registerd
*
* Description:
* Return whether any notification is registered or not
*
************************************************************************************/
****************************************************************************/
static bool is_notify_registerd(void)
{
@@ -195,13 +201,13 @@ static bool is_notify_registerd(void)
return false;
}
/************************************************************************************
/****************************************************************************
* Name: pmic_int_worker
*
* Description:
* Work queue for pmic interrupt
*
************************************************************************************/
****************************************************************************/
static void pmic_int_worker(void *arg)
{
@@ -236,13 +242,13 @@ static void pmic_int_worker(void *arg)
leave_critical_section(flags);
}
/************************************************************************************
/****************************************************************************
* Name: pmic_int_handler
*
* Description:
* Interrupt handler for pmic interrupt
*
************************************************************************************/
****************************************************************************/
static int pmic_int_handler(int irq, void *context, void *arg)
{
@@ -451,7 +457,7 @@ int cxd56_pmic_set_gpo_hiz(uint8_t chset)
* chset : GPO Channel number(s)
*
* Returned Value:
* Return true if all of the specified chset are high. Otherwise, return false
* Return true if all of the specified chset are high. Else, return false
*
****************************************************************************/
@@ -691,17 +697,19 @@ int cxd56_pmic_get_rtc(uint64_t *count)
ret = cxd56_pmic_write(PMIC_REG_RRQ_TIME, &data, sizeof(data));
if (ret) goto error;
do {
do
{
ret = cxd56_pmic_read(PMIC_REG_RRQ_LRQ_STATUS, &data, sizeof(data));
if (ret) goto error;
} while (!(RRQ_TIME_STATE & data));
}
while (!(RRQ_TIME_STATE & data));
ret = cxd56_pmic_read(PMIC_REG_RTC, rtc, sizeof(rtc));
if (ret) goto error;
*count =
(((uint64_t)((rtc[5] << 24) | (rtc[4] << 16) | (rtc[3] << 8) | rtc[2]) << 15) |
((rtc[1] << 8) | rtc[0]));
(((uint64_t)((rtc[5] << 24) | (rtc[4] << 16) | (rtc[3] << 8) |
rtc[2]) << 15) | ((rtc[1] << 8) | rtc[0]));
error:
return ret;
@@ -1112,7 +1120,7 @@ int cxd56_pmic_setchargecompcurrent(int current)
break;
}
return PM_PmicControl(PMIC_CMD_SET_CHG_IFIN, (void*)val);
return PM_PmicControl(PMIC_CMD_SET_CHG_IFIN, (void *)val);
}
/****************************************************************************
arch/arm/src/cxd56xx/cxd56_pmic.h
+6 -6
View File
@@ -165,7 +165,7 @@ struct pmic_mon_s
struct pmic_mon_status_s
{
int bRun;
int brun;
int index;
int latest;
int total_watt;
@@ -174,8 +174,8 @@ struct pmic_mon_status_s
struct pmic_mon_set_s
{
int clearBuf;
int clearSum;
int clearbuf;
int clearsum;
};
struct pmic_mon_rec_s
@@ -305,7 +305,7 @@ int cxd56_pmic_set_gpo_hiz(uint8_t chset);
* chset : GPO Channel number(s)
*
* Returned Value:
* Return true if all of the specified chset are high. Otherwise, return false
* Return true if all of the specified chset are high. Else, return false
*
****************************************************************************/
@@ -573,7 +573,7 @@ int cxd56_pmic_getchargestate(FAR uint8_t *state);
*
****************************************************************************/
int cxd56_pmic_setrechargevol(int mV);
int cxd56_pmic_setrechargevol(int mv);
/****************************************************************************
* Name: cxd56_pmic_getrechargevol
@@ -589,7 +589,7 @@ int cxd56_pmic_setrechargevol(int mV);
*
****************************************************************************/
int cxd56_pmic_getrechargevol(FAR int *mV);
int cxd56_pmic_getrechargevol(FAR int *mv);
/****************************************************************************
* Name: cxd56_pmic_setchargecompcurrent
arch/arm/src/cxd56xx/cxd56_sdhci.c
+275 -167
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/cxd56xx/cxd56_sdhci.h
+84 -53
View File
@@ -89,6 +89,7 @@ extern "C"
#define CXD56_SDHCI_USERDEF2CTL_OFFSET (0x0274) /* User Define2 Control Register */
/* Register Addresses *******************************************************/
#define CXD56_SDHCI_BASE CXD56_SDIO_BASE
#define CXD56_SDHCI_DSADDR (CXD56_SDHCI_BASE+CXD56_SDHCI_DSADDR_OFFSET)
@@ -122,13 +123,14 @@ extern "C"
/* DMA System Address Register */
#define SDHCI_DSADDR_SHIFT (1) /* Bits 1-31: DMA System Address */
#define SDHCI_DSADDR_MASK (0xfffffffe)
/* Bits 0-1: Reserved */
#define SDHCI_DSADDR_MASK (0xfffffffe) /* Bits 0-1: Reserved */
/* Block Attributes Register */
#define SDHCI_BLKATTR_SIZE_SHIFT (0) /* Bits 0-12: Transfer Block Size */
#define SDHCI_BLKATTR_SIZE_MASK (0x1fff << SDHCI_BLKATTR_SIZE_SHIFT)
/* Bits 13-15: Reserved */
#define SDHCI_BLKATTR_CNT_SHIFT (16) /* Bits 16-31: Blocks Count For Current Transfer */
#define SDHCI_BLKATTR_CNT_MASK (0xffff << SDHCI_BLKATTR_CNT_SHIFT)
@@ -139,29 +141,33 @@ extern "C"
#define SDHCI_XFERTYP_DMAEN (1 << 0) /* Bit 0: DMA Enable */
#define SDHCI_XFERTYP_BCEN (1 << 1) /* Bit 1: Block Count Enable */
#define SDHCI_XFERTYP_AC12EN (1 << 2) /* Bit 2: Auto CMD12 Enable */
/* Bit 3: Reserved */
/* Bit 3: Reserved */
#define SDHCI_XFERTYP_DTDSEL (1 << 4) /* Bit 4: Data Transfer Direction Select */
#define SDHCI_XFERTYP_MSBSEL (1 << 5) /* Bit 5: Multi/Single Block Select */
/* Bits 6-15: Reserved */
/* Bits 6-15: Reserved */
#define SDHCI_XFERTYP_RSPTYP_SHIFT (16) /* Bits 16-17: Response Type Select */
#define SDHCI_XFERTYP_RSPTYP_MASK (3 << SDHCI_XFERTYP_RSPTYP_SHIFT)
# define SDHCI_XFERTYP_RSPTYP_NONE (0 << SDHCI_XFERTYP_RSPTYP_SHIFT) /* No response */
# define SDHCI_XFERTYP_RSPTYP_LEN136 (1 << SDHCI_XFERTYP_RSPTYP_SHIFT) /* Response length 136 */
# define SDHCI_XFERTYP_RSPTYP_LEN48 (2 << SDHCI_XFERTYP_RSPTYP_SHIFT) /* Response length 48 */
# define SDHCI_XFERTYP_RSPTYP_LEN48BSY (3 << SDHCI_XFERTYP_RSPTYP_SHIFT) /* Response length 48, check busy */
#define SDHCI_XFERTYP_RSPTYP_NONE (0 << SDHCI_XFERTYP_RSPTYP_SHIFT) /* No response */
#define SDHCI_XFERTYP_RSPTYP_LEN136 (1 << SDHCI_XFERTYP_RSPTYP_SHIFT) /* Response length 136 */
#define SDHCI_XFERTYP_RSPTYP_LEN48 (2 << SDHCI_XFERTYP_RSPTYP_SHIFT) /* Response length 48 */
#define SDHCI_XFERTYP_RSPTYP_LEN48BSY (3 << SDHCI_XFERTYP_RSPTYP_SHIFT) /* Response length 48, check busy */
/* Bit 18: Reserved */
#define SDHCI_XFERTYP_CCCEN (1 << 19) /* Bit 19: Command CRC Check Enable */
#define SDHCI_XFERTYP_CICEN (1 << 20) /* Bit 20: Command Index Check Enable */
#define SDHCI_XFERTYP_DPSEL (1 << 21) /* Bit 21: Data Present Select */
#define SDHCI_XFERTYP_CMDTYP_SHIFT (22) /* Bits 22-23: Command Type */
#define SDHCI_XFERTYP_CMDTYP_MASK (3 << SDHCI_XFERTYP_CMDTYP_SHIFT)
# define SDHCI_XFERTYP_CMDTYP_NORMAL (0 << SDHCI_XFERTYP_CMDTYP_SHIFT) /* Normal other commands */
# define SDHCI_XFERTYP_CMDTYP_SUSPEND (1 << SDHCI_XFERTYP_CMDTYP_SHIFT) /* Suspend CMD52 for writing bus suspend in CCCR */
# define SDHCI_XFERTYP_CMDTYP_RESUME (2 << SDHCI_XFERTYP_CMDTYP_SHIFT) /* Resume CMD52 for writing function select in CCCR */
# define SDHCI_XFERTYP_CMDTYP_ABORT (3 << SDHCI_XFERTYP_CMDTYP_SHIFT) /* Abort CMD12, CMD52 for writing I/O abort in CCCR */
#define SDHCI_XFERTYP_CMDTYP_NORMAL (0 << SDHCI_XFERTYP_CMDTYP_SHIFT) /* Normal other commands */
#define SDHCI_XFERTYP_CMDTYP_SUSPEND (1 << SDHCI_XFERTYP_CMDTYP_SHIFT) /* Suspend CMD52 for writing bus suspend in CCCR */
#define SDHCI_XFERTYP_CMDTYP_RESUME (2 << SDHCI_XFERTYP_CMDTYP_SHIFT) /* Resume CMD52 for writing function select in CCCR */
#define SDHCI_XFERTYP_CMDTYP_ABORT (3 << SDHCI_XFERTYP_CMDTYP_SHIFT) /* Abort CMD12, CMD52 for writing I/O abort in CCCR */
#define SDHCI_XFERTYP_CMDINX_SHIFT (24) /* Bits 24-29: Command Index */
#define SDHCI_XFERTYP_CMDINX_MASK (63 << SDHCI_XFERTYP_CMDINX_SHIFT)
/* Bits 30-31: Reserved */
/* Command Response 0-3 (32-bit response data) */
/* Buffer Data Port Register (32-bit data content) */
@@ -180,17 +186,18 @@ extern "C"
#define SDHCI_PRSSTAT_RTA (1 << 9) /* Bit 9: Read Transfer Active */
#define SDHCI_PRSSTAT_BWEN (1 << 10) /* Bit 10: Buffer Write Enable */
#define SDHCI_PRSSTAT_BREN (1 << 11) /* Bit 11: Buffer Read Enable */
/* Bits 12-15: Reserved */
/* Bits 12-15: Reserved */
#define SDHCI_PRSSTAT_CINS (1 << 16) /* Bit 16: Card Inserted */
#define SDHCI_PRSSTAT_CSTS (1 << 17) /* Bit 17: Card State Stable */
#define SDHCI_PRSSTAT_SDCD (1 << 18) /* Bit 18: Card Detect Pin Level */
#define SDHCI_PRSSTAT_SDWPN (1 << 19) /* Bit 19: Write Protect Switch Pin Level*/
#define SDHCI_PRSSTAT_SDWPN (1 << 19) /* Bit 19: Write Protect Switch Pin Level*/
#define SDHCI_PRSSTAT_DLSL_SHIFT (20) /* Bits 20-23: DAT Line Signal Level */
#define SDHCI_PRSSTAT_DLSL_MASK (0xf << SDHCI_PRSSTAT_DLSL_SHIFT)
# define SDHCI_PRSSTAT_DLSL_DAT0 (0x1 << SDHCI_PRSSTAT_DLSL_SHIFT)
# define SDHCI_PRSSTAT_DLSL_DAT1 (0x2 << SDHCI_PRSSTAT_DLSL_SHIFT)
# define SDHCI_PRSSTAT_DLSL_DAT2 (0x4 << SDHCI_PRSSTAT_DLSL_SHIFT)
# define SDHCI_PRSSTAT_DLSL_DAT3 (0x8 << SDHCI_PRSSTAT_DLSL_SHIFT)
#define SDHCI_PRSSTAT_DLSL_DAT0 (0x1 << SDHCI_PRSSTAT_DLSL_SHIFT)
#define SDHCI_PRSSTAT_DLSL_DAT1 (0x2 << SDHCI_PRSSTAT_DLSL_SHIFT)
#define SDHCI_PRSSTAT_DLSL_DAT2 (0x4 << SDHCI_PRSSTAT_DLSL_SHIFT)
#define SDHCI_PRSSTAT_DLSL_DAT3 (0x8 << SDHCI_PRSSTAT_DLSL_SHIFT)
#define SDHCI_PRSSTAT_CLSL (1 << 24) /* Bit 23: CMD Line Signal Level */
/* Protocol Control Register */
@@ -198,24 +205,27 @@ extern "C"
#define SDHCI_PROCTL_LCTL (1 << 0) /* Bit 0: LED Control */
#define SDHCI_PROCTL_DTW_SHIFT (1) /* Bits 1-2: Data Transfer Width */
#define SDHCI_PROCTL_DTW_MASK (1 << SDHCI_PROCTL_DTW_SHIFT)
# define SDHCI_PROCTL_DTW_1BIT (0 << SDHCI_PROCTL_DTW_SHIFT) /* 1-bit mode */
# define SDHCI_PROCTL_DTW_4BIT (1 << SDHCI_PROCTL_DTW_SHIFT) /* 4-bit mode */
#define SDHCI_PROCTL_DTW_1BIT (0 << SDHCI_PROCTL_DTW_SHIFT) /* 1-bit mode */
#define SDHCI_PROCTL_DTW_4BIT (1 << SDHCI_PROCTL_DTW_SHIFT) /* 4-bit mode */
#define SDHCI_PROCTL_DMAS_SHIFT (3) /* Bits 8-9: DMA Select */
#define SDHCI_PROCTL_DMAS_MASK (3 << SDHCI_PROCTL_DMAS_SHIFT)
# define SDHCI_PROCTL_DMAS_NODMA (0 << SDHCI_PROCTL_DMAS_SHIFT) /* No DMA or simple DMA is selected */
# define SDHCI_PROCTL_DMAS_ADMA2 (2 << SDHCI_PROCTL_DMAS_SHIFT) /* ADMA2 is selected */
#define SDHCI_PROCTL_DMAS_NODMA (0 << SDHCI_PROCTL_DMAS_SHIFT) /* No DMA or simple DMA is selected */
#define SDHCI_PROCTL_DMAS_ADMA2 (2 << SDHCI_PROCTL_DMAS_SHIFT) /* ADMA2 is selected */
#define SDHCI_PROCTL_CDTL (1 << 6) /* Bit 6: Card Detect Test Level */
#define SDHCI_PROCTL_CDSS (1 << 7) /* Bit 7: Card Detect Signal Selection */
/* Bits 10-15: Reserved */
/* Bits 10-15: Reserved */
#define SDHCI_PROCTL_SABGREQ (1 << 16) /* Bit 16: Stop At Block Gap Request */
#define SDHCI_PROCTL_CREQ (1 << 17) /* Bit 17: Continue Request */
#define SDHCI_PROCTL_RWCTL (1 << 18) /* Bit 18: Read Wait Control */
#define SDHCI_PROCTL_IABG (1 << 19) /* Bit 19: Interrupt At Block Gap */
/* Bits 20-23: Reserved */
/* Bits 20-23: Reserved */
#define SDHCI_PROCTL_WECINT (1 << 24) /* Bit 24: Wakeup Event Enable On Card Interrupt */
#define SDHCI_PROCTL_WECINS (1 << 25) /* Bit 25: Wakeup Event Enable On SD Card Insertion */
#define SDHCI_PROCTL_WECRM (1 << 26) /* Bit 26: Wakeup Event Enable On SD Card Removal */
/* Bits 27-31: Reserved */
/* Bits 27-31: Reserved */
/* System Control Register */
#define SDHCI_SYSCTL_ICLKEN (1 << 0) /* Bit 0: Internal Clock Enable */
@@ -228,14 +238,17 @@ extern "C"
#define SDHCI_SYSCTL_SDCLKFS_MASK (0xff << SDHCI_SYSCTL_SDCLKFS_SHIFT)
#define SDHCI_SYSCTL_DTOCV_SHIFT (16) /* Bits 16-19: Data Timeout Counter Value */
#define SDHCI_SYSCTL_DTOCV_MASK (0xf << SDHCI_SYSCTL_DTOCV_SHIFT)
# define SDHCI_SYSCTL_DTOCV_MUL(n) (((n)-213) << SDHCI_SYSCTL_DTOCV_SHIFT) /* SDCLK x n, n=213..227 */
#define SDHCI_SYSCTL_DTOCV_MUL(n) (((n)-213) << SDHCI_SYSCTL_DTOCV_SHIFT) /* SDCLK x n, n=213..227 */
/* Bits 20-23: Reserved */
#define SDHCI_SYSCTL_RSTA (1 << 24) /* Bit 24: Software Reset For ALL */
#define SDHCI_SYSCTL_RSTC (1 << 25) /* Bit 25: Software Reset For CMD Line */
#define SDHCI_SYSCTL_RSTD (1 << 26) /* Bit 26: Software Reset For DAT Line */
#define SDHCI_SYSCTL_INITA (1 << 27) /* Bit 27: Initialization Active */
/* Bits 28-31: Reserved */
/* Interrupt Status Register, Interrupt Status Enable Register, and Interrupt Signal Enable Register
/* Interrupt Status Register, Interrupt Status Enable Register,
* and Interrupt Signal Enable Register
* Common interrupt bit definitions
*/
@@ -248,7 +261,8 @@ extern "C"
#define SDHCI_INT_CINS (1 << 6) /* Bit 6: Card Insertion */
#define SDHCI_INT_CRM (1 << 7) /* Bit 7: Card Removal */
#define SDHCI_INT_CINT (1 << 8) /* Bit 8: Card Interrupt */
/* Bits 9-15: Reserved */
/* Bits 9-15: Reserved */
#define SDHCI_INT_CTOE (1 << 16) /* Bit 16: Command Timeout Error */
#define SDHCI_INT_CCE (1 << 17) /* Bit 17: Command CRC Error */
#define SDHCI_INT_CEBE (1 << 18) /* Bit 18: Command End Bit Error */
@@ -256,11 +270,14 @@ extern "C"
#define SDHCI_INT_DTOE (1 << 20) /* Bit 20: Data Timeout Error */
#define SDHCI_INT_DCE (1 << 21) /* Bit 21: Data CRC Error */
#define SDHCI_INT_DEBE (1 << 22) /* Bit 22: Data End Bit Error */
/* Bit 23: Reserved */
/* Bit 23: Reserved */
#define SDHCI_INT_AC12E (1 << 24) /* Bit 24: Auto CMD12 Error */
/* Bits 25-27: Reserved */
/* Bits 25-27: Reserved */
#define SDHCI_INT_DMAE (1 << 28) /* Bit 28: DMA Error */
/* Bits 29-31: Reserved */
/* Bits 29-31: Reserved */
#define SDHCI_INT_ALL 0x117f01ff
/* Auto CMD12 Error Status Register */
@@ -270,18 +287,23 @@ extern "C"
#define SDHCI_AC12ERR_EBE (1 << 2) /* Bit 2: Auto CMD12 End Bit Error */
#define SDHCI_AC12ERR_CE (1 << 3) /* Bit 3: Auto CMD12 CRC Error */
#define SDHCI_AC12ERR_IE (1 << 4) /* Bit 4: Auto CMD12 Index Error */
/* Bits 5-6: Reserved */
/* Bits 5-6: Reserved */
#define SDHCI_AC12ERR_CNI (1 << 7) /* Bit 7: Command Not Issued By Auto CMD12 Error */
/* Bits 8-31: Reserved */
/* Bits 8-31: Reserved */
/* Host Controller Capabilities */
/* Bits 0-15: Reserved */
#define SDHCI_HTCAPBLT_MBL_SHIFT (16) /* Bits 16-18: Max Block Length */
#define SDHCI_HTCAPBLT_MBL_MASK (7 << SDHCI_HTCAPBLT_MBL_SHIFT)
# define SDHCI_HTCAPBLT_MBL_512BYTES (0 << SDHCI_HTCAPBLT_MBL_SHIFT)
# define SDHCI_HTCAPBLT_MBL_1KB (1 << SDHCI_HTCAPBLT_MBL_SHIFT)
# define SDHCI_HTCAPBLT_MBL_2KB (2 << SDHCI_HTCAPBLT_MBL_SHIFT)
# define SDHCI_HTCAPBLT_MBL_4KB (3 << SDHCI_HTCAPBLT_MBL_SHIFT)
/* Bit 19: Reserved */
#define SDHCI_HTCAPBLT_MBL_512BYTES (0 << SDHCI_HTCAPBLT_MBL_SHIFT)
#define SDHCI_HTCAPBLT_MBL_1KB (1 << SDHCI_HTCAPBLT_MBL_SHIFT)
#define SDHCI_HTCAPBLT_MBL_2KB (2 << SDHCI_HTCAPBLT_MBL_SHIFT)
#define SDHCI_HTCAPBLT_MBL_4KB (3 << SDHCI_HTCAPBLT_MBL_SHIFT)
/* Bit 19: Reserved */
#define SDHCI_HTCAPBLT_ADMAS (1 << 20) /* Bit 20: ADMA Support */
#define SDHCI_HTCAPBLT_HSS (1 << 21) /* Bit 21: High Speed Support */
#define SDHCI_HTCAPBLT_DMAS (1 << 22) /* Bit 22: DMA Support */
@@ -290,6 +312,7 @@ extern "C"
#define SDHCI_HTCAPBLT_VS30 (1 << 25) /* Bit 25: Voltage Support 3.0 V */
#define SDHCI_HTCAPBLT_VS18 (1 << 26) /* Bit 26: Voltage Support 1.8 */
/* Bits 27-31: Reserved */
/* Force Event Register */
#define SDHCI_FEVT_AC12NE (1 << 0) /* Bit 0: Force Event Auto Command 12 Not Executed */
@@ -297,9 +320,11 @@ extern "C"
#define SDHCI_FEVT_AC12CE (1 << 2) /* Bit 2: Force Event Auto Command 12 CRC Error */
#define SDHCI_FEVT_AC12EBE (1 << 3) /* Bit 3: Force Event Auto Command 12 End Bit Error */
#define SDHCI_FEVT_AC12IE (1 << 4) /* Bit 4: Force Event Auto Command 12 Index Error */
/* Bits 5-6: Reserved */
/* Bits 5-6: Reserved */
#define SDHCI_FEVT_CNIBAC12E (1 << 7) /* Bit 7: Force Event Command Not Executed By Auto Command 12 Error */
/* Bits 8-15: Reserved */
/* Bits 8-15: Reserved */
#define SDHCI_FEVT_CTOE (1 << 16) /* Bit 16: Force Event Command Time Out Error */
#define SDHCI_FEVT_CCE (1 << 17) /* Bit 17: Force Event Command CRC Error */
#define SDHCI_FEVT_CEBE (1 << 18) /* Bit 18: Force Event Command End Bit Error */
@@ -307,35 +332,40 @@ extern "C"
#define SDHCI_FEVT_DTOE (1 << 20) /* Bit 20: Force Event Data Time Out Error */
#define SDHCI_FEVT_DCE (1 << 21) /* Bit 21: Force Event Data CRC Error */
#define SDHCI_FEVT_DEBE (1 << 22) /* Bit 22: Force Event Data End Bit Error */
/* Bit 23: Reserved */
/* Bit 23: Reserved */
#define SDHCI_FEVT_AC12E (1 << 24) /* Bit 24: Force Event Auto Command 12 Error */
/* Bits 25-27: Reserved */
/* Bits 25-27: Reserved */
#define SDHCI_FEVT_DMAE (1 << 28) /* Bit 28: Force Event DMA Error */
/* Bits 29-30: Reserved */
/* Bits 29-30: Reserved */
#define SDHCI_FEVT_CINT (1 << 31) /* Bit 31: Force Event Card Interrupt */
/* ADMA Error Status Register */
#define SDHCI_ADMAES_SHIFT (0) /* Bits 0-1: ADMA Error State (when ADMA Error is occurred) */
#define SDHCI_ADMAES_MASK (3 << SDHCI_ADMAES_ADMAES_SHIFT)
# define SDHCI_ADMAES_STOP (0 << SDHCI_ADMAES_ADMAES_SHIFT) /* Stop DMA */
# define SDHCI_ADMAES_FDS (1 << SDHCI_ADMAES_ADMAES_SHIFT) /* Fetch descriptor */
# define SDHCI_ADMAES_CADR (2 << SDHCI_ADMAES_ADMAES_SHIFT) /* Change address */
# define SDHCI_ADMAES_TFR (3 << SDHCI_ADMAES_ADMAES_SHIFT) /* Transfer data */
#define SDHCI_ADMAES_STOP (0 << SDHCI_ADMAES_ADMAES_SHIFT) /* Stop DMA */
#define SDHCI_ADMAES_FDS (1 << SDHCI_ADMAES_ADMAES_SHIFT) /* Fetch descriptor */
#define SDHCI_ADMAES_CADR (2 << SDHCI_ADMAES_ADMAES_SHIFT) /* Change address */
#define SDHCI_ADMAES_TFR (3 << SDHCI_ADMAES_ADMAES_SHIFT) /* Transfer data */
#define SDHCI_ADMAES_LME (1 << 2) /* Bit 2: ADMA Length Mismatch Error */
#define SDHCI_ADMAES_DCE (1 << 3) /* Bit 3: ADMA Descriptor Error */
/* Bits 4-31: Reserved */
/* Bits 4-31: Reserved */
/* ADMA System Address Register */
#define SDHCI_ADSADDR_SHIFT (1) /* Bits 1-31: ADMA System Address */
#define SDHCI_ADSADDR_MASK (0xfffffffe)
/* Bits 0-1: Reserved */
/* Bits 0-1: Reserved */
/* Vendor Specific Register */
#define SDHCI_VENDOR_EXTDMAEN (1 << 0) /* Bit 0: External DMA Request Enable */
#define SDHCI_VENDOR_EXBLKNU (1 << 1) /* Bit 1: Exact block number block read enable for SDIO CMD53 */
/* Bits 2-15: Reserved */
/* Bits 2-15: Reserved */
#define SDHCI_VENDOR_INTSTVAL_SHIFT (16) /* Bits 16-23: Internal State Value */
#define SDHCI_VENDOR_INTSTVAL_MASK (0xff << SDHCI_VENDOR_INTSTVAL_SHIFT)
/* Bits 24-31: Reserved */
@@ -387,7 +417,6 @@ struct sdio_dev_s;
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: cxd56_sdhci_initialize
*
@@ -398,7 +427,8 @@ struct sdio_dev_s;
* slotno - Not used.
*
* Returned Values:
* A reference to an SDIO interface structure. NULL is returned on failures.
* A reference to an SDIO interface structure.
* NULL is returned on failures.
*
****************************************************************************/
@@ -414,7 +444,8 @@ FAR struct sdio_dev_s *cxd56_sdhci_initialize(int slotno);
* slotno - Not used.
*
* Returned Values:
* A reference to an SDIO interface structure. NULL is returned on failures.
* A reference to an SDIO interface structure.
* NULL is returned on failures.
*
****************************************************************************/
arch/arm/src/cxd56xx/cxd56_start.c
+5 -4
View File
@@ -47,10 +47,11 @@
* The boot starts after reset is released. The IRC is selected as CPU clock
* and the Cortex-M4 starts the boot loader. By default the JTAG access to the
* chip is disabled at reset. The boot ROM determines the boot mode based on
* the OTP BOOT_SRC value or reset state pins. For flash-based parts, the part
* boots from internal flash by default. Otherwse, the boot ROM copies the
* image to internal SRAM at location 0x1000:0000, sets the ARM's shadow
* pointer to 0x1000:0000, and jumps to that location.
* the OTP BOOT_SRC value or reset state pins. For flash-based parts,
* the part boots from internal flash by default.
* Otherwse, the boot ROM copies the image to internal SRAM at location
* 0x1000:0000, sets the ARM's shadow pointer to 0x1000:0000,
* and jumps to that location.
*
* However, using JTAG the executable image can be also loaded directly into
* and executed from SRAM.
arch/arm/src/cxd56xx/cxd56_usbdev.c
+27 -20
View File
@@ -76,6 +76,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* TOPREG VBUS regsiter */
#define CLR_EDGE (1 << 9)
@@ -424,7 +425,8 @@ struct cxd56_usbdev_file_s
};
static struct pm_cpu_freqlock_s g_hv_lock =
PM_CPUFREQLOCK_INIT(PM_CPUFREQLOCK_TAG('U', 'S', 0), PM_CPUFREQLOCK_FLAG_HV);
PM_CPUFREQLOCK_INIT(PM_CPUFREQLOCK_TAG('U', 'S', 0),
PM_CPUFREQLOCK_FLAG_HV);
static struct pm_cpu_wakelock_s g_wake_lock =
{
.count = 0,
@@ -500,7 +502,8 @@ static int cxd56_epstall(FAR struct usbdev_ep_s *ep, bool resume);
static FAR struct usbdev_ep_s *cxd56_allocep(FAR struct usbdev_s *dev,
uint8_t epno, bool in,
uint8_t eptype);
static void cxd56_freeep(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep);
static void cxd56_freeep(FAR struct usbdev_s *dev,
FAR struct usbdev_ep_s *ep);
static int cxd56_getframe(FAR struct usbdev_s *dev);
static int cxd56_wakeup(FAR struct usbdev_s *dev);
static int cxd56_selfpowered(FAR struct usbdev_s *dev, bool selfpowered);
@@ -519,7 +522,8 @@ static int cxd56_usbdev_open(FAR struct file *filep, FAR const char *relpath,
static int cxd56_usbdev_close(FAR struct file *filep);
static ssize_t cxd56_usbdev_read(FAR struct file *filep, FAR char *buffer,
size_t buflen);
static int cxd56_usbdev_dup(FAR const struct file *oldp, FAR struct file *newp);
static int cxd56_usbdev_dup(FAR const struct file *oldp,
FAR struct file *newp);
static int cxd56_usbdev_stat(FAR const char *relpath, FAR struct stat *buf);
#endif
@@ -612,7 +616,8 @@ static const struct cxd56_epinfo_s g_epinfo[CXD56_NENDPOINTS] =
USB_EP_ATTR_XFER_INT, /* Type: Interrupt */
CXD56_INTRMAXPACKET, /* Max packet size */
CXD56_INTRBUFSIZE, /* Buffer size */
}};
}
};
static uint8_t g_ep0outbuffer[CXD56_EP0MAXPACKET];
@@ -793,7 +798,8 @@ static inline void cxd56_abortrequest(FAR struct cxd56_ep_s *privep,
FAR struct cxd56_req_s *privreq,
int16_t result)
{
usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_REQABORTED), (uint16_t)privep->epphy);
usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_REQABORTED),
(uint16_t)privep->epphy);
/* Save the result in the request structure */
@@ -1053,7 +1059,8 @@ static int cxd56_rdrequest(FAR struct cxd56_ep_s *privep)
/* Ready to receive next packet */
ctrl = getreg32(CXD56_USB_OUT_EP_CONTROL(privep->epphy));
putreg32(ctrl | USB_RRDY | USB_CNAK, CXD56_USB_OUT_EP_CONTROL(privep->epphy));
putreg32(ctrl | USB_RRDY | USB_CNAK,
CXD56_USB_OUT_EP_CONTROL(privep->epphy));
return OK;
}
@@ -1127,7 +1134,8 @@ static void cxd56_cancelrequests(FAR struct cxd56_ep_s *privep)
while (!cxd56_rqempty(privep))
{
usbtrace(TRACE_COMPLETE(privep->epphy), (cxd56_rqpeek(privep))->req.xfrd);
usbtrace(TRACE_COMPLETE(privep->epphy),
(cxd56_rqpeek(privep))->req.xfrd);
cxd56_reqcomplete(privep, -ESHUTDOWN);
}
@@ -1202,8 +1210,8 @@ static void cxd56_dispatchrequest(FAR struct cxd56_usbdev_s *priv)
usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_DISPATCH), 0);
if (priv && priv->driver)
{
ret = CLASS_SETUP(priv->driver, &priv->usbdev, &priv->ctrl, priv->ep0data,
priv->ep0datlen);
ret = CLASS_SETUP(priv->driver, &priv->usbdev, &priv->ctrl,
priv->ep0data, priv->ep0datlen);
if (ret < 0)
{
/* Stall on failure */
@@ -1299,7 +1307,8 @@ static inline void cxd56_ep0setup(FAR struct cxd56_usbdev_s *priv)
usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_GETSTATUS), 0);
if (len != 2 || (priv->ctrl.type & USB_REQ_DIR_IN) == 0 || value != 0)
if (len != 2 || (priv->ctrl.type & USB_REQ_DIR_IN) == 0 ||
value != 0)
{
usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_STALLEDGETST),
priv->ctrl.req);
@@ -1326,7 +1335,8 @@ static inline void cxd56_ep0setup(FAR struct cxd56_usbdev_s *priv)
case USB_REQ_RECIPIENT_DEVICE:
case USB_REQ_RECIPIENT_INTERFACE:
usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_GETIFDEV), 0);
usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_GETIFDEV),
0);
break;
default:
@@ -1356,7 +1366,8 @@ static inline void cxd56_ep0setup(FAR struct cxd56_usbdev_s *priv)
{
cxd56_dispatchrequest(priv);
}
else if (priv->paddrset != 0 && value == USB_FEATURE_ENDPOINTHALT &&
else if (priv->paddrset != 0 &&
value == USB_FEATURE_ENDPOINTHALT &&
len == 0 &&
(privep = cxd56_epfindbyaddr(priv, index)) != NULL)
{
@@ -1583,9 +1594,7 @@ static int cxd56_epinterrupt(int irq, FAR void *context)
cxd56_txdmacomplete(privep);
/* Clear NAK to raise IN interrupt for send next IN
* packets.
*/
/* Clear NAK to raise IN interrupt for send next IN packets */
putreg32(ctrl | USB_CNAK, CXD56_USB_IN_EP_CONTROL(n));
}
@@ -1717,11 +1726,9 @@ static int cxd56_epinterrupt(int irq, FAR void *context)
ctrl = getreg32(CXD56_USB_OUT_EP_CONTROL(n));
/* Make sure want to be DMA transfer stopped.
*
* XXX: S bit needs to be clear by hand, it is not found in
* the specification documents.
*/
/* Make sure that want the DMA transfer stopped. */
/* The S bit needs to be clear by hand */
ctrl &= ~USB_STALL;
arch/arm/src/cxd56xx/cxd56_usbdev.h
+6 -5
View File
@@ -39,17 +39,18 @@
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_USB_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_USB_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* Register offsets */
/* Register offsets *************************************************************************/
/* Common Register Offsets */
#define CXD56_USB_IN_EP_CONTROL(x) (CXD56_USBDEV_BASE + 0x0000 + ((x) * 0x20))