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tlsr82: first commit of telink tlsr82xx chip port.

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tlsr82: first commit of telink tlsr82xx chip port.

 - tc32 archtecture context switch;
 - tc32 backtrace;
 - timer, uart, pwm, gpio, adc driver;
 - flash, watchdog driver;
 - uart txdma/rxdma;
 - spi console driver;
 - add board bringup and reset;

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
This commit is contained in:
wangbowen6
2022-04-24 14:19:21 +08:00
committed by Xiang Xiao
parent 32a47f7e3d
commit 73f7cc5855
79 changed files with 17064 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/Kconfig
+14 -2
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@@ -489,6 +489,15 @@ config ARCH_CHIP_PHY62XX
---help---
Phyplus PHY62XX architectures (ARM Cortex-M0).
config ARCH_CHIP_TLSR82
bool "Telink TLSR82XX"
select ARCH_ARMV6M
select ARCH_HAVE_BACKTRACE
select ARCH_HAVE_RESET
select LIBC_ARCH_ATOMIC
---help---
Telink tlsr82xx architectures (Customed armv6m)
config ARCH_CHIP_ARM_CUSTOM
bool "Custom ARM chip"
select ARCH_CHIP_CUSTOM
@@ -848,6 +857,7 @@ config ARCH_CHIP
default "xmc4" if ARCH_CHIP_XMC4
default "cxd56xx" if ARCH_CHIP_CXD56XX
default "phy62xx" if ARCH_CHIP_PHY62XX
default "tlsr82" if ARCH_CHIP_TLSR82
config ARCH_HAVE_TRUSTZONE
bool
@@ -908,7 +918,7 @@ config ARM_FPU_ABI_SOFT
default n
depends on ARCH_HAVE_FPU
---help---
Pass float value via integer register (-mfloat-abi=softfp)
Pass float value via integer register (-mfloat-abi=softfp)
config ARM_DPFPU32
bool "FPU with 32 double-precision register"
@@ -1241,5 +1251,7 @@ endif
if ARCH_CHIP_CXD56XX
source "arch/arm/src/cxd56xx/Kconfig"
endif
if ARCH_CHIP_TLSR82
source "arch/arm/src/tlsr82/Kconfig"
endif
endif # ARCH_ARM
arch/arm/include/tlsr82/chip.h
+24
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@@ -0,0 +1,24 @@
/****************************************************************************
* arch/arm/include/tlsr82/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_TLSR82_CHIP_H
#define __ARCH_ARM_INCLUDE_TLSR82_CHIP_H
#endif /* __ARCH_ARM_INCLUDE_TLSR82_CHIP_H */
arch/arm/include/tlsr82/irq.h
+259
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@@ -0,0 +1,259 @@
/****************************************************************************
* arch/arm/include/tlsr82/irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_TLSR82_IRQ_H
#define __ARCH_ARM_INCLUDE_TLSR82_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/irq.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/* Define this to prevent the arch irq.h include */
#define __ARCH_ARM_INCLUDE_ARMV6_M_IRQ_H
#define _REG_BASE_ADDR 0x00800000
#define _REG_ADDR8(a) (*(volatile uint8_t *)(_REG_BASE_ADDR + (a)))
#define _REG_ADDR32(a) (*(volatile uint32_t *)(_REG_BASE_ADDR + (a)))
#define _IRQ_MASK_REG _REG_ADDR32(0x640)
#define _IRQ_EN_REG _REG_ADDR8(0x643)
#define NR_TIMER0_IRQ 0
#define NR_TIMER1_IRQ 1
#define NR_TIMER2_IRQ 2
#define NR_USB_PWDN_IRQ 3
#define NR_DMA_IRQ 4
#define NR_DMA_FIFO_IRQ 5
#define NR_UART_IRQ 6
#define NR_MIX_CMD_IRQ 7
#define NR_EP0_SETUP_IRQ 8
#define NR_EP0_DATA_IRQ 9
#define NR_EP0_STA_IRQ 10
#define NR_SET_INTF_IRQ 11
#define NR_EP_DATA_IRQ 12
#define NR_RF_IRQ 13
#define NR_SW_PWM_IRQ 14
#define NR_PKE_IRQ 15
#define NR_USB_250US_IRQ 16
#define NR_USB_RST_IRQ 17
#define NR_GPIO_IRQ 18
#define NR_PM_IRQ 19
#define NR_SYSTEM_TIMER_IRQ 20
#define NR_GPIO_RISC0_IRQ 21
#define NR_GPIO_RISC1_IRQ 22
#define NR_IRQS 23
/* IRQ Stack Frame Format:
*
* Low Address |
* | regs --> 1 PC (aka R15)
* | 1 SP (aka R13)
* | 5 R12 ~ R8
* | 1 IRQ_STATE
* | 1 CPSR
* | 8 R7 ~ R0
* | 1 R14 (aka R14)
* High Address v
*
* This results in the following set of indices that
* can be used to access individual registers in the
* xcp.regs array:
*/
#define REG_START (0)
#define REG_R15 (0)
#define REG_R13 (1)
#define REG_R12 (2)
#define REG_R11 (3)
#define REG_R10 (4)
#define REG_R9 (5)
#define REG_R8 (6)
#define REG_IRQ_EN (7)
#define REG_CPSR (8)
#define REG_R7 (9)
#define REG_R6 (10)
#define REG_R5 (11)
#define REG_R4 (12)
#define REG_R3 (13)
#define REG_R2 (14)
#define REG_R1 (15)
#define REG_R0 (16)
#define REG_R14 (17)
#define REG_END (18)
#define XCPTCONTEXT_REGS (18)
#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
#define REG_FP REG_R7
#define REG_IP REG_R12
#define REG_SP REG_R13
#define REG_LR REG_R14
#define REG_PC REG_R15
/* The PIC register is usually R10. It can be R9 is stack checking is enabled
* or if the user changes it with -mpic-register on the GCC command line.
*/
#define REG_PIC REG_R10
/****************************************************************************
* Public Types
****************************************************************************/
/* This struct defines the way the registers are stored. We
* need to save:
*
* Low Address |
* | regs --> 1 PC (aka R15)
* | 1 SP (aka R13)
* | 5 R12 ~ R8
* | 1 IRQ_STATE
* | 1 CPSR
* | 8 R7 ~ R0
* | 1 R14 (aka R14)
* High Address v
*
* For a total of 18 (XCPTCONTEXT_REGS).
*
* Note: all the register are saved by software, hardware not
* push register into the stack automatically when interrupt
* occur.
*/
#ifndef __ASSEMBLY__
struct xcptcontext
{
/* The following function pointer is non-zero if there
* are pending signals to be processed.
*/
void *sigdeliver; /* Actual type is sig_deliver_t */
/* These are saved register array pointer used during
* signal processing.
*/
uint32_t *saved_regs;
/* Register save area */
uint32_t *regs;
};
#endif
/****************************************************************************
* Inline functions
****************************************************************************/
#ifndef __ASSEMBLY__
/* Name: up_irq_save, up_irq_restore, and friends.
*
* NOTE: This function should never be called from application code and,
* as a general rule unless you really know what you are doing, this
* function should not be called directly from operation system code either:
* Typically, the wrapper functions, enter_critical_section() and
* leave_critical section(), are probably what you really want.
*/
/* Save the current interrupt enable state & disable IRQs. */
static inline irqstate_t up_irq_save(void)
{
irqstate_t r = _IRQ_EN_REG;
_IRQ_EN_REG = 0;
return r;
}
/* Restore saved IRQ & FIQ state */
static inline void up_irq_restore(irqstate_t flags)
{
_IRQ_EN_REG = flags;
}
/* Enable IRQs and return the previous IRQ state */
static inline irqstate_t up_irq_enable(void)
{
irqstate_t r = _IRQ_EN_REG;
_IRQ_EN_REG = 1;
return r;
}
static inline void up_irq_disable(void)
{
up_irq_save();
}
static inline void up_disable_irq(int irq)
{
_IRQ_MASK_REG &= ~(1 << irq);
}
static inline void up_enable_irq(int irq)
{
_IRQ_MASK_REG |= (1 << irq);
}
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_TLSR82_IRQ_H */
arch/arm/src/tlsr82/Kconfig
+344
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@@ -0,0 +1,344 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_CHIP_TLSR82
comment "TLSR82XX Configuration Options"
choice
prompt "TLSR82XX Chip Selection"
default ARCH_CHIP_TLSR8278
depends on ARCH_CHIP_TLSR82
config ARCH_CHIP_TLSR8278
bool "TELINK_TLSR8278"
select TLSR82_FLASH_512K
select TLSR82_SRAM_64K
---help---
Multi-mode, Bluetooth LE5.1, AoA/AoD QFN 7x7, 48 pins,
512KB FLASH, 64KB SRAM
endchoice # TLSR82XX Chip Selection
config TLSR82_FLASH_1M
bool
default n
config TLSR82_FLASH_512K
bool
default n
config TLSR82_SRAM_64K
bool
default n
config TLSR82_SRAM_32K
bool
default n
config TLSR82_FLASH_SIZE_KB
int
default 1024 if TLSR82_FLASH_1M
default 512 if TLSR82_FLASH_512K
config TLSR82_SRAM_SIZE_KB
int
default 64 if TLSR82_SRAM_64K
default 32 if TLSR82_SRAM_32K
config TLSR82_CPU_CLK_MHZ
int "TLSR82_CPU_CLK (Mhz)"
default 48
config TLSR82_BOOTLOADER
bool "TLSR82_BOOTLOADER"
default n
---help---
Configure and position code for use with the telink bootloader.
Do not select this option if you will load code using JTAG/SWM.
config TLSR82_SOFT_FPU
bool "TLSR82 Software Fpu Enable"
default n
---help---
Enable software fpu support for tlsr82.
config TLSR82_SOFT_FPU_LIB_NAME
string "TLSR82 Software Fpu Library Name"
default "soft-fp"
depends on TLSR82_SOFT_FPU
---help---
This is the software fpu library name.
config TLSR82_SOFT_FPU_LIB_PATH
string "TLSR82 Software Fpu Library Path"
default "arch/arm/src/tlsr82/common"
depends on TLSR82_SOFT_FPU
---help---
This is the software fpu library path.
config TLSR8278_BLE_SDK
bool "TLSR8278 Bluetooth SDK Enable"
default n
depends on ARCH_CHIP_TLSR8278
---help---
Enable the Bluetooth SDK Code of tlsr8278.
config TLSR8278_BLE_SDK_LIB_NAME
string "TLSR8278 Bluetooth SDK Library Name"
default "lt_8278"
depends on TLSR8278_BLE_SDK
---help---
This is the library name needed by bluetooth sdk.
config TLSR8278_BLE_SDK_LIB_PATH
string "TLSR8278 Bluetooth SDK Library Path"
default "../apps/vendor/telink/proj_lib"
depends on TLSR8278_BLE_SDK
---help---
This is the library path needed by bluetooth sdk.
menu "TLSR82 Peripheral Support"
# These are the peripheral selections proper
# "Timer Configuration"
menuconfig TLSR82_TIMER
bool "Timer Configuration"
default n
if TLSR82_TIMER
config TLSR82_TIMER1
bool "Tlsr82 Timer1"
default n
config TLSR82_TIMER2
bool "Tlsr82 Timer2"
default n
depends on !TLSR82_WATCHDOG
config TLSR82_WATCHDOG
bool "Tlsr82 WatchDoag"
default n
config TLSR82_WDOG_DEFTIMOUT
int "Tlsr82 Watchdog deafult timeout time (ms)"
default 5000
depends on TLSR82_WATCHDOG
---help---
This value is the default watchdog timeout time.
endif
# "Uart Configuration"
menuconfig TLSR82_UART
bool "Uart Configuration"
default n
if TLSR82_UART
config TLSR82_UART0
bool "Tlsr82 Uart0"
default n
config TLSR82_UART0_TX_BUF_SIZE
int "Tlsr82 Uart0 Tx Buffer Size"
default 240
depends on TLSR82_UART0
---help---
The Uart0 transmit buffer size.
config TLSR82_UART0_RX_BUF_SIZE
int "Tlsr82 Uart0 Rx Buffer Size"
default 240
depends on TLSR82_UART0
---help---
The Uart0 receive buffer size.
config TLSR82_UART0_RXDMA
bool "Tlsr82 Uart0 RxDma Enable"
default n
depends on TLSR82_UART0
select SERIAL_RXDMA
config TLSR82_UART0_RXDMA_BUF_SIZE
int "Tlsr82 Uart0 RxDma Buffer Size"
default 240
range 16 240
depends on TLSR82_UART0_RXDMA
---help---
This value is the uart0 rx dma buffer size, this size must be less
than 240 and be multiple of 16.
config TLSR82_UART0_TXDMA
bool "Tlsr82 Uart0 TxDma Enable"
default n
depends on TLSR82_UART0
select SERIAL_TXDMA
config TLSR82_UART0_TXDMA_BUF_SIZE
int "Tlsr82 Uart0 TxDma Buffer Size"
default 240
range 16 240
depends on TLSR82_UART0_TXDMA
---help---
This value is the uart0 tx dma buffer size, this size must be less
than 240 and be multiple of 16.
endif
menuconfig TLSR82_GPIO
bool "GPIO Configuration"
default n
if TLSR82_GPIO
config TLSR82_GPIO_IRQ
bool "Tlsr82 gpio interrupt enable"
default n
config TLSR82_GPIO_VALIDATION
bool "Tlsr82 gpio validation enable"
default n
---help---
If enable this config, when config the gpio as multiplex function,
function tlsr82_gpio_cfg_check() can be used to check whether the
gpio can be configured be this multiplex function. But this function
need more flash space.
endif
menuconfig TLSR82_I2C
bool "I2C Configuration"
default n
# "SPI Configuration"
menuconfig TLSR82_SPI
bool "SPI Configuration"
default n
if TLSR82_SPI
config TLSR82_SPI_CONSOLE
bool "TLSR82 SPI as console output"
default n
---help---
This configuration will enable the spi as the console output
(printf), input function is not implemented in current code.
This is a useful debug option, beacause some tc32 archtecture chips
only have one uart, another debug log output channel is needed
when the only uart is used for doing other things.
config TLSR82_SPI_SYSLOG
bool "TLSR82 SPI as syslog output"
default n
---help---
This configuration will enable the spi as the syslog output
channel (syslog). This is a useful debug option, beacause some tc32
archtecture chips only have one uart, another debug log output
channel is needed when the only uart is used for doing other things.
endif
menuconfig TLSR82_USB
bool "USB Configuration"
default n
menuconfig TLSR82_PWM
bool "PWM Configuration"
default n
menuconfig TLSR82_AUDIO
bool "AUDIO Configuration"
default n
menuconfig TLSR82_QEDC
bool "QEDE Configuration"
default n
menuconfig TLSR82_MEDC
bool "MEDC Configuration"
default n
menuconfig TLSR82_ADC
bool "ADC Configuration"
default n
menuconfig TLSR82_LPCOMP
bool "LPCOMP Configuration"
default n
menuconfig TLSR82_PKE
bool "PKE Configuration"
default n
menuconfig TLSR82_AES
bool "AES Configuration"
default n
menuconfig TLSR82_RNG
bool "RNG Configuration"
default n
menuconfig TLSR82_PTA
bool "PTA Configuration"
default n
menuconfig TLSR82_FLASH
bool "FLASH Configuration"
default n
depends on MTD
select MTD_BYTE_WRITE
if TLSR82_FLASH
config TLSR82_FLASH_FS_OFFSET
hex "Start address of flash used by the file system"
default 0x00060000
---help---
This value is the start address of flash used by the file system,
therefore, this value must be larger than the end of code address.
config TLSR82_FLASH_FS_SIZE
hex "Size of flash used by the file system"
default 0x20000
---help---
This value is the size of flash used by the file system, therefore,
TLSR82_FLASH_FS_SIZE + TLSR82_FLASH_FS_OFFSET must less than the
boundary address of flash.
config TLSR82_FLASH_WRITE_BUFFER
bool "Enable the flash byte write buffer"
default n
depends on MTD_BYTE_WRITE
---help---
When enable this config, the flash byte write opreation will write the
data to a middle buffer and then write the flash using this buffer to
avoid the data buffer passed by apps is at flash. The flash not support
read during writing.
config TLSR82_FLASH_WRITE_BUFFER_SIZE
int "Flash byte write buffer size"
default 40
range 16 256
depends on TLSR82_FLASH_WRITE_BUFFER
---help---
Flash byte write buffer size, the larger this size, the higher byte write
efficiency.
config TLSR82_FLASH_TEST
bool "Enable the falsh test when initializing"
default n
---help---
When enable this config, the flash test function will execute when
the flash initializing. This config is useful to debug the flash
problem.
endif
endmenu # "TLSR82 Peripheral Support"
endif # ARCH_CHIP_TLSR82
arch/arm/src/tlsr82/Make.defs
+62
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@@ -0,0 +1,62 @@
############################################################################
# arch/tc32/src/tlsr82/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include tlsr82/tc32/Make.defs
# Chip devices related files in arch/arm/src/tlsr82
CHIP_CSRCS += tlsr82_start.c tlsr82_irq.c tlsr82_gpio.c tlsr82_timer_isr.c
CHIP_CSRCS += tlsr82_serial.c tlsr82_gpio_cfg.c tlsr82_analog.c
CHIP_CSRCS += tlsr82_clock.c tlsr82_cpu.c tlsr82_flash.c tlsr82_flash_mtd.c
ifeq ($(CONFIG_TLSR82_SPI),y)
CHIP_CSRCS += tlsr82_spi_console.c
endif
ifeq ($(CONFIG_TLSR82_TIMER),y)
CHIP_CSRCS += tlsr82_timer.c tlsr82_timer_lowerhalf.c
ifeq ($(CONFIG_TLSR82_WATCHDOG), y)
CHIP_CSRCS += tlsr82_watchdog.c
endif
endif
ifeq ($(CONFIG_TLSR82_PWM),y)
CHIP_CSRCS += tlsr82_pwm.c
endif
ifeq ($(CONFIG_TLSR82_ADC),y)
CHIP_CSRCS += tlsr82_adc.c
endif
VPATH += chip/tc32
VPATH += chip/chip/b87/boot
CFLAGS += -I$(TOPDIR)/arch/arm/src/arm
CFLAGS += -I$(TOPDIR)/arch/arm/src/tlsr82/tc32
ifeq ($(CONFIG_TLSR8278_BLE_SDK),y)
EXTRA_LIBPATHS += -L$(TOPDIR)/$(CONFIG_TLSR8278_BLE_SDK_LIB_PATH)
EXTRA_LIBS += -l$(CONFIG_TLSR8278_BLE_SDK_LIB_NAME)
endif
ifeq ($(CONFIG_TLSR82_SOFT_FPU),y)
EXTRA_LIBPATHS += -L$(TOPDIR)/$(CONFIG_TLSR82_SOFT_FPU_LIB_PATH)
EXTRA_LIBS += -l$(CONFIG_TLSR82_SOFT_FPU_LIB_NAME)
endif
arch/arm/src/tlsr82/Toolchain.defs
+195
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@@ -0,0 +1,195 @@
############################################################################
# arch/arm/src/tlsr82/Toolchain.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
# Setup for the selected toolchain
#
# Handle old-style chip-specific toolchain names in the absence of
# a new-style toolchain specification, force the selection of a single
# toolchain and allow the selected toolchain to be overridden by a
# command-line selection.
#
ifeq ($(filter y, $(CONFIG_ARMV6M_TOOLCHAIN_BUILDROOT)),y)
CONFIG_ARMV6M_TOOLCHAIN ?= BUILDROOT
endif
ifeq ($(filter y, $(CONFIG_ARMV6M_TOOLCHAIN_GNU_EABI)),y)
CONFIG_ARMV6M_TOOLCHAIN ?= GNU_EABI
endif
ifeq ($(filter y, $(CONFIG_ARMV6M_TOOLCHAIN_CLANG)),y)
CONFIG_ARMV6M_TOOLCHAIN ?= CLANG
endif
#
# Supported toolchains
#
# Each toolchain definition should set:
#
# CROSSDEV The GNU toolchain triple (command prefix)
# ARCHCPUFLAGS CPU-specific flags selecting the instruction set
# options, etc.
# ARCHOPTIMIZATION The optimization level that results in
# reliable code generation.
#
ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y)
ARCHOPTIMIZATION += $(CONFIG_DEBUG_OPTLEVEL)
else ifeq ($(CONFIG_DEBUG_FULLOPT),y)
ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),CLANG)
ARCHOPTIMIZATION += -Oz
else
ARCHOPTIMIZATION += -Os
endif
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += -fno-strict-aliasing
endif
ifeq ($(CONFIG_FRAME_POINTER),y)
ARCHOPTIMIZATION += -fno-omit-frame-pointer -fno-optimize-sibling-calls
else
ARCHOPTIMIZATION += -fomit-frame-pointer
endif
ifeq ($(CONFIG_STACK_CANARIES),y)
ARCHOPTIMIZATION += -fstack-protector-all
endif
# Clang Configuration files
ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),CLANG)
TOOLCHAIN_MARCH := --config armv6m_soft_nofp_nosys
endif
# Link Time Optimization
ifeq ($(CONFIG_LTO_THIN),y)
ARCHOPTIMIZATION += -flto=thin
else ifeq ($(CONFIG_LTO_FULL),y)
ARCHOPTIMIZATION += -flto
endif
# NuttX buildroot under Linux or Cygwin
ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),BUILDROOT)
CROSSDEV ?= arm-nuttx-eabi-
ARCHCPUFLAGS = $(TOOLCHAIN_MARCH) $(TOOLCHAIN_MTUNE) $(TOOLCHAIN_MFLOAT)
endif
# Generic GNU EABI toolchain
ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),GNU_EABI)
CROSSDEV ?= tc32-elf-
ARCHCPUFLAGS = $(TOOLCHAIN_MARCH) $(TOOLCHAIN_MTUNE) $(TOOLCHAIN_MFLOAT)
endif
# Clang toolchain
ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),CLANG)
ARCHCPUFLAGS = $(TOOLCHAIN_MARCH) $(TOOLCHAIN_MTUNE) $(TOOLCHAIN_MFLOAT)
CC = clang
CXX = clang++
CPP = clang -E -P -x c
LD = ld.lld -m armelf
STRIP = llvm-strip --strip-unneeded
AR = llvm-ar rcs
NM = llvm-nm
OBJCOPY = llvm-objcopy
OBJDUMP = llvm-objdump
# Since the no_builtin attribute is not fully supported on Clang
# disable the built-in functions, refer:
# https://github.com/apache/incubator-nuttx/pull/5971
ARCHOPTIMIZATION += -fno-builtin
# Default toolchain
else
CC = $(CROSSDEV)gcc
CXX = $(CROSSDEV)g++
CPP = $(CROSSDEV)gcc -E -P -x c
LD = $(CROSSDEV)ld
STRIP = $(CROSSDEV)strip --strip-unneeded
AR = $(CROSSDEV)ar rcs
NM = $(CROSSDEV)nm
OBJCOPY = $(CROSSDEV)objcopy
OBJDUMP = $(CROSSDEV)objdump
endif
# Architecture flags
ifeq ($(CONFIG_MM_KASAN),y)
ARCHCPUFLAGS += -fsanitize=kernel-address
endif
ARCHCFLAGS += -fno-common
ARCHCXXFLAGS += -fno-common -nostdinc++
ifneq ($(CONFIG_CXX_EXCEPTION),y)
ARCHCXXFLAGS += -fno-exceptions -fcheck-new
endif
ifneq ($(CONFIG_CXX_RTTI),y)
ARCHCXXFLAGS += -fno-rtti
endif
# Optimization of unused sections
ifeq ($(CONFIG_DEBUG_OPT_UNUSED_SECTIONS),y)
LDFLAGS += --gc-sections
ARCHOPTIMIZATION += -ffunction-sections -fdata-sections
endif
# Debug link map
ifeq ($(CONFIG_DEBUG_LINK_MAP),y)
LDFLAGS += --cref -Map=$(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx.map)
endif
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
LDFLAGS += -g
ARCHOPTIMIZATION += -g
endif
# Add the builtin library
COMPILER_RT_LIB = $(shell $(CC) $(ARCHCPUFLAGS) --print-libgcc-file-name)
ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),CLANG)
ifeq ($(wildcard $(COMPILER_RT_LIB)),)
# if "--print-libgcc-file-name" unable to find the correct libgcc PATH
# then go ahead and try "--print-file-name"
COMPILER_RT_LIB := $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name $(notdir $(COMPILER_RT_LIB))))
endif
endif
EXTRA_LIBS += $(COMPILER_RT_LIB)
ifneq ($(CONFIG_LIBM),y)
EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a))
endif
ifeq ($(CONFIG_LIBSUPCXX),y)
EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a))
endif
arch/arm/src/tlsr82/chip.h
+41
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@@ -0,0 +1,41 @@
/****************************************************************************
* arch/arm/src/tlsr82/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_CHIP_H
#define __ARCH_ARM_SRC_TLSR82_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/irq.h>
/* Include the chip capabilities file */
#define ARMV6M_PERIPHERAL_INTERRUPTS NR_IRQS
/* Include the memory map file.
* Other chip hardware files should then include this file for the proper
* setup.
*/
#endif /* __ARCH_ARM_SRC_TLSR82_CHIP_H */
arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S
+571
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arch/arm/src/tlsr82/hardware/tlsr82_adc.h
+154
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/****************************************************************************
* arch/arm/src/tlsr82/hardware/tlsr82_adc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_ADC_H
#define __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_ADC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/tlsr82/chip.h>
#include "hardware/tlsr82_register.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define ADC_VREF_REG (0xea)
#define ADC_CHAN_REG (0xeb)
#define ADC_MODE_REG (0xec)
#define ADC_SAMP0_REG (0xee)
#define ADC_SAMP1_REG (0xef)
#define ADC_SAMP2_REG (0xf0)
#define ADC_SAMP3_REG (0xf1)
#define ADC_CTRL0_REG (0xf2)
#define ADC_CTRL1_REG (0xf3)
#define ADC_CLKDIV_REG (0xf4)
#define ADC_STATUS_REG (0xf6)
#define ADC_DATAL_REG (0xf7)
#define ADC_DATAH_REG (0xf8)
#define ADC_DIVIDER_REG (0xf9)
#define ADC_SCALE_REG (0xfa)
#define ADC_PAG_CTRL_REG (0xfc)
#define ADC_CLK_REG (0x82)
/* ADC Reference Voltage definition */
#define ADC_VREF_SHIFT 0
#define ADC_VREF_MASK (0x3 << ADC_VREF_SHIFT)
#define ADC_VREF_RSVD1 (0x0 << ADC_VREF_SHIFT)
#define ADC_VREF_0P9V (0x1 << ADC_VREF_SHIFT)
#define ADC_VREF_1P2V (0x2 << ADC_VREF_SHIFT)
#define ADC_VREF_RSVD2 (0x3 << ADC_VREF_SHIFT)
/* ADC Mode, Resolution definition */
#define ADC_MODE_RES_SHIFT 0
#define ADC_MODE_RES_MASK (0x3 << ADC_MODE_RES_SHIFT)
#define ADC_MODE_RES_8BIT (0x0 << ADC_MODE_RES_SHIFT)
#define ADC_MODE_RES_10BIT (0x1 << ADC_MODE_RES_SHIFT)
#define ADC_MODE_RES_12BIT (0x2 << ADC_MODE_RES_SHIFT)
#define ADC_MODE_RES_14BIT (0x3 << ADC_MODE_RES_SHIFT)
#define ADC_MODE_INPUT_SHIFT 6
#define ADC_MODE_INPUT_MASK (0x1 << ADC_MODE_INPUT_SHIFT)
#define ADC_MODE_INPUT_RSVD (0x0 << ADC_MODE_INPUT_SHIFT)
#define ADC_MODE_INPUT_DIFF (0x1 << ADC_MODE_INPUT_SHIFT)
/* ADC Sample 0 defnition
* - Sample cycle
*/
/* ADC Sample cycle definition */
#define ADC_SAMP0_CYCLE_SHIFT 0
#define ADC_SAMP0_CYCLE_MASK (0xf << ADC_SAMP0_CYCLE_SHIFT)
#define ADC_SAMP0_CYCLE_3 (0x0 << ADC_SAMP0_CYCLE_SHIFT)
#define ADC_SAMP0_CYCLE_6 (0x1 << ADC_SAMP0_CYCLE_SHIFT)
#define ADC_SAMP0_CYCLE_9 (0x2 << ADC_SAMP0_CYCLE_SHIFT)
#define ADC_SAMP0_CYCLE_48 (0xf << ADC_SAMP0_CYCLE_SHIFT)
/* ADC Control 0 definition
* - Channal enable
* - Sample length
*/
/* ADC Channel enabel definition */
#define ADC_CTRL0_CHANEN_SHIFT 2
#define ADC_CTRL0_CHANEN_MASK (0x1 << ADC_CTRL0_CHANEN_SHIFT)
#define ADC_CTRL0_CHANEN_ENABLE (0x1 << ADC_CTRL0_CHANEN_SHIFT)
#define ADC_CTRL0_CHANEN_DISABLE (0x0 << ADC_CTRL0_CHANEN_SHIFT)
/* ADC Sample length definition */
#define ADC_CTRL0_SAMPLEN_SHIFT 4
#define ADC_CTRL0_SAMPLEN_MASK (0x3 << ADC_CTRL0_SAMPLEN_SHIFT)
/* ADC Control 1 definition
* - Adc Sample Control
*/
#define ADC_CTRL1_SAMP_SHIFT 0
#define ADC_CTRL1_SAMP_MASK (0x1 << ADC_CTRL1_SAMP_SHIFT)
#define ADC_CTRL1_SAMP_ON (0x0 << ADC_CTRL1_SAMP_SHIFT)
#define ADC_CTRL1_SAMP_OFF (0x1 << ADC_CTRL1_SAMP_SHIFT)
/* ADC clock divide definition */
#define ADC_CLKDIV_SHIFT 0
#define ADC_CLKDIV_MASK (0x3 << ADC_CLKDIV_SHIFT)
#define ADC_CLKDIV_0 (0x0 << ADC_CLKDIV_SHIFT)
#define ADC_CLKDIV_1 (0x1 << ADC_CLKDIV_SHIFT)
#define ADC_CLKDIV_2 (0x2 << ADC_CLKDIV_SHIFT)
#define ADC_CLKDIV_3 (0x3 << ADC_CLKDIV_SHIFT)
/* The adc vbat divider specification can not found in datasheet, below
* definition follows the sdk code.
*/
#define ADC_DIVIDER_SEL_SHIFT 2
#define ADC_DIVIDER_SEL_MASK (0x3 << ADC_DIVIDER_SEL_SHIFT)
#define ADC_DIVIDER_SEL_OFF (0x0 << ADC_DIVIDER_SEL_SHIFT)
#define ADC_DIVIDER_SEL_1F3 (0x2 << ADC_DIVIDER_SEL_SHIFT)
/* ADC input pre-scaline select */
#define ADC_SCALE_SHIFT 6
#define ADC_SCALE_MASK (0x3 << ADC_SCALE_SHIFT)
#define ADC_SCALE_1 (0x0 << ADC_SCALE_SHIFT)
#define ADC_SCALE_RSVD1 (0x1 << ADC_SCALE_SHIFT)
#define ADC_SCALE_RSVD2 (0x2 << ADC_SCALE_SHIFT)
#define ADC_SCALE_1F8 (0x3 << ADC_SCALE_SHIFT)
#define ADC_POWER_SHIFT 5
#define ADC_POWER_MASK (0x1 << ADC_POWER_SHIFT)
#define ADC_POWER_UP (0x1 << ADC_POWER_SHIFT)
#define ADC_POWER_DOWN (0x0 << ADC_POWER_SHIFT)
#define ADC_CLK_24M_EN_SHIFT 6
#define ADC_CLK_24M_EN_MASK (0x1 << ADC_CLK_24M_EN_SHIFT)
#define ADC_CLK_24M_EN (0x1 << ADC_CLK_24M_EN_SHIFT)
#endif /* __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_ADC_H */
arch/arm/src/tlsr82/hardware/tlsr82_analog.h
+41
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/****************************************************************************
* arch/arm/src/tlsr82/hardware/tlsr82_analog.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_ANALOG_H
#define __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_ANALOG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/tlsr82/chip.h>
#include "hardware/tlsr82_register.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define ANALOG_ADDR_REG REG_ADDR8(0xb8)
#define ANALOG_DATA_REG REG_ADDR8(0xb9)
#define ANALOG_CTRL_REG REG_ADDR8(0xba)
#endif /* __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_ANALOG_H */
arch/arm/src/tlsr82/hardware/tlsr82_clock.h
+78
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/****************************************************************************
* arch/arm/src/tlsr82/hardware/tlsr82_clock.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_CLOCK_H
#define __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_CLOCK_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/tlsr82/chip.h>
#include "hardware/tlsr82_register.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define CPU_CLK (CONFIG_TLSR82_CPU_CLK_MHZ * 1000000)
#define CLK_EN1_REG REG_ADDR8(0x63)
#define CLK_EN2_REG REG_ADDR8(0x64)
#define CLK_EN3_REG REG_ADDR8(0x65)
#define CLK_SYS_SEL REG_ADDR8(0x66)
#define CLK_EN1_SPI BIT(0)
#define CLK_EN1_I2C BIT(1)
#define CLK_EN1_UART BIT(2)
#define CLK_EN1_USB BIT(3)
#define CLK_EN1_PWM BIT(4)
#define CLK_EN1_QDEC BIT(5)
#define CLK_EN1_IR BIT(6)
#define CLK_EN1_SWIRE BIT(7)
#define CLK_EN2_ZB BIT(0)
#define CLK_EN2_SYSTIM BIT(1)
#define CLK_EN2_DMA BIT(2)
#define CLK_EN2_ALGM BIT(3)
#define CLK_EN2_AES BIT(4)
#define CLK_EN2_RSVD1 BIT(5)
#define CLK_EN2_RSVD2 BIT(6)
#define CLK_EN2_PKE BIT(7)
#define CLK_EN3_AIF BIT(0)
#define CLK_EN3_AUDIO BIT(1)
#define CLK_EN3_DFIFO BIT(2)
#define CLK_EN3_TRNG BIT(3)
#define CLK_EN3_MC BIT(4)
#define CLK_EN3_MCIC BIT(5)
#define CLK_EN3_RSVD1 BIT(6)
#define CLK_EN3_RSVD2 BIT(7)
#define CLK_SYS_12M_CRYSTAL 0x44
#define CLK_SYS_16M_CRYSTAL 0x43
#define CLK_SYS_24M_CRYSTAL 0x42
#define CLK_SYS_32M_CRYSTAL 0x60
#define CLK_SYS_48M_CRYSTAL 0x20
#define CLK_SYS_RC_THRES 0x10
#endif /* __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_CLOCK_H */
arch/arm/src/tlsr82/hardware/tlsr82_dma.h
+127
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/****************************************************************************
* arch/arm/src/tlsr82/hardware/tlsr82_dma.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_DMA_H
#define __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_DMA_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/tlsr82/chip.h>
#include "hardware/tlsr82_register.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* DMA address, size, mode resigster definitions
* By default, DMA0 is for Uart RX
* By default, DMA1 is for Uart TX
* By default, DMA2 is for RF RX
* By default, DMA3,4,5 is for RF TX
* By default, DMA7 is for PWM
*/
#define DMA0_ADDR_REG REG_ADDR16(0xc00)
#define DMA0_ADDRHI_REG REG_ADDR8(0xc40)
#define DMA0_SIZE_REG REG_ADDR8(0xc02)
#define DMA0_MODE_REG REG_ADDR8(0xc03)
#define DMA_UART_RX_ADDR_REG DMA0_ADDR_REG
#define DMA_UART_RX_ADDRHI_REG DMA0_ADDRHI_REG
#define DMA_UART_RX_SIZE_REG DMA0_SIZE_REG
#define DMA_UART_RX_MODE_REG DMA0_MODE_REG
#define DMA1_ADDR_REG REG_ADDR16(0xc04)
#define DMA1_ADDRHI_REG REG_ADDR8(0xc41)
#define DMA1_SIZE_REG REG_ADDR8(0xc06)
#define DMA1_MODE_REG REG_ADDR8(0xc07)
#define DMA_UART_TX_ADDR_REG DMA1_ADDR_REG
#define DMA_UART_TX_ADDRHI_REG DMA1_ADDRHI_REG
#define DMA_UART_TX_SIZE_REG DMA1_SIZE_REG
#define DMA_UART_TX_MODE_REG DMA1_MODE_REG
#define DMA2_ADDR_REG REG_ADDR16(0xc08)
#define DMA2_SIZE_REG REG_ADDR8(0xc0a)
#define DMA2_MODE_REG REG_ADDR8(0xc0b)
#define DMA3_ADDR_REG REG_ADDR16(0xc0c)
#define DMA3_SIZE_REG REG_ADDR8(0xc0e)
#define DMA3_MODE_REG REG_ADDR8(0xc0f)
#define DMA4_ADDR_REG REG_ADDR16(0xc10)
#define DMA4_SIZE_REG REG_ADDR8(0xc16)
#define DMA4_MODE_REG REG_ADDR8(0xc17)
#define DMA5_ADDR_REG REG_ADDR16(0xc14)
#define DMA5_SIZE_REG REG_ADDR8(0xc16)
#define DMA5_MODE_REG REG_ADDR8(0xc17)
#define DMA7_ADDR_REG REG_ADDR16(0xc18)
#define DMA7_SIZE_REG REG_ADDR8(0xc1a)
#define DMA7_MODE_REG REG_ADDR8(0xc1b)
/* DMA realdy register definitions */
#define DMA_TX_RDY0_REG REG_ADDR8(0xc24)
#define DMA_TX_RDY1_REG REG_ADDR8(0xc25)
#define DMA_RX_RDY0_REG REG_ADDR8(0xc26)
#define DMA_RX_RDY1_REG REG_ADDR8(0xc27)
/* DMA irq register definitions
* DMA_IRQ_MASK_REG: enable or disable the dma interrupt
* DMA_IRQ_EN_REG : enable or disable the dma channel
* DMA_IRQ_STA_REG : get the dma interupt status and write 1 to clear
*/
#define DMA_IRQ_MASK_REG REG_ADDR8(0xc21)
#define DMA_IRQ_EN_REG REG_ADDR8(0xc20)
#define DMA_IRQ_STA_REG REG_ADDR8(0xc26)
/* DMA Channel */
#define DMA_CHAN0 BIT(0)
#define DMA_CHAN1 BIT(1)
#define DMA_CHAN2 BIT(2)
#define DMA_CHAN3 BIT(3)
#define DMA_CHAN4 BIT(4)
#define DMA_CHAN5 BIT(5)
#define DMA_CHAN7 BIT(7)
#define DMA_CHAN_UART_RX DMA_CHAN0
#define DMA_CHAN_UART_TX DMA_CHAN1
#define DMA_CHAN_RF_RX DMA_CHAN2
#define DMA_CHAN_RF_TX DMA_CHAN3
#define DMA_CHAN_AES_OUT DMA_CHAN4
#define DMA_CHAN_AES_IN DMA_CHAN5
#define DMA_CHAN_PWM DMA_CHAN7
/* DMA Mode */
#define DMA_MODE_WR_MEM BIT(0)
#define DMA_MODE_PINGPONG_EN BIT(1)
#define DMA_MODE_FIFO_EN BIT(2)
#define DMA_MODE_AUTO_MODE BIT(3)
#define DMA_MODE_READ_MODE BIT(4)
#define DMA_MODE_BYTE_MODE BIT(5)
#endif /* __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_DMA_H */
arch/arm/src/tlsr82/hardware/tlsr82_gpio.h
+111
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@@ -0,0 +1,111 @@
/****************************************************************************
* arch/arm/src/tlsr82/hardware/tlsr82_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_GPIO_H
#define __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/tlsr82/chip.h>
#include "hardware/tlsr82_register.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* GPIO register definitions */
#define GPIO_SET_PA_ACT_REG REG_ADDR8(0x586)
#define GPIO_SET_PA_IN_REG REG_ADDR8(0x580)
#define GPIO_SET_PA_IE_REG REG_ADDR8(0x581)
#define GPIO_SET_PA_OEN_REG REG_ADDR8(0x582)
#define GPIO_SET_PA_OUT_REG REG_ADDR8(0x583)
#define GPIO_SET_PA_POL_REG REG_ADDR8(0x584)
#define GPIO_SET_PA_DS_REG REG_ADDR8(0x585)
#define GPIO_SET_PB_ACT_REG REG_ADDR8(0x586 + 8)
#define GPIO_SET_PB_IN_REG REG_ADDR8(0x580 + 8)
#define GPIO_SET_PB_IE_REG REG_ADDR8(0x581 + 8)
#define GPIO_SET_PB_OEN_REG REG_ADDR8(0x582 + 8)
#define GPIO_SET_PB_OUT_REG REG_ADDR8(0x583 + 8)
#define GPIO_SET_PB_POL_REG REG_ADDR8(0x584 + 8)
#define GPIO_SET_PB_DS_REG REG_ADDR8(0x585 + 8)
#define GPIO_SET_PC_ACT_REG REG_ADDR8(0x586 + 16)
#define GPIO_SET_PC_IN_REG REG_ADDR8(0x580 + 16)
#define ANALOG_PC_IE_ADDR 0xc0
#define GPIO_SET_PC_OEN_REG REG_ADDR8(0x582 + 16)
#define GPIO_SET_PC_OUT_REG REG_ADDR8(0x583 + 16)
#define GPIO_SET_PC_POL_REG REG_ADDR8(0x584 + 16)
#define ANALOG_PC_DS_ADDR 0xc2
#define GPIO_SET_PD_ACT_REG REG_ADDR8(0x586 + 24)
#define GPIO_SET_PD_IN_REG REG_ADDR8(0x580 + 24)
#define GPIO_SET_PD_IE_REG REG_ADDR8(0x581 + 24)
#define GPIO_SET_PD_OEN_REG REG_ADDR8(0x582 + 24)
#define GPIO_SET_PD_OUT_REG REG_ADDR8(0x583 + 24)
#define GPIO_SET_PD_POL_REG REG_ADDR8(0x584 + 24)
#define GPIO_SET_PD_DS_REG REG_ADDR8(0x585 + 24)
#define GPIO_SET_PE_ACT_REG REG_ADDR8(0x5A6)
#define GPIO_SET_PE_IN_REG REG_ADDR8(0x5A0)
#define GPIO_SET_PE_IE_REG REG_ADDR8(0x5A1)
#define GPIO_SET_PE_OEN_REG REG_ADDR8(0x5A2)
#define GPIO_SET_PE_OUT_REG REG_ADDR8(0x5A3)
#define GPIO_SET_PE_POL_REG REG_ADDR8(0x5A4)
#define GPIO_SET_PE_DS_REG REG_ADDR8(0x5A5)
#define GPIO_SETTING_ACT_REG(group) REG_ADDR8(0x586 + ((group) << 3))
#define GPIO_SETTING_IN_REG(group) REG_ADDR8(0x580 + ((group) << 3))
#define GPIO_SETTING_IE_REG(group) REG_ADDR8(0x581 + ((group) << 3))
#define GPIO_SETTING_OEN_REG(group) REG_ADDR8(0x582 + ((group) << 3))
#define GPIO_SETTING_OUT_REG(group) REG_ADDR8(0x583 + ((group) << 3))
#define GPIO_SETTING_POL_REG(group) REG_ADDR8(0x584 + ((group) << 3))
#define GPIO_SETTING_DS_REG(group) REG_ADDR8(0x585 + ((group) << 3))
#define GPIO_MUX_REG(group, pin) REG_ADDR8(0x5a8 + ((group) << 1) \
+ (((pin) >= 4) ? 1 : 0))
#define GPIO_IRQ_NORMAL_ALL_REG REG_ADDR8(0x5b5)
#define GPIO_IRQ_RISC_EN_REG REG_ADDR8(0x642)
#define GPIO_IRQ_NORMAL_REG(group) REG_ADDR8(0x587 + (group))
#define GPIO_IRQ_M0_REG(group) REG_ADDR8(0x5b8 + (group))
#define GPIO_IRQ_M1_REG(group) REG_ADDR8(0x5c0 + (group))
#define GPIO_IRQ_M2_REG(group) REG_ADDR8(0x5c8 + (group))
#define GPIO_IRQ_NORMAL_ALL_WAKEUP (1 << 2)
#define GPIO_IRQ_NORMAL_ALL_EN (1 << 3)
#define GPIO_IRQ_RISC0_EN (1 << 5)
#define GPIO_IRQ_RISC1_EN (1 << 6)
#define GPIO_SET_AS_GPIO(group, pin) BM_SET(GPIO_SETTING_ACT_REG(group), BIT(pin))
#define GPIO_SET_AS_MUX(group, pin) BM_CLR(GPIO_SETTING_ACT_REG(group), BIT(pin))
#define GPIO_SET_OUT_HIGH(group, pin)
#define GPIO_SET_OUT_LOW(group, pin)
#define GPIO_SET_IN_VAL(group, pin)
#endif /* __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_GPIO_H */
arch/arm/src/tlsr82/hardware/tlsr82_irq.h
+43
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/****************************************************************************
* arch/arm/src/tlsr82/hardware/tlsr82_irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_IRQ_H
#define __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/tlsr82/chip.h>
#include "hardware/tlsr82_register.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IRQ_MASK_REG REG_ADDR32(0x640)
#define IRQ_PRIO_REG REG_ADDR32(0x644)
#define IRQ_SRC_REG REG_ADDR32(0x648)
#define IRQ_SRC3_REG REG_ADDR8(0x64a)
#define IRQ_EN_REG REG_ADDR8(0x643)
#endif /* __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_IRQ_H */
arch/arm/src/tlsr82/hardware/tlsr82_mspi.h
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/****************************************************************************
* arch/arm/src/tlsr82/hardware/tlsr82_mspi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_MSPI_H
#define __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_MSPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/tlsr82/chip.h>
#include "hardware/tlsr82_register.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define MSPI_DATA_REG REG_ADDR8(0x0c)
#define MSPI_CTRL_REG REG_ADDR8(0x0d)
#define MSPI_MODE_REG REG_ADDR8(0x0f)
#define MSPI_CTRL_CS_SHIFT 0
#define MSPI_CTRL_CS_MASK (0x1 << MSPI_CTRL_CS_SHIFT)
#define MSPI_CTRL_CS_HIGH (0x1 << MSPI_CTRL_CS_SHIFT)
#define MSPI_CTRL_CS_LOW (0x0 << MSPI_CTRL_CS_SHIFT)
#define MSPI_CTRL_SDO_SHIFT 1
#define MSPI_CTRL_SDO_MASK (0x1 << MSPI_CTRL_SDO_SHIFT)
#define MSPI_CTRL_CONT_SHIFT 2
#define MSPI_CTRL_CONT_MASK (0x1 << MSPI_CTRL_CONT_SHIFT)
#define MSPI_CTRL_RD_SHIFT 3
#define MSPI_CTRL_RD_MASK (0x1 << MSPI_CTRL_RD_SHIFT)
#define MSPI_CTRL_BUSY_SHIFT 4
#define MSPI_CTRL_BUSY_MASK (0x1 << MSPI_CTRL_BUSY_SHIFT)
#define MSPI_MODE_DUAL_DATA_SHIFT 0
#define MSPI_MODE_DUAL_DATA_MASK (0x1 << MSPI_MODE_DUAL_DATA_SHIFT)
#define MSPI_MODE_DUAL_ADDR_SHIFT 1
#define MSPI_MODE_DUAL_ADDR_MASK (0x1 << MSPI_MODE_DUAL_ADDR_SHIFT)
#define MSPI_MODE_CLKDIV_SHIFT 2
#define MSPI_MODE_CLKDIV_MASK (0x3f << MSPI_MODE_CLKDIV_SHIFT)
/* MSPI Operation Macros, follow the telink SDK */
#define MSPI_CS_HIGH() (MSPI_CTRL_REG = MSPI_CTRL_CS_MASK)
#define MSPI_CS_LOW() (MSPI_CTRL_REG = 0)
#define MSPI_WRITE(data) (MSPI_DATA_REG = (data))
#define MSPI_READ() (MSPI_DATA_REG)
#define MSPI_WAIT() while (MSPI_CTRL_REG & MSPI_CTRL_BUSY_MASK)
#define MSPI_AUTO_MODE() (MSPI_CTRL_REG = 0x0a)
#endif /* __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_MSPI_H */
arch/arm/src/tlsr82/hardware/tlsr82_pwm.h
+69
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/****************************************************************************
* arch/arm/src/tlsr82/hardware/tlsr82_pwm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_PWM_H
#define __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_PWM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/tlsr82/chip.h>
#include "hardware/tlsr82_register.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define PWM_CLKDIV_REG REG_ADDR8(0x782)
#define PWM_ENABLE0_REG REG_ADDR8(0x781)
#define PWM_MODE0_REG REG_ADDR8(0x783)
#define PWM_ENABLE_REG REG_ADDR8(0x780)
#define PWM_INVERT_REG REG_ADDR8(0x784)
#define PWM_N_INVERT_REG REG_ADDR8(0x785)
#define PWM_POL_REG REG_ADDR8(0x786)
#define PWM_CYCLE_REG(n) REG_ADDR32(0x794 + ((n) << 2))
#define PWM_CMP_REG(n) REG_ADDR16(0x794 + ((n) << 2))
#define PWM_MAX_REG(n) REG_ADDR16(0x796 + ((n) << 2))
#define PWM_PLUSE_NUM_REG REG_ADDR16(0x7ac)
#define PWM_IRQ_CTRL_REG REG_ADDR8(0x7b0)
#define PWM_IRQ_STA_REG REG_ADDR8(0x7b1)
#define PWM_PLUSE_CNT_REG REG_ADDR8(0x7c0)
/* PWM IRQ status */
#define PWM_IRQ_STA_PNUM0 BIT(0)
#define PWM_IRQ_STA_IRFIFO0 BIT(1)
#define PWM_IRQ_STA_CYCLE0 BIT(2)
#define PWM_IRQ_STA_CYCLE1 BIT(3)
#define PWM_IRQ_STA_CYCLE2 BIT(4)
#define PWM_IRQ_STA_CYCLE3 BIT(5)
#define PWM_IRQ_STA_CYCLE4 BIT(6)
#define PWM_IRQ_STA_CYCLE5 BIT(7)
#endif /* __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_PWM_H */
arch/arm/src/tlsr82/hardware/tlsr82_register.h
+99
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/****************************************************************************
* arch/arm/src/tlsr82/hardware/tlsr82_register.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_REGISTER_H
#define __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_REGISTER_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Regisger base address */
#define REG_BASE_ADDR 0x00800000
#define REG_ADDR8(a) getreg8(REG_BASE_ADDR + (a))
#define REG_ADDR16(a) getreg16(REG_BASE_ADDR + (a))
#define REG_ADDR32(a) getreg32(REG_BASE_ADDR + (a))
#define write_reg8(addr,v) putreg8(v, REG_BASE_ADDR + (addr))
#define write_reg16(addr,v) putreg16(v, REG_BASE_ADDR + (addr))
#define write_reg32(addr,v) putreg32(v, REG_BASE_ADDR + (addr))
/* Common macros definition */
#define BIT(n) (1 << (n))
#define BIT_MASK_LEN(len) (BIT(len)-1)
#define BIT_RNG(s, e) (BIT_MASK_LEN((e) - (s) + 1) << (s))
#define BM_SET(x, m) ((x) |= (m))
#define BM_CLR(x, m) ((x) &= ~(m))
#define BM_IS_SET(x, m) ((x) & (m))
#define BM_IS_CLR(x, m) ((~(x)) & (m))
#define BM_FLIP(x, m) ((x) ^= (mask))
/* Reset register definition */
#define RESET_RST0_REG REG_ADDR8(0x60)
#define RESET_RST1_REG REG_ADDR8(0x61)
#define RESET_RST2_REG REG_ADDR8(0x62)
#define RESET_PWDNEN_REG REG_ADDR8(0x6f)
/* Reset reson definition */
#define RESET_RST0_SPI BIT(0)
#define RESET_RST0_I2C BIT(1)
#define RESET_RST0_UART BIT(2)
#define RESET_RST0_USB BIT(3)
#define RESET_RST0_PWM BIT(4)
#define RESET_RST0_QDEC BIT(5)
#define RESET_RST0_IR BIT(6)
#define RESET_RST0_SWIRE BIT(7)
#define RESET_RST1_ZB BIT(0)
#define RESET_RST1_SYSTIM BIT(1)
#define RESET_RST1_DMA BIT(2)
#define RESET_RST1_ALGM BIT(3)
#define RESET_RST1_AES BIT(4)
#define RESET_RST1_ADC BIT(5)
#define RESET_RST1_ALG BIT(6)
#define RESET_RST1_PKE BIT(7)
#define RESET_RST2_AIF BIT(0)
#define RESET_RST2_AUDIO BIT(1)
#define RESET_RST2_DFIFO BIT(2)
#define RESET_RST2_TRNG BIT(3)
#define RESET_RST2_RISC BIT(4)
#define RESET_RST2_MCIC BIT(5)
#define RESET_RST2_RSIC1R BIT(6)
#define RESET_RST2_MCIC1R BIT(7)
#define RESET_PWDNEN_SUSP_EN BIT(0)
#define RESET_PWDNEN_RESET_ALL BIT(5)
#define RESET_PWDNEN_SUSP BIT(7)
#endif /* __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_REGISTER_H */
arch/arm/src/tlsr82/hardware/tlsr82_spi.h
+91
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/****************************************************************************
* arch/arm/src/tlsr82/hardware/tlsr82_spi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_SPI_H
#define __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_SPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/tlsr82/chip.h>
#include "hardware/tlsr82_register.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* SPI and I2C Group select register */
#define SPI_I2C_GROUP_REG REG_ADDR8(0x5b6)
#define SPI_I2C_GROUPA_EN BIT_RNG(4,5)
#define SPI_I2C_GROUPB_EN BIT(6)
#define SPI_I2C_GROUPD_EN BIT(7)
/* SPI and I2C Pin select register */
#define SPI_I2C_PIN_REG REG_ADDR8(0x5b7)
#define SPI_PA3_SPI_EN BIT(0)
#define SPI_PA4_SPI_EN BIT(1)
#define SPI_PB6_SPI_EN BIT(2)
#define SPI_PD7_SPI_EN BIT(3)
#define I2C_PA3_I2C_EN BIT(4)
#define I2C_PA4_I2C_EN BIT(5)
#define I2C_PB6_I2C_EN BIT(6)
#define I2C_PD7_I2C_EN BIT(7)
/* SPI Data register */
#define SPI_DATA_REG REG_ADDR8(0x08)
/* SPI Control register */
#define SPI_CTRL_REG REG_ADDR8(0x09)
#define SPI_CTRL_CS BIT(0)
#define SPI_CTRL_MASTER_EN BIT(1)
#define SPI_CTRL_OUT_OFF BIT(2)
#define SPI_CTRL_RW_STA BIT(3)
#define SPI_CTRL_ADDR_ADD BIT(4)
#define SPI_CTRL_SHARE_MODE BIT(5)
#define SPI_CTRL_BUSY BIT(6)
#define SPI_CS_HIGH BM_SET(SPI_CTRL_REG, SPI_CTRL_CS)
#define SPI_CS_LOW BM_CLR(SPI_CTRL_REG, SPI_CTRL_CS)
/* SPI Clock register */
#define SPI_CLK_REG REG_ADDR8(0x0a)
#define SPI_CLK_DIV BIT_RNG(0,6)
#define SPI_CLK_EN BIT(7)
/* SPI Mode select register, CPOL, CPHA */
#define SPI_MODE_REG REG_ADDR8(0x0b)
#define SPI_MODE_CPOL BIT(0)
#define SPI_MODE_CPHA BIT(1)
#endif /* __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_SPI_H */
arch/arm/src/tlsr82/hardware/tlsr82_timer.h
+109
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/****************************************************************************
* arch/arm/src/tlsr82/hardware/tlsr82_timer.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_TIMER_H
#define __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_TIMER_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/tlsr82/chip.h>
#include "hardware/tlsr82_register.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Watchdog Register definitions */
#define WDOG_STATUS_REG REG_ADDR8(0x72)
#define WDOG_CTRL_REG REG_ADDR32(0x620)
/* Bit definitions */
#define WDOG_STATUS_RESET_SHIFT 0
#define WDOG_STATUS_RESET_MASK (0x1 << WDOG_STATUS_RESET_SHIFT)
#define WDOG_STATUS_RESET_YES (0x1 << WDOG_STATUS_RESET_SHIFT)
#define WDOG_STATUS_RESET_NO (0x0 << WDOG_STATUS_RESET_SHIFT)
#define WDOG_CTRL_CAPT_SHIFT 9
#define WDOG_CTRL_CAPT_MASK (0x3fff << WDOG_CTRL_CAPT_SHIFT)
#define WDOG_CTRL_ENABLE_SHIFT 23
#define WDOG_CTRL_ENABLE_MASK (0x1 << WDOG_CTRL_ENABLE_SHIFT)
#define WDOG_CTRL_ENABLE_ON (0x1 << WDOG_CTRL_ENABLE_SHIFT)
#define WDOG_CTRL_ENABLE_OFF (0x0 << WDOG_CTRL_ENABLE_SHIFT)
/* Timer Regisger definitions */
#define TIMER_CTRL_REG REG_ADDR32(0x620)
#define TIMER_STATUS_REG REG_ADDR8(0x623)
#define TIMER_CAPT_REG(n) REG_ADDR32(0x624 + ((n) << 2))
#define TIMER_CAPT0_REG REG_ADDR32(0x624)
#define TIMER_CAPT1_REG REG_ADDR32(0x628)
#define TIMER_CAPT2_REG REG_ADDR32(0x62c)
#define TIMER_TICK_REG(n) REG_ADDR32(0x630 + ((n) << 2))
#define TIMER_TICK0_REG REG_ADDR32(0x630)
#define TIMER_TICK1_REG REG_ADDR32(0x634)
#define TIMER_TICK2_REG REG_ADDR32(0x638)
#define SYSTIMER_TICK_REG REG_ADDR32(0x740)
#define SYSTIMER_CAPT_REG REG_ADDR32(0x744)
#define SYSTIMER_CALI_REG REG_ADDR8(0x749)
#define SYSTIMER_CTRL_REG REG_ADDR8(0x74a)
#define SYSTIMER_STATUS_REG REG_ADDR8(0x74b)
#define SYSTIMER_IRQ_MASK_REG REG_ADDR8(0x748)
/* Bit definition */
#define TIMER_CTRL_T0_ENABLE_SHIFT 0
#define TIMER_CTRL_T0_MODE_SHIFT 1
#define TIMER_CTRL_T1_ENABLE_SHIFT 3
#define TIMER_CTRL_T1_MODE_SHIFT 4
#define TIMER_CTRL_T2_ENABLE_SHIFT 6
#define TIMER_CTRL_T2_MODE_SHIFT 7
#define TIMER_CTRL_WDOG_CAPT_SHIFT 9
#define TIMER_CTRL_T0_ENABLE BIT(0)
#define TIMER_CTRL_T0_MODE BIT_RNG(1, 2)
#define TIMER_CTRL_T1_ENABLE BIT(3)
#define TIMER_CTRL_T1_MODE BIT_RNG(4, 5)
#define TIMER_CTRL_T2_ENABLE BIT(6)
#define TIMER_CTRL_T2_MODE BIT_RNG(7, 8)
#define TIMER_CTRL_WDOG_CAPT BIT(9, 22)
#define TIMER_STATUS_T0_CLR BIT(0)
#define TIMER_STATUS_T1_CLR BIT(1)
#define TIMER_STATUS_T2_CLR BIT(2)
#define TIMER_STATUS_WDOG_CLR BIT(3)
#define SYSTIMER_CTRL_TIMER_EN BIT(1)
#define SYSTIMER_CTRL_CALI_EN BIT(3)
#define SYSTIMER_IRQ_MASK_EN BIT(2)
#endif /* __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_TIMER_H */
arch/arm/src/tlsr82/hardware/tlsr82_uart.h
+157
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/****************************************************************************
* arch/arm/src/tlsr82/hardware/tlsr82_uart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_UART_H
#define __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/tlsr82/chip.h>
#include "hardware/tlsr82_register.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Uart buffer register definitions */
#define UART_BUF_REG REG_ADDR32(0x90)
#define UART_BUF0_REG REG_ADDR8(0x90)
#define UART_BUF1_REG REG_ADDR8(0x91)
#define UART_BUF2_REG REG_ADDR8(0x92)
#define UART_BUF3_REG REG_ADDR8(0x93)
#define UART_BUF(n) REG_ADDR8(0x90 + (n))
/* Uart clock register definitions */
#define UART_CLK_REG REG_ADDR16(0x94)
#define UART_CLK_DIV 0x7fff
#define UART_CLK_EN_SHIFT 15
#define UART_CLK_EN (0x1 << UART_CLK_EN_SHIFT)
/* Uart control register definitions */
#define UART_CTRL_REG REG_ADDR32(0x96)
#define UART_CTRL0_REG REG_ADDR8(0x96)
#define UART_CTRL1_REG REG_ADDR8(0x97)
#define UART_CTRL2_REG REG_ADDR8(0x98)
#define UART_CTRL3_REG REG_ADDR8(0x99)
#define UART_CTRL0_BWPC_SHIFT 0
#define UART_CTRL0_BWPC (0xf << UART_CTRL0_BWPC_SHIFT)
#define UART_CTRL0_RX_DMA_EN_SHIFT 4
#define UART_CTRL0_RX_DMA_EN (0x1 << UART_CTRL0_RX_DMA_EN_SHIFT)
#define UART_CTRL0_TX_DMA_EN_SHIFT 5
#define UART_CTRL0_TX_DMA_EN (0x1 << UART_CTRL0_TX_DMA_EN_SHIFT)
#define UART_CTRL0_RX_IRQ_EN_SHIFT 6
#define UART_CTRL0_RX_IRQ_EN (0x1 << UART_CTRL0_RX_IRQ_EN_SHIFT)
#define UART_CTRL0_TX_IRQ_EN_SHIFT 7
#define UART_CTRL0_TX_IRQ_EN (0x1 << UART_CTRL0_TX_IRQ_EN_SHIFT)
#define UART_CTRL1_CTS_SEL_SHIFT 0
#define UART_CTRL1_CTS_SEL (0x1 << UART_CTRL1_CTS_SEL_SHIFT)
#define UART_CTRL1_CTS_EN_SHIFT 1
#define UART_CTRL1_CTS_EN (0x1 << UART_CTRL1_CTS_EN_SHIFT)
#define UART_CTRL1_PARITY_EN_SHIFT 2
#define UART_CTRL1_PARITY_EN (0x1 << UART_CTRL1_PARITY_EN_SHIFT)
#define UART_CTRL1_PARITY_SEL_SHIFT 3
#define UART_CTRL1_PARITY_SEL (0x1 << UART_CTRL1_PARITY_SEL_SHIFT)
#define UART_CTRL1_STOPBIT_SHIFT 4
#define UART_CTRL1_STOPBIT (0x3 << UART_CTRL1_STOPBIT_SHIFT)
#define UART_CTRL1_TTL_SHIFT 6
#define UART_CTRL1_TTL (0x1 << UART_CTRL1_TTL_SHIFT)
#define UART_CTRL1_LOOPBACK_SHIFT 7
#define UART_CTRL1_LOOPBACK (0x1 << UART_CTRL1_LOOPBACK_SHIFT)
#define UART_CTRL2_RTS_TRI_LEVEL_SHIFT 0
#define UART_CTRL2_RTS_TRI_LEVEL (0xf << UART_CTRL2_RTS_TRI_LEVEL_SHIFT)
#define UART_CTRL2_RTS_PARITY_SHIFT 4
#define UART_CTRL2_RTS_PARITY (0x1 << UART_CTRL2_RTS_PARITY_SHIFT)
#define UART_CTRL2_RTS_MUL_VAL_SHIFT 5
#define UART_CTRL2_RTS_MUL_VAL (0x1 << UART_CTRL2_RTS_MUL_VAL_SHIFT)
#define UART_CTRL2_RTS_MUL_EN_SHIFT 6
#define UART_CTRL2_RTS_MUL_EN (0x1 << UART_CTRL2_RTS_MUL_EN_SHIFT)
#define UART_CTRL2_RTS_EN_SHIFT 7
#define UART_CTRL2_RTS_EN (0x1 << UART_CTRL2_RTS_EN_SHIFT)
#define UART_CTRL3_RX_TRI_LEVEL_SHIFT 0
#define UART_CTRL3_RX_TRI_LEVEL (0xf << UART_CTRL3_RX_TRI_LEVEL_SHIFT)
#define UART_CTRL3_TX_TRI_LEVEL_SHIFT 4
#define UART_CTRL3_TX_TRI_LEVEL (0xf << UART_CTRL3_TX_TRI_LEVEL_SHIFT)
/* Uart rx timeout register definitions */
#define UART_RXTIMEOUT0_REG REG_ADDR8(0x9a)
#define UART_RXTIMEOUT1_REG REG_ADDR8(0x9b)
#define UART_RXTIMEOUT1_SEL_SHIFT 0
#define UART_RXTIMEOUT1_SEL (0x3 << UART_RXTIMEOUT1_SEL_SHIFT)
#define UART_RXTIMEOUT1_P7816_EN_SHIFT 5
#define UART_RXTIMEOUT1_P7816_EN (0x1 << UART_RXTIMEOUT1_P7816_EN_SHIFT)
#define UART_RXTIMEOUT1_MASK_TXDONE_SHIFT 6
#define UART_RXTIMEOUT1_MASK_TXDONE (0x1 << UART_RXTIMEOUT1_MASK_TXDONE_SHIFT)
#define UART_RXTIMEOUT1_MASK_ERR_SHIFT 7
#define UART_RXTIMEOUT1_MASK_ERR (0x1 << UART_RXTIMEOUT1_MASK_ERR_SHIFT)
/* Uart buffer count register definitions */
#define UART_BUF_CNT0_REG REG_ADDR8(0x9c)
#define UART_BUF_CNT1_REG REG_ADDR8(0x9d)
#define UART_BUF_CNT0_RX_CNT_SHIFT 0
#define UART_BUF_CNT0_RX_CNT (0xf << UART_BUF_CNT0_RX_CNT_SHIFT)
#define UART_BUF_CNT0_TX_CNT_SHIFT 4
#define UART_BUF_CNT0_TX_CNT (0xf << UART_BUF_CNT0_TX_CNT_SHIFT)
#define UART_BUF_CNT1_RB_CNT 0x07
#define UART_BUF_CNT1_IRQ BIT(3)
#define UART_BUF_CNT1_WB_CNT 0x70
#define UART_BUF_CNT1_RX_CLR BIT(6)
#define UART_BUF_CNT1_TX_CLR BIT(7)
#define UART_BUF_CNT1_RX_ERR BIT(7)
#define UART_GET_RX_BUF_CNT() ((UART_BUF_CNT0_REG & UART_BUF_CNT0_RX_CNT) >>\
UART_BUF_CNT0_RX_CNT_SHIFT)
#define UART_GET_TX_BUF_CNT() ((UART_BUF_CNT0_REG & UART_BUF_CNT0_TX_CNT) >>\
UART_BUF_CNT0_TX_CNT_SHIFT)
/* Uart interupt register definitions */
#define UART_IRQ_REG REG_ADDR8(0x9e)
#define UART_IRQ_TXDONE (0x1 << 0)
#define UART_IRQ_TXBUF (0x1 << 1)
#define UART_IRQ_RXDONE (0x1 << 2)
#define UART_IRQ_RXBUF (0x1 << 3)
#define UART_IRQ_CLR_RX (0x1 << 6)
#define UART_IRQ_CLR_TX (0x1 << 7)
#define UART_STATE_REG REG_ADDR8(0x9f)
#define UART_STATE_TX 0x07
#define UART_STATE_RX 0xf0
#endif /* __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_UART_H */
arch/arm/src/tlsr82/tc32/Make.defs
+56
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############################################################################
# arch/arm/src/tlsr82/tc32/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include common/Make.defs
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
HEAD_ASRC = cstartup_flash.S
# Arch Flags
AFLAGS += -DMCU_STARTUP_FLASH
# Filter-out unnecessary .S files
CMN_ASRCS :=
# Filter-out unnecessary .c files
TC32_CSRCS_FILTER := arm_backtrace_fp.c arm_backtrace_thumb.c
TC32_CSRCS_FILTER += arm_switchcontext.c arm_fullcontextrestore.c
TC32_CSRCS_FILTER += arm_saveusercontext.c
CMN_CSRCS := $(filter-out $(TC32_CSRCS_FILTER), $(CMN_CSRCS))
# Common files in arch/arm/src/armv6-m
CMN_CSRCS += arm_sigdeliver.c
# Common files in arch/arm/src/tlsr82/tc32
CMN_ASRCS += tc32_fullcontextrestore.S tc32_switchcontext.S tc32_saveusercontext.S
CMN_CSRCS += tc32_doirq.c tc32_initialstate.c tc32_schedulesigaction.c
CMN_CSRCS += tc32_syscall.c tc32_udelay.c
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += tc32_backtrace.c
endif
arch/arm/src/tlsr82/tc32/div_mod.S
+320
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/****************************************************************************
* arch/arm/src/tlsr82/tc32/div_mod.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#define UDIV #0
#define SDIV #1
#define UMOD #2
#define SMOD #3
#define MUL2_STEP 8
.code 16
.text
.align 2
.global __modsi3
.code 16
.thumb_func
.type __modsi3, %function
__modsi3:
tmov r2, SMOD
tj div
.size __modsi3, .-__modsi3
.align 2
.global __divsi3
.code 16
.thumb_func
.type __divsi3, %function
__divsi3:
tmov r2, SDIV
tj div
.size __divsi3, .-__divsi3
.align 2
.global __umodsi3
.code 16
.thumb_func
.type __umodsi3, %function
__umodsi3:
tmov r2, UMOD
tj div
.size __umodsi3, .-__umodsi3
.align 2
.global __udivsi3
.code 16
.thumb_func
.type __udivsi3, %function
__udivsi3:
tmov r2, UDIV
tj div
.size __udivsi3, .-__udivsi3
.align 2
.global div
.code 16
.thumb_func
.type div, %function
div:
tmrcs r3
tpush {r3, r4}
tmov r4, #0x80
tor r3, r4
tmcsr r3
tloadr r3, .L11
tstorer r0, [r3]
tadd r3, r3, #4
tstorer r1, [r3]
tsub r3, r3, #8
tstorerb r2, [r3]
.L2:
tloadrb r0, [r3]
tcmp r0, #0
tjne .L2
tcmp r2, #1
tjls .L4
tadd r3, r3, #8
tloadr r0, [r3]
tj .L6
.L4:
tadd r3, r3, #4
tloadr r0, [r3]
.L6:
tpop {r3, r4}
tmcsr r3
tjex lr
.align 4
.L11:
.word(0x800664)
.word(0x800660)
.word(0x800668)
.size div, .-div
#if 1
.align 4
.global mul32x32_64
.thumb_func
.type mul32x32_64, %function
mul32x32_64:
tmul r0, r1
tloadr r1, [pc, #4]
tloadr r1, [r1, #0]
tjex lr
.word(0x008006fc)
#endif
#if 1
.align 4
.global mz_mul1
.thumb_func
.type mz_mul1, %function
mz_mul1:
tpush {r4, r5, r6, r7}
tmov r4, r8
tpush {r4}
tmov r4, #1
tmov r8, r4 //r8 = 1
tloadr r6, [pc, #4] //r6 REG_ADDR32(0x6fc)
tmovs r5, #0 //clear carry
tj MZ_MUL1_END
.word(0x008006fc)
MZ_MUL1_START:
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r5 // l0 + c => c0
tsubc r5, r5 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r5, r8 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0
taddc r5, r7 // cn = c0 + h1 + c1
MZ_MUL1_END:
tloadm r1!, {r4} // load *a
tsub r2, #1 // r2--
tcmp r2, #0
tjge MZ_MUL1_START // carry set
tstorem r0!, {r5}
tpop {r4}
tmov r8, r4
tpop {r4, r5, r6, r7}
tjex lr
#endif
.align 4
.global mz_mul2
.thumb_func
.type mz_mul2, %function
mz_mul2:
tpush {r4, r5, r6, r7}
tmov r4, r8
tmov r5, r9
tmov r6, r10
tmov r7, r11
tpush {r4, r5, r6, r7}
tmov r8, r2 //r8 = n, loop number
tmov r2, #1
tmov r10, r2 // r10 = 1
tsub r2, #(MUL2_STEP + 1)
tmov r9, r2 //r9 = -MUL2_STEP
tmov r2, #0
tmov r2, #0
tloadr r6, [pc, #4] //r6 REG_ADDR32(0x6fc)
tmov r11,r2 //r11 = 0
tj MZ_MUL2_LOOP
//tj MZ_MUL2_LOOP2
.word(0x008006fc)
MZ_MUL2_START:
//a0
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0 y1
taddc r2, r7 // cn = c0 + h1 + c1
tmul r5, r3 // l1 = a1 * b
tloadr r7, [r0, #0] // y1
tadd r5, r2 // l1 + cn => c2
tsubc r2, r2 // c2 - 1
tadd r5, r7 // l1 + c + y1 => c3
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r5} // store y0 y1
tloadm r1!, {r4, r5} // load *a
taddc r2, r7 // cn2 = c2 + h1 + c3
//a0
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0 y1
taddc r2, r7 // cn = c0 + h1 + c1
tmul r5, r3 // l1 = a1 * b
tloadr r7, [r0, #0] // y1
tadd r5, r2 // l1 + cn => c2
tsubc r2, r2 // c2 - 1
tadd r5, r7 // l1 + c + y1 => c3
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r5} // store y0 y1
tloadm r1!, {r4, r5} // load *a
taddc r2, r7 // cn2 = c2 + h1 + c3
//a0
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0 y1
taddc r2, r7 // cn = c0 + h1 + c1
tmul r5, r3 // l1 = a1 * b
tloadr r7, [r0, #0] // y1
tadd r5, r2 // l1 + cn => c2
tsubc r2, r2 // c2 - 1
tadd r5, r7 // l1 + c + y1 => c3
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r5} // store y0 y1
tloadm r1!, {r4, r5} // load *a
taddc r2, r7 // cn2 = c2 + h1 + c3
///// next 2
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0 y1
taddc r2, r7 // cn = c0 + h1 + c1
tmul r5, r3 // l1 = a1 * b
tloadr r7, [r0, #0] // y1
tadd r5, r2 // l1 + cn => c2
tsubc r2, r2 // c2 - 1
tadd r5, r7 // l1 + c + y1 => c3
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r5} // store y0 y1
taddc r2, r7 // cn2 = c2 + h1 + c3
MZ_MUL2_LOOP:
tloadm r1!, {r4, r5} // load *a
tadd r8, r9 // r8 -= MUL2_STEP
tcmp r8, r11 // const 0
tjge MZ_MUL2_START // carry set
tmov r5, r8
tadd r5, #MUL2_STEP
tsub r1, #8
tj MZ_MUL2_LOOP2
MZ_MUL2_START2:
tmul r4, r3 // l0 = a0 * b
tloadr r7, [r0, #0] // y0
tadd r4, r2 // l0 + c => c0
tsubc r2, r2 // c0 - 1
tadd r4, r7 // l0 + c + y0 => c1
tloadr r7, [r6, #0] // r7 = h0
tadd r2, r10 // c0 - 1 + 1 = c0 (nc)
tstorem r0!, {r4} // store y0
taddc r2, r7 // cn = c0 + h1 + c1
MZ_MUL2_LOOP2:
tloadm r1!, {r4} // load *a
tsub r5, #1 // r7--
tcmp r5, #0
tjge MZ_MUL2_START2 // carry set
MZ_MUL2_END:
//tmov r2, #13
tstorem r0!, {r2}
tpop {r4, r5, r6, r7}
tmov r8, r4
tmov r9, r5
tmov r10, r6
tmov r11, r7
tpop {r4, r5, r6, r7}
tjex lr
tnop
arch/arm/src/tlsr82/tc32/tc32.h
+80
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@@ -0,0 +1,80 @@
/****************************************************************************
* arch/arm/src/tlsr82/tc32/tc32.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_TC32_TC32_H
#define __ARCH_ARM_SRC_TLSR82_TC32_TC32_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* TC32 */
/* PSR bits */
#define PSR_MODE_MASK 0x0000001f /* Bits 0-4: Mode bits */
#define PSR_MODE_IRQ 0x00000012 /* 32-bit IRQ mode */
#define PSR_MODE_SVC 0x00000013 /* 32-bit Supervisor mode */
#define PSR_I_BIT 0x00000080 /* Bit 7: IRQ disable */
/* Bits 8-23: Reserved */
#define PSR_J_BIT 0x01000000 /* Bit 24: Jazelle state bit */
/* Bits 25-26: Reserved */
#define PSR_Q_BIT 0x08000000 /* Bit 27: Sticky overflow */
#define PSR_V_BIT 0x10000000 /* Bit 28: Overflow */
#define PSR_C_BIT 0x20000000 /* Bit 29: Carry/Borrow/Extend */
#define PSR_Z_BIT 0x40000000 /* Bit 30: Zero */
#define PSR_N_BIT 0x80000000 /* Bit 31: Negative/Less than */
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_TLSR82_TC32_TC32_H */
arch/arm/src/tlsr82/tc32/tc32_backtrace.c
+556
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File diff suppressed because it is too large Load Diff
arch/arm/src/tlsr82/tc32/tc32_doirq.c
+270
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@@ -0,0 +1,270 @@
/****************************************************************************
* arch/arm/src/tlsr82/tc32/tc32_doirq.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/compiler.h>
#include <nuttx/board.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "group/group.h"
#include "hardware/tlsr82_irq.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
static const uint8_t tc32_lowbit_bitmap[] =
{
0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 00 */
4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 10 */
5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 20 */
4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 30 */
6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 40 */
4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 50 */
5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 60 */
4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 70 */
7, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 80 */
4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 90 */
5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* A0 */
4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* B0 */
6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* C0 */
4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* D0 */
5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* E0 */
4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* F0 */
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: tc32_ffs
*
* Description:
* This function finds the first bit set (beginning with the least
* significant bit) in value and return the index of that bit.
* TC32 archtecture does not support clz instruction.
*
* Parameters:
* uint32_t - value
*
* Return Value:
* [1, 32] - On Success.
* 0 - No set bit in value (value = 0).
*
****************************************************************************/
static inline int locate_code(".ram_code") tc32_ffs(uint32_t value)
{
int ret;
if (value == 0)
{
ret = 0;
}
else if (value & 0xff)
{
ret = (int)tc32_lowbit_bitmap[value & 0xff] + 1;
}
else if (value & 0xff00)
{
ret = (int)tc32_lowbit_bitmap[(value & 0xff00) >> 8] + 9;
}
else if (value & 0xff0000)
{
ret = (int)tc32_lowbit_bitmap[(value & 0xff0000) >> 16] + 17;
}
else
{
ret = (int)tc32_lowbit_bitmap[(value & 0xff000000) >> 24] + 25;
}
return ret;
}
/****************************************************************************
* Name: tc32_getirq
*
* Description:
* This function is used to get the interrupt number based on the
* interrupt source flag register.
*
* Parameters:
* void
*
* Return Value:
* [0, NR_IRQS-1] - On success, found interrupt number, success.
* NR_IRQS - Error, invalid interrupt number.
*
****************************************************************************/
static int locate_code(".ram_code") tc32_getirq(void)
{
int irq;
/* Only detect the enable interrupt */
irq = tc32_ffs(IRQ_SRC_REG & IRQ_MASK_REG);
if (irq > 0 && irq <= NR_IRQS)
{
/* Minus one to obatin the correct irq number */
irq = irq - 1;
}
else
{
/* Invalid irq number */
irq = NR_IRQS;
}
return irq;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/**
* @brief This function serves to handle the interrupt of MCU
* @param[in] none
* @return none
*/
uint32_t *arm_doirq(int irq, uint32_t *regs)
{
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
/* Current regs non-zero indicates that we are processing an interrupt;
* g_current_regs is also used to manage interrupt level context switches.
*
* Nested interrupts are not supported
*/
DEBUGASSERT(CURRENT_REGS == NULL);
CURRENT_REGS = regs;
/* Disable further occurrences of this interrupt (until the interrupt
* sources have been clear by the driver).
*/
/* Deliver the IRQ */
irq_dispatch(irq, regs);
#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV)
/* Check for a context switch. If a context switch occurred, then
* g_current_regs will have a different value than it did on entry. If an
* interrupt level context switch has occurred, then restore the floating
* point state and the establish the correct address environment before
* returning from the interrupt.
*/
if (regs != CURRENT_REGS)
{
#ifdef CONFIG_ARCH_FPU
/* Restore floating point registers */
riscv_restorefpu(CURRENT_REGS);
#endif
#ifdef CONFIG_ARCH_ADDRENV
/* Make sure that the address environment for the previously
* running task is closed down gracefully (data caches dump,
* MMU flushed) and set up the address environment for the new
* thread at the head of the ready-to-run list.
*/
group_addrenv(NULL);
#endif
}
#endif
/* If a context switch occurred while processing the interrupt then
* g_current_regs may have change value. If we return any value different
* from the input regs, then the lower level will know that a context
* switch occurred during interrupt processing.
*/
regs = (uint32_t *)CURRENT_REGS;
/* Set g_current_regs to NULL to indicate that we are no longer in an
* interrupt handler.
*/
CURRENT_REGS = NULL;
/* Unmask the last interrupt (global interrupts are still disabled) */
#endif
board_autoled_off(LED_INIRQ);
return regs;
}
/****************************************************************************
* Name: irq_handler
*
* Description:
* This function is the common interrupt handler for all interrupts.
*
* Parameters:
* uint32_t *regs - the saved context array pointer of interrpted task,
* size = XCPTCONTEXT_REGS.
*
* Return Value:
* uint32_t *regs - if occur context switch, regs = the saved context
* array pointer of next task, if not, regs = input regs,
* size = XCPTCONTEXT_REGS.
*
****************************************************************************/
uint32_t * locate_code(".ram_code") irq_handler(uint32_t *regs)
{
int irq = tc32_getirq();
return arm_doirq(irq, regs);
}
arch/arm/src/tlsr82/tc32/tc32_fullcontextrestore.S
+156
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@@ -0,0 +1,156 @@
/****************************************************************************
* arch/arm/src/tlsr82/tc32/tc32_fullcontextrestore.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/chip/irq.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Symbols
****************************************************************************/
.file "tc32_fullcontextrestore.S"
/****************************************************************************
* Macros
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_fullcontextrestore
*
* Description:
* Restore the current thread context. Full prototype is:
*
* void arm_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
*
* Returned Value:
* None
*
****************************************************************************/
.align 2
.code 16
.thumb_func
.section .ram_code,"ax"
.global arm_fullcontextrestore
.type arm_fullcontextrestore, function
arm_fullcontextrestore:
/* Move saved register to register R1 ~ R7
* R8 --> R1
* R9 --> R2
* R10 --> R3
* R11 --> R4
* R12 --> R5
* R13 (SP) --> R6
* R15 (PC) --> R7
*/
tloadr r1, [r0, #(4 * REG_R8)]
tloadr r2, [r0, #(4 * REG_R9)]
tloadr r3, [r0, #(4 * REG_R10)]
tloadr r4, [r0, #(4 * REG_R11)]
tloadr r5, [r0, #(4 * REG_R12)]
tloadr r6, [r0, #(4 * REG_R13)]
tloadr r7, [r0, #(4 * REG_R15)]
/* Restore register R8 ~ R12 */
tmov r8, r1
tmov r9, r2
tmov r10, r3
tmov r11, r4
tmov r12, r5
/* Restore register SP (SVC mode)*/
tmov r13, r6
/* Restore LR (R14, SVC mode) as PC (R15), not accurate though */
tmov r14, r7
/* Set CPSR be 0x00000092 to switch to IRQ mode */
tloadr r1, _REG_IRQ_EN2 + 4
tnop
tmcsr r1
tnop
/* Get the saved IRQ_STATE and restore to [0x00800643] */
tloadr r1, _REG_IRQ_EN2
tloadr r2, [r0, #(4 * REG_IRQ_EN)]
tstorerb r2, [r1]
/* Get the saved CPSR and restore to SPSR, when return
* to SVC mode, the value of CPSR will be automatically
* updated to the value of SPSR.
*/
tloadr r1, [r0, #(4 * REG_CPSR)]
tmssr r1
/* Get the saved R14 (LR, IRQ mode), clear the bit0 in LR to make
* return address be even, then restore it to LR
*/
tloadr r1, [r0, #(4 * REG_R14)]
tloadr r2, _REG_IRQ_EN2 + 8
tand r1, r2
tmov r14, r1
/* Restore saved registers R1 ~ R7 */
tloadr r1, [r0, #(4 * REG_R1)]
tloadr r2, [r0, #(4 * REG_R2)]
tloadr r3, [r0, #(4 * REG_R3)]
tloadr r4, [r0, #(4 * REG_R4)]
tloadr r5, [r0, #(4 * REG_R5)]
tloadr r6, [r0, #(4 * REG_R6)]
tloadr r7, [r0, #(4 * REG_R7)]
/* Restore saved register R0 */
tloadr r0, [r0, #(4 * REG_R0)]
/* Push the R14 and pop to pc, return from IRQ mode */
tpush {r14}
treti {r15}
.align 2
_REG_IRQ_EN2:
.word 0x00800643
.word 0x00000092
.word 0xfffffffe
.size arm_fullcontextrestore, .-arm_fullcontextrestore
.end
arch/arm/src/tlsr82/tc32/tc32_initialstate.c
+152
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@@ -0,0 +1,152 @@
/****************************************************************************
* arch/arm/src/tlsr82/tc32/tc32_initialstate.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <string.h>
#include <debug.h>
#include <execinfo.h>
#include <nuttx/arch.h>
#include "tc32.h"
#include "arm_internal.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_initial_state
*
* Description:
* A new thread is being started and a new TCB
* has been created. This function is called to initialize
* the processor specific portions of the new TCB.
*
* This function must setup the initial architecture registers
* and/or stack so that execution will begin at tcb->start
* on the next context switch.
*
****************************************************************************/
void up_initial_state(struct tcb_s *tcb)
{
struct xcptcontext *xcp = &tcb->xcp;
uint32_t cpsr;
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
/* Initialize the idle thread stack */
if (tcb->pid == IDLE_PROCESS_ID)
{
tcb->stack_alloc_ptr = (void *)(g_idle_topstack -
CONFIG_IDLETHREAD_STACKSIZE);
tcb->stack_base_ptr = tcb->stack_alloc_ptr;
tcb->adj_stack_size = CONFIG_IDLETHREAD_STACKSIZE;
#ifdef CONFIG_STACK_COLORATION
/* If stack debug is enabled, then fill the stack with a
* recognizable value that we can use later to test for high
* water marks.
*/
arm_stack_color(tcb->stack_alloc_ptr, 0);
#endif /* CONFIG_STACK_COLORATION */
return;
}
/* Initialize the context registers to stack top */
xcp->regs = (void *)((uint32_t)tcb->stack_base_ptr +
tcb->adj_stack_size -
XCPTCONTEXT_SIZE);
/* Initialize the xcp registers */
memset(xcp->regs, 0, XCPTCONTEXT_SIZE);
/* Save the initial stack pointer */
xcp->regs[REG_SP] = (uint32_t)tcb->stack_base_ptr +
tcb->adj_stack_size;
/* Save the task entry point */
xcp->regs[REG_LR] = (uint32_t)tcb->start & ~1;
xcp->regs[REG_IRQ_EN] = 1;
/* If this task is running PIC, then set the PIC base register to the
* address of the allocated D-Space region.
*/
#ifdef CONFIG_PIC
if (tcb->dspace != NULL)
{
/* Set the PIC base register (probably R10) to the address of the
* alloacated D-Space region.
*/
xcp->regs[REG_PIC] = (uint32_t)tcb->dspace->region;
}
#endif
/* Set supervisor- or user-mode, depending on how NuttX is configured and
* what kind of thread is being started. Disable FIQs in any event
*/
#ifdef CONFIG_BUILD_KERNEL
if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_KERNEL)
{
/* It is a kernel thread.. set supervisor mode */
cpsr = PSR_MODE_SVC | PSR_F_BIT;
}
else
{
/* It is a normal task or a pthread. Set user mode */
cpsr = PSR_MODE_USR | PSR_F_BIT;
}
#else
/* If the kernel build is not selected, then all threads run in
* supervisor-mode.
*/
cpsr = PSR_MODE_SVC;
#endif
/* Enable or disable interrupts, based on user configuration */
# ifdef CONFIG_SUPPRESS_INTERRUPTS
cpsr |= PSR_I_BIT;
# endif
xcp->regs[REG_CPSR] = cpsr;
}
arch/arm/src/tlsr82/tc32/tc32_saveusercontext.S
+123
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@@ -0,0 +1,123 @@
/****************************************************************************
* arch/arm/src/tlsr82/tc32/tc32_saveusercontext.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Symbols
****************************************************************************/
.file "tc32_saveusercontext.S"
/****************************************************************************
* Macros
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_saveusercontext
*
* Description:
* Restore the current thread context. Full prototype is:
*
* int arm_saveusercontext(uint32_t *saveregs);
*
* R0 = saveregs = pinter saved array
*
* Returned Value:
* None
*
****************************************************************************/
.align 2
.code 16
.thumb_func
.section .ram_code,"ax"
.global up_saveusercontext
.type up_saveusercontext, function
up_saveusercontext:
/*
* r0 = pointer to the saveregs array
* Save r0 ~ r7 into the saved register array
*/
tstorer r0, [r0, #64]
tstorer r1, [r0, #60]
tstorer r2, [r0, #56]
tstorer r3, [r0, #52]
tstorer r4, [r0, #48]
tstorer r5, [r0, #44]
tstorer r6, [r0, #40]
tstorer r7, [r0, #36]
/* Save r14 (lr) into the saved register array */
tmov r1, r14
tstorer r1, [r0, #68]
/* Get CPSR and save it into the saved register array */
tmrcs r1
tstorer r1, [r0, #32]
/* Save IRQ_STATE into the saved register array */
tloadr r1, _REG_IRQ_EN1
tloadrb r2, [r1]
tstorer r2, [r0, #28]
/* Save r8 ~ r14 into the saved register array, r13(sp) r14 (lr/pc) */
tmov r1, r8
tstorer r1, [r0, #24]
tmov r1, r9
tstorer r1, [r0, #20]
tmov r1, r10
tstorer r1, [r0, #16]
tmov r1, r11
tstorer r1, [r0, #12]
tmov r1, r12
tstorer r1, [r0, #8]
tmov r1, r13
tstorer r1, [r0, #4]
tmov r1, r14
tstorer r1, [r0, #0]
/* Return 0 */
tmov r0, #0
tjex lr
.align 2
_REG_IRQ_EN1:
.word 0x00800643
.size up_saveusercontext, .-up_saveusercontext
.end
arch/arm/src/tlsr82/tc32/tc32_schedulesigaction.c
+195
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@@ -0,0 +1,195 @@
/****************************************************************************
* arch/arm/src/tlsr82/tc32/tc32_schedulesigaction.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <sched.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include "tc32.h"
#include "sched/sched.h"
#include "arm_internal.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_schedule_sigaction
*
* Description:
* This function is called by the OS when one or more
* signal handling actions have been queued for execution.
* The architecture specific code must configure things so
* that the 'sigdeliver' callback is executed on the thread
* specified by 'tcb' as soon as possible.
*
* This function may be called from interrupt handling logic.
*
* This operation should not cause the task to be unblocked
* nor should it cause any immediate execution of sigdeliver.
* Typically, a few cases need to be considered:
*
* (1) This function may be called from an interrupt handler
* During interrupt processing, all xcptcontext structures
* should be valid for all tasks. That structure should
* be modified to invoke sigdeliver() either on return
* from (this) interrupt or on some subsequent context
* switch to the recipient task.
* (2) If not in an interrupt handler and the tcb is NOT
* the currently executing task, then again just modify
* the saved xcptcontext structure for the recipient
* task so it will invoke sigdeliver when that task is
* later resumed.
* (3) If not in an interrupt handler and the tcb IS the
* currently executing task -- just call the signal
* handler now.
*
* Assumptions:
* Called from critical section
*
****************************************************************************/
void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
{
sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
/* Refuse to handle nested signal actions */
if (!tcb->xcp.sigdeliver)
{
/* First, handle some special cases when the signal is
* being delivered to the currently executing task.
*/
sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
if (tcb == this_task())
{
/* CASE 1: We are not in an interrupt handler and
* a task is signalling itself for some reason.
*/
if (!CURRENT_REGS)
{
/* In this case just deliver the signal now. */
sigdeliver(tcb);
}
/* CASE 2: We are in an interrupt handler AND the
* interrupted task is the same as the one that
* must receive the signal, then we will have to modify
* the return state as well as the state in the TCB.
*
* Hmmm... there looks like a latent bug here: The following
* logic would fail in the strange case where we are in an
* interrupt handler, the thread is signalling itself, but
* a context switch to another task has occurred so that
* CURRENT_REGS does not refer to the thread of this_task()!
*/
else
{
/* Save the return lr and cpsr and one scratch register
* These will be restored by the signal trampoline after
* the signals have been delivered.
*/
tcb->xcp.sigdeliver = sigdeliver;
/* And make sure that the saved context in the TCB
* is the same as the interrupt return context.
*/
arm_savestate(tcb->xcp.saved_regs);
/* Duplicate the register context. These will be
* restored by the signal trampoline after the signal has been
* delivered.
*/
CURRENT_REGS = (void *)((uint32_t)CURRENT_REGS -
(uint32_t)XCPTCONTEXT_SIZE);
memcpy((uint32_t *)CURRENT_REGS, tcb->xcp.saved_regs,
XCPTCONTEXT_SIZE);
CURRENT_REGS[REG_SP] = (uint32_t)CURRENT_REGS +
(uint32_t)XCPTCONTEXT_SIZE;
/* Then set up to vector to the trampoline with interrupts
* disabled
*/
CURRENT_REGS[REG_LR] = (uint32_t)arm_sigdeliver;
CURRENT_REGS[REG_CPSR] = PSR_MODE_SVC | PSR_I_BIT;
CURRENT_REGS[REG_IRQ_EN] = 0;
}
}
/* Otherwise, we are (1) signaling a task is not running
* from an interrupt handler or (2) we are not in an
* interrupt handler and the running task is signalling
* some non-running task.
*/
else
{
/* Save the return lr and cpsr and one scratch register
* These will be restored by the signal trampoline after
* the signals have been delivered.
*/
tcb->xcp.sigdeliver = sigdeliver;
/* Save the current register context location */
tcb->xcp.saved_regs = tcb->xcp.regs;
/* Duplicate the register context. These will be
* restored by the signal trampoline after the signal has been
* delivered.
*/
tcb->xcp.regs = (void *)((uint32_t)tcb->xcp.regs -
(uint32_t)XCPTCONTEXT_SIZE);
memcpy(tcb->xcp.regs, tcb->xcp.saved_regs, XCPTCONTEXT_SIZE);
tcb->xcp.regs[REG_SP] = (uint32_t)tcb->xcp.regs +
(uint32_t)XCPTCONTEXT_SIZE;
/* Then set up to vector to the trampoline with interrupts
* disabled
*/
tcb->xcp.regs[REG_LR] = (uint32_t)arm_sigdeliver;
tcb->xcp.regs[REG_CPSR] = PSR_MODE_SVC | PSR_I_BIT;
tcb->xcp.regs[REG_IRQ_EN] = 0;
}
}
}
arch/arm/src/tlsr82/tc32/tc32_switchcontext.S
+138
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@@ -0,0 +1,138 @@
/****************************************************************************
* arch/arm/src/tlsr82/tc32/tc32_switchcontext.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch/chip/irq.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Symbols
****************************************************************************/
.file "tc32_switchcontext.S"
/****************************************************************************
* Macros
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_switchcontext
*
* Description:
* Restore the current thread context. Full prototype is:
*
* void arm_switchcontext(uint32_t **saveregs, uint32_t *restoreregs);
*
* R0 = saveregs , pointer to the current task tcb->regs, the sp after
current task context save should be saved in it.
* R1 = restoreregs , next task sp, using it to restore next task context.
*
* Returned Value:
* None
*
****************************************************************************/
.align 2
.code 16
.thumb_func
.section .ram_code,"ax"
.extern arm_fullcontextrestore
.global arm_switchcontext
.type arm_switchcontext, function
arm_switchcontext:
/* Save LR, R0 ~ R7 into current task stack */
tpush {lr}
tpush {r0}
tpush {r1}
tpush {r2}
tpush {r3}
tpush {r4}
tpush {r5}
tpush {r6}
tpush {r7}
/* Get current CPSR and save it into current task stack */
tmrcs r3
tpush {r3}
/* Save IRQ_STATE into current task stack */
tloadr r3, _REG_IRQ_EN3
tloadrb r2, [r3]
tpush {r2}
/* Save r8 ~ r12 into current task stack */
tmov r3, r8
tpush {r3}
tmov r3, r9
tpush {r3}
tmov r3, r10
tpush {r3}
tmov r3, r11
tpush {r3}
tmov r3, r12
tpush {r3}
/* Get the SP (before context save) value and
* save it into current task stack
*/
tmov r2, #(XCPTCONTEXT_SIZE - 8)
tmov r3, r13
tadd r3, r3, r2
tpush {r3}
/* Save PC into current task stack */
tmov r3, r14
tpush {r3}
/* Save back current sp to the tcb->regs */
tmov r3, r13
tstorer r3, [r0]
/* r0 = r1 = next task tcb->regs (actualy sp) */
tmov r0, r1
/* Call arm_fullcontextrestore to restore the context */
tjl arm_fullcontextrestore
.align 2
_REG_IRQ_EN3:
.word 0x00800643
.size arm_switchcontext, .-arm_switchcontext
.end
arch/arm/src/tlsr82/tc32/tc32_syscall.c
+57
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@@ -0,0 +1,57 @@
/****************************************************************************
* arch/arm/src/tlsr82/tc32/tc32_syscall.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <debug.h>
#include <assert.h>
#include <arch/irq.h>
#include "arm_internal.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_syscall
*
* Description:
* SWI interrupts will vector here with insn=the SWI instruction and
* xcp=the interrupt context
*
* The handler may get the SWI number be de-referencing
* the return address saved in the xcp and decoding
* the SWI instruction
*
****************************************************************************/
void arm_syscall(uint32_t *regs)
{
_alert("Syscall from 0x%" PRIx32 "\n", regs[REG_PC]);
CURRENT_REGS = regs;
PANIC();
}
arch/arm/src/tlsr82/tc32/tc32_udelay.c
+57
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@@ -0,0 +1,57 @@
/****************************************************************************
* arch/arm/src/tlsr82/tc32/tc32_udelay.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <sys/types.h>
#include <nuttx/arch.h>
#include "tlsr82_timer.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_udelay
*
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***
*
****************************************************************************/
void locate_code(".ram_code") up_udelay(useconds_t microseconds)
{
uint32_t current = SYSTIMER_TICK_REG;
while ((SYSTIMER_TICK_REG - current) <= (microseconds * 16));
}
arch/arm/src/tlsr82/tlsr82_adc.c
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arch/arm/src/tlsr82/tlsr82_adc.h
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/****************************************************************************
* arch/arm/src/tlsr82/tlsr82_adc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_TLSR82_ADC_H
#define __ARCH_ARM_SRC_TLSR82_TLSR82_ADC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tlsr82_adc.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: tlsr82_adc_init
****************************************************************************/
int tlsr82_adc_init(const char *devpath, int miror);
#endif /* __ARCH_ARM_SRC_TLSR82_TLSR82_ADC_H */
arch/arm/src/tlsr82/tlsr82_analog.c
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/****************************************************************************
* arch/arm/src/tlsr82/tlsr82_analog.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <nuttx/irq.h>
#include <assert.h>
#include <debug.h>
#include "hardware/tlsr82_register.h"
#include "hardware/tlsr82_analog.h"
#include "tlsr82_analog.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define ANALOG_BUSY BIT(0)
#define ANALOG_RSV BIT(4)
#define ANALOG_RW BIT(5)
#define ANALOG_START BIT(6)
#define ANALOG_CYC BIT(7)
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: tlsr82_analog_wait
*
* Description:
* Wait until the analog quit from busy state
*
* Input Parameters:
* void
*
* Returned Value:
* void
*
****************************************************************************/
static inline void tlsr82_analog_wait(void)
{
while (ANALOG_CTRL_REG & ANALOG_BUSY);
}
/****************************************************************************
* Name: tlsr82_analog_read
*
* Description:
* Read the analog register value at address <addr>
*
* Input Parameters:
* addr - the address of analog register that read
*
* Returned Value:
* read value
*
****************************************************************************/
uint8_t locate_code(".ram_code") tlsr82_analog_read(uint8_t addr)
{
irqstate_t flags;
uint8_t data;
flags = enter_critical_section();
/* Read analog address addr */
ANALOG_ADDR_REG = addr;
ANALOG_CTRL_REG = ANALOG_START;
/* Wait until the read finish */
tlsr82_analog_wait();
/* Get the data and clear the analog contrl register */
data = ANALOG_DATA_REG;
ANALOG_CTRL_REG = 0;
leave_critical_section(flags);
return data;
}
/****************************************************************************
* Name: tlsr82_analog_read
*
* Description:
* Write the analog register value at address <addr>
*
* Input Parameters:
* addr - the address of analog register that write
* val - the write value
*
* Returned Value:
* void
*
****************************************************************************/
void locate_code(".ram_code") tlsr82_analog_write(uint8_t addr, uint8_t val)
{
irqstate_t flags;
flags = enter_critical_section();
/* Set the write address and value */
ANALOG_ADDR_REG = addr;
ANALOG_DATA_REG = val;
ANALOG_CTRL_REG = (ANALOG_START | ANALOG_RW);
/* Wait until the write finish */
tlsr82_analog_wait();
/* Clear the analog contrl register */
ANALOG_CTRL_REG = 0;
leave_critical_section(flags);
}
/****************************************************************************
* Name: tlsr82_analog_modify
*
* Description:
* Modity the value at <addr>
*
* Input Parameters:
* addr - the address of analog register that write
* val - the write value
* mask - mask of the modified value
* shift - modified value shift
*
* Returned Value:
* void
*
****************************************************************************/
void locate_code(".ram_code") tlsr82_analog_modify(uint8_t addr,
uint8_t mask,
uint8_t val)
{
tlsr82_analog_write(addr, (tlsr82_analog_read(addr) & (~mask)) | val);
}
arch/arm/src/tlsr82/tlsr82_analog.h
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/****************************************************************************
* arch/arm/src/tlsr82/tlsr82_analog.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_TLSR82_ANALOG_H
#define __ARCH_ARM_SRC_TLSR82_TLSR82_ANALOG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: tlsr82_analog_read
****************************************************************************/
uint8_t locate_code(".ram_code") tlsr82_analog_read(uint8_t addr);
/****************************************************************************
* Name: tlsr82_analog_write
****************************************************************************/
void locate_code(".ram_code") tlsr82_analog_write(uint8_t addr, uint8_t val);
/****************************************************************************
* Name: tlsr82_analog_modify
****************************************************************************/
void locate_code(".ram_code") tlsr82_analog_modify(uint8_t addr,
uint8_t mask,
uint8_t val);
#endif /* __ARCH_ARM_SRC_TLSR82_TLSR82_ANALOG_H */
arch/arm/src/tlsr82/tlsr82_clock.c
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/****************************************************************************
* arch/arm/src/tlsr82/tlsr82_clock.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <nuttx/irq.h>
#include <assert.h>
#include <debug.h>
#include "tlsr82_clock.h"
#include "tlsr82_analog.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define MCU_CORE_B87 1
#define SYSCLK_RC_CLOCK_EN 0
#define CLOCK_SYS_CLOCK_HZ CPU_CLK
#if (CLOCK_SYS_CLOCK_HZ == 12000000)
# define SYS_CLK CLK_SYS_12M_CRYSTAL
#elif (CLOCK_SYS_CLOCK_HZ == 16000000)
# define SYS_CLK CLK_SYS_16M_CRYSTAL
#elif (CLOCK_SYS_CLOCK_HZ == 24000000)
# define SYS_CLK CLK_SYS_24M_CRYSTAL
#elif ((CLOCK_SYS_CLOCK_HZ == 32000000) && (MCU_CORE_B85 || MCU_CORE_B87))
# define SYS_CLK CLK_SYS_32M_CRYSTAL
#elif ((CLOCK_SYS_CLOCK_HZ == 48000000) && (MCU_CORE_B85 || MCU_CORE_B87))
# define SYS_CLK CLK_SYS_48M_CRYSTAL
#else
# error "sys clock error or undefined"
#endif
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
void clock_rc24m_init(void)
{
uint8_t cap;
tlsr82_analog_write(0xc8, 0x80);
tlsr82_analog_write(0x30, tlsr82_analog_read(0x30) | BIT(7));
tlsr82_analog_write(0xc7, 0x0e);
tlsr82_analog_write(0xc7, 0x0f);
while ((tlsr82_analog_read(0xcf) & 0x80) == 0);
/* Write 24m cap into manual register */
cap = tlsr82_analog_read(0xcb);
tlsr82_analog_write(0x33, cap);
tlsr82_analog_write(0x30, tlsr82_analog_read(0x30) & (~BIT(7)));
tlsr82_analog_write(0xc7, 0x0e);
}
/****************************************************************************
* Public Functions
****************************************************************************/
void tlsr82_clock_init(void)
{
CLK_SYS_SEL = (uint8_t)SYS_CLK;
#if (SYSCLK_RC_CLOCK_EN)
if (SYS_CLK < SYS_CLK_RC_THRES)
{
clock_rc_set(SYS_CLK);
}
#endif
clock_rc24m_init();
}
arch/arm/src/tlsr82/tlsr82_clock.h
+69
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/****************************************************************************
* arch/arm/src/tlsr82/tlsr82_clock.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_TLSR82_CLOCK_H
#define __ARCH_ARM_SRC_TLSR82_TLSR82_CLOCK_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/tlsr82_clock.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
void tlsr82_clock_init(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_TLSR82_TLSR82_SPI_CONSOLE_H */
arch/arm/src/tlsr82/tlsr82_cpu.c
+306
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/****************************************************************************
* arch/arm/src/tlsr82/tlsr82_cpu.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include "tlsr82_cpu.h"
#include "tlsr82_analog.h"
#include "tlsr82_clock.h"
#include "tlsr82_gpio.h"
#include "tlsr82_timer.h"
#include "hardware/tlsr82_dma.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
#define XTAL_READY_CHECK_TIMING_OPTIMIZE 1
#define BLC_PM_DEEP_RETENTION_MODE_EN 0
void locate_code (".ram_code") tlsr82_pm_wait_bbpll_done(void)
{
volatile uint8_t i;
uint8_t j;
uint8_t ana_81 = tlsr82_analog_read(0x81);
tlsr82_analog_write(0x81, ana_81 | BIT (6));
for (j = 0; j < 3; j++)
{
/* Delay about 20us */
for (i = 0; i < 30; i++)
{
asm("tnop");
}
if (BIT (5) == (tlsr82_analog_read(0x88) & BIT (5)))
{
tlsr82_analog_write(0x81, ana_81 & 0xbf);
break;
}
else
{
if (j == 0)
{
tlsr82_analog_write(0x01, 0x4e);
}
else if (j == 1)
{
tlsr82_analog_write(0x01, 0x4b);
}
else
{
tlsr82_analog_write(0x81, ana_81 & 0xbf);
}
}
}
}
void tlsr82_cpu_wakeup_init(power_mode_t power_mode, xtal_t xtal)
{
/* This code strictly follow the telink code, just modity the comment */
/* poweron_default : 0x7c -> 0x00
* poweron_default : 0xff -> 0x00
* poweron_default : 0xcf -> 0xc8
* <7> : mcic1,R default:1
* <6> : risc1,R default:1
* <3> : trng default:1
*/
write_reg8(0x60, 0x00);
write_reg8(0x61, 0x00);
write_reg8(0x62, 0x08);
/* poweron_default : 0x83 -> 0xff
* poweron_default : 0x00 -> 0x9f
* <5/6> : undefined, default:0
*/
write_reg8(0x63, 0xff);
write_reg8(0x64, 0xff);
/* poweron_default : 0x30 -> 0x37
* <0> : aif -> disable 32k for qdec
* <5/6> : undefined, default:0
*/
write_reg8(0x65, 0xf7);
/* when load code twice without power down dut, dut will
* use crystal clock in here, xo_quick_settle manual mode
* need to use in RC colck.
* poweron_default : set RC clock as system clock.
*/
write_reg8(0x66, 0x06);
/* poweron_default : 0xcf -> 0xce
* <0> : power on bbpll LDO
* <4> : power on otp LDO
*/
tlsr82_analog_write(0x06, 0xce);
/* xo_quict_settle with auto will cause the pragram crash
* in high temperature, must be set to manual mode.
* (add by Yi Bao, confirmed by wenfeng 20190911)
*/
unsigned char ana_2c = tlsr82_analog_read(0x2c);
unsigned char ana_05 = tlsr82_analog_read(0x05);
/* 0x2c<5>: xo_quick_rst
* <5> 1b'1: xtal 24M quick settle count
* 0x05<3>: 24M_xtl_pd
* <3> 1b'0 : Power up 24MHz XTL oscillator
* <3> 1b'1 : Power down 24MHz XTL oscillator
*/
tlsr82_analog_write(0x2c, ana_2c | 0x20);
tlsr82_analog_write(0x2c, ana_2c & 0xdf);
tlsr82_analog_write(0x05, ana_05 | 0x08);
tlsr82_analog_write(0x05, ana_05 & 0xf7);
/* poweron_default: 0x05 -> 0x25
* <3:0>: bbpll setting
* <5>: enable 48M clock to digital core
* <6>: enable signal of 24M clock to sar
*/
tlsr82_analog_write(0x82, 0x65);
/* poweron_default: 0x07 -> 0x80
* <0>: power on baseband
* <1>: power on usb
* <2>: power on audio
* <7>: enable change power sequence clk
*/
tlsr82_analog_write(0x34, 0x80);
/* When using the BDT tool to download a program through USB,
* if the dp pull-up is turned off, the device will be disconnected,
* so the dp pull-up is set to be keep, modify by kaixin(2019.12.27).
*/
/* default: 0x7b
* <7>: enable_b signal of 1.5K pullup resistor for DP PAD--keep
* <6>: enable signal of 1M pullup resistor for mscn PAD, avoid current
* leakage 1->0
* <5:4>: reference scale select 11->11
* <1:0>: power on native 1.8v/1.4v 11->00
*/
tlsr82_analog_write(0x0b, (tlsr82_analog_read(0x0b) & 0x80) | 0x38);
/* poweron_default: 0x00
* <1> set 1: reg_xo_en_clk_ana_ana, to enable external 24M crystal
*/
tlsr82_analog_write(0x8c, 0x02);
/* poweron_default: 0x18
* <7> MSB of ret_ldo_trim, 0: 0.8-1.15V; 1: 0.6-0.95V
*/
tlsr82_analog_write(0x00, tlsr82_analog_read(0x00) & 0x7f);
/* poweron_default: 0xa4,
* <2:0> ret_ldo_trim, set 0x04: 1.00V
*/
tlsr82_analog_write(0x02, 0xa4);
/* pragram can crash in high temperature,
* ana_01 and pm_wait_bbpll_done() is order to solve this problem.
*/
tlsr82_analog_write(0x01, 0x4d);
if (xtal == EXTERNAL_XTAL_48M)
{
/* use external 48M crystal instead of external 24M crystal
* poweron_default: 0x15
* <6>: 0 - 24M XTAL
* 1 - 48M XTAL
*/
tlsr82_analog_write(0x2d, tlsr82_analog_read(0x2d) | BIT (6));
}
/* poweron_default: 0x40
* <1:0>: 00 - LDO
* 01 - LDO_DC
* 11 - DCDC
* when use the LDO_1P4_DCDC_1P8, should use synchronize mode
* (0x0a <2>: 1-synchronize mode, 0-asynchronize mode) to avoid
* the current abnormal in A0.
*/
tlsr82_analog_write(0x0a, power_mode);
if (LDO_MODE != power_mode)
{
/* poweron_default: 0xc4, 1.4v voltage turn dowm 100mv */
tlsr82_analog_write(0x0c, 0xa4);
}
/* poweron_default: 0x00, PA gpio wakeup disable */
tlsr82_analog_write(0x27, 0x00);
/* poweron_default: 0x00 PB gpio wakeup disable */
tlsr82_analog_write(0x28, 0x00);
/* poweron_default: 0x00 PC gpio wakeup disable */
tlsr82_analog_write(0x29, 0x00);
/* poweron_default: 0x00 PD gpio wakeup disable */
tlsr82_analog_write(0x2a, 0x00);
/* poweron_default: 0x00000000 -> 0x04040404 */
write_reg32(0xc40, 0x04040404);
/* poweron_default: 0x00000000 -> 0x04040404 */
write_reg32(0xc44, 0x04040404);
/* poweron_default: 0x00 -> 0x04 */
write_reg8(0xc48, 0x04);
/* core_c20/c21 power on default all enable, so we disable them first,
* then if use, enable them by manual
* note that: PWM/RF Tx/RF Rx/AES code/AES dcode dma may be affected
* by this, you must handle them when initialization.
*/
DMA_IRQ_EN_REG = 0;
DMA_IRQ_MASK_REG = 0;
GPIO_IRQ_NORMAL_ALL_REG = GPIO_IRQ_NORMAL_ALL_WAKEUP |
GPIO_IRQ_NORMAL_ALL_WAKEUP;
/* xo_ready check should be done after Xtal manual on_off, we put it here
* to save code running time, code running time between Xtal manual on_off
* and xo_ready check can be used as Xtal be stable timimg
* 0x88<7>: xo_ready_ana
*/
while (BIT (7) != (tlsr82_analog_read(0x88) & (BIT (7))));
tlsr82_pm_wait_bbpll_done();
/* System timer config, enable system timer and interrupt */
SYSTIMER_CTRL_REG |= SYSTIMER_CTRL_TIMER_EN | SYSTIMER_CTRL_CALI_EN;
SYSTIMER_IRQ_MASK_REG |= SYSTIMER_IRQ_MASK_EN;
}
arch/arm/src/tlsr82/tlsr82_cpu.h
+53
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/****************************************************************************
* arch/arm/src/tlsr82/tlsr82_cpu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_TLSR82_CPU_H
#define __ARCH_ARM_SRC_TLSR82_TLSR82_CPU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Types
****************************************************************************/
typedef enum
{
LDO_MODE = 0x40, /* LDO mode */
DCDC_LDO_MODE = 0x41, /* DCDC_LDO mode */
DCDC_MODE = 0x43, /* DCDC mode (16pin chip not suported) */
} power_mode_t;
typedef enum
{
EXTERNAL_XTAL_24M = 0,
EXTERNAL_XTAL_48M = 1,
} xtal_t;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
void tlsr82_cpu_wakeup_init(power_mode_t power_mode, xtal_t xtal);
#endif /* __ARCH_ARM_SRC_TLSR82_TLSR82_CPU_H */
arch/arm/src/tlsr82/tlsr82_flash.c
+478
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@@ -0,0 +1,478 @@
/****************************************************************************
* arch/arm/src/tlsr82/tlsr82_flash.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/compiler.h>
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <assert.h>
#include <debug.h>
#include "hardware/tlsr82_mspi.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Manufacturer id definitions */
#if defined(CONFIG_ARCH_CHIP_TLSR8278)
# define FLASH_MID_GD25LD10C 0x1160c8
# define FLASH_MID_GD25LD40C 0x1360c8
# define FLASH_MID_GD25LD80C 0x1460c8
# define FLASH_MID_ZB25WD10A 0x11325e
# define FLASH_MID_ZB25WD40B 0x13325e
# define FLASH_MID_ZB25WD80B 0x14325e
# define FLASH_MID_ZB25WD20A 0x12325e
#elif defined(CONFIG_ARCH_CHIP_TLSR8258)
# define FLASH_MID_ZB25WD40B 0x13325e
# define FLASH_MID_ZB25WD80B 0x14325e
# define FLASH_MID_GD25LD05C 0x1060c8
# define FLASH_MID_GD25LD40C 0x1360c8
# define FLASH_MID_GD25LD80C 0x1460c8
# define FLASH_MID_GD25LE80C 0x1460c8
# define FLASH_MID_GD25LQ80C 0x1460c8
# define FLASH_MID_MD25D40D 0x134051
# define FLASH_MID_P25Q40L 0x136085
# define FLASH_MID_TH25D40LA 0x1360eb
# define FLASH_MID_TH25D40UA 0x1360eb
#endif
/* Flash command definitions */
#define FLASH_INVALID_ADDR 0xffffffff
#define FLASH_CMD_WRITE 0x02
#define FLASH_CMD_WRITE_ENABLE 0x06
#define FLASH_CMD_WRITE_DISABLE 0x04
#define FLASH_CMD_WRITE_SECURITY_REG 0x42
#define FLASH_CMD_WRITE_STATUS_LBYTE 0x01
#define FLASH_CMD_WRITE_STATUS_HBYTE 0x31
#define FLASH_CMD_READ 0x03
#define FLASH_CMD_READ_SECURITY_REG 0x48
#define FLASH_CMD_READ_JEDEC_ID 0x9f
#define FLASH_CMD_READ_STATUS_LBYTE 0x05
#define FLASH_CMD_READ_STATUS_HBYTE 0x35
#define FLASH_CMD_ERASE_SECTOR 0x20
#define FLASH_CMD_ERASE_SECURITY_REG 0x44
/* Read the flash uniqe id command
* FLASH_CMD_READ_UID1: GD_PUYA_ZB_TH
* FLASH_CMD_READ_UID2: XTX
*/
#define FLASH_CMD_READ_UID1 0x4b
#define FLASH_CMD_READ_UID2 0x5a
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
static const uint8_t g_invalid_uid[16] =
{
0x51, 0x01, 0x51, 0x01,
0x51, 0x01, 0x51, 0x01,
0x51, 0x01, 0x51, 0x01,
0x51, 0x01, 0x51, 0x01,
};
#if defined(CONFIG_ARCH_CHIP_TLSR8278)
static const uint32_t g_support_mid[] =
{
0x1160c8, /* FLASH_MID_GD25LD10C */
0x1360c8, /* FLASH_MID_GD25LD40C */
0x1460c8, /* FLASH_MID_GD25LD80C */
0x11325e, /* FLASH_MID_ZB25WD10A */
0x12325e, /* FLASH_MID_ZB25WD20A */
0x13325e, /* FLASH_MID_ZB25WD40B */
0x14325e, /* FLASH_MID_ZB25WD80B */
};
#elif defined(CONFIG_ARCH_CHIP_TLSR8258)
static const uint32_t g_support_mid[] =
{
0x0013325e, /* FLASH_MID_ZB25WD40B */
0x0014325e, /* FLASH_MID_ZB25WD80B */
0x001060c8, /* FLASH_MID_GD25LD05C */
0x001360c8, /* FLASH_MID_GD25LD40C */
0x001460c8, /* FLASH_MID_GD25LD80C, FLASH_MID_GD25LE80C */
0x011460c8, /* FLASH_MID_GD25LQ80C */
0x00134051, /* FLASH_MID_MD25D40D */
0x00136085, /* FLASH_MID_P25Q40L */
0x001360eb, /* FLASH_MID_TH25D40LA, FLASH_MID_TH25D40UA */
};
#endif
static const uint32_t g_support_mid_num =
sizeof(g_support_mid) / sizeof(uint32_t);
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: flash_send_cmd
*
* Description:
* Configurate the gpio drive strength be high/low.
*
* Input Parameters:
* cmd - GPIO config information
*
* Returned Value:
* void
*
****************************************************************************/
static void locate_code(".ram_code") flash_send_cmd(uint8_t cmd)
{
MSPI_CS_HIGH();
up_udelay(1);
MSPI_CS_LOW();
MSPI_WRITE(cmd);
MSPI_WAIT();
}
static void locate_code(".ram_code") flash_send_addr(uint32_t addr)
{
MSPI_WRITE((uint8_t)(addr >> 16));
MSPI_WAIT();
MSPI_WRITE((uint8_t)(addr >> 8));
MSPI_WAIT();
MSPI_WRITE((uint8_t)(addr));
MSPI_WAIT();
}
static void locate_code(".ram_code") flash_wait_done(void)
{
int i;
up_udelay(100);
flash_send_cmd(FLASH_CMD_READ_STATUS_LBYTE);
for (i = 0; i < 10000000; i++)
{
MSPI_WRITE(0);
MSPI_WAIT();
if ((MSPI_READ() & 0x01) == 0)
{
break;
}
}
MSPI_CS_HIGH();
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: tlsr82_flash_read
*
* Description:
* Write data to addr
*
* Input Parameters:
* cmd - flash write command
* addr - flash write address
* buf - flash write buffer
* len - flash write buffer length
*
* Returned Value:
* void
*
****************************************************************************/
void locate_code(".ram_code") tlsr82_flash_read(uint8_t cmd, uint32_t addr,
uint8_t dummy_cnt,
uint8_t *buf, uint32_t len)
{
int i;
irqstate_t flags;
flags = enter_critical_section();
flash_send_cmd(cmd);
/* If send read address first, send the address */
if (addr != FLASH_INVALID_ADDR)
{
flash_send_addr(addr);
}
/* Write dummy data, why ? */
for (i = 0; i < dummy_cnt; i++)
{
MSPI_WRITE(0);
MSPI_WAIT();
}
/* Issue clock, why ? */
MSPI_WRITE(0);
MSPI_WAIT();
/* Switch to auto mode */
MSPI_AUTO_MODE();
MSPI_WAIT();
/* Read data */
for (i = 0; i < len; i++)
{
buf[i] = MSPI_READ();
MSPI_WAIT();
}
/* Write finish, pull-up the cs */
MSPI_CS_HIGH();
leave_critical_section(flags);
}
/****************************************************************************
* Name: tlsr82_flash_write
*
* Description:
* Write data to addr
*
* Input Parameters:
* cmd - flash write command
* addr - flash write address
* buf - flash write buffer
* len - flash write buffer length
*
* Returned Value:
* void
*
****************************************************************************/
void locate_code(".ram_code") tlsr82_flash_write(uint8_t cmd, uint32_t addr,
const uint8_t *buf,
uint32_t len)
{
int i;
irqstate_t flags;
flags = enter_critical_section();
flash_send_cmd(FLASH_CMD_WRITE_ENABLE);
flash_send_cmd(cmd);
/* If send write address first, send the address */
if (addr != FLASH_INVALID_ADDR)
{
flash_send_addr(addr);
}
/* Write data */
for (i = 0; i < len; i++)
{
MSPI_WRITE(buf[i]);
MSPI_WAIT();
}
/* Write finish, pull-up the cs */
MSPI_CS_HIGH();
/* Wait the flash write finish */
flash_wait_done();
leave_critical_section(flags);
}
/****************************************************************************
* Name: tlsr82_flash_erase_sector
*
* Description:
* Erase the section addr at
*
* Input Parameters:
* addr - flash erase address
*
* Returned Value:
* void
*
****************************************************************************/
void tlsr82_flash_erase_sector(uint32_t addr)
{
DEBUGASSERT(addr != FLASH_INVALID_ADDR);
tlsr82_flash_write(FLASH_CMD_ERASE_SECTOR, addr, NULL, 0);
}
/****************************************************************************
* Name: tlsr82_flash_read_data
*
* Description:
* Read the data at address addr
*
* Input Parameters:
* addr - flash read start address
* buf - flash read buffer
* len - flash read buffer length
*
* Returned Value:
* void
*
****************************************************************************/
void tlsr82_flash_read_data(uint32_t addr, uint8_t *buf, uint32_t len)
{
tlsr82_flash_read(FLASH_CMD_READ, addr, 0, buf, len);
}
/****************************************************************************
* Name: tlsr82_flash_write_data
*
* Description:
* Write the data at address addr
*
* Input Parameters:
* addr - flash write start address
* buf - flash write buffer
* len - flash write buffer length
*
* Returned Value:
* void
*
****************************************************************************/
void tlsr82_flash_write_data(uint32_t addr, const uint8_t *buf, uint32_t len)
{
tlsr82_flash_write(FLASH_CMD_WRITE, addr, buf, len);
}
/****************************************************************************
* Name: tlsr82_flash_read_uid
*
* Description:
* Read the flash unique id
*
* Input Parameters:
* cmd - read uid command
* buf - uid read buffer
*
* Returned Value:
* void
*
****************************************************************************/
void tlsr82_flash_read_uid(uint8_t cmd, uint8_t *buf)
{
if (cmd == FLASH_CMD_READ_UID1)
{
tlsr82_flash_read(FLASH_CMD_READ_UID1, 0, 1, buf, 16);
}
}
/****************************************************************************
* Name: tlsr82_flash_read_mid
*
* Description:
* Read the flash chip manufacaturer ID
*
* Input Parameters:
* pmid - manufacaturer ID pointer, size 4 bytes
* puid - unique ID pointer, size 16 bytes
*
* Returned Value:
* Positive on success, negative on fail
*
****************************************************************************/
int tlsr82_flash_miduid_check(uint32_t *pmid, uint8_t *puid)
{
int i;
#ifdef CONFIG_ARCH_CHIP_TLSR8258
uint8_t buf[4];
#endif
DEBUGASSERT(pmid != NULL && puid != NULL);
/* Read the flash manufacaturer ID */
tlsr82_flash_read(FLASH_CMD_READ_JEDEC_ID, FLASH_INVALID_ADDR,
0, (uint8_t *)pmid, 3);
#ifdef CONFIG_ARCH_CHIP_TLSR8258
if (mid == FLASH_MID_GD25LE80C)
{
tlsr82_flash_read(FLASH_CMD_READ_UID2, 0, 1, buf, 4);
if ((buf[0] == 0x53) && (buf[1] == 0x46) &&
(buf[2] == 0x44) && (buf[3] == 0x50))
{
mid = 0x011460c8;
}
}
#endif
/* Check the validation of the manufacaturer ID */
for (i = 0; i < g_support_mid_num; i++)
{
if (g_support_mid[i] == *pmid)
{
tlsr82_flash_read_uid(FLASH_CMD_READ_UID1, (uint8_t *)puid);
break;
}
}
if (i == g_support_mid_num)
{
ferr("Current flash device is not supported, mid=0x%lu\n", *pmid);
return -ENOTSUP;
}
/* Check the validation of the unique ID */
if (memcmp(g_invalid_uid, puid, 16) == 0)
{
ferr("Current flash no unique id\n");
return -ENOTSUP;
}
return OK;
}
arch/arm/src/tlsr82/tlsr82_flash.h
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/****************************************************************************
* arch/arm/src/tlsr82/tlsr82_flash.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_TLSR82_FLASH_H
#define __ARCH_ARM_SRC_TLSR82_TLSR82_FLASH_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "chip.h"
#include "hardware/tlsr82_mspi.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
void tlsr82_flash_erase_sector(uint32_t addr);
void tlsr82_flash_read_data(uint32_t addr, uint8_t *buf, uint32_t len);
void tlsr82_flash_write_data(uint32_t addr, const uint8_t *buf,
uint32_t len);
int tlsr82_flash_miduid_check(uint32_t *pmid, uint8_t *puid);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_TLSR82_TLSR82_FLASH_H */
arch/arm/src/tlsr82/tlsr82_flash_mtd.c
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arch/arm/src/tlsr82/tlsr82_flash_mtd.h
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/****************************************************************************
* arch/arm/src/tlsr82/tlsr82_flash_mtd.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_TLSR82_FLASH_MTD_H
#define __ARCH_ARM_SRC_TLSR82_TLSR82_FLASH_MTD_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/mtd/mtd.h>
#include <stdint.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
struct mtd_dev_s *tlsr82_flash_initialize(uint32_t offset, uint32_t size);
#ifdef CONFIG_MTD_PARTITION
int tlsr82_partition_init(const char *path);
#endif
#endif /* __ARCH_ARM_SRC_TLSR82_TLSR82_FLASH_MTD_H */
arch/arm/src/tlsr82/tlsr82_gpio.c
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arch/arm/src/tlsr82/tlsr82_gpio.h
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/****************************************************************************
* arch/arm/src/tlsr82/tlsr82_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_TLSR82_GPIO_H
#define __ARCH_ARM_SRC_TLSR82_TLSR82_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <stdint.h>
#include <stdbool.h>
#include "hardware/tlsr82_irq.h"
#include "hardware/tlsr82_gpio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* GPIO definitions t = type, n = name, c = config, p = pinset */
#define GPIO_VAL(t, n) (GPIO_##t##_##n >> GPIO_##t##_SHIFT)
#define GPIO_GET(t, c) (((c) & GPIO_##t##_MASK) >> GPIO_##t##_SHIFT)
#define GPIO_IS(t, n, c) (((c) & GPIO_##t##_MASK) == GPIO_##t##_##n)
#define GPIO_CFG2SDKPIN(p) (((p) & GPIO_GROUP_MASK) | (1 << GPIO_GET(PIN, p)))
#define GPIO_CFG2PIN(p) ((p) & (GPIO_GROUP_MASK | GPIO_PIN_MASK))
#define GPIO_PIN2NUM(p) (GPIO_GET(PIN, p) + (GPIO_GET(GROUP, p) << 3))
#define GPIO_ALL_MASK (GPIO_PIN_MASK | GPIO_GROUP_MASK | GPIO_AF_MASK |\
GPIO_PUPD_MASK | GPIO_DS_MASK | GPIO_IRQ_MASK |\
GPIO_POL_MASK)
#define GPIO_INVLD_CFG (~GPIO_ALL_MASK)
#define GPIO_VALID(c) (((c) & (~GPIO_ALL_MASK)) == 0)
/* Gpio pin option, each gpio group has 8 pin
* Mask in pinset 0x0000 00FF
*/
#define GPIO_PIN_SHIFT 0
#define GPIO_PIN_MASK (0xFF << GPIO_PIN_SHIFT)
#define GPIO_PIN(n) ((n) << GPIO_PIN_SHIFT)
#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
/* Gpio group option
* Mask in pinset 0x0000 0300
*/
#define GPIO_GROUP_SHIFT 8
#define GPIO_GROUP_MASK (0x3 << GPIO_GROUP_SHIFT)
#define GPIO_GROUP_A (0 << GPIO_GROUP_SHIFT)
#define GPIO_GROUP_B (1 << GPIO_GROUP_SHIFT)
#define GPIO_GROUP_C (2 << GPIO_GROUP_SHIFT)
#define GPIO_GROUP_D (3 << GPIO_GROUP_SHIFT)
/* Gpio alternative function option
* Mask in config 0x0000 7000
*/
#define GPIO_AF_SHIFT 12
#define GPIO_AF_MASK (0x7 << GPIO_AF_SHIFT)
#define GPIO_AF_SHUTDOWN (0 << GPIO_AF_SHIFT)
#define GPIO_AF_INPUT (1 << GPIO_AF_SHIFT)
#define GPIO_AF_OUTPUT (2 << GPIO_AF_SHIFT)
#define GPIO_AF_MUX0 (3 << GPIO_AF_SHIFT)
#define GPIO_AF_MUX1 (4 << GPIO_AF_SHIFT)
#define GPIO_AF_MUX2 (5 << GPIO_AF_SHIFT)
#define GPIO_AF_MUX3 (6 << GPIO_AF_SHIFT)
/* Pull-up and Pull-down option
* Mask in config 0x0003 0000
*/
#define GPIO_PUPD_SHIFT 16
#define GPIO_PUPD_MASK (0x3 << GPIO_PUPD_SHIFT)
#define GPIO_PUPD_NONE (0 << GPIO_PUPD_SHIFT)
#define GPIO_PUPD_PU1M (1 << GPIO_PUPD_SHIFT)
#define GPIO_PUPD_PD100K (2 << GPIO_PUPD_SHIFT)
#define GPIO_PUPD_PU10K (3 << GPIO_PUPD_SHIFT)
/* Driver Strength option
* Mask in config 0x0004 0000
*/
#define GPIO_DS_SHIFT 18
#define GPIO_DS_MASK (0x1 << GPIO_DS_SHIFT)
#define GPIO_DS_LOW (0 << GPIO_DS_SHIFT)
#define GPIO_DS_HIGH (1 << GPIO_DS_SHIFT)
/* Gpio interrupt type option
* Mask in config 0x0070 0000
*/
#define GPIO_IRQ_SHIFT 20
#define GPIO_IRQ_MASK (0x7 << GPIO_IRQ_SHIFT)
#define GPIO_IRQ_DISABLE (0 << GPIO_IRQ_SHIFT)
#define GPIO_IRQ_NORMAL (1 << GPIO_IRQ_SHIFT)
#define GPIO_IRQ_M0 (2 << GPIO_IRQ_SHIFT)
#define GPIO_IRQ_M1 (3 << GPIO_IRQ_SHIFT)
#define GPIO_IRQ_M2 (4 << GPIO_IRQ_SHIFT)
#define GPIO_IRQ_RISC0 (5 << GPIO_IRQ_SHIFT)
#define GPIO_IRQ_RISC1 (6 << GPIO_IRQ_SHIFT)
#define GPIO_IRQ_NORMAL_VAL 1
#define GPIO_IRQ_M0_VAL 2
#define GPIO_IRQ_M1_VAL 3
#define GPIO_IRQ_M2_VAL 4
#define GPIO_IRQ_RISC0_VAL 5
#define GPIO_IRQ_RISC1_VAL 6
/* Gpio interrupt polarity option
* Mask in config 0x0080 0000
*/
#define GPIO_POL_SHIFT 23
#define GPIO_POL_MASK (0x1 << GPIO_POL_SHIFT)
#define GPIO_POL_RISE (0 << GPIO_POL_SHIFT)
#define GPIO_POL_FAIL (1 << GPIO_POL_SHIFT)
/* GPIO specific pin definitions */
#define GPIO_PIN_PA0 (GPIO_GROUP_A | GPIO_PIN0)
#define GPIO_PIN_PA1 (GPIO_GROUP_A | GPIO_PIN1)
#define GPIO_PIN_PA2 (GPIO_GROUP_A | GPIO_PIN2)
#define GPIO_PIN_PA3 (GPIO_GROUP_A | GPIO_PIN3)
#define GPIO_PIN_PA4 (GPIO_GROUP_A | GPIO_PIN4)
#define GPIO_PIN_PA5 (GPIO_GROUP_A | GPIO_PIN5)
#define GPIO_PIN_PA6 (GPIO_GROUP_A | GPIO_PIN6)
#define GPIO_PIN_PA7 (GPIO_GROUP_A | GPIO_PIN7)
#define GPIO_PIN_PB0 (GPIO_GROUP_B | GPIO_PIN0)
#define GPIO_PIN_PB1 (GPIO_GROUP_B | GPIO_PIN1)
#define GPIO_PIN_PB2 (GPIO_GROUP_B | GPIO_PIN2)
#define GPIO_PIN_PB3 (GPIO_GROUP_B | GPIO_PIN3)
#define GPIO_PIN_PB4 (GPIO_GROUP_B | GPIO_PIN4)
#define GPIO_PIN_PB5 (GPIO_GROUP_B | GPIO_PIN5)
#define GPIO_PIN_PB6 (GPIO_GROUP_B | GPIO_PIN6)
#define GPIO_PIN_PB7 (GPIO_GROUP_B | GPIO_PIN7)
#define GPIO_PIN_PC0 (GPIO_GROUP_C | GPIO_PIN0)
#define GPIO_PIN_PC1 (GPIO_GROUP_C | GPIO_PIN1)
#define GPIO_PIN_PC2 (GPIO_GROUP_C | GPIO_PIN2)
#define GPIO_PIN_PC3 (GPIO_GROUP_C | GPIO_PIN3)
#define GPIO_PIN_PC4 (GPIO_GROUP_C | GPIO_PIN4)
#define GPIO_PIN_PC5 (GPIO_GROUP_C | GPIO_PIN5)
#define GPIO_PIN_PC6 (GPIO_GROUP_C | GPIO_PIN6)
#define GPIO_PIN_PC7 (GPIO_GROUP_C | GPIO_PIN7)
#define GPIO_PIN_PD0 (GPIO_GROUP_D | GPIO_PIN0)
#define GPIO_PIN_PD1 (GPIO_GROUP_D | GPIO_PIN1)
#define GPIO_PIN_PD2 (GPIO_GROUP_D | GPIO_PIN2)
#define GPIO_PIN_PD3 (GPIO_GROUP_D | GPIO_PIN3)
#define GPIO_PIN_PD4 (GPIO_GROUP_D | GPIO_PIN4)
#define GPIO_PIN_PD5 (GPIO_GROUP_D | GPIO_PIN5)
#define GPIO_PIN_PD6 (GPIO_GROUP_D | GPIO_PIN6)
#define GPIO_PIN_PD7 (GPIO_GROUP_D | GPIO_PIN7)
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/* Must be big enough to hold the above encodings */
typedef uint32_t gpio_cfg_t;
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
void tlsr82_gpio_as_gpio(gpio_cfg_t cfg, bool enable);
void tlsr82_gpio_input_ctrl(gpio_cfg_t cfg, bool enable);
void tlsr82_gpio_output_ctrl(gpio_cfg_t cfg, bool enable);
void tlsr82_gpio_pupd_ctrl(gpio_cfg_t cfg, uint8_t pupd);
/****************************************************************************
* Name: tlsr82_gpioconfig
*
* Description:
* Configure a GPIO pin based on encoded pin config.
*
****************************************************************************/
int tlsr82_gpioconfig(gpio_cfg_t cfg);
/****************************************************************************
* Name: tlsr82_unconfiggpio
*
* Description:
* Un-configure a GPIO pin based on encoded pin config.
*
****************************************************************************/
int tlsr82_gpiounconfig(gpio_cfg_t cfg);
/****************************************************************************
* Name: tlsr82_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void tlsr82_gpiowrite(gpio_cfg_t cfg, bool value);
/****************************************************************************
* Name: tlsr82_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool tlsr82_gpioread(gpio_cfg_t cfg);
/****************************************************************************
* Name: tlsr82_gpioirqinitialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
****************************************************************************/
#ifdef CONFIG_TLSR82_GPIO_IRQ
void tlsr82_gpioirqinitialize(void);
#else
# define tlsr82_gpioirqinitialize()
#endif
#ifdef CONFIG_TLSR82_GPIO_IRQ
int tlsr82_gpioirqconfig(gpio_cfg_t cfg, xcpt_t func, void *arg);
#else
# define tlsr82_gpioirqconfig(cfg, func, arg)
#endif
/****************************************************************************
* Name: tlsr82_gpioirqenable
*
* Description:
* Enable the interrupt for specified GPIO IRQ
*
****************************************************************************/
#ifdef CONFIG_TLSR82_GPIO_IRQ
void tlsr82_gpioirqenable(gpio_cfg_t cfg);
#else
# define tlsr82_gpioirqenable(cfg)
#endif
/****************************************************************************
* Name: tlsr82_gpioirqdisable
*
* Description:
* Disable the interrupt for specified GPIO IRQ
*
****************************************************************************/
#ifdef CONFIG_TLSR82_GPIO_IRQ
void tlsr82_gpioirqdisable(gpio_cfg_t cfg);
#else
# define tlsr82_gpioirqdisable(cfg)
#endif
/****************************************************************************
* Name: tlsr82_gpioirqdisable_all
*
* Description:
* Disable all the gpio interrupt (not clear gpio pin corresponding
* interrupt bit.)
*
****************************************************************************/
#ifdef CONFIG_TLSR82_GPIO_IRQ
void tlsr82_gpioirqdisable_all(void);
#else
# define tlsr82_gpioirqdisable_all()
#endif
/****************************************************************************
* Name: tlsr82_gpioirqenable_all
*
* Description:
* Enable all the gpio interrupt (not set gpio pin corresponding
* interrupt bit.)
*
****************************************************************************/
#ifdef CONFIG_TLSR82_GPIO_IRQ
void tlsr82_gpioirqenable_all(void);
#else
# define tlsr82_gpioirqenable_all()
#endif
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_SRC_TLSR82_TLSR82_GPIO_H */
arch/arm/src/tlsr82/tlsr82_gpio_cfg.c
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/****************************************************************************
* arch/arm/src/tlsr82/tlsr82_gpio_cfg.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <assert.h>
#include <debug.h>
#include "tlsr82_analog.h"
#include "tlsr82_gpio.h"
#include "tlsr82_gpio_cfg.h"
#include "tlsr82_gpio_default.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define MUX_NONE TLSR82_MUX_NONE
#define MUX_UART TLSR82_MUX_UART
#define MUX_PWM TLSR82_MUX_PWM
#define MUX_DMIC TLSR82_MUX_DMIC
#define MUX_I2C TLSR82_MUX_I2C
#define MUX_SPI TLSR82_MUX_SPI
#define MUX_U7816 TLSR82_MUX_U7816
#define MUX_SDM TLSR82_MUX_SDM
#define MUX_I2S TLSR82_MUX_I2S
#define MUX_ATSEL TLSR82_MUX_ATSEL
#define MUX_SWS TLSR82_MUX_SWS
#define MUX_AMP TLSR82_MUX_AMP
#define MUX_USB TLSR82_MUX_USB
#define MUX_ADC TLSR82_MUX_ADC
#define MUX_LPC TLSR82_MUX_LPC
#define MUX_INPUT TLSR82_MUX_INPUT
#define MUX_OUTPUT TLSR82_MUX_OUTPUT
#define I2C_SPI (MUX_I2C | MUX_SPI)
#define UART7816 (MUX_UART | MUX_U7816)
#define ADC_LPC (MUX_ADC | MUX_LPC)
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef CONFIG_TLSR82_GPIO_VALIDATION
const static struct tlsr82_gpio_mux_s gpio_mux_tbl[GPIO_NUM] =
{
{MUX_DMIC, MUX_PWM , MUX_UART , MUX_NONE}, /* -- PA0 */
{MUX_DMIC, MUX_U7816, MUX_I2S , MUX_NONE}, /* PA1 */
{MUX_SPI , MUX_UART , MUX_PWM , MUX_NONE}, /* PA2 */
{I2C_SPI , MUX_UART , MUX_PWM , MUX_NONE}, /* PA3 */
{I2C_SPI , MUX_UART , MUX_PWM , MUX_NONE}, /* PA4 */
{MUX_SWS , MUX_NONE , MUX_NONE , MUX_NONE}, /* PA5 */
{MUX_SWS , MUX_NONE , MUX_NONE , MUX_NONE}, /* PA6 */
{MUX_SWS , MUX_UART , MUX_NONE , MUX_NONE}, /* PA7 */
{MUX_PWM , MUX_UART , MUX_ATSEL, ADC_LPC }, /* -- PB0 */
{MUX_PWM , MUX_UART , MUX_ATSEL, ADC_LPC }, /* PB1 */
{MUX_PWM , MUX_UART , MUX_AMP , ADC_LPC }, /* PB2 */
{MUX_PWM , MUX_UART , MUX_AMP , ADC_LPC }, /* PB3 */
{MUX_SDM , MUX_PWM , MUX_NONE , ADC_LPC }, /* PB4 */
{MUX_SDM , MUX_UART , MUX_NONE , ADC_LPC }, /* PB5 */
{MUX_SDM , I2C_SPI , MUX_UART , ADC_LPC }, /* PB6 */
{MUX_SDM , MUX_SPI , MUX_UART , ADC_LPC }, /* PB7 */
{MUX_I2C , MUX_PWM , MUX_UART , MUX_NONE}, /* -- PC0 */
{MUX_I2C , MUX_PWM , MUX_PWM , MUX_NONE}, /* PC1 */
{MUX_PWM , UART7816 , MUX_I2C , MUX_NONE}, /* PC2 */
{MUX_PWM , MUX_UART , MUX_I2C , MUX_NONE}, /* PC3 */
{MUX_PWM , MUX_UART , MUX_PWM , MUX_ADC }, /* PC4 */
{MUX_PWM , MUX_UART , MUX_ATSEL, MUX_ADC }, /* PC5 */
{MUX_AMP , MUX_ATSEL, MUX_PWM , MUX_NONE}, /* PC6 */
{MUX_AMP , MUX_ATSEL, MUX_PWM , MUX_NONE}, /* PC7 */
{MUX_AMP , MUX_NONE , UART7816 , MUX_NONE}, /* -- PD0 */
{MUX_AMP , MUX_NONE , MUX_UART , MUX_NONE}, /* PD1 */
{MUX_SPI , MUX_I2S , MUX_PWM , MUX_NONE}, /* PD2 */
{MUX_PWM , MUX_I2S , UART7816 , MUX_NONE}, /* PD3 */
{MUX_SWS , MUX_I2S , MUX_PWM , MUX_NONE}, /* PD4 */
{MUX_PWM , MUX_NONE , MUX_PWM , MUX_NONE}, /* PD5 */
{MUX_SPI , MUX_UART , MUX_ATSEL, MUX_NONE}, /* PD6 */
{I2C_SPI , MUX_I2S , UART7816 , MUX_NONE}, /* PD7 */
};
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: tlsr82_gpio_cfg_check
*
* Description:
* Check weather the mux function is supported or not by the input pin.
*
* Input Parameters:
* cfg - the pin config information, include the group and pin num
* information.
* mux - mux function.
*
* Returned Value:
* Zero on success; a negated errno value on failure
*
****************************************************************************/
int tlsr82_gpio_cfg_check(uint32_t cfg, uint32_t mux)
{
#ifdef CONFIG_TLSR82_GPIO_VALIDATION
int muxid;
uint32_t mux3;
uint32_t cfg_af;
uint16_t pinnum;
DEBUGASSERT(GPIO_VALID(cfg));
pinnum = GPIO_PIN2NUM(cfg);
cfg_af = GPIO_GET(AF, cfg);
/* ADC and LPC is not configed by gpio mux register */
if ((mux == MUX_ADC) || (mux == MUX_LPC))
{
mux3 = gpio_mux_tbl[pinnum].muxs[3];
return (mux3 & mux) ? 0 : -1;
}
/* If af is not mux0 ~ mux3, return -2 */
if (cfg_af < GPIO_VAL(AF, MUX0))
{
return -2;
}
/* Get the muxid [0, 3], if mux is not supported by
* this gpio pin, return -1, otherwise return 0.
*/
muxid = cfg_af - GPIO_VAL(AF, MUX0);
if ((gpio_mux_tbl[pinnum].muxs[muxid] & mux) == 0)
{
return -1;
}
#endif
return 0;
}
/****************************************************************************
* Name: tlsr82_gpio_init
*
* Description:
* GPIO config initialization.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void tlsr82_gpio_init(void)
{
/* Group A */
GPIO_SET_PA_IE_REG = GPIO_DEFAULT_IE_GET(A);
GPIO_SET_PA_OEN_REG = GPIO_DEFAULT_OEN_GET(A);
GPIO_SET_PA_OUT_REG = GPIO_DEFAULT_OUT_GET(A);
GPIO_SET_PA_DS_REG = GPIO_DEFAULT_DS_GET(A);
GPIO_SET_PA_ACT_REG = GPIO_DEFAULT_ACT_GET(A);
/* Group B */
GPIO_SET_PB_IE_REG = GPIO_DEFAULT_IE_GET(B);
GPIO_SET_PB_OEN_REG = GPIO_DEFAULT_OEN_GET(B);
GPIO_SET_PB_OUT_REG = GPIO_DEFAULT_OUT_GET(B);
GPIO_SET_PB_DS_REG = GPIO_DEFAULT_DS_GET(B);
GPIO_SET_PB_ACT_REG = GPIO_DEFAULT_ACT_GET(B);
/* Group C */
tlsr82_analog_write(ANALOG_PC_IE_ADDR, GPIO_DEFAULT_IE_GET(C));
GPIO_SET_PC_OEN_REG = GPIO_DEFAULT_OEN_GET(C);
GPIO_SET_PC_OUT_REG = GPIO_DEFAULT_OUT_GET(C);
tlsr82_analog_write(ANALOG_PC_DS_ADDR, GPIO_DEFAULT_DS_GET(C));
GPIO_SET_PC_ACT_REG = GPIO_DEFAULT_ACT_GET(C);
/* Group D */
GPIO_SET_PD_IE_REG = GPIO_DEFAULT_IE_GET(D);
GPIO_SET_PD_OEN_REG = GPIO_DEFAULT_OEN_GET(D);
GPIO_SET_PD_OUT_REG = GPIO_DEFAULT_OUT_GET(D);
GPIO_SET_PD_DS_REG = GPIO_DEFAULT_DS_GET(D);
GPIO_SET_PD_ACT_REG = GPIO_DEFAULT_ACT_GET(D);
/* Group E */
GPIO_SET_PE_IE_REG = GPIO_DEFAULT_IE_GET_E;
GPIO_SET_PE_OEN_REG = GPIO_DEFAULT_OEN_GET_E;
GPIO_SET_PE_OUT_REG = GPIO_DEFAULT_OUT_GET_E;
GPIO_SET_PE_DS_REG = GPIO_DEFAULT_DS_GET_E;
GPIO_SET_PE_ACT_REG = GPIO_DEFAULT_ACT_GET_E;
}
arch/arm/src/tlsr82/tlsr82_gpio_cfg.h
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/****************************************************************************
* arch/arm/src/tlsr82/tlsr82_gpio_cfg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TLSR82_TLSR82_GPIO_CFG_H
#define __ARCH_ARM_SRC_TLSR82_TLSR82_GPIO_CFG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/tlsr82/chip.h>
#include "hardware/tlsr82_gpio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define GPIO_NUM (4 * 8)
#define TLSR82_MUX_NONE (0)
#define TLSR82_MUX_INPUT (1 << 0)
#define TLSR82_MUX_OUTPUT (1 << 1)
#define TLSR82_MUX_UART (1 << 2)
#define TLSR82_MUX_PWM (1 << 3)
#define TLSR82_MUX_DMIC (1 << 4)
#define TLSR82_MUX_I2C (1 << 5)
#define TLSR82_MUX_SPI (1 << 6)
#define TLSR82_MUX_U7816 (1 << 7)
#define TLSR82_MUX_SDM (1 << 8)
#define TLSR82_MUX_I2S (1 << 9)
#define TLSR82_MUX_ATSEL (1 << 10)
#define TLSR82_MUX_SWS (1 << 11)
#define TLSR82_MUX_AMP (1 << 12)
#define TLSR82_MUX_USB (1 << 13)
#define TLSR82_MUX_ADC (1 << 14)
#define TLSR82_MUX_LPC (1 << 15)
/****************************************************************************
* Public Types
****************************************************************************/
struct tlsr82_gpio_mux_s
{
uint32_t muxs[4];
};
struct tlsr82_gpio_cfg_s
{
uint32_t mux;
uint32_t cfg;
};
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: tlsr82_gpio_cfg_check
*
* Description:
* Check weather the mux function is supported or not by the input pin.
*
* Input Parameters:
* cfg - the pin config information, include the group and pin num
* information.
* mux - mux function.
*
* Returned Value:
* Zero on success; a negated errno value on failure
*
****************************************************************************/
int tlsr82_gpio_cfg_check(uint32_t cfg, uint32_t mux);
/****************************************************************************
* Name: tlsr82_gpio_init
*
* Description:
* GPIO config initialization.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void tlsr82_gpio_init(void);
#endif /* __ARCH_ARM_SRC_TLSR82_TLSR82_GPIO_CFG_H */
arch/arm/src/tlsr82/tlsr82_gpio_default.h
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arch/arm/src/tlsr82/tlsr82_irq.c
+76
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/****************************************************************************
* arch/arm/src/tlsr82/tlsr82_irq.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "arm_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/* g_current_regs[] holds a references to the current interrupt level
* register storage structure. If is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void)
{
int i;
/* Disable all the interrupts */
up_irq_disable();
for (i = 0; i < NR_IRQS; i++)
{
up_disable_irq(i);
}
/* currents_regs is non-NULL only while processing an interrupt */
CURRENT_REGS = NULL;
/* And finally, enable interrupts */
up_irq_enable();
}

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