mirror of
https://github.com/apache/nuttx.git
synced 2026-05-25 09:45:55 +08:00
arch/arm/src/tiva/hardware: Add ADI 2 REFSYS header file.
This commit is contained in:
Gregory Nutt
@@ -45,9 +45,12 @@
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#include <nuttx/config.h>
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#include "tiva_chipinfo.h"
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#include "hardware/tiva_vims.h"
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#include "hardware/tiva_ccfg.h"
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#include "hardware/tiva_flash.h"
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#include "hardware/tiva_prcm.h"
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#include "hardware/tiva_vims.h"
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#include "hardware/tiva_ddi0_osc.h"
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#include "hardware/tiva_adi2_refsys.h"
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/******************************************************************************
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* Private Functions
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@@ -196,8 +199,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
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}
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}
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regval8 = (vtrim_udig << ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_SHIFT) |
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(vtrim_bod << ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_SHIFT);
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regval8 = (vtrim_udig << ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_SHIFT) |
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(vtrim_bod << ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD_SHIFT);
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putreg8(regval, TIVA_ADI2_SOCLDOCTL0);
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}
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@@ -45,10 +45,14 @@
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#include <nuttx/config.h>
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#include "tiva_chipinfo.h"
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#include "hardware/tiva_vims.h"
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#include "hardware/tiva_ccfg.h"
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#include "hardware/tiva_flash.h"
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#include "hardware/tiva_prcm.h"
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#include "hardware/tiva_vims.h"
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#include "hardware/tiva_ddi0_osc.h"
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#include "hardware/tiva_aon_pmctl.h"
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#include "hardware/tiva_aon_rtc.h"
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#include "hardware/tiva_adi2_refsys.h"
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/******************************************************************************
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* Pre-processor Definitions
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@@ -98,13 +102,15 @@ static void Step_RCOSCHF_CTRIM(uint32_t toCode)
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uint32_t current_rcoschfctrl;
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uint32_t current_trim;
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current_rcoschfctrl = getreg16(TIVA_AUX_DDI0_OSCRCOSCHFCTL);
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current_rcoschfctrl = getreg16(TIVA_DDI0_OSC_RCOSCMFCTL);
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current_trim =
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(((current_rcoschfctrl & DDI0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_MASK) >>
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DDI0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_SHIFT) ^ 0xc0);
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while (toCode != current_trim)
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{
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uint16_t regval16;
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/* Wait for next edge on SCLK_LF (positive or negative) */
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(void)getreg32(TIVA_AON_RTC_SYNCLF);
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@@ -122,7 +128,7 @@ static void Step_RCOSCHF_CTRIM(uint32_t toCode)
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~DDI0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_MASK) |
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((current_trim ^ 0xc0) <<
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DDI0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_SHIFT);
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putreg16(regval16, TIVA_AUX_DDI0_OSCRCOSCHFCTL);
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putreg16(regval16, TIVA_DDI0_OSC_RCOSCMFCTL);
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}
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}
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@@ -141,8 +147,8 @@ static void Step_VBG(int32_t target_signed)
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{
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/* VBG (ANA_TRIM[5:0]=TRIMTEMP --> ADI_3_REFSYS:REFSYSCTL3.TRIM_VBG) */
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uint32_t ref_sysctl;
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int32_t current_signed;
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uint8_t ref_sysctl;
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do
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{
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@@ -156,7 +162,7 @@ static void Step_VBG(int32_t target_signed)
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/* Wait for next edge on SCLK_LF (positive or negative) */
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HWREG(TIVA_AON_RTC_SYNCLF);
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(void)getreg32(TIVA_AON_RTC_SYNCLF);
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if (target_signed != current_signed)
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{
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@@ -169,16 +175,15 @@ static void Step_VBG(int32_t target_signed)
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current_signed--;
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}
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regval = (ref_sysctl &
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~(ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN |
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ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_MASK)) |
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((((uint32_t)current_signed) <<
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ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT) &
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ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_MASK);
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putreg8((uint8_t)regval, TIVA_ADI3_REFSYS_REFSYSCTL3);
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ref_sysctl &= ~(ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN |
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ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_MASK)) |
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((((uint32_t)current_signed) <<
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ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT) &
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ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_MASK);
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putreg8(ref_sysctl, TIVA_ADI3_REFSYS_REFSYSCTL3);
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regval |= ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
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putreg8((uint8_t)regval, TIVA_ADI3_REFSYS_REFSYSCTL3);
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ref_sysctl |= ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
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putreg8(ref_sysctl, TIVA_ADI3_REFSYS_REFSYSCTL3);
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}
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}
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while (target_signed != current_signed);
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@@ -229,9 +234,9 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
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* OSCHfSourceSwitch().
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*/
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HWREG(TIVA_AUX_DDI0_OSCMASK16B + (DDI0_OSC_CTL0_OFFSET << 1) + 4) =
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DDI0_OSC_CTL0_CLK_DCDC_SRC_SEL_MASK |
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(DDI0_OSC_CTL0_CLK_DCDC_SRC_SEL_MASK >> 16);
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regval = DDI0_OSC_CTL0_CLK_DCDC_SRC_SEL_MASK |
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(DDI0_OSC_CTL0_CLK_DCDC_SRC_SEL_MASK >> 16);
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putreg32(regval, TIVA_AUX_DDI0_OSCMASK16B + (DDI0_OSC_CTL0_OFFSET << 1) + 4);
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/* Dummy read to ensure that the write has propagated */
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@@ -264,6 +269,9 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
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{
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uint32_t fusedata;
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uint32_t org_resetctl;
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uint32_t regval;
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uint16_t regval16;
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uint8_t regval8;
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/* Get VTRIM_COARSE and VTRIM_DIG from EFUSE shadow register
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* OSC_BIAS_LDO_TRIM
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@@ -276,28 +284,28 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
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FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_SHIFT);
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/* Write to register SOCLDO_0_1 (addr offset 3) bits[7:4] (VTRIM_COARSE)
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* and bits[3:0] (VTRIM_DIG) in ADI_2_REFSYS. Direct write can be used
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* and bits[3:0] (VTRIM_DIG) in ADI2_REFSYS. Direct write can be used
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* since all register bit fields are trimmed.
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*/
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regval8 = ((((fusedata & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_MASK) >>
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FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_SHIFT) <<
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ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_SHIFT) |
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ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_SHIFT) |
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(((fusedata & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_MASK) >>
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FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_SHIFT) <<
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ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_SHIFT));
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putreg8(regval8, TIVA_ADI2_DIR + ADI_2_REFSYS_SOCLDOCTL1_OFFSET);
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ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG_SHIFT));
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putreg8(regval8, TIVA_ADI2_DIR + ADI2_REFSYS_SOCLDOCTL1_OFFSET);
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/* Write to register CTLSOCREFSYS0 (addr offset 0) bits[4:0] (TRIMIREF) in
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* ADI_2_REFSYS. Avoid using masked write access since bit field spans
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* ADI2_REFSYS. Avoid using masked write access since bit field spans
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* nibble boundary. Direct write can be used since this is the only defined
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* bit field in this register.
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*/
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regval8 = (((fusedata & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_MASK) >>
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FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_SHIFT) <<
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ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_SHIFT);
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putreg8(regval8, TIVA_ADI2_DIR + ADI_2_REFSYS_REFSYSCTL0_OFFSET);
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ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_SHIFT);
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putreg8(regval8, TIVA_ADI2_DIR + ADI2_REFSYS_REFSYSCTL0_OFFSET);
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/* Write to register CTLSOCREFSYS2 (addr offset 4) bits[7:4] (TRIMMAG) in
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* ADI_3_REFSYS
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@@ -318,14 +326,15 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
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org_resetctl =
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(getreg32(TIVA_AON_PMCTL_RESETCTL) &
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~AON_PMCTL_RESETCTL_MCU_WARM_RESET_MASK);
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HWREG(TIVA_AON_PMCTL_RESETCTL) =
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(org_resetctl &
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~(AON_PMCTL_RESETCTL_CLK_LOSS_EN | AON_PMCTL_RESETCTL_VDD_LOSS_EN |
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AON_PMCTL_RESETCTL_VDDR_LOSS_EN | AON_PMCTL_RESETCTL_VDDS_LOSS_EN));
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regval = (org_resetctl &
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~(AON_PMCTL_RESETCTL_CLK_LOSS_EN | AON_PMCTL_RESETCTL_VDD_LOSS_EN |
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AON_PMCTL_RESETCTL_VDDR_LOSS_EN | AON_PMCTL_RESETCTL_VDDS_LOSS_EN));
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putreg32(regval, TIVA_AON_PMCTL_RESETCTL);
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/* Wait for xxx_LOSS_EN setting to propagate */
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HWREG(TIVA_AON_RTC_SYNC);
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(void)getreg32(TIVA_AON_RTC_SYNC);
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/* The VDDS_BOD trim and the VDDR trim is already stepped up to max/HH if
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* "CC1352 boost mode" is requested. See function
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@@ -389,22 +398,24 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
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/* Wait for next edge on SCLK_LF (positive or negative) */
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HWREG(TIVA_AON_RTC_SYNCLF);
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(void)getreg32(TIVA_AON_RTC_SYNCLF);
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/* Wait for next edge on SCLK_LF (positive or negative) */
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HWREG(TIVA_AON_RTC_SYNCLF);
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(void)getreg32(TIVA_AON_RTC_SYNCLF);
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HWREG(TIVA_AON_PMCTL_RESETCTL) = org_resetctl;
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(void)getreg32(TIVA_AON_PMCTL_RESETCTL) = org_resetctl;
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/* Wait for xxx_LOSS_EN setting to propagate */
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HWREG(TIVA_AON_RTC_SYNC);
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(void)getreg32(TIVA_AON_RTC_SYNC);
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}
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{
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uint32_t trimreg;
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uint32_t trimvalue;
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uint16_t regval16;
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uint8_t regval8;
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/*Propagate the LPM_BIAS trim */
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@@ -45,8 +45,9 @@
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#include <nuttx/config.h>
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#include "tiva_chipinfo.h"
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#include "hardware/tiva_vims.h"
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#include "hardware/tiva_ccfg.h"
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#include "hardware/tiva_flash.h"
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#include "hardware/tiva_vims.h"
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#include "hardware/tiva_ddi0_osc.h"
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#include "hardware/tiva_aon_pmctl.h"
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@@ -188,6 +189,9 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
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/* Set LPM_BIAS_WIDTH_TRIM according to FCFG1 configuration */
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{
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uint32_t trimwidth;
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uint16_t regval16;
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uint32_t trimwidth =
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((trimreg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_MASK) >>
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FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_SHIFT);
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@@ -0,0 +1,194 @@
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/********************************************************************************************************************
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* arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi2_refsys.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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*
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* Technical content derives from a TI header file that has a compatible BSD license:
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*
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* Copyright (c) 2015-2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI2_REFSYS_H
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#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI2_REFSYS_H
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/********************************************************************************************************************
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* Included Files
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********************************************************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/tiva_memorymap.h"
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/********************************************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************************************/
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/* ADI2 REFSYS Register Offsets *************************************************************************************/
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#define TIVA_ADI2_REFSYS_REFSYSCTL0_OFFSET 0x0000
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#define TIVA_ADI2_REFSYS_SOCLDOCTL0_OFFSET 0x0002
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#define TIVA_ADI2_REFSYS_SOCLDOCTL1_OFFSET 0x0003
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#define TIVA_ADI2_REFSYS_SOCLDOCTL2_OFFSET 0x0004
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#define TIVA_ADI2_REFSYS_SOCLDOCTL3_OFFSET 0x0005
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#define TIVA_ADI2_REFSYS_SOCLDOCTL4_OFFSET 0x0006
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#define TIVA_ADI2_REFSYS_SOCLDOCTL5_OFFSET 0x0007
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#define TIVA_ADI2_REFSYS_HPOSCCTL0_OFFSET 0x000a
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#define TIVA_ADI2_REFSYS_HPOSCCTL1_OFFSET 0x000b
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#define TIVA_ADI2_REFSYS_HPOSCCTL2_OFFSET 0x000c
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/* ADI2 REFSYS Register Addresses ***********************************************************************************/
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#define TIVA_ADI2_REFSYS_REFSYSCTL0 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_REFSYSCTL0_OFFSET)
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#define TIVA_ADI2_REFSYS_SOCLDOCTL0 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_SOCLDOCTL0_OFFSET)
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#define TIVA_ADI2_REFSYS_SOCLDOCTL1 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_SOCLDOCTL1_OFFSET)
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#define TIVA_ADI2_REFSYS_SOCLDOCTL2 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_SOCLDOCTL2_OFFSET)
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#define TIVA_ADI2_REFSYS_SOCLDOCTL3 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_SOCLDOCTL3_OFFSET)
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#define TIVA_ADI2_REFSYS_SOCLDOCTL4 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_SOCLDOCTL4_OFFSET)
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#define TIVA_ADI2_REFSYS_SOCLDOCTL5 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_SOCLDOCTL5_OFFSET)
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#define TIVA_ADI2_REFSYS_HPOSCCTL0 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_HPOSCCTL0_OFFSET)
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#define TIVA_ADI2_REFSYS_HPOSCCTL1 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_HPOSCCTL1_OFFSET)
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#define TIVA_ADI2_REFSYS_HPOSCCTL2 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_HPOSCCTL2_OFFSET)
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/* ADI2 REFSYS Bitfield Definitions *********************************************************************************/
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/* ADI2_REFSYS_REFSYSCTL0 */
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#define ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_SHIFT (0) /* Bit 0-4 */
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#define ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_MASK (15 << ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_SHIFT)
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# define ADI2_REFSYS_REFSYSCTL0_TRIM_IREF(n) ((uint32_t)(n) << ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_SHIFT)
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/* ADI2_REFSYS_SOCLDOCTL0 */
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#define ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD_SHIFT (0) /* Bits 0-3 */
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#define ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD_MASK (15 << ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD_SHIFT)
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# define ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD_SHIFT)
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#define ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_SHIFT (4) /* Bits 4-7 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_MASK (15 << ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_SHIFT)
|
||||
|
||||
/* ADI2_REFSYS_SOCLDOCTL1 */
|
||||
|
||||
#define ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG_SHIFT (0) /* Bits 0-3 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG_MASK (15 << ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG_SHIFT)
|
||||
#define ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_SHIFT (4) /* Bit 4-7 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_MASK (15 << ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_SHIFT)
|
||||
|
||||
/* ADI2_REFSYS_SOCLDOCTL2 */
|
||||
|
||||
#define ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_SHIFT (0) /* Bits 0-2 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_MASK (7 << ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_SHIFT)
|
||||
|
||||
/* ADI2_REFSYS_SOCLDOCTL3 */
|
||||
|
||||
#define ADI2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_SHIFT (0) /* Bits 0-2 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_MASK (7 << ADI2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_SHIFT)
|
||||
#define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_SHIFT (3) /* Bits 3-5 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_MASK (7 << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_60P (0 << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_80P (3 << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_100P (5 << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_120P (7 << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_SHIFT)
|
||||
#define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_SHIFT (6) /* Bits 6-7 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_MASK (3 << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_SHIFT)
|
||||
|
||||
/* ADI2_REFSYS_SOCLDOCTL4 */
|
||||
|
||||
#define ADI2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN (1 << 0) /* Bit 0 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL4_BIAS_DIS (1 << 1) /* Bit 1 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_SHIFT (2) /* Bits 2-4 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_MASK (7 << ADI2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_SHIFT)
|
||||
#define ADI2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_SHIFT (5) /* Bits 5-6 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_MASK (3 << ADI2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_SHIFT)
|
||||
|
||||
/* ADI2_REFSYS_SOCLDOCTL5 */
|
||||
|
||||
#define ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT (0) /* Bits 0-2 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL5_TESTSEL_MASK (7 << ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL5_TESTSEL(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL5_TESTSEL_NC (0 << ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL5_TESTSEL_ITEST (1 << ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL5_TESTSEL_VREF_AMP (2 << ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON (4 << ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT)
|
||||
#define ADI2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN (1 << 3) /* Bit 3 */
|
||||
|
||||
/* ADI2_REFSYS_HPOSCCTL0 */
|
||||
|
||||
#define ADI2_REFSYS_HPOSCCTL0_DIV3_BYPASS (1 << 0) /* Bit 0 */
|
||||
# define ADI2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ (0)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_2520MHZ ADI2_REFSYS_HPOSCCTL0_DIV3_BYPASS
|
||||
#define ADI2_REFSYS_HPOSCCTL0_SERIES_CAP_SHIFT (1) /* Bits 1-2 */
|
||||
#define ADI2_REFSYS_HPOSCCTL0_SERIES_CAP_MASK (3 << ADI2_REFSYS_HPOSCCTL0_SERIES_CAP_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_SERIES_CAP(n) ((uint32_t)(n) << ADI2_REFSYS_HPOSCCTL0_SERIES_CAP_SHIFT)
|
||||
#define ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT (3) /* Bits 3-4 */
|
||||
#define ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_MASK (3 << ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_TUNE_CAP(n) ((uint32_t)(n) << ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_0 (0 << ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M35 (1 << ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M70 (2 << ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M108 (3 << ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT)
|
||||
#define ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_SHIFT (5) /* Bits 5-6 */
|
||||
#define ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MASK (3 << ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY(n) ((uint32_t)(n) << ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X1 (0 << ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X2 (1 << ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X4 (2 << ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 (3 << ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_SHIFT)
|
||||
#define ADI2_REFSYS_HPOSCCTL0_FILTER_EN (1 << 7) /* Bit 7 */
|
||||
|
||||
/* ADI2_REFSYS_HPOSCCTL1 */
|
||||
|
||||
#define ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET_SHIFT (0) /* Bits 0-3 */
|
||||
#define ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET_MASK (15 << ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET(n) ((uint32_t)(n) << ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET_SHIFT)
|
||||
#define ADI2_REFSYS_HPOSCCTL1_PWRDET_EN (1 << 4) /* Bit 4 */
|
||||
#define ADI2_REFSYS_HPOSCCTL1_BIAS_DIS (1 << 5) /* Bit 5 */
|
||||
|
||||
/* ADI2_REFSYS_HPOSCCTL2 */
|
||||
|
||||
#define ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_SHIFT (0) /* Bits 0-3 */
|
||||
#define ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_MASK (15 << ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO(n) ((uint32_t)(n) << ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_SHIFT)
|
||||
#define ADI2_REFSYS_HPOSCCTL2_ATEST_SEL_SHIFT (4) /* Bits 4-5 */
|
||||
#define ADI2_REFSYS_HPOSCCTL2_ATEST_SEL_MASK (3 << ADI2_REFSYS_HPOSCCTL2_ATEST_SEL_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL2_ATEST_SEL(n) ((uint32_t)(n) << ADI2_REFSYS_HPOSCCTL2_ATEST_SEL_SHIFT)
|
||||
#define ADI2_REFSYS_HPOSCCTL2_TESTMUX_EN (1 << 6) /* Bit 6 */
|
||||
#define ADI2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN (1 << 7) /* Bit 7 */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI2_REFSYS_H */
|
||||
@@ -257,7 +257,7 @@
|
||||
# define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE (0xc5 << CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_SHIFT)
|
||||
#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_SHIFT (16) /* Bits 16-23: Enable CPU DAP */
|
||||
#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_MASK (0xff << CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_SHIFT)
|
||||
# efine CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE (0xc5 << CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_SHIFT)
|
||||
# define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE (0xc5 << CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_SHIFT)
|
||||
|
||||
/* TIVA_CCFG_CCFG_TAP_DAP_1 */
|
||||
|
||||
@@ -374,7 +374,7 @@
|
||||
# define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87 (1 << 23)
|
||||
# define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88 (1 << 24)
|
||||
# define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89 (1 << 25)
|
||||
# define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80 (1 << 26)
|
||||
# define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90 (1 << 26)
|
||||
# define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91 (1 << 27)
|
||||
# define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92 (1 << 28)
|
||||
# define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93 (1 << 29)
|
||||
|
||||
@@ -0,0 +1,194 @@
|
||||
/********************************************************************************************************************
|
||||
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Technical content derives from a TI header file that has a compatible BSD license:
|
||||
*
|
||||
* Copyright (c) 2015-2017, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_ADI2_REFSYS_H
|
||||
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_ADI2_REFSYS_H
|
||||
|
||||
/********************************************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/tiva_memorymap.h"
|
||||
|
||||
/********************************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
********************************************************************************************************************/
|
||||
|
||||
/* ADI2 REFSYS Register Offsets *************************************************************************************/
|
||||
|
||||
#define TIVA_ADI2_REFSYS_REFSYSCTL0_OFFSET 0x0000
|
||||
#define TIVA_ADI2_REFSYS_SOCLDOCTL0_OFFSET 0x0002
|
||||
#define TIVA_ADI2_REFSYS_SOCLDOCTL1_OFFSET 0x0003
|
||||
#define TIVA_ADI2_REFSYS_SOCLDOCTL2_OFFSET 0x0004
|
||||
#define TIVA_ADI2_REFSYS_SOCLDOCTL3_OFFSET 0x0005
|
||||
#define TIVA_ADI2_REFSYS_SOCLDOCTL4_OFFSET 0x0006
|
||||
#define TIVA_ADI2_REFSYS_SOCLDOCTL5_OFFSET 0x0007
|
||||
#define TIVA_ADI2_REFSYS_HPOSCCTL0_OFFSET 0x000a
|
||||
#define TIVA_ADI2_REFSYS_HPOSCCTL1_OFFSET 0x000b
|
||||
#define TIVA_ADI2_REFSYS_HPOSCCTL2_OFFSET 0x000c
|
||||
|
||||
/* ADI2 REFSYS Register Addresses ***********************************************************************************/
|
||||
|
||||
#define TIVA_ADI2_REFSYS_REFSYSCTL0 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_REFSYSCTL0_OFFSET)
|
||||
#define TIVA_ADI2_REFSYS_SOCLDOCTL0 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_SOCLDOCTL0_OFFSET)
|
||||
#define TIVA_ADI2_REFSYS_SOCLDOCTL1 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_SOCLDOCTL1_OFFSET)
|
||||
#define TIVA_ADI2_REFSYS_SOCLDOCTL2 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_SOCLDOCTL2_OFFSET)
|
||||
#define TIVA_ADI2_REFSYS_SOCLDOCTL3 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_SOCLDOCTL3_OFFSET)
|
||||
#define TIVA_ADI2_REFSYS_SOCLDOCTL4 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_SOCLDOCTL4_OFFSET)
|
||||
#define TIVA_ADI2_REFSYS_SOCLDOCTL5 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_SOCLDOCTL5_OFFSET)
|
||||
#define TIVA_ADI2_REFSYS_HPOSCCTL0 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_HPOSCCTL0_OFFSET)
|
||||
#define TIVA_ADI2_REFSYS_HPOSCCTL1 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_HPOSCCTL1_OFFSET)
|
||||
#define TIVA_ADI2_REFSYS_HPOSCCTL2 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_HPOSCCTL2_OFFSET)
|
||||
|
||||
/* ADI2 REFSYS Bitfield Definitions *********************************************************************************/
|
||||
|
||||
/* ADI2_REFSYS_REFSYSCTL0 */
|
||||
|
||||
#define ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_SHIFT (0) /* Bit 0-4 */
|
||||
#define ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_MASK (15 << ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_SHIFT)
|
||||
# define ADI2_REFSYS_REFSYSCTL0_TRIM_IREF(n) ((uint32_t)(n) << ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_SHIFT)
|
||||
|
||||
/* ADI2_REFSYS_SOCLDOCTL0 */
|
||||
|
||||
#define ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD_SHIFT (0) /* Bits 0-3 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD_MASK (15 << ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD_SHIFT)
|
||||
#define ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_SHIFT (4) /* Bits 4-7 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_MASK (15 << ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_SHIFT)
|
||||
|
||||
/* ADI2_REFSYS_SOCLDOCTL1 */
|
||||
|
||||
#define ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG_SHIFT (0) /* Bits 0-3 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG_MASK (15 << ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG_SHIFT)
|
||||
#define ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_SHIFT (4) /* Bit 4-7 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_MASK (15 << ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_SHIFT)
|
||||
|
||||
/* ADI2_REFSYS_SOCLDOCTL2 */
|
||||
|
||||
#define ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_SHIFT (0) /* Bits 0-2 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_MASK (7 << ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_SHIFT)
|
||||
|
||||
/* ADI2_REFSYS_SOCLDOCTL3 */
|
||||
|
||||
#define ADI2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_SHIFT (0) /* Bits 0-2 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_MASK (7 << ADI2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_SHIFT)
|
||||
#define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_SHIFT (3) /* Bits 3-5 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_MASK (7 << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_60P (0 << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_80P (3 << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_100P (5 << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_120P (7 << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_SHIFT)
|
||||
#define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_SHIFT (6) /* Bits 6-7 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_MASK (3 << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_SHIFT)
|
||||
|
||||
/* ADI2_REFSYS_SOCLDOCTL4 */
|
||||
|
||||
#define ADI2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN (1 << 0) /* Bit 0 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL4_BIAS_DIS (1 << 1) /* Bit 1 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_SHIFT (2) /* Bits 2-4 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_MASK (7 << ADI2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_SHIFT)
|
||||
#define ADI2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_SHIFT (5) /* Bits 5-6 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_MASK (3 << ADI2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_SHIFT)
|
||||
|
||||
/* ADI2_REFSYS_SOCLDOCTL5 */
|
||||
|
||||
#define ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT (0) /* Bits 0-2 */
|
||||
#define ADI2_REFSYS_SOCLDOCTL5_TESTSEL_MASK (7 << ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL5_TESTSEL(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL5_TESTSEL_NC (0 << ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL5_TESTSEL_ITEST (1 << ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL5_TESTSEL_VREF_AMP (2 << ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT)
|
||||
# define ADI2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON (4 << ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT)
|
||||
#define ADI2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN (1 << 3) /* Bit 3 */
|
||||
|
||||
/* ADI2_REFSYS_HPOSCCTL0 */
|
||||
|
||||
#define ADI2_REFSYS_HPOSCCTL0_DIV3_BYPASS (1 << 0) /* Bit 0 */
|
||||
# define ADI2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ (0)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_2520MHZ ADI2_REFSYS_HPOSCCTL0_DIV3_BYPASS
|
||||
#define ADI2_REFSYS_HPOSCCTL0_SERIES_CAP_SHIFT (1) /* Bits 1-2 */
|
||||
#define ADI2_REFSYS_HPOSCCTL0_SERIES_CAP_MASK (3 << ADI2_REFSYS_HPOSCCTL0_SERIES_CAP_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_SERIES_CAP(n) ((uint32_t)(n) << ADI2_REFSYS_HPOSCCTL0_SERIES_CAP_SHIFT)
|
||||
#define ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT (3) /* Bits 3-4 */
|
||||
#define ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_MASK (3 << ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_TUNE_CAP(n) ((uint32_t)(n) << ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_0 (0 << ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M35 (1 << ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M70 (2 << ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M108 (3 << ADI2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT)
|
||||
#define ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_SHIFT (5) /* Bits 5-6 */
|
||||
#define ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MASK (3 << ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY(n) ((uint32_t)(n) << ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X1 (0 << ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X2 (1 << ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X4 (2 << ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 (3 << ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_SHIFT)
|
||||
#define ADI2_REFSYS_HPOSCCTL0_FILTER_EN (1 << 7) /* Bit 7 */
|
||||
|
||||
/* ADI2_REFSYS_HPOSCCTL1 */
|
||||
|
||||
#define ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET_SHIFT (0) /* Bits 0-3 */
|
||||
#define ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET_MASK (15 << ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET(n) ((uint32_t)(n) << ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET_SHIFT)
|
||||
#define ADI2_REFSYS_HPOSCCTL1_PWRDET_EN (1 << 4) /* Bit 4 */
|
||||
#define ADI2_REFSYS_HPOSCCTL1_BIAS_DIS (1 << 5) /* Bit 5 */
|
||||
|
||||
/* ADI2_REFSYS_HPOSCCTL2 */
|
||||
|
||||
#define ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_SHIFT (0) /* Bits 0-3 */
|
||||
#define ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_MASK (15 << ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO(n) ((uint32_t)(n) << ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_SHIFT)
|
||||
#define ADI2_REFSYS_HPOSCCTL2_ATEST_SEL_SHIFT (4) /* Bits 4-5 */
|
||||
#define ADI2_REFSYS_HPOSCCTL2_ATEST_SEL_MASK (3 << ADI2_REFSYS_HPOSCCTL2_ATEST_SEL_SHIFT)
|
||||
# define ADI2_REFSYS_HPOSCCTL2_ATEST_SEL(n) ((uint32_t)(n) << ADI2_REFSYS_HPOSCCTL2_ATEST_SEL_SHIFT)
|
||||
#define ADI2_REFSYS_HPOSCCTL2_TESTMUX_EN (1 << 6) /* Bit 6 */
|
||||
#define ADI2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN (1 << 7) /* Bit 7 */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_ADI2_REFSYS_H */
|
||||
@@ -257,7 +257,7 @@
|
||||
# define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE (0xc5 << CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_SHIFT)
|
||||
#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_SHIFT (16) /* Bits 16-23: Enable CPU DAP */
|
||||
#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_MASK (0xff << CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_SHIFT)
|
||||
# efine CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE (0xc5 << CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_SHIFT)
|
||||
# define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE (0xc5 << CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_SHIFT)
|
||||
|
||||
/* TIVA_CCFG_CCFG_TAP_DAP_1 */
|
||||
|
||||
@@ -374,7 +374,7 @@
|
||||
# define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87 (1 << 23)
|
||||
# define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88 (1 << 24)
|
||||
# define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89 (1 << 25)
|
||||
# define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80 (1 << 26)
|
||||
# define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90 (1 << 26)
|
||||
# define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91 (1 << 27)
|
||||
# define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92 (1 << 28)
|
||||
# define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93 (1 << 29)
|
||||
|
||||
@@ -0,0 +1,73 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/tiva/hardware/tiva_adi2_refsys.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADI2_REFSYS_H
|
||||
#define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADI2_REFSYS_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
/* These architectures do not support the ADI2 REFSYS block */
|
||||
#elif defined(CONFIG_ARCH_CHIP_CC13X0)
|
||||
# include "hardware/cc13x0/cc13x0_adi2_refsys.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_CC13X2)
|
||||
# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h"
|
||||
#else
|
||||
# error "Unsupported Tiva/Stellaris/SimpleLink ADI2 REFSYS"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADI2_REFSYS_H */
|
||||
@@ -0,0 +1,73 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/tiva/hardware/tiva_aon_rtc.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_RTC_H
|
||||
#define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_RTC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
/* These architectures do not support the AON RTC block */
|
||||
#elif defined(CONFIG_ARCH_CHIP_CC13X0)
|
||||
# include "hardware/cc13x0/cc13x0_aon_rtc.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_CC13X2)
|
||||
# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_rtc.h"
|
||||
#else
|
||||
# error "Unsupported Tiva/Stellaris/SimpleLink AON RTC"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_RTC_H */
|
||||
@@ -42,15 +42,23 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/* The TM4C129 family has a different FLASH register layout */
|
||||
#if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# include "hardware/tm4c/tm4c_flash.h"
|
||||
|
||||
/* Others (including LM4F and TM4C123) are similar to the LM3S family */
|
||||
/* The TM4C129 family has a different FLASH register layout. Others (including LM4F
|
||||
* and TM4C123) are similar to the LM3S family
|
||||
*/
|
||||
|
||||
# if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# include "hardware/tm4c/tm4c_flash.h"
|
||||
# else
|
||||
# include "hardware/lm/lm3s_flash.h"
|
||||
# endif
|
||||
#elif defined(CONFIG_ARCH_CHIP_CC13X0)
|
||||
# include "hardware/cc13x0/cc13x0_flash.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_CC13X2)
|
||||
# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_flash.h"
|
||||
#else
|
||||
# include "hardware/lm/lm3s_flash.h"
|
||||
# error "Unsupported Tiva/Stellaris FLASH"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_FLASH_H */
|
||||
|
||||
Reference in New Issue
Block a user