mirror of
https://github.com/apache/nuttx.git
synced 2026-05-25 01:39:44 +08:00
Merged in raiden00/nuttx_h7 (pull request #742)
Add basic SPI support for H7 * stm32h7: basic SPI support (nodma, noirq) * nucleo-h743zi: nrf24l01 support * nrf24l01.c: fix compilation errors * stm32h7x3xx_rcc.c: enable SYSCFG clock Approved-by: GregoryN <gnutt@nuttx.org>
This commit is contained in:
Mateusz Szafoni
committed by
GregoryN
GregoryN
parent
ea1689409f
commit
7329c81503
@@ -93,20 +93,60 @@ config STM32H7_HAVE_SPI6
|
||||
# These "hidden" settings are the OR of individual peripheral selections
|
||||
# indicating that the general capability is required.
|
||||
|
||||
config STM32H7_ADC
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32H7_CAN
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32H7_DAC
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32H7_DMA
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32H7_I2C
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32H7_SAI
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32H7_SDMMC
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32H7_SPI
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32H7_TIM
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32H7_USART
|
||||
bool
|
||||
default n
|
||||
|
||||
# These are the peripheral selections proper
|
||||
|
||||
config STM32H7_DMA1
|
||||
bool "DMA1"
|
||||
default n
|
||||
select STM32H7_DMA
|
||||
select ARCH_DMA
|
||||
|
||||
config STM32H7_DMA2
|
||||
bool "DMA2"
|
||||
default n
|
||||
select STM32H7_DMA
|
||||
select ARCH_DMA
|
||||
|
||||
menu "STM32H7 I2C Selection"
|
||||
|
||||
config STM32H7_I2C1
|
||||
@@ -136,39 +176,42 @@ menu "STM32H7 SPI Selection"
|
||||
config STM32H7_SPI1
|
||||
bool "SPI1"
|
||||
default n
|
||||
depends on EXPERIMENTAL
|
||||
select SPI
|
||||
select STM32H7_SPI
|
||||
|
||||
config STM32H7_SPI2
|
||||
bool "SPI2"
|
||||
default n
|
||||
depends on EXPERIMENTAL
|
||||
select SPI
|
||||
select STM32H7_SPI
|
||||
|
||||
config STM32H7_SPI3
|
||||
bool "SPI3"
|
||||
default n
|
||||
depends on EXPERIMENTAL
|
||||
select SPI
|
||||
select STM32H7_SPI
|
||||
|
||||
config STM32H7_SPI4
|
||||
bool "SPI4"
|
||||
default n
|
||||
depends on STM32H7_HAVE_SPI4
|
||||
depends on STM32H7_HAVE_SPI4 && EXPERIMENTAL
|
||||
select SPI
|
||||
select STM32H7_SPI
|
||||
|
||||
config STM32H7_SPI5
|
||||
bool "SPI5"
|
||||
default n
|
||||
depends on STM32H7_HAVE_SPI5
|
||||
depends on STM32H7_HAVE_SPI5 && EXPERIMENTAL
|
||||
select SPI
|
||||
select STM32H7_SPI
|
||||
|
||||
config STM32H7_SPI6
|
||||
bool "SPI6"
|
||||
default n
|
||||
depends on STM32H7_HAVE_SPI6
|
||||
depends on STM32H7_HAVE_SPI6 && EXPERIMENTAL
|
||||
select SPI
|
||||
select STM32H7_SPI
|
||||
|
||||
|
||||
@@ -114,6 +114,14 @@ ifneq ($(CONFIG_SCHED_TICKLESS),y)
|
||||
CHIP_CSRCS += stm32_timerisr.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STM32H7_DMA),y)
|
||||
CHIP_CSRCS += stm32_dma.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STM32H7_I2C),y)
|
||||
CHIP_CSRCS += stm32_i2c.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STM32H7_SPI),y)
|
||||
CHIP_CSRCS += stm32_spi.c
|
||||
endif
|
||||
|
||||
@@ -1079,6 +1079,15 @@
|
||||
|
||||
/* TODO: DMAMUX12 request generator interrupt clear flag register */
|
||||
|
||||
/* DMA Stream mapping.
|
||||
* TODO:
|
||||
*/
|
||||
|
||||
#define STM32_DMA_MAP(d,s,c) ((d) << 7 | (s) << 4 | (c))
|
||||
#define STM32_DMA_CONTROLLER(m) (((m) >> 7) & 1)
|
||||
#define STM32_DMA_STREAM(m) (((m) >> 4) & 7)
|
||||
#define STM32_DMA_CHANNEL(m) ((m) & 15)
|
||||
|
||||
/* DMAMUX1 mapping ****************************************************/
|
||||
|
||||
/* NOTE: DMAMUX1 channels 0 to 7 are connected to DMA1 channels 0 to 7.
|
||||
|
||||
@@ -197,9 +197,184 @@
|
||||
#define SPI_CR2_TSER_SHIFT (16) /* Bits 16-31 */
|
||||
#define SPI_CR2_TSER_MASK (0xff << SPI_CR2_TSER_SHIFT)
|
||||
|
||||
/* TODO: SPI configuration register 1 */
|
||||
/* SPI configuration register 1 */
|
||||
|
||||
/* TODO: SPI configuration register 2 */
|
||||
#define SPI_CFG1_DSIZE_SHIFT (0) /* Bits 0-4: number of bits in at single SPI data frame */
|
||||
#define SPI_CFG1_DSIZE_VAL(n) ((n-1) << SPI_CFG1_DSIZE_SHIFT)
|
||||
#define SPI_CFG1_DSIZE_MASK (0x1f << SPI_CFG1_DSIZE_SHIFT)
|
||||
/* 00000 - 00010 - not used */
|
||||
# define SPI_CFG1_DSIZE_4BIT (3 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_5BIT (4 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_6BIT (5 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_7BIT (6 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_8BIT (7 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_9BIT (8 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_10BIT (9 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_11BIT (10 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_12BIT (11 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_13BIT (12 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_14BIT (13 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_15BIT (14 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_16BIT (15 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_17BIT (16 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_18BIT (17 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_19BIT (18 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_20BIT (19 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_21BIT (20 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_22BIT (21 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_23BIT (22 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_24BIT (23 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_25BIT (24 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_26BIT (25 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_27BIT (26 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_28BIT (27 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_29BIT (28 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_30BIT (29 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_31BIT (30 << SPI_CFG1_DSIZE_SHIFT)
|
||||
# define SPI_CFG1_DSIZE_32BIT (31 << SPI_CFG1_DSIZE_SHIFT)
|
||||
#define SPI_CFG1_FTHLV_SHIFT (5) /* Bits 5-8: FIFO threshold level */
|
||||
#define SPI_CFG1_FTHLV_MASK (0xf << SPI_CFG1_FTHLV_SHIFT)
|
||||
# define SPI_CFG1_FTHLV_1DATA (0 << SPI_CFG1_FTHLV_SHIFT)
|
||||
# define SPI_CFG1_FTHLV_2DATA (1 << SPI_CFG1_FTHLV_SHIFT)
|
||||
# define SPI_CFG1_FTHLV_3DATA (2 << SPI_CFG1_FTHLV_SHIFT)
|
||||
# define SPI_CFG1_FTHLV_4DATA (3 << SPI_CFG1_FTHLV_SHIFT)
|
||||
# define SPI_CFG1_FTHLV_5DATA (4 << SPI_CFG1_FTHLV_SHIFT)
|
||||
# define SPI_CFG1_FTHLV_6DATA (5 << SPI_CFG1_FTHLV_SHIFT)
|
||||
# define SPI_CFG1_FTHLV_7DATA (6 << SPI_CFG1_FTHLV_SHIFT)
|
||||
# define SPI_CFG1_FTHLV_8DATA (7 << SPI_CFG1_FTHLV_SHIFT)
|
||||
# define SPI_CFG1_FTHLV_9DATA (8 << SPI_CFG1_FTHLV_SHIFT)
|
||||
# define SPI_CFG1_FTHLV_10DATA (9 << SPI_CFG1_FTHLV_SHIFT)
|
||||
# define SPI_CFG1_FTHLV_11DATA (10 << SPI_CFG1_FTHLV_SHIFT)
|
||||
# define SPI_CFG1_FTHLV_12DATA (11 << SPI_CFG1_FTHLV_SHIFT)
|
||||
# define SPI_CFG1_FTHLV_13DATA (12 << SPI_CFG1_FTHLV_SHIFT)
|
||||
# define SPI_CFG1_FTHLV_14DATA (13 << SPI_CFG1_FTHLV_SHIFT)
|
||||
# define SPI_CFG1_FTHLV_15DATA (14 << SPI_CFG1_FTHLV_SHIFT)
|
||||
# define SPI_CFG1_FTHLV_16DATA (15 << SPI_CFG1_FTHLV_SHIFT)
|
||||
#define SPI_CFG1_UDRCFG_SHIFT (9) /* Bits 9-10: behavior of slave transmitter at underrun condition */
|
||||
#define SPI_CFG1_UDRCFG_MASK (0x3 << SPI_CFG1_UDRCFG_SHIFT)
|
||||
# define SPI_CFG1_UDRCFG_CONST (0 << SPI_CFG1_UDRCFG_SHIFT)
|
||||
# define SPI_CFG1_UDRCFG_LASTRX (1 << SPI_CFG1_UDRCFG_SHIFT)
|
||||
# define SPI_CFG1_UDRCFG_LASTTX (2 << SPI_CFG1_UDRCFG_SHIFT)
|
||||
/* 11: Reserved */
|
||||
#define SPI_CFG1_UDRDET_SHIFT (11) /* Bits 11-12: detection of underrun condition at slave transmitter */
|
||||
#define SPI_CFG1_UDRDET_MASK (0x3 << SPI_CFG1_UDRDET_SHIFT)
|
||||
# define SPI_CFG1_UDRDET_BEG (0 << SPI_CFG1_UDRDET_SHIFT)
|
||||
# define SPI_CFG1_UDRDET_END (1 << SPI_CFG1_UDRDET_SHIFT)
|
||||
# define SPI_CFG1_UDRDET_SS (2 << SPI_CFG1_UDRDET_SHIFT)
|
||||
/* 11: Reserved */
|
||||
/* Bit 13: Reserved */
|
||||
#define SPI_CFG1_RXDMAEN (1 << 14) /* Bit 14: RX-DMA stream enable */
|
||||
#define SPI_CFG1_TXDMAEN (1 << 15) /* Bit 15: TX-DMA stream enable */
|
||||
#define SPI_CFG1_CRCSIZE_SHIFT (16) /* Bits 16-20: length of CRC frame to be transacted and compared */
|
||||
#define SPI_CFG1_CRCSIZE_VAL(n) ((n-1) << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
#define SPI_CFG1_CRCSIZE_MASK (0x1f << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
/* 00000-00010: Reserved */
|
||||
# define SPI_CFG1_CRCSIZE_4BIT (3 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_5BIT (4 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_6BIT (5 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_7BIT (6 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_8BIT (7 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_9BIT (8 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_10BIT (9 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_11BIT (10 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_12BIT (11 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_13BIT (12 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_14BIT (13 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_15BIT (14 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_16BIT (15 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_17BIT (16 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_18BIT (17 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_19BIT (18 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_20BIT (19 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_21BIT (20 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_22BIT (21 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_23BIT (22 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_24BIT (23 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_25BIT (24 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_26BIT (25 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_27BIT (26 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_28BIT (27 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_29BIT (28 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_30BIT (29 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_31BIT (30 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
# define SPI_CFG1_CRCSIZE_32BIT (31 << SPI_CFG1_CRCSIZE_SHIFT)
|
||||
/* Bit 21: Reserved */
|
||||
#define SPI_CFG1_CRCEN (1 << 22) /* Bit 22: hardware CRC computation enable */
|
||||
/* Bits 23-27: Reserved */
|
||||
#define SPI_CFG1_MBR_SHIFT (28) /* Bits 28-30: master baud rate */
|
||||
#define SPI_CFG1_MBR_MASK (0x7 << SPI_CFG1_MBR_SHIFT)
|
||||
# define SPI_CFG1_MBR_FPCLKd2 (0 << SPI_CFG1_MBR_SHIFT)
|
||||
# define SPI_CFG1_MBR_FPCLKd4 (1 << SPI_CFG1_MBR_SHIFT)
|
||||
# define SPI_CFG1_MBR_FPCLKd8 (2 << SPI_CFG1_MBR_SHIFT)
|
||||
# define SPI_CFG1_MBR_FPCLKd16 (3 << SPI_CFG1_MBR_SHIFT)
|
||||
# define SPI_CFG1_MBR_FPCLKd32 (4 << SPI_CFG1_MBR_SHIFT)
|
||||
# define SPI_CFG1_MBR_FPCLKd64 (5 << SPI_CFG1_MBR_SHIFT)
|
||||
# define SPI_CFG1_MBR_FPCLKd128 (6 << SPI_CFG1_MBR_SHIFT)
|
||||
# define SPI_CFG1_MBR_FPCLKd256 (7 << SPI_CFG1_MBR_SHIFT)
|
||||
/* Bit 31: Reserved */
|
||||
|
||||
/* SPI configuration register 2 */
|
||||
|
||||
#define SPI_CFG2_MSSI_SHIFT (0) /* Bits 0-3:master SS idleness */
|
||||
#define SPI_CFG2_MSSI_MASK (0xf << SPI_CFG2_MSSI_SHIFT)
|
||||
# define SPI_CFG2_MSSI_0CLK (0 << SPI_CFG2_MSSI_SHIFT)
|
||||
# define SPI_CFG2_MSSI_1CLK (1 << SPI_CFG2_MSSI_SHIFT)
|
||||
# define SPI_CFG2_MSSI_2CLK (2 << SPI_CFG2_MSSI_SHIFT)
|
||||
# define SPI_CFG2_MSSI_3CLK (3 << SPI_CFG2_MSSI_SHIFT)
|
||||
# define SPI_CFG2_MSSI_4CLK (4 << SPI_CFG2_MSSI_SHIFT)
|
||||
# define SPI_CFG2_MSSI_5CLK (5 << SPI_CFG2_MSSI_SHIFT)
|
||||
# define SPI_CFG2_MSSI_6CLK (6 << SPI_CFG2_MSSI_SHIFT)
|
||||
# define SPI_CFG2_MSSI_7CLK (7 << SPI_CFG2_MSSI_SHIFT)
|
||||
# define SPI_CFG2_MSSI_8CLK (8 << SPI_CFG2_MSSI_SHIFT)
|
||||
# define SPI_CFG2_MSSI_9CLK (9 << SPI_CFG2_MSSI_SHIFT)
|
||||
# define SPI_CFG2_MSSI_10CLK (10 << SPI_CFG2_MSSI_SHIFT)
|
||||
# define SPI_CFG2_MSSI_11CLK (11 << SPI_CFG2_MSSI_SHIFT)
|
||||
# define SPI_CFG2_MSSI_12CLK (12 << SPI_CFG2_MSSI_SHIFT)
|
||||
# define SPI_CFG2_MSSI_13CLK (13 << SPI_CFG2_MSSI_SHIFT)
|
||||
# define SPI_CFG2_MSSI_14CLK (14 << SPI_CFG2_MSSI_SHIFT)
|
||||
# define SPI_CFG2_MSSI_15CLK (15 << SPI_CFG2_MSSI_SHIFT)
|
||||
#define SPI_CFG2_MIDI_SHIFT (0) /* Bits 4-7: master Inter-Data idleness */
|
||||
#define SPI_CFG2_MIDI_MASK (0xf << SPI_CFG2_MIDI_SHIFT)
|
||||
# define SPI_CFG2_MIDI_0CLK (0 << SPI_CFG2_MIDI_SHIFT)
|
||||
# define SPI_CFG2_MIDI_1CLK (1 << SPI_CFG2_MIDI_SHIFT)
|
||||
# define SPI_CFG2_MIDI_2CLK (2 << SPI_CFG2_MIDI_SHIFT)
|
||||
# define SPI_CFG2_MIDI_3CLK (3 << SPI_CFG2_MIDI_SHIFT)
|
||||
# define SPI_CFG2_MIDI_4CLK (4 << SPI_CFG2_MIDI_SHIFT)
|
||||
# define SPI_CFG2_MIDI_5CLK (5 << SPI_CFG2_MIDI_SHIFT)
|
||||
# define SPI_CFG2_MIDI_6CLK (6 << SPI_CFG2_MIDI_SHIFT)
|
||||
# define SPI_CFG2_MIDI_7CLK (7 << SPI_CFG2_MIDI_SHIFT)
|
||||
# define SPI_CFG2_MIDI_8CLK (8 << SPI_CFG2_MIDI_SHIFT)
|
||||
# define SPI_CFG2_MIDI_9CLK (9 << SPI_CFG2_MIDI_SHIFT)
|
||||
# define SPI_CFG2_MIDI_10CLK (10 << SPI_CFG2_MIDI_SHIFT)
|
||||
# define SPI_CFG2_MIDI_11CLK (11 << SPI_CFG2_MIDI_SHIFT)
|
||||
# define SPI_CFG2_MIDI_12CLK (12 << SPI_CFG2_MIDI_SHIFT)
|
||||
# define SPI_CFG2_MIDI_13CLK (13 << SPI_CFG2_MIDI_SHIFT)
|
||||
# define SPI_CFG2_MIDI_14CLK (14 << SPI_CFG2_MIDI_SHIFT)
|
||||
# define SPI_CFG2_MIDI_15CLK (15 << SPI_CFG2_MIDI_SHIFT)
|
||||
/* Bits 8-14: Reserved */
|
||||
#define SPI_CFG2_IOSWP (1 << 15) /* Bit 15: swap functionality of MISO and MOSI pins */
|
||||
/* Bit 16: Reserved */
|
||||
#define SPI_CFG2_COMM_SHIFT (17) /* Bits 17-18: SPI communication mode */
|
||||
#define SPI_CFG2_COMM_MASK (0x3 << SPI_CFG2_COMM_SHIFT)
|
||||
# define SPI_CFG2_COMM_FULL (0 << SPI_CFG2_COMM_SHIFT)
|
||||
# define SPI_CFG2_COMM_STX (1 << SPI_CFG2_COMM_SHIFT)
|
||||
# define SPI_CFG2_COMM_SRX (2 << SPI_CFG2_COMM_SHIFT)
|
||||
# define SPI_CFG2_COMM_HALF (3 << SPI_CFG2_COMM_SHIFT)
|
||||
#define SPI_CFG2_SP_SHIFT (19) /* Bits 19-21: serial protocol */
|
||||
#define SPI_CFG2_SP_MASK (0x7 << SPI_CFG2_SP_SHIFT)
|
||||
# define SPI_CFG2_SP_MOTOROLA (0 << SPI_CFG2_SP_SHIFT)
|
||||
# define SPI_CFG2_SP_TI (1 << SPI_CFG2_SP_SHIFT)
|
||||
/* 010-111: Reserved */
|
||||
#define SPI_CFG2_MASTER (1 << 22) /* Bit 22: SPI master */
|
||||
#define SPI_CFG2_LSBFRST (1 << 23) /* Bit 23: data frame format */
|
||||
#define SPI_CFG2_CPHA (1 << 24) /* Bit 24: clock phase */
|
||||
#define SPI_CFG2_CPOL (1 << 25) /* Bit 25: clock polarity */
|
||||
#define SPI_CFG2_SSM (1 << 26) /* Bit 26: software management of SS signal input */
|
||||
/* Bit 27: Reserved */
|
||||
#define SPI_CFG2_SSIOP (1 << 28) /* Bit 28: SS input/output polarity */
|
||||
#define SPI_CFG2_SSOE (1 << 29) /* Bit 29: SS output enable */
|
||||
#define SPI_CFG2_SSOM (1 << 30) /* Bit 30: SS output management in master mode */
|
||||
#define SPI_CFG2_AFCNTR (1 << 31) /* Bit 31: alternate function GPIOs control */
|
||||
|
||||
/* SPI/I2S status register */
|
||||
|
||||
|
||||
@@ -56,6 +56,7 @@
|
||||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32_i2c.h"
|
||||
#include "stm32_spi.h"
|
||||
#include "stm32_rcc.h"
|
||||
#include "stm32_lowputc.h"
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,208 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32h7/stm32_spi.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Modified for STM32H7 by Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H7_STM32_SPI_H
|
||||
#define __ARCH_ARM_SRC_STM32H7_STM32_SPI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/stm32_spi.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
struct spi_dev_s; /* Forward reference */
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_spibus_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected SPI bus
|
||||
*
|
||||
* Input Parameters:
|
||||
* bus number (for hardware that has mutiple SPI interfaces)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid SPI device structure reference on succcess; a NULL on failure
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
FAR struct spi_dev_s *stm32_spibus_initialize(int bus);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_spi1/2/...select and stm32_spi1/2/...status
|
||||
*
|
||||
* Description:
|
||||
* The external functions, stm32_spi1/2/...select, stm32_spi1/2/...status, and
|
||||
* stm32_spi1/2/...cmddata must be provided by board-specific logic. These are
|
||||
* implementations of the select, status, and cmddata methods of the SPI interface
|
||||
* defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods
|
||||
* (including stm32_spibus_initialize()) are provided by common STM32 logic. To use this
|
||||
* common SPI logic on your board:
|
||||
*
|
||||
* 1. Provide logic in stm32_boardinitialize() to configure SPI chip select
|
||||
* pins.
|
||||
* 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() functions in your
|
||||
* board-specific logic. These functions will perform chip selection and
|
||||
* status operations using GPIOs in the way your board is configured.
|
||||
* 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, then
|
||||
* provide stm32_spi1/2/...cmddata() functions in your board-specific logic.
|
||||
* These functions will perform cmd/data selection operations using GPIOs in the
|
||||
* way your board is configured.
|
||||
* 4. Add a calls to stm32_spibus_initialize() in your low level application
|
||||
* initialization logic
|
||||
* 5. The handle returned by stm32_spibus_initialize() may then be used to bind the
|
||||
* SPI driver to higher level logic (e.g., calling
|
||||
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
|
||||
* the SPI MMC/SD driver).
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI1
|
||||
void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
|
||||
uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid);
|
||||
int stm32_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI2
|
||||
void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
|
||||
uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid);
|
||||
int stm32_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI3
|
||||
void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
|
||||
uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid);
|
||||
int stm32_spi3cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI4
|
||||
void stm32_spi4select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
|
||||
uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, uint32_t devid);
|
||||
int stm32_spi4cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI5
|
||||
void stm32_spi5select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
|
||||
uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, uint32_t devid);
|
||||
int stm32_spi5cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI6
|
||||
void stm32_spi6select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
|
||||
uint8_t stm32_spi6status(FAR struct spi_dev_s *dev, uint32_t devid);
|
||||
int stm32_spi6cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_spi1/2/...register
|
||||
*
|
||||
* Description:
|
||||
* If the board supports a card detect callback to inform the SPI-based MMC/SD
|
||||
* driver when an SD card is inserted or removed, then CONFIG_SPI_CALLBACK should
|
||||
* be defined and the following function(s) must be implemented. These functions
|
||||
* implements the registercallback method of the SPI interface (see
|
||||
* include/nuttx/spi/spi.h for details)
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* callback - The function to call on the media change
|
||||
* arg - A caller provided value to return with the callback
|
||||
*
|
||||
* Returned Value:
|
||||
* 0 on success; negated errno on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SPI_CALLBACK
|
||||
#ifdef CONFIG_STM32H7_SPI1
|
||||
int stm32_spi1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI2
|
||||
int stm32_spi2register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI3
|
||||
int stm32_spi3register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI4
|
||||
int stm32_spi4register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI5
|
||||
int stm32_spi5register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI6
|
||||
int stm32_spi6register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_SPI_H */
|
||||
@@ -289,7 +289,6 @@ static inline void rcc_enableapb1(void)
|
||||
|
||||
regval = getreg32(STM32_RCC_APB1LENR);
|
||||
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI2
|
||||
/* SPI2 clock enable */
|
||||
|
||||
@@ -413,6 +412,10 @@ static inline void rcc_enableapb4(void)
|
||||
|
||||
regval = getreg32(STM32_RCC_APB4ENR);
|
||||
|
||||
/* System configuration controller clock enable */
|
||||
|
||||
regval |= RCC_APB4ENR_SYSCFGEN;
|
||||
|
||||
#ifdef CONFIG_STM32H7_I2C4
|
||||
/* I2C4 clock enable */
|
||||
|
||||
@@ -562,6 +565,8 @@ static void stm32_stdclockconfig(void)
|
||||
#endif
|
||||
putreg32(regval, STM32_RCC_PLLCKSELR);
|
||||
|
||||
/* Each PLL offers 3 outputs with post-dividers (PLLxP/PLLxQ/PLLxR) */
|
||||
|
||||
/* Configure PLL1 dividers */
|
||||
|
||||
regval = (STM32_PLLCFG_PLL1N |
|
||||
@@ -625,7 +630,7 @@ static void stm32_stdclockconfig(void)
|
||||
|
||||
putreg32(regval, STM32_FLASH_ACR);
|
||||
|
||||
/* Select the PLL1 as system clock source */
|
||||
/* Select the PLL1P as system clock source */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_SW_MASK;
|
||||
|
||||
@@ -100,12 +100,6 @@
|
||||
* PLLP1 = {2, 4, 6, 8, ..., 128}
|
||||
* PLLP2,3 = {2, 3, 4, ..., 128}
|
||||
* CPUCLK <= 400 MHz
|
||||
*
|
||||
*/
|
||||
|
||||
/* PLL1_VCO = (8,000,000 / 2) * 200 = 800 MHz
|
||||
* SYSCLK = 800 MHz / 2 = 400 MHz
|
||||
* CPUCLK = 800 MHz / 1 = 400 MHz
|
||||
*/
|
||||
|
||||
#define STM32_BOARD_USEHSE
|
||||
@@ -113,85 +107,122 @@
|
||||
|
||||
#define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE
|
||||
|
||||
/* Wide PLL1, 4 - 8 MHz input, enable DIVP */
|
||||
/* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR
|
||||
*
|
||||
* PLL1_VCO = (8,000,000 / 2) * 200 = 800 MHz
|
||||
*
|
||||
* PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz
|
||||
* PLL1Q = PLL1_VCO/4 = 800 MHz / 4 = 200 MHz
|
||||
* PLL1R = PLL1_VCO/8 = 800 MHz / 8 = 100 MHz
|
||||
*/
|
||||
|
||||
#define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \
|
||||
RCC_PLLCFGR_PLL1RGE_4_8_MHZ | \
|
||||
RCC_PLLCFGR_DIVP1EN)
|
||||
RCC_PLLCFGR_DIVP1EN | \
|
||||
RCC_PLLCFGR_DIVQ1EN | \
|
||||
RCC_PLLCFGR_DIVR1EN)
|
||||
#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(2)
|
||||
#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(200)
|
||||
#define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2)
|
||||
#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4)
|
||||
#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(8)
|
||||
|
||||
#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 200)
|
||||
#define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2)
|
||||
#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4)
|
||||
#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 8)
|
||||
|
||||
/* PLL2 */
|
||||
|
||||
#define STM32_PLLCFG_PLL2CFG 0
|
||||
#define STM32_PLLCFG_PLL2M 0
|
||||
#define STM32_PLLCFG_PLL2N 0
|
||||
#define STM32_PLLCFG_PLL2P 0
|
||||
#define STM32_PLLCFG_PLL2Q 0
|
||||
#define STM32_PLLCFG_PLL2R 0
|
||||
#define STM32_PLLCFG_PLL2M 0
|
||||
#define STM32_PLLCFG_PLL2N 0
|
||||
#define STM32_PLLCFG_PLL2P 0
|
||||
#define STM32_PLLCFG_PLL2Q 0
|
||||
#define STM32_PLLCFG_PLL2R 0
|
||||
|
||||
#define STM32_VCO2_FREQUENCY
|
||||
#define STM32_PLL2P_FREQUENCY
|
||||
#define STM32_PLL2Q_FREQUENCY
|
||||
#define STM32_PLL2R_FREQUENCY
|
||||
|
||||
/* PLL3 */
|
||||
|
||||
#define STM32_PLLCFG_PLL3CFG 0
|
||||
#define STM32_PLLCFG_PLL3M 0
|
||||
#define STM32_PLLCFG_PLL3N 0
|
||||
#define STM32_PLLCFG_PLL3P 0
|
||||
#define STM32_PLLCFG_PLL3Q 0
|
||||
#define STM32_PLLCFG_PLL3R 0
|
||||
#define STM32_PLLCFG_PLL3M 0
|
||||
#define STM32_PLLCFG_PLL3N 0
|
||||
#define STM32_PLLCFG_PLL3P 0
|
||||
#define STM32_PLLCFG_PLL3Q 0
|
||||
#define STM32_PLLCFG_PLL3R 0
|
||||
|
||||
#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 4) * 200)
|
||||
#define STM32_SYSCLK_FREQUENCY (STM32_VCO1_FREQUENCY / 1)
|
||||
#define STM32_VCO3_FREQUENCY
|
||||
#define STM32_PLL3P_FREQUENCY
|
||||
#define STM32_PLL3Q_FREQUENCY
|
||||
#define STM32_PLL3R_FREQUENCY
|
||||
|
||||
/*
|
||||
* SYSCLK = PLL1P = 400 MHz
|
||||
* CPUCLK = SYSCLK / 1 = 400 MHz
|
||||
*/
|
||||
|
||||
#define STM32_SYSCLK_FREQUENCY (STM32_PLL1P_FREQUENCY)
|
||||
#define STM32_CPUCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 1)
|
||||
|
||||
/* Configure Clock Assignments */
|
||||
|
||||
// TODO ....
|
||||
|
||||
/* Several prescalers allow the configuration of the two AHB buses, the
|
||||
* high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
|
||||
* frequency of the two AHB buses is 216 MHz while the maximum frequency of
|
||||
* the high-speed APB domains is 108 MHz. The maximum allowed frequency of
|
||||
* the low-speed APB domain is 54 MHz.
|
||||
/* AHB clock (HCLK) is SYSCLK/2 (200 MHz max)
|
||||
* HCLK1 = HCLK2 = HCLK3 = HCLK4
|
||||
*/
|
||||
|
||||
/* AHB3 clock is SYSCLK (216 MHz) */
|
||||
|
||||
#define STM32_RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_SYSCLKd2 /* HCLK = SYSCLK / 2 */
|
||||
#define STM32_ACLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* ACLK in D1, HCLK3 in D1 */
|
||||
#define STM32_HCLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* HCLK in D2, HCLK4 in D3 */
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
|
||||
|
||||
/* APB3 clock (PCLK1) is HCLK/4 (54 MHz) */
|
||||
|
||||
#define STM32_RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_HCLKd4 /* PCLK1 = HCLK / 4 */
|
||||
#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY/4)
|
||||
|
||||
/* APB1 clock is HCLK/4 (54 MHz) */
|
||||
/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
|
||||
|
||||
#define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
|
||||
|
||||
/* APB2 clock is HCLK/4 (54 MHz) */
|
||||
/* APB2 clock (PCLK2) is HCLK/4 (54 MHz) */
|
||||
|
||||
#define STM32_RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_HCLKd4 /* PCLK1 = HCLK / 4 */
|
||||
#define STM32_RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_HCLKd4 /* PCLK2 = HCLK / 4 */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/4)
|
||||
|
||||
/* APB4 clock is HCLK/4 (54 MHz) */
|
||||
/* APB3 clock (PCLK3) is HCLK/4 (54 MHz) */
|
||||
|
||||
#define STM32_RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_HCLKd4 /* PCLK1 = HCLK / 4 */
|
||||
#define STM32_RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_HCLKd4 /* PCLK3 = HCLK / 4 */
|
||||
#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY/4)
|
||||
|
||||
/* APB4 clock (PCLK4) is HCLK/4 (54 MHz) */
|
||||
|
||||
#define STM32_RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_HCLKd4 /* PCLK4 = HCLK / 4 */
|
||||
#define STM32_PCLK4_FREQUENCY (STM32_HCLK_FREQUENCY/4)
|
||||
|
||||
/* Kernel Clock Configuration
|
||||
*
|
||||
* Note: look at Table 54 in ST Manual
|
||||
*/
|
||||
|
||||
/* I2C123 clock source */
|
||||
/* I2C123 clock source - HSI */
|
||||
|
||||
#define STM32_RCC_D2CCIP2R_I2C123SRC RCC_D2CCIP2R_I2C123SEL_HSI
|
||||
|
||||
/* I2C4 clock source */
|
||||
/* I2C4 clock source - HSI */
|
||||
|
||||
#define STM32_RCC_D2CCIP3R_I2C4SRC RCC_D2CCIP3R_I2C4SEL_HSI
|
||||
#define STM32_RCC_D2CCIP3R_I2C4SRC RCC_D2CCIP3R_I2C4SEL_HSI
|
||||
|
||||
/* SPI123 clock source - PLL1 */
|
||||
|
||||
#define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL1
|
||||
|
||||
/* SPI45 clock source - APB (PCLK2?) */
|
||||
|
||||
#define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_APB
|
||||
|
||||
/* SPI6 clock source - APB (PCLK4) */
|
||||
|
||||
#define STM32_RCC_D3CCIP1R_SPI6SRC RCC_D3CCIP1R_SPI6SEL_PCLK4
|
||||
|
||||
/* FLASH wait states
|
||||
*
|
||||
@@ -291,7 +322,12 @@
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 /* PB8 */
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 /* PB9 */
|
||||
|
||||
/* */
|
||||
/* SPI3 */
|
||||
|
||||
#define GPIO_SPI3_MISO GPIO_SPI3_MISO_1 /* PB4 */
|
||||
#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_4 /* PB5 */
|
||||
#define GPIO_SPI3_SCK GPIO_SPI3_SCK_1 /* PB3 */
|
||||
#define GPIO_SPI3_NSS GPIO_SPI3_NSS_2 /* PA4 */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
|
||||
@@ -64,4 +64,8 @@ ifeq ($(CONFIG_LIB_BOARDCTL),y)
|
||||
CSRCS += stm32_appinitialize.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_WL_NRF24L01),y)
|
||||
CSRCS += stm32_nrf24l01.c
|
||||
endif
|
||||
|
||||
include $(TOPDIR)/configs/Board.mk
|
||||
|
||||
@@ -88,6 +88,18 @@
|
||||
#define GPIO_LSM6DSL_INT1 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN4)
|
||||
#define GPIO_LSM6DSL_INT2 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN5)
|
||||
|
||||
/* NRF24L01
|
||||
* CS - PA4
|
||||
* CE - PF12 (D8)
|
||||
* IRQ - PD15 (D9)
|
||||
*/
|
||||
|
||||
#define GPIO_NRF24L01_CS (GPIO_OUTPUT | GPIO_SPEED_50MHz| \
|
||||
GPIO_OUTPUT_SET | GPIO_PORTA | GPIO_PIN4)
|
||||
#define GPIO_NRF24L01_CE (GPIO_OUTPUT | GPIO_SPEED_50MHz| \
|
||||
GPIO_OUTPUT_CLEAR | GPIO_PORTF | GPIO_PIN12)
|
||||
#define GPIO_NRF24L01_IRQ (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTD | GPIO_PIN15)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
@@ -157,4 +169,15 @@ int stm32_lsm6dsl_initialize(char *devpath);
|
||||
int stm32_lsm303agr_initialize(char *devpath);
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: stm32_wlinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize NRF24L01 wireless interaface.
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_WL_NRF24L01
|
||||
int stm32_wlinitialize(void);
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIGS_NUCLEO_H743ZI_SRC_NUCLEO_H743ZI_H */
|
||||
|
||||
@@ -70,7 +70,7 @@
|
||||
|
||||
int stm32_bringup(void)
|
||||
{
|
||||
int ret;
|
||||
int ret = OK;
|
||||
|
||||
UNUSED(ret);
|
||||
|
||||
@@ -130,5 +130,13 @@ int stm32_bringup(void)
|
||||
}
|
||||
#endif /* CONFIG_SENSORS_LSM303AGR */
|
||||
|
||||
#ifdef CONFIG_WL_NRF24L01
|
||||
ret = stm32_wlinitialize();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", ret);
|
||||
}
|
||||
#endif /* CONFIG_WL_NRF24L01 */
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,136 @@
|
||||
/************************************************************************************
|
||||
* configs/nucleo-h743zi/src/stm32_nrf24l01.c
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <nuttx/wireless/nrf24l01.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "chip.h"
|
||||
#include "stm32.h"
|
||||
#include "nucleo-h743zi.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#define NRF24L01_SPI 3
|
||||
|
||||
/************************************************************************************
|
||||
* Private Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
static int nrf24l01_irq_attach(xcpt_t isr, FAR void *arg);
|
||||
static void nrf24l01_chip_enable(bool enable);
|
||||
|
||||
/************************************************************************************
|
||||
* Private Data
|
||||
************************************************************************************/
|
||||
|
||||
static struct nrf24l01_config_s nrf_cfg =
|
||||
{
|
||||
.irqattach = nrf24l01_irq_attach,
|
||||
.chipenable = nrf24l01_chip_enable,
|
||||
};
|
||||
|
||||
static xcpt_t g_isr;
|
||||
static FAR void *g_arg;
|
||||
|
||||
/************************************************************************************
|
||||
* Private Functions
|
||||
************************************************************************************/
|
||||
|
||||
static int nrf24l01_irq_attach(xcpt_t isr, FAR void *arg)
|
||||
{
|
||||
wlinfo("Attach IRQ\n");
|
||||
g_isr = isr;
|
||||
g_arg = arg;
|
||||
(void)stm32_gpiosetevent(GPIO_NRF24L01_IRQ, false, true, false, g_isr, g_arg);
|
||||
return OK;
|
||||
}
|
||||
|
||||
static void nrf24l01_chip_enable(bool enable)
|
||||
{
|
||||
wlinfo("CE:%d\n", enable);
|
||||
stm32_gpiowrite(GPIO_NRF24L01_CE, enable);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
int stm32_wlinitialize(void)
|
||||
{
|
||||
FAR struct spi_dev_s *spidev;
|
||||
int ret = OK;
|
||||
|
||||
syslog(LOG_INFO, "Register the nRF24L01 module\n");
|
||||
|
||||
/* Setup CE & IRQ line IOs */
|
||||
|
||||
stm32_configgpio(GPIO_NRF24L01_CE);
|
||||
stm32_configgpio(GPIO_NRF24L01_IRQ);
|
||||
|
||||
/* Init SPI bus */
|
||||
|
||||
spidev = stm32_spibus_initialize(NRF24L01_SPI);
|
||||
if (!spidev)
|
||||
{
|
||||
wlerr("ERROR: Failed to initialize SPI %d bus\n", NRF24L01_SPI);
|
||||
ret = -ENODEV;
|
||||
goto errout;
|
||||
}
|
||||
|
||||
ret = nrf24l01_register(spidev, &nrf_cfg);
|
||||
if (ret != OK)
|
||||
{
|
||||
wlerr("ERROR: Failed to register initialize SPI bus\n");
|
||||
goto errout;
|
||||
}
|
||||
|
||||
errout:
|
||||
return ret;
|
||||
}
|
||||
@@ -70,7 +70,20 @@
|
||||
|
||||
void stm32_spidev_initialize(void)
|
||||
{
|
||||
/* Configure SPI CS GPIO for output */
|
||||
/* NOTE: Clocking for SPI1 and/or SPI3 was already provided in stm32_rcc.c.
|
||||
* Configurations of SPI pins is performed in stm32_spi.c.
|
||||
* Here, we only initialize chip select pins unique to the board
|
||||
* architecture.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI3
|
||||
# ifdef CONFIG_WL_NRF24L01
|
||||
/* Configure the SPI-based NRF24L01 chip select GPIO */
|
||||
spiinfo("Configure GPIO for SPI3/CS\n");
|
||||
stm32_configgpio(GPIO_NRF24L01_CS);
|
||||
stm32_gpiowrite(GPIO_NRF24L01_CS, true);
|
||||
# endif
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -127,13 +140,36 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
#ifdef CONFIG_STM32H7_SPI3
|
||||
void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
|
||||
{
|
||||
spiinfo("devid: %08lx CS: %s\n",
|
||||
(unsigned long)devid, selected ? "assert" : "de-assert");
|
||||
switch (devid)
|
||||
{
|
||||
#ifdef CONFIG_WL_NRF24L01
|
||||
case SPIDEV_WIRELESS(0):
|
||||
spiinfo("nRF24L01 device %s\n", selected ? "asserted" : "de-asserted");
|
||||
|
||||
/* Set the GPIO low to select and high to de-select */
|
||||
|
||||
stm32_gpiowrite(GPIO_NRF24L01_CS, !selected);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
{
|
||||
return 0;
|
||||
uint8_t status = 0;
|
||||
switch (devid)
|
||||
{
|
||||
#ifdef CONFIG_WL_NRF24L01
|
||||
case SPIDEV_WIRELESS(0):
|
||||
status |= SPI_STATUS_PRESENT;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@@ -223,7 +223,7 @@ static void nrf24l01_worker(FAR void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DEBUG_WIRELESS
|
||||
static void binarycvt(char *deststr, const uint8_t *srcbin, size_t srclen)
|
||||
static void binarycvt(char *deststr, const uint8_t *srcbin, size_t srclen);
|
||||
#endif
|
||||
|
||||
/* POSIX API */
|
||||
@@ -759,7 +759,7 @@ static void nrf24l01_worker(FAR void *arg)
|
||||
}
|
||||
else
|
||||
{
|
||||
wlerr("invalid length in rx: %d\n", (int)pktlen);
|
||||
/* wlerr("invalid length in rx: %d\n", (int)pktlen); */
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user