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coresight: add etm3 device support

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Signed-off-by: liaoao <liaoao@xiaomi.com>
This commit is contained in:
liaoao
2023-09-15 21:33:00 +08:00
committed by Xiang Xiao
parent e3e23f7eaf
commit 71e4267a7a
10 changed files with 914 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/coresight/CMakeLists.txt
+4
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@@ -21,6 +21,10 @@
if(CONFIG_CORESIGHT)
set(SRCS coresight_core.c coresight_common.c)
if(CONFIG_CORESIGHT_ETM_VERSION STREQUAL "v3")
list(APPEND SRCS coresight_etm3.c)
endif()
if(CONFIG_CORESIGHT_FUNNEL)
list(APPEND SRCS coresight_funnel.c)
endif()
drivers/coresight/Kconfig
+16
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@@ -19,6 +19,22 @@ config CORESIGHT_TIMEOUT
int "Timeout us for waiting register state change"
default 100
config CORESIGHT_ETM
bool "ETM coresight device support"
default n
if CORESIGHT_ETM
config CORESIGHT_ETM_VERSION
string "Coresight ETM version"
default "v3"
config CORESIGHT_ETM_USE_COPROCESSOR
bool "Whether use coprocessor to access ETM registers"
default n
endif # CORESIGHT_ETM
config CORESIGHT_FUNNEL
bool "Funnel coresight device support"
default n
drivers/coresight/Make.defs
+4
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@@ -24,6 +24,10 @@ ifeq ($(CONFIG_CORESIGHT),y)
CSRCS += coresight_core.c coresight_common.c
ifeq ($(CONFIG_CORESIGHT_ETM_VERSION),"v3")
CSRCS += coresight_etm3.c
endif
ifeq ($(CONFIG_CORESIGHT_FUNNEL),y)
CSRCS += coresight_funnel.c
endif
drivers/coresight/coresight_common.c
+3 -4
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@@ -272,15 +272,14 @@ void coresight_put_system_trace_id(int traceid)
*
****************************************************************************/
int coresight_timeout(uintptr_t addr, uint32_t off,
uint32_t bitmask, uint32_t val)
int coresight_timeout(uint32_t val, uint32_t mask, uintptr_t addr)
{
int i;
for (i = CONFIG_CORESIGHT_TIMEOUT; i > 0; i--)
{
uint32_t value = coresight_get32(addr + off);
if ((value & bitmask) == val)
uint32_t value = coresight_get32(addr);
if ((value & mask) == val)
{
return 0;
}
drivers/coresight/coresight_common.h
+1 -2
View File
@@ -183,8 +183,7 @@ void coresight_put_system_trace_id(int traceid);
*
****************************************************************************/
int coresight_timeout(uintptr_t addr, uint32_t off,
uint32_t bitmask, uint32_t val);
int coresight_timeout(uint32_t val, uint32_t mask, uintptr_t addr);
/****************************************************************************
* Name: coresight_insert_barrier_packet
drivers/coresight/coresight_etm3.c
+733
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File diff suppressed because it is too large Load Diff
drivers/coresight/coresight_stm.c
+2 -2
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@@ -150,8 +150,8 @@ static void stm_hw_disable(FAR struct coresight_stm_dev_s *stmdev)
coresight_put32(0x0, stmdev->csdev.addr + STM_HEER);
coresight_put32(0x0, stmdev->csdev.addr + STM_HETER);
if (coresight_timeout(stmdev->csdev.addr, STM_TCSR,
STM_TCSR_BUSY, 0) < 0)
if (coresight_timeout(0x0, STM_TCSR_BUSY,
stmdev->csdev.addr + STM_TCSR) < 0)
{
cserr("timeout waiting for STM stopped\n");
}
drivers/coresight/coresight_tpiu.c
+8 -11
View File
@@ -107,25 +107,22 @@ static int tpiu_hw_enable(FAR struct coresight_tpiu_dev_s *tpiudev)
static void tpiu_hw_disable(FAR struct coresight_tpiu_dev_s *tpiudev)
{
uint32_t ffcr;
coresight_unlock(tpiudev->csdev.addr);
/* Trigger a formatter stop event. */
ffcr = coresight_get32(tpiudev->csdev.addr + TPIU_FFCR);
ffcr |= TPIU_FFCR_STOP_FI;
coresight_put32(ffcr, tpiudev->csdev.addr + TPIU_FFCR);
ffcr |= TPIU_FFCR_FON_MAN;
coresight_put32(ffcr, tpiudev->csdev.addr + TPIU_FFCR);
if (coresight_timeout(tpiudev->csdev.addr, TPIU_FFCR,
TPIU_FFCR_FON_MAN, 0) < 0)
coresight_modify32(TPIU_FFCR_STOP_FI, TPIU_FFCR_STOP_FI,
tpiudev->csdev.addr + TPIU_FFCR);
coresight_modify32(TPIU_FFCR_FON_MAN, TPIU_FFCR_FON_MAN,
tpiudev->csdev.addr + TPIU_FFCR);
if (coresight_timeout(0, TPIU_FFCR_FON_MAN,
tpiudev->csdev.addr + TPIU_FFCR) < 0)
{
cserr("timeout while waiting for completion of Manual Flush\n");
}
if (coresight_timeout(tpiudev->csdev.addr, TPIU_FFSR,
TPIU_FFSR_FT_STOPPED, TPIU_FFSR_FT_STOPPED) < 0)
if (coresight_timeout(TPIU_FFSR_FT_STOPPED, TPIU_FFSR_FT_STOPPED,
tpiudev->csdev.addr + TPIU_FFSR) < 0)
{
cserr("timeout while waiting for Formatter to Stop\n");
}
include/nuttx/coresight/coresight.h
+4
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@@ -122,6 +122,10 @@ struct coresight_desc_s
enum coresight_dev_type_e type;
union coresight_dev_subtype_u subtype;
/* Used in ETM device. */
uint8_t cpu;
/* Used in funnel devices. */
int inport_num;
include/nuttx/coresight/coresight_etm.h
+139
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@@ -0,0 +1,139 @@
/****************************************************************************
* include/nuttx/coresight/coresight_etm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __INCLUDE_NUTTX_CORESIGHT_CORESIGHT_ETM_H
#define __INCLUDE_NUTTX_CORESIGHT_CORESIGHT_ETM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/coresight/coresight.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define ETM_MAX_ADDR_CMP 16
#define ETM_MAX_CNTR 4
#define ETM_MAX_CTXID_CMP 3
/****************************************************************************
* Public Types
****************************************************************************/
struct etm_config_s
{
uint32_t ctrl; /* ETMCR */
uint32_t trigger_event; /* ETMTRIGGER */
uint32_t startstop_ctrl; /* ETMTSSCR */
uint32_t enable_event; /* ETMTEEVR */
uint32_t enable_ctrl1; /* ETMTECR1 */
uint32_t enable_ctrl2; /* ETMTECR2 */
uint32_t fifofull_level; /* ETMFFLR */
uint8_t addr_idx; /* Index for the address comparator selection. */
uint32_t addr_val[ETM_MAX_ADDR_CMP]; /* Value for address comparator register. */
uint32_t addr_acctype[ETM_MAX_ADDR_CMP]; /* Access type for address comparator register. */
uint32_t addr_type[ETM_MAX_ADDR_CMP]; /* Current status of the comparator register. */
uint8_t cntr_idx; /* Index for the counter register selection */
uint32_t cntr_rld_val[ETM_MAX_CNTR]; /* Reload value of a counter register. */
uint32_t cntr_event[ETM_MAX_CNTR]; /* Control for counter enable register. */
uint32_t cntr_rld_event[ETM_MAX_CNTR]; /* Value for counter reload event register. */
uint32_t cntr_val[ETM_MAX_CNTR]; /* Counter value register. */
uint32_t seq_12_event; /* Event causing the transition from 1 to 2 */
uint32_t seq_21_event; /* Event causing the transition from 2 to 1 */
uint32_t seq_23_event; /* Event causing the transition from 2 to 3 */
uint32_t seq_31_event; /* Event causing the transition from 3 to 1 */
uint32_t seq_32_event; /* Event causing the transition from 3 to 2 */
uint32_t seq_13_event; /* Event causing the transition from 1 to 3 */
uint32_t seq_curr_state; /* Current value of the sequencer register. */
uint8_t ctxid_idx; /* Index for the context ID registers. */
uint32_t ctxid_pid[ETM_MAX_CTXID_CMP]; /* Value for the context ID to trigger on */
uint32_t ctxid_mask; /* Mask applicable to all the context IDs. */
uint32_t sync_freq; /* Synchronisation frequency. */
uint32_t timestamp_event; /* ETMTSEVR */
};
struct coresight_etm_dev_s
{
struct coresight_dev_s csdev;
struct etm_config_s cfg;
uint8_t refcnt;
int cpu; /* The cpu this component is affined to */
int port_size; /* Out port size */
int traceid; /* Trace id */
uint8_t arch; /* ETM/PTM version number */
uint8_t nr_addr_cmp; /* Number of pairs of address comparators */
uint8_t nr_cntr; /* Number of counters */
uint8_t nr_ext_inp; /* Number of external input */
uint8_t nr_ext_out; /* Number of external output */
uint8_t nr_ctxid_cmp; /* Number of contextID comparators */
};
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: etm_register
*
* Description:
* Register an ETM/PTM devices.
*
* Input Parameters:
* desc - A description of this coresight device.
*
* Returned Value:
* Pointer to an ETM device on success; NULL on failure.
*
****************************************************************************/
FAR struct coresight_etm_dev_s *
etm_register(FAR const struct coresight_desc_s *desc);
/****************************************************************************
* Name: etm_unregister
*
* Description:
* Unregister an EMT/PTM device.
*
****************************************************************************/
void etm_unregister(FAR struct coresight_etm_dev_s *etmdev);
/****************************************************************************
* Name: etm_config
*
* Description:
* Configure the etm device.
*
* Input Parameters:
* etmdev - Pointer to the ETM device to config.
* config - Configuration need to be set to ETM device.
*
* Returned Value:
* Zero on success; a negative value on failure.
*
****************************************************************************/
int etm_config(FAR struct coresight_etm_dev_s *etmdev,
FAR const struct etm_config_s *config);
#endif //__INCLUDE_NUTTX_CORESIGHT_CORESIGHT_ETM_H