mirror of
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Add support for the STM32446. From David Sidrane
This commit is contained in:
David Sidrane
committed by
Gregory Nutt
Gregory Nutt
parent
e5a9919c8d
commit
70cd1095b0
@@ -2021,6 +2021,158 @@
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F446M) /* WLCSP81 256/512KiB flash 128KiB SRAM */
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# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
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# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
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# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_VALUELINE /* STM32F100x */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
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# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
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# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */
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# define STM32_NFSMC 0 /* FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 4 /* SPI1-4 */
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# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 2 /* CAN1-2 */
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# define STM32_NSDIO 1 /* SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
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# define STM32_NGPIO 114 /* GPIOA-I */
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# define STM32_NADC 2 /* 12-bit ADC1-3, 14 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */
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# define STM32_NRNG 0 /* Random number generator (RNG) */
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# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F446R) /* LQFP64 256/512KiB flash 128KiB SRAM */
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# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
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# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
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# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_VALUELINE /* STM32F100x */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
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# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
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# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */
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# define STM32_NFSMC 0 /* FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 4 /* SPI1-4 */
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# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 2 /* CAN1-2 */
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# define STM32_NSDIO 1 /* SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
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# define STM32_NGPIO 114 /* GPIOA-I */
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# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */
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# define STM32_NRNG 0 /* Random number generator (RNG) */
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# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F446V) /* LQFP100 256/512KiB flash 128KiB SRAM */
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# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
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# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
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# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_VALUELINE /* STM32F100x */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
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# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
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# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 4 /* SPI1-4 */
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# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 2 /* CAN1-2 */
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# define STM32_NSDIO 1 /* SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
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# define STM32_NGPIO 114 /* GPIOA-I */
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# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */
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# define STM32_NRNG 0 /* Random number generator (RNG) */
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# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F446Z) /* LQFP144 UFBGA144 256/512KiB flash 128KiB SRAM */
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# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
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# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
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# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_VALUELINE /* STM32F100x */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
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# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
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# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 4 /* SPI1-4 */
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# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 2 /* CAN1-2 */
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# define STM32_NSDIO 1 /* SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
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# define STM32_NGPIO 114 /* GPIOA-I */
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# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */
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# define STM32_NRNG 0 /* Random number generator (RNG) */
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# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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#else
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# error "Unsupported STM32 chip"
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#endif
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@@ -89,6 +89,8 @@
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# include <arch/stm32/stm32f37xxx_irq.h>
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#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
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# include <arch/stm32/stm32f42xxx_irq.h>
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#elif defined(CONFIG_STM32_STM32F446)
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# include <arch/stm32/stm32f44xxx_irq.h>
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#elif defined(CONFIG_STM32_STM32F40XX)
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# include <arch/stm32/stm32f40xxx_irq.h>
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#else
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@@ -0,0 +1,205 @@
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/****************************************************************************************************
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* arch/arm/include/stm32s/stm32f44xxx_irq.h
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*
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* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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/* This file should never be included directed but, rather,
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* only indirectly through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_STM32F44XXX_IRQ_H
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#define __ARCH_ARM_INCLUDE_STM32F44XXX_IRQ_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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#if defined(CONFIG_STM32_STM32F446)
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
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* bits in the NVIC. This does, however, waste several words of memory in the IRQ
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* to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15). These common definitions can be found
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* in nuttx/arch/arm/include/stm32/irq.h
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*
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* External interrupts (vectors >= 16)
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*/
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#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
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#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
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#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
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#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
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#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
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#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
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#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
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#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
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#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
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#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
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#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
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#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
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#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
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#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
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#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
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#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
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#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
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#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
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#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
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#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
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#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
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#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
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#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
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#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
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#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
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#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
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#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
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#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
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#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
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#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
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#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
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#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
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#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
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#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
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#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
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#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
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#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
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#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
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#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
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#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
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#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
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#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
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#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
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#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
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#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
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#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
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#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
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#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
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#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
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#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
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#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
|
||||
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
|
||||
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
|
||||
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
|
||||
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */
|
||||
#define STM32_IRQ_SDIO (STM32_IRQ_FIRST+49) /* 49: SDIO global interrupt */
|
||||
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
|
||||
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
|
||||
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
|
||||
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
|
||||
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
|
||||
#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
|
||||
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
|
||||
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
|
||||
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
|
||||
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
|
||||
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
|
||||
#define STM32_IRQ_RES01 (STM32_IRQ_FIRST+61) /* 61: 1st Reserved (Ethernet global) interrupt */
|
||||
#define STM32_IRQ_RES02 (STM32_IRQ_FIRST+62) /* 62: 2nd Reserved (Ethernet Wakeup through EXTI line) interrupt */
|
||||
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
|
||||
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
|
||||
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
|
||||
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
|
||||
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
|
||||
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
|
||||
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
|
||||
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
|
||||
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
|
||||
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
|
||||
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
|
||||
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
|
||||
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
|
||||
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
|
||||
#define STM32_IRQ_RES03 (STM32_IRQ_FIRST+79) /* 79: 3rd Reserved (CRYP crypto global) interrupt */
|
||||
#define STM32_IRQ_RES04 (STM32_IRQ_FIRST+80) /* 80: 4th Reserved (Hash and Rng global) interrupt */
|
||||
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
|
||||
#define STM32_IRQ_RES05 (STM32_IRQ_FIRST+82) /* 82: 5th Reserved (UART7)interrupt */
|
||||
#define STM32_IRQ_RES06 (STM32_IRQ_FIRST+83) /* 83: 6th Reserved (UART8) interrupt */
|
||||
#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 interrupt */
|
||||
#define STM32_IRQ_RES07 (STM32_IRQ_FIRST+85) /* 85: 7th Reserved (SPI5) interrupt */
|
||||
#define STM32_IRQ_RES08 (STM32_IRQ_FIRST+86) /* 86: 8th Reserved (SPI6) interrupt */
|
||||
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 interrupt */
|
||||
#define STM32_IRQ_RES09 (STM32_IRQ_FIRST+88) /* 88: 9th Reserved (LTDCINT interrupt */
|
||||
#define STM32_IRQ_RES10 (STM32_IRQ_FIRST+89) /* 89: 10th Reserved (LTDCERRINT) interrupt */
|
||||
#define STM32_IRQ_RES11 (STM32_IRQ_FIRST+90) /* 90: 11th Reserved (DMA2D) interrupt */
|
||||
|
||||
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 Global interrupt */
|
||||
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI Global interrupt */
|
||||
#define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+93) /* 93: HDMI-CEC Global interrupt */
|
||||
#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+94) /* 94: SPDIF-Rx Global interrupt */
|
||||
#define STM32_IRQ_FMPI2C1 (STM32_IRQ_FIRST+95) /* 95: FMPI2C1 event interrupt */
|
||||
#define STM32_IRQ_FMPI2C1ERR (STM32_IRQ_FIRST+96) /* 96: FMPI2C1 Error event interrupt */
|
||||
|
||||
#define NR_VECTORS (STM32_IRQ_FIRST+97)
|
||||
#define NR_IRQS (STM32_IRQ_FIRST+97)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F446 */
|
||||
#endif /* __ARCH_ARM_INCLUDE_STM32F44XXX_IRQ_H */
|
||||
@@ -737,6 +737,35 @@ config ARCH_CHIP_STM32F429N
|
||||
select STM32_STM32F429
|
||||
select ARCH_HAVE_FPU
|
||||
|
||||
config ARCH_CHIP_STM32F446M
|
||||
bool "STM32F446M"
|
||||
select ARCH_CORTEXM4
|
||||
select STM32_STM32F40XX
|
||||
select STM32_STM32F446
|
||||
select ARCH_HAVE_FPU
|
||||
|
||||
config ARCH_CHIP_STM32F446R
|
||||
bool "STM32F446R"
|
||||
select ARCH_CORTEXM4
|
||||
select STM32_STM32F40XX
|
||||
select STM32_STM32F446
|
||||
select ARCH_HAVE_FPU
|
||||
|
||||
config ARCH_CHIP_STM32F446V
|
||||
bool "STM32F446V"
|
||||
select ARCH_CORTEXM4
|
||||
select STM32_STM32F40XX
|
||||
select STM32_STM32F446
|
||||
select ARCH_HAVE_FPU
|
||||
|
||||
config ARCH_CHIP_STM32F446Z
|
||||
bool "STM32F446Z"
|
||||
select ARCH_CORTEXM4
|
||||
select STM32_STM32F40XX
|
||||
select STM32_STM32F446
|
||||
select ARCH_HAVE_FPU
|
||||
|
||||
|
||||
endchoice
|
||||
|
||||
# This is really 15XX/16XX, but we treat the two the same.
|
||||
@@ -1119,6 +1148,31 @@ config STM32_STM32F429
|
||||
select STM32_HAVE_SPI5
|
||||
select STM32_HAVE_SPI6
|
||||
|
||||
config STM32_STM32F446
|
||||
bool
|
||||
default n
|
||||
select STM32_HAVE_USART3
|
||||
select STM32_HAVE_UART4
|
||||
select STM32_HAVE_UART5
|
||||
select STM32_HAVE_USART6
|
||||
select STM32_HAVE_TIM1
|
||||
select STM32_HAVE_TIM6
|
||||
select STM32_HAVE_TIM7
|
||||
select STM32_HAVE_TIM8
|
||||
select STM32_HAVE_TIM9
|
||||
select STM32_HAVE_TIM10
|
||||
select STM32_HAVE_TIM11
|
||||
select STM32_HAVE_TIM12
|
||||
select STM32_HAVE_TIM13
|
||||
select STM32_HAVE_TIM14
|
||||
select STM32_HAVE_ADC2
|
||||
select STM32_HAVE_ADC3
|
||||
select STM32_HAVE_CAN1
|
||||
select STM32_HAVE_CAN2
|
||||
select STM32_HAVE_SPI2
|
||||
select STM32_HAVE_SPI3
|
||||
select STM32_HAVE_SPI4
|
||||
|
||||
config STM32_DFU
|
||||
bool "DFU bootloader"
|
||||
default n
|
||||
@@ -1884,7 +1938,7 @@ endmenu
|
||||
config STM32_FLASH_PREFETCH
|
||||
bool "Enable FLASH Pre-fetch"
|
||||
depends on STM32_STM32F207 || STM32_STM32F40XX
|
||||
default y if STM32_STM32F427 || STM32_STM32F429
|
||||
default y if STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446
|
||||
default n
|
||||
---help---
|
||||
Enable FLASH prefetch and F2 and F4 parts (FLASH pre-fetch is always enabled
|
||||
|
||||
@@ -131,6 +131,8 @@
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# include "chip/stm32f42xxx_pinmap.h"
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# include "chip/stm32f44xxx_pinmap.h"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_pinmap.h"
|
||||
#else
|
||||
@@ -154,6 +156,8 @@
|
||||
# include "chip/stm32f37xxx_vectors.h"
|
||||
# elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# include "chip/stm32f42xxx_vectors.h"
|
||||
# elif defined(CONFIG_STM32_STM32F446)
|
||||
# include "chip/stm32f44xxx_vectors.h"
|
||||
# elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_vectors.h"
|
||||
# else
|
||||
|
||||
@@ -94,7 +94,8 @@
|
||||
#define STM32_FLASH_SR_OFFSET 0x000c
|
||||
#define STM32_FLASH_CR_OFFSET 0x0010
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
# define STM32_FLASH_AR_OFFSET 0x0014
|
||||
# define STM32_FLASH_OBR_OFFSET 0x001c
|
||||
# define STM32_FLASH_WRPR_OFFSET 0x0020
|
||||
@@ -114,7 +115,8 @@
|
||||
#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
|
||||
#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
# define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET)
|
||||
# define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
|
||||
# define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET)
|
||||
@@ -147,7 +149,8 @@
|
||||
# define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 110: Six wait states */
|
||||
# define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 111: Seven wait states */
|
||||
|
||||
# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
|
||||
# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
# define FLASH_ACR_HLFCYA (1 << 3) /* Bit 3: FLASH half cycle access */
|
||||
# define FLASH_ACR_PRTFBE (1 << 4) /* Bit 4: FLASH prefetch enable */
|
||||
# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
|
||||
@@ -164,7 +167,8 @@
|
||||
|
||||
/* Flash Status Register (SR) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
# define FLASH_SR_BSY (1 << 0) /* Busy */
|
||||
# define FLASH_SR_PGERR (1 << 2) /* Programming Error */
|
||||
# define FLASH_SR_WRPRT_ERR (1 << 4) /* Write Protection Error */
|
||||
@@ -181,7 +185,8 @@
|
||||
|
||||
/* Flash Control Register (CR) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
# define FLASH_CR_PG (1 << 0) /* Bit 0: Program Page */
|
||||
# define FLASH_CR_PER (1 << 1) /* Bit 1: Page Erase */
|
||||
# define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase */
|
||||
@@ -248,6 +253,15 @@
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-27: Not write protect (high bank) */
|
||||
# define FLASH_OPTCR1_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT)
|
||||
|
||||
# define FLASH_OPTCR1_BFB2_SHIFT (4) /* Bits 4: Dual-bank Boot option byte */
|
||||
# define FLASH_OPTCR1_BFB2_MASK (1 << FLASH_OPTCR_NWRP_SHIFT)
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-23: Not write protect (high bank) */
|
||||
# define FLASH_OPTCR1_NWRP_MASK (0xff << FLASH_OPTCR_NWRP_SHIFT)
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_FLASH_H */
|
||||
|
||||
@@ -51,7 +51,8 @@
|
||||
#define STM32_I2C_SR2_OFFSET 0x0018 /* Status register 2 (16-bit) */
|
||||
#define STM32_I2C_CCR_OFFSET 0x001c /* Clock control register (16-bit) */
|
||||
#define STM32_I2C_TRISE_OFFSET 0x0020 /* TRISE Register (16-bit) */
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446)
|
||||
# define STM32_I2C_FLTR_OFFSET 0x0024 /* FLTR Register (16-bit) */
|
||||
#endif
|
||||
|
||||
@@ -203,9 +204,9 @@
|
||||
/* FLTR Register */
|
||||
|
||||
#ifdef STM32_I2C_FLTR_OFFSET
|
||||
# define I2C_FLTR_ANOFF (1 << 4) /* Bit 4: Analog noise filter disable */
|
||||
# define I2C_FLTR_DNF_SHIFT 0 /* Bits 0-3: Digital noise filter */
|
||||
# define I2C_FLTR_DNF_MASK (0xf << I2C_FLTR_DNF_SHIFT)
|
||||
# define I2C_FLTR_ANOFF (1 << 4) /* Bit 4: Analog noise filter disable */
|
||||
# define I2C_FLTR_DNF_SHIFT 0 /* Bits 0-3: Digital noise filter */
|
||||
# define I2C_FLTR_DNF_MASK (0xf << I2C_FLTR_DNF_SHIFT)
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_H */
|
||||
|
||||
@@ -92,7 +92,8 @@
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
# define PWR_CR_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */
|
||||
# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446)
|
||||
# define PWR_CR_ADCDC1 (1 << 13) /* Bit 13: see AN4073 for details */
|
||||
# define PWR_CR_VOS_MASK (3 << 14) /* Bits 14-15: Regulator voltage scaling output selection */
|
||||
# define PWR_CR_VOS_SCALE_1 (3 << 14) /* Fmax = 168MHz */
|
||||
@@ -114,11 +115,16 @@
|
||||
# define PWR_CR_LPRUN (1 << 14) /* Low power run mode */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F429)
|
||||
#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F446)
|
||||
# define PWR_CR_ODEN (1 << 16) /* Over Drive enable */
|
||||
# define PWR_CR_ODSWEN (1 << 17) /* Over Drive switch enabled */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define PWR_CR_FMSSR (1 << 20) /* Flash Memory Stop while System Run */
|
||||
# define PWR_CR_FISSR (1 << 21) /* Flash Interface Stop while System Run*/
|
||||
#endif
|
||||
|
||||
/* Power control/status register */
|
||||
|
||||
#define PWR_CSR_WUF (1 << 0) /* Bit 0: Wakeup Flag */
|
||||
@@ -149,7 +155,7 @@
|
||||
# define PWR_CSR_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F429)
|
||||
#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F446)
|
||||
# define PWR_CSR_ODRDY (1 << 16) /* Over Drive generator ready */
|
||||
# define PWR_CSR_ODSWRDY (1 << 17) /* Over Drive Switch ready */
|
||||
#endif
|
||||
|
||||
@@ -61,7 +61,7 @@
|
||||
*
|
||||
* #define GPIO_CAN1_RX GPIO_CAN1_RX_1
|
||||
*
|
||||
* The driver will then automatically configre PA11 as the CAN1 RX pin.
|
||||
* The driver will then automatically configure PA11 as the CAN1 RX pin.
|
||||
*/
|
||||
|
||||
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
|
||||
@@ -138,7 +138,7 @@
|
||||
#define GPIO_CAN2_TX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_CAN2_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
|
||||
|
||||
/* DAC -" Once the DAC channelx is enabled, the corresponding GPIO pin
|
||||
/* DAC - "Once the DAC channelx is enabled, the corresponding GPIO pin
|
||||
* (PA4 or PA5) is automatically connected to the analog converter output
|
||||
* (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin
|
||||
* should first be configured to analog (AIN)".
|
||||
|
||||
@@ -64,11 +64,11 @@
|
||||
#define STM32_RCC_AHB3ENR_OFFSET 0x0038 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB1ENR_OFFSET 0x0040 /* APB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB2ENR_OFFSET 0x0044 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB1LPENR_OFFSET 0x0050 /* RCC AHB1 low power modeperipheral clock enable register */
|
||||
#define STM32_RCC_AH2BLPENR_OFFSET 0x0054 /* RCC AHB2 low power modeperipheral clock enable register */
|
||||
#define STM32_RCC_AH3BLPENR_OFFSET 0x0058 /* RCC AHB3 low power modeperipheral clock enable register */
|
||||
#define STM32_RCC_APB1LPENR_OFFSET 0x0060 /* RCC APB1 low power modeperipheral clock enable register */
|
||||
#define STM32_RCC_APB2LPENR_OFFSET 0x0064 /* RCC APB2 low power modeperipheral clock enable register */
|
||||
#define STM32_RCC_AHB1LPENR_OFFSET 0x0050 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB2LPENR_OFFSET 0x0054 /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB3LPENR_OFFSET 0x0058 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_APB1LPENR_OFFSET 0x0060 /* RCC APB1 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_APB2LPENR_OFFSET 0x0064 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_BDCR_OFFSET 0x0070 /* Backup domain control register */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0074 /* Control/status register */
|
||||
#define STM32_RCC_SSCGR_OFFSET 0x0080 /* Spread spectrum clock generation register */
|
||||
@@ -93,8 +93,8 @@
|
||||
#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
|
||||
#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB1LPENR (STM32_RCC_BASE+STM32_RCC_AHB1LPENR_OFFSET)
|
||||
#define STM32_RCC_AH2BLPENR (STM32_RCC_BASE+STM32_RCC_AH2BLPENR)
|
||||
#define STM32_RCC_AH3BLPENR (STM32_RCC_BASE+STM32_RCC_AH3BLPENR_OFFSET)
|
||||
#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE+STM32_RCC_AHB2LPENR)
|
||||
#define STM32_RCC_AHB3LPENR (STM32_RCC_BASE+STM32_RCC_AHB3LPENR_OFFSET)
|
||||
#define STM32_RCC_APB1LPENR (STM32_RCC_BASE+STM32_RCC_APB1LPENR_OFFSET)
|
||||
#define STM32_RCC_APB2LPENR (STM32_RCC_BASE+STM32_RCC_APB2LPENR_OFFSET)
|
||||
#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
|
||||
@@ -486,7 +486,7 @@
|
||||
#define RCC_APB1LPENR_UART7LPEN (1 << 30) /* Bit 30: UART7 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_UART8LPEN (1 << 31) /* Bit 31: UART8 clock enable during Sleep mode */
|
||||
|
||||
/* RCC APB2 low power modeperipheral clock enable register */
|
||||
/* RCC APB2 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* Bit 0: TIM1 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_TIM8LPEN (1 << 1) /* Bit 1: TIM8 clock enable during Sleep mode */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,166 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f44xxx_syscfg.h
|
||||
*
|
||||
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F44XXX_SYSCFG_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F44XXX_SYSCFG_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32_SYSCFG_PMC_OFFSET 0x0004 /* SYSCFG peripheral mode configuration register */
|
||||
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
|
||||
#define STM32_SYSCFG_CMPCR_OFFSET 0x0020 /* Compensation cell control register */
|
||||
#define STM32_SYSCFG_CFGR_OFFSET 0x002c /* SYSCFG configuration register */
|
||||
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32_SYSCFG_PMC (STM32_SYSCFG_BASE+STM32_SYSCFG_PMC_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_CMPCR (STM32_SYSCFG_BASE+STM32_SYSCFG_CMPCR_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR_OFFSET)
|
||||
|
||||
/* Register Bit field Definitions ********************************************************************/
|
||||
|
||||
/* SYSCFG memory remap register */
|
||||
|
||||
#define SYSCFG_MEMRMP_SHIFT (0) /* Bits 1:0 MEM_MODE: Memory mapping selection */
|
||||
#define SYSCFG_MEMRMP_MASK (3 << SYSCFG_MEMRMP_SHIFT)
|
||||
# define SYSCFG_MEMRMP_FLASH (0 << SYSCFG_MEMRMP_SHIFT) /* 00: Main Flash memory mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_SYSTEM (1 << SYSCFG_MEMRMP_SHIFT) /* 01: System Flash memory mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_FSMC (2 << SYSCFG_MEMRMP_SHIFT) /* 10: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_SRAM (3 << SYSCFG_MEMRMP_SHIFT) /* 11: Embedded SRAM (112kB) mapped at 0x0000 0000 */
|
||||
|
||||
#define SYSCFG_SWPFMC_SHIFT (0) /* Bits 10:11 SWP_FMC: FMC memory mapping swap */
|
||||
#define SYSCFG_SWPFMC_MASK (3 << SYSCFG_SWPFMC_SHIFT)
|
||||
# define SYSCFG_SWPFMC_NOSWAP (0 << SYSCFG_SWPFMC_SHIFT) /* 00: No FMC memory mapping swap */
|
||||
# define SYSCFG_SWPFMC_SWAP (1 << SYSCFG_SWPFMC_SHIFT) /* 01: SDRAM banks and NAND Bank 2/PCCARD mapping are swapped */
|
||||
|
||||
/* SYSCFG peripheral mode configuration register */
|
||||
|
||||
#define SYSCFG_PMC_ADC3DC2 (1 << 18) /* Bit 18: See AN4073 */
|
||||
#define SYSCFG_PMC_ADC2DC2 (1 << 17) /* Bit 17: See AN4073 */
|
||||
#define SYSCFG_PMC_ADC1DC2 (1 << 16) /* Bit 16: See AN4073 */
|
||||
|
||||
/* SYSCFG external interrupt configuration register 1-4 */
|
||||
|
||||
#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[C] pin */
|
||||
#define SYSCFG_EXTICR_PORTG (6) /* 0110: PG[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTH (7) /* 0111: PH[x] pin */
|
||||
|
||||
#define SYSCFG_EXTICR_PORT_MASK (15)
|
||||
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
|
||||
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
|
||||
|
||||
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
|
||||
|
||||
/* Compensation cell control register */
|
||||
|
||||
#define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */
|
||||
#define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */
|
||||
|
||||
/* SYSCFG configuration register */
|
||||
|
||||
#define SYSCFG_CFGR_FMPI2C1_SCL (1 << 0) /* Bit 0: Forces FM+ drive capability on SCL */
|
||||
#define SYSCFG_CFGR_FMPI2C1_SDA (1 << 1) /* Bit 8: Forces FM+ drive capability on SDA */
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F446 */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F44XXX_SYSCFG_H */
|
||||
@@ -0,0 +1,159 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f44xxx_vectors.h
|
||||
*
|
||||
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* This file is included by stm32_vectors.S. It provides the macro VECTOR that
|
||||
* supplies ach STM32F40xxx vector in terms of a (lower-case) ISR label and an
|
||||
* (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f40xxx_irq.h.
|
||||
* stm32_vectors.S will define the VECTOR macro in different ways in order to generate
|
||||
* the interrupt vectors and handlers in their final form.
|
||||
*/
|
||||
|
||||
/* If the common ARMv7-M vector handling is used, then all it needs is the following
|
||||
* definition that provides the number of supported vectors.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARMV7M_CMNVECTOR
|
||||
|
||||
/* Reserve interrupt table entries for I/O interrupts. */
|
||||
|
||||
#define ARMV7M_PERIPHERAL_INTERRUPTS 97
|
||||
|
||||
#else
|
||||
|
||||
VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* Vector 16+0: Window Watchdog interrupt */
|
||||
VECTOR(stm32_pvd, STM32_IRQ_PVD) /* Vector 16+1: PVD through EXTI Line detection interrupt */
|
||||
VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* Vector 16+2: Tamper and time stamp interrupts */
|
||||
VECTOR(stm32_rtc_wkup, STM32_IRQ_RTC_WKUP) /* Vector 16+3: RTC global interrupt */
|
||||
VECTOR(stm32_flash, STM32_IRQ_FLASH) /* Vector 16+4: Flash global interrupt */
|
||||
VECTOR(stm32_rcc, STM32_IRQ_RCC) /* Vector 16+5: RCC global interrupt */
|
||||
VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* Vector 16+6: EXTI Line 0 interrupt */
|
||||
VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* Vector 16+7: EXTI Line 1 interrupt */
|
||||
VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* Vector 16+8: EXTI Line 2 interrupt */
|
||||
VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* Vector 16+9: EXTI Line 3 interrupt */
|
||||
VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* Vector 16+10: EXTI Line 4 interrupt */
|
||||
VECTOR(stm32_dma1s0, STM32_IRQ_DMA1S0) /* Vector 16+11: DMA1 Stream 0 global interrupt */
|
||||
VECTOR(stm32_dma1s1, STM32_IRQ_DMA1S1) /* Vector 16+12: DMA1 Stream 1 global interrupt */
|
||||
VECTOR(stm32_dma1s2, STM32_IRQ_DMA1S2) /* Vector 16+13: DMA1 Stream 2 global interrupt */
|
||||
VECTOR(stm32_dma1s3, STM32_IRQ_DMA1S3) /* Vector 16+14: DMA1 Stream 3 global interrupt */
|
||||
VECTOR(stm32_dma1s4, STM32_IRQ_DMA1S4) /* Vector 16+15: DMA1 Stream 4 global interrupt */
|
||||
VECTOR(stm32_dma1s5, STM32_IRQ_DMA1S5) /* Vector 16+16: DMA1 Stream 5 global interrupt */
|
||||
VECTOR(stm32_dma1s6, STM32_IRQ_DMA1S6) /* Vector 16+17: DMA1 Stream 6 global interrupt */
|
||||
VECTOR(stm32_adc, STM32_IRQ_ADC) /* Vector 16+18: ADC1, ADC2, and ADC3 global interrupt */
|
||||
VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX) /* Vector 16+19: CAN1 TX interrupts */
|
||||
VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0) /* Vector 16+20: CAN1 RX0 interrupts */
|
||||
VECTOR(stm32_can1rx1, STM32_IRQ_CAN1RX1) /* Vector 16+21: CAN1 RX1 interrupt */
|
||||
VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE) /* Vector 16+22: CAN1 SCE interrupt */
|
||||
VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* Vector 16+23: EXTI Line[9:5] interrupts */
|
||||
VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK) /* Vector 16+24: TIM1 Break interrupt/TIM9 global interrupt */
|
||||
VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP) /* Vector 16+25: TIM1 Update interrupt/TIM10 global interrupt */
|
||||
VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM) /* Vector 16+26: TIM1 Trigger and Commutation interrupts/TIM11 global interrupt */
|
||||
VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC) /* Vector 16+27: TIM1 Capture Compare interrupt */
|
||||
VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* Vector 16+28: TIM2 global interrupt */
|
||||
VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* Vector 16+29: TIM3 global interrupt */
|
||||
VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* Vector 16+30: TIM4 global interrupt */
|
||||
VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* Vector 16+31: I2C1 event interrupt */
|
||||
VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* Vector 16+32: I2C1 error interrupt */
|
||||
VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* Vector 16+33: I2C2 event interrupt */
|
||||
VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* Vector 16+34: I2C2 error interrupt */
|
||||
VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* Vector 16+35: SPI1 global interrupt */
|
||||
VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* Vector 16+36: SPI2 global interrupt */
|
||||
VECTOR(stm32_usart1, STM32_IRQ_USART1) /* Vector 16+37: USART1 global interrupt */
|
||||
VECTOR(stm32_usart2, STM32_IRQ_USART2) /* Vector 16+38: USART2 global interrupt */
|
||||
VECTOR(stm32_usart3, STM32_IRQ_USART3) /* Vector 16+39: USART3 global interrupt */
|
||||
VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* Vector 16+40: EXTI Line[15:10] interrupts */
|
||||
VECTOR(stm32_rtcalrm, STM32_IRQ_RTCALRM) /* Vector 16+41: RTC alarm through EXTI line interrupt */
|
||||
VECTOR(stm32_otgfswkup, STM32_IRQ_OTGFSWKUP) /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */
|
||||
VECTOR(stm32_tim8brk, STM32_IRQ_TIM8BRK) /* Vector 16+43: TIM8 Break interrupt/TIM12 global interrupt */
|
||||
VECTOR(stm32_tim8up, STM32_IRQ_TIM8UP) /* Vector 16+44: TIM8 Update interrupt/TIM13 global interrupt */
|
||||
VECTOR(stm32_tim8trgcom, STM32_IRQ_TIM8TRGCOM) /* Vector 16+45: TIM8 Trigger and Commutation interrupts/TIM14 global interrupt */
|
||||
VECTOR(stm32_tim8cc, STM32_IRQ_TIM8CC) /* Vector 16+46: TIM8 Capture Compare interrupt */
|
||||
VECTOR(stm32_dma1s7, STM32_IRQ_DMA1S7) /* Vector 16+47: DMA1 Stream 7 global interrupt */
|
||||
VECTOR(stm32_fsmc, STM32_IRQ_FSMC) /* Vector 16+48: FSMC global interrupt */
|
||||
VECTOR(stm32_sdio, STM32_IRQ_SDIO) /* Vector 16+49: SDIO global interrupt */
|
||||
VECTOR(stm32_tim5, STM32_IRQ_TIM5) /* Vector 16+50: TIM5 global interrupt */
|
||||
VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* Vector 16+51: SPI3 global interrupt */
|
||||
VECTOR(stm32_uart4, STM32_IRQ_UART4) /* Vector 16+52: UART4 global interrupt */
|
||||
VECTOR(stm32_uart5, STM32_IRQ_UART5) /* Vector 16+53: UART5 global interrupt */
|
||||
VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* Vector 16+54: TIM6 global interrupt/DAC1 and DAC2 underrun error interrupts */
|
||||
VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* Vector 16+55: TIM7 global interrupt */
|
||||
VECTOR(stm32_dma2s0, STM32_IRQ_DMA2S0) /* Vector 16+56: DMA2 Stream 0 global interrupt */
|
||||
VECTOR(stm32_dma2s1, STM32_IRQ_DMA2S1) /* Vector 16+57: DMA2 Stream 1 global interrupt */
|
||||
VECTOR(stm32_dma2s2, STM32_IRQ_DMA2S2) /* Vector 16+58: DMA2 Stream 2 global interrupt */
|
||||
VECTOR(stm32_dma2s3, STM32_IRQ_DMA2S3) /* Vector 16+59: DMA2 Stream 3 global interrupt */
|
||||
VECTOR(stm32_dma2s4, STM32_IRQ_DMA2S4) /* Vector 16+60: DMA2 Stream 4 global interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES01) /* Vector 16+61: 1st Reserved (Ethernet global) interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES02) /* Vector 16+62: 2nd Reserved (Ethernet Wakeup through EXTI line) interrupt */
|
||||
VECTOR(stm32_can2tx, STM32_IRQ_CAN2TX) /* Vector 16+63: CAN2 TX interrupts */
|
||||
VECTOR(stm32_can2rx0, STM32_IRQ_CAN2RX0) /* Vector 16+64: CAN2 RX0 interrupts */
|
||||
VECTOR(stm32_can2rx1, STM32_IRQ_CAN2RX1) /* Vector 16+65: CAN2 RX1 interrupt */
|
||||
VECTOR(stm32_can2sce, STM32_IRQ_CAN2SCE) /* Vector 16+66: CAN2 SCE interrupt */
|
||||
VECTOR(stm32_otgfs, STM32_IRQ_OTGFS) /* Vector 16+67: USB On The Go FS global interrupt */
|
||||
VECTOR(stm32_dma2s5, STM32_IRQ_DMA2S5) /* Vector 16+68: DMA2 Stream 5 global interrupt */
|
||||
VECTOR(stm32_dma2s6, STM32_IRQ_DMA2S6) /* Vector 16+69: DMA2 Stream 6 global interrupt */
|
||||
VECTOR(stm32_dma2s7, STM32_IRQ_DMA2S7) /* Vector 16+70: DMA2 Stream 7 global interrupt */
|
||||
VECTOR(stm32_usart6, STM32_IRQ_USART6) /* Vector 16+71: USART6 global interrupt */
|
||||
VECTOR(stm32_i2c3ev, STM32_IRQ_I2C3EV) /* Vector 16+72: I2C3 event interrupt */
|
||||
VECTOR(stm32_i2c3er, STM32_IRQ_I2C3ER) /* Vector 16+73: I2C3 error interrupt */
|
||||
VECTOR(stm32_otghsep1out, STM32_IRQ_OTGHSEP1OUT) /* Vector 16+74: USB On The Go HS End Point 1 Out global interrupt */
|
||||
VECTOR(stm32_otghsep1in, STM32_IRQ_OTGHSEP1IN) /* Vector 16+75: USB On The Go HS End Point 1 In global interrupt */
|
||||
VECTOR(stm32_otghswkup, STM32_IRQ_OTGHSWKUP) /* Vector 16+76: USB On The Go HS Wakeup through EXTI interrupt */
|
||||
VECTOR(stm32_otghs, STM32_IRQ_OTGHS) /* Vector 16+77: USB On The Go HS global interrupt */
|
||||
VECTOR(stm32_dcmi, STM32_IRQ_DCMI) /* Vector 16+78: DCMI global interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES03) /* Vector 16+79: 3rd Reserved (CRYP crypto global) interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES04) /* Vector 16+80: 4th Reserved (Hash and Rng global) interrupt */
|
||||
VECTOR(stm32_fpu, STM32_IRQ_FPU) /* Vector 16+81: FPU global interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES05) /* Vector 16+82: 5th Reserved (UART7)interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES06) /* Vector 16+83: 6th Reserved (UART8) interrupt */
|
||||
VECTOR(stm32_spi4, STM32_IRQ_SPI4) /* Vector 16+84: SPI4 interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES07) /* Vector 16+85: 7th Reserved (SPI5) interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES08) /* Vector 16+86: 8th Reserved (SPI6) interrupt */
|
||||
VECTOR(stm32_sai1, STM32_IRQ_SAI1) /* Vector 16+87: SAI1 interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES09) /* Vector 16+88: 9th Reserved (LTDCINT interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES10) /* Vector 16+89: 10th Reserved (LTDCERRINT) interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES11) /* Vector 16+90: 11th Reserved (DMA2D) interrupt */
|
||||
/* todo:Implemnt 91-96 */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_SAI2) /* Vector 16+91: SAI2 Global interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_QUADSPI) /* Vector 16+92: QuadSPI Global interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_HDMICEC) /* Vector 16+93: HDMI-CEC Global interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_SPDIFRX) /* Vector 16+94: SPDIF-Rx Global interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_FMPI2C1) /* Vector 16+95: FMPI2C1 event interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_FMPI2C1ERR) /* Vector 16+96: FMPI2C1 Error event interrupt */
|
||||
|
||||
#endif /* CONFIG_ARMV7M_CMNVECTOR */
|
||||
@@ -187,7 +187,9 @@
|
||||
/* Only one memory region. Force Configuration 1 */
|
||||
|
||||
# ifndef CONFIG_STM32_CCMEXCLUDE
|
||||
# warning "CCM SRAM excluded from the heap"
|
||||
# if CONFIG_STM32_HAVE_CCM
|
||||
# warning "CCM SRAM excluded from the heap"
|
||||
# endif
|
||||
# define CONFIG_STM32_CCMEXCLUDE 1
|
||||
# endif
|
||||
|
||||
@@ -392,7 +394,9 @@
|
||||
# endif
|
||||
|
||||
# if CONFIG_MM_REGIONS < 2
|
||||
# error "CCM SRAM excluded from the heap because CONFIG_MM_REGIONS < 2"
|
||||
# if CONFIG_STM32_HAVE_CCM
|
||||
# error "CCM SRAM excluded from the heap because CONFIG_MM_REGIONS < 2"
|
||||
# endif
|
||||
# undef CONFIG_STM32_CCMEXCLUDE
|
||||
# define CONFIG_STM32_CCMEXCLUDE 1
|
||||
# elif CONFIG_MM_REGIONS > 2
|
||||
|
||||
@@ -54,6 +54,8 @@
|
||||
# include "chip/stm32f20xxx_dma.h"
|
||||
#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# include "chip/stm32f42xxx_dma.h"
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# include "chip/stm32f44xxx_dma.h"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_dma.h"
|
||||
#else
|
||||
|
||||
@@ -86,6 +86,10 @@
|
||||
# include "stm32f30xxx_rcc.c"
|
||||
#elif defined(CONFIG_STM32_STM32F37XX)
|
||||
# include "stm32f37xxx_rcc.c"
|
||||
#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F427)
|
||||
# include "stm32f42xxx_rcc.c"
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# include "stm32f44xxx_rcc.c"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "stm32f40xxx_rcc.c"
|
||||
#else
|
||||
|
||||
@@ -57,6 +57,8 @@
|
||||
# include "chip/stm32f37xxx_rcc.h"
|
||||
#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# include "chip/stm32f42xxx_rcc.h"
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# include "chip/stm32f44xxx_rcc.h"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_rcc.h"
|
||||
#endif
|
||||
|
||||
@@ -53,6 +53,8 @@
|
||||
# include "chip/stm32f37xxx_syscfg.h"
|
||||
#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# include "chip/stm32f42xxx_syscfg.h"
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# include "chip/stm32f44xxx_syscfg.h"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_syscfg.h"
|
||||
#endif
|
||||
|
||||
@@ -182,6 +182,8 @@ _vectors:
|
||||
# include "chip/stm32f37xxx_vectors.h"
|
||||
#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# include "chip/stm32f42xxx_vectors.h"
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# include "chip/stm32f44xxx_vectors.h"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_vectors.h"
|
||||
#else
|
||||
@@ -229,6 +231,8 @@ handlers:
|
||||
# include "chip/stm32f37xxx_vectors.h"
|
||||
#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# include "chip/stm32f42xxx_vectors.h"
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# include "chip/stm32f44xxx_vectors.h"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_vectors.h"
|
||||
#else
|
||||
|
||||
@@ -3,6 +3,7 @@
|
||||
*
|
||||
* Copyright (C) 2011-2012, 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -665,12 +666,7 @@ static void stm32_stdclockconfig(void)
|
||||
putreg32(regval, STM32_RCC_APB1ENR);
|
||||
|
||||
regval = getreg32(STM32_PWR_CR);
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
regval &= ~PWR_CR_VOS_MASK;
|
||||
regval |= PWR_CR_VOS_SCALE_1;
|
||||
#else
|
||||
regval |= PWR_CR_VOS;
|
||||
#endif
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
|
||||
/* Set the HCLK source/divider */
|
||||
@@ -726,24 +722,6 @@ static void stm32_stdclockconfig(void)
|
||||
{
|
||||
}
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F429)
|
||||
/* Enable the Over-drive to extend the clock frequency to 180 Mhz */
|
||||
|
||||
regval = getreg32(STM32_PWR_CR);
|
||||
regval |= PWR_CR_ODEN;
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
regval = getreg32(STM32_PWR_CR);
|
||||
regval |= PWR_CR_ODSWEN;
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODSWRDY) == 0)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
|
||||
|
||||
#ifdef CONFIG_STM32_FLASH_PREFETCH
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user