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Merge branch 'master' of bitbucket.org:nuttx/arch

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This commit is contained in:
Gregory Nutt
2015-08-24 13:46:19 -06:00
parent c9603b27c0 bddc4dbd6a
commit 706d50d97a
76 changed files with 11533 additions and 544 deletions
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arch/arm/Kconfig
+1
View File
@@ -227,6 +227,7 @@ config ARCH_CHIP_MOXART
bool "MoxART"
select ARCH_ARM7TDMI
select ARCH_HAVE_RESET
select ARCH_HAVE_SERIAL_TERMIOS
---help---
MoxART family
arch/arm/include/moxart/irq.h
+3 -2
View File
@@ -81,7 +81,8 @@ extern "C"
#define IRQ_SYSTIMER 19
#define NR_IRQS 32
#define VIRQ_START 32
#define NR_IRQS (VIRQ_START+2)
#endif /* __ARCH_ARM_INCLUDE_MOXART_IRQ_H */
arch/arm/include/samv7/chip.h
+2 -2
View File
@@ -86,7 +86,7 @@
# define SAMV7_NTCCHIO 36 /* 12 Timer/counter channels I/O */
# define SAMV7_NUSART 3 /* 3 USARTs */
# define SAMV7_NUART 5 /* 5 UARTs */
# define SAMV7_NQSPI 5 /* 1 Quad SPI */
# define SAMV7_NQSPI 1 /* 1 Quad SPI */
# define SAMV7_NSPI 2 /* 2 SPI, SPI0-1 */
# define SAMV7_NTWIHS 3 /* 3 TWIHS */
# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
@@ -142,7 +142,7 @@
# define SAMV7_NTCCHIO 9 /* 12 Timer/counter channels I/O */
# define SAMV7_NUSART 3 /* 3 USARTs */
# define SAMV7_NUART 5 /* 5 UARTs */
# define SAMV7_NQSPI 5 /* 1 Quad SPI */
# define SAMV7_NQSPI 1 /* 1 Quad SPI */
# define SAMV7_NSPI 1 /* 1 SPI, SPI0 */
# define SAMV7_NTWIHS 3 /* 3 TWIHS */
# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
arch/arm/include/stm32/chip.h
+120
View File
@@ -1212,6 +1212,86 @@
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303K6) || defined(CONFIG_ARCH_CHIP_STM32F303K8)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */
# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3
* (1) 32-bit general timers with DMA: TIM2
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
# define STM32_NGTIMNDMA 0 /* All timers have DMA */
# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */
# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */
# define STM32_NSPI 1 /* (1) SPI1 */
# define STM32_NI2S 0 /* (0) No I2S */
# define STM32_NUSART 2 /* (2) USART1-2, no UARTs */
# define STM32_NI2C 1 /* (1) I2C1 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 25 /* GPIOA-F */
# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */
# define STM32_NDAC 3 /* (2) 12-bit DAC1-3 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303C6) || defined(CONFIG_ARCH_CHIP_STM32F303C8)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */
# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3
* (1) 32-bit general timers with DMA: TIM2
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
# define STM32_NGTIMNDMA 0 /* All timers have DMA */
# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */
# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */
# define STM32_NSPI 1 /* (1) SPI1 */
# define STM32_NI2S 0 /* (0) No I2S */
# define STM32_NUSART 3 /* (3) USART1-3, no UARTs */
# define STM32_NI2C 1 /* (1) I2C1 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 37 /* GPIOA-F */
# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */
# define STM32_NDAC 3 /* (2) 12-bit DAC1-3 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303CB) || defined(CONFIG_ARCH_CHIP_STM32F303CC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
@@ -1292,6 +1372,46 @@
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303RD) || defined(CONFIG_ARCH_CHIP_STM32F303RE)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */
# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4
* (1) 32-bit general timers with DMA: TIM2
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
# define STM32_NGTIMNDMA 0 /* All timers have DMA */
# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */
# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */
# define STM32_NSPI 4 /* (4) SPI1-4 */
# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */
# define STM32_NI2C 3 /* (2) I2C1-3 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 51 /* GPIOA-F */
# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303VB) || defined(CONFIG_ARCH_CHIP_STM32F303VC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
arch/arm/src/armv7-m/up_ramvec_initialize.c
+16 -1
View File
@@ -56,6 +56,21 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Alignment ****************************************************************/
/* Per the ARMv7M Architecture reference manual, the NVIC vector table
* requires 7-bit address alignment (i.e, bits 0-6 of the address of the
* vector table must be zero). In this case alignment to a 128 byte address
* boundary is sufficient.
*
* Some parts, such as the LPC17xx family, require alignment to a 256 byte
* address boundary. Any other unusual alignment requirements for the vector
* can be specified for a given architecture be redefining
* NVIC_VECTAB_TBLOFF_MASK in the chip-specific chip.h header file for the
* appropriate mask.
*/
#define RAMVEC_ALIGN ((~NVIC_VECTAB_TBLOFF_MASK & 0xffff) + 1)
/* Debug ********************************************************************/
/* Non-standard debug that may be enabled just for testing the interrupt
* config. NOTE: that only lldbg types are used so that the output is
@@ -91,7 +106,7 @@
*/
up_vector_t g_ram_vectors[ARMV7M_VECTAB_SIZE]
__attribute__ ((section (".ram_vectors"), aligned (128)));
__attribute__ ((section (".ram_vectors"), aligned (RAMVEC_ALIGN)));
/****************************************************************************
* Private Variables
arch/arm/src/efm32/efm32_irq.c
+20 -1
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/efm32/efm32_irq.c
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -79,8 +79,18 @@
* Public Data
****************************************************************************/
/* This is the address of current interrupt saved state data. Used for
* context switching. Only value during interrupt handling.
*/
volatile uint32_t *current_regs;
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern uint32_t _vectors[];
/****************************************************************************
* Private Data
****************************************************************************/
@@ -363,6 +373,15 @@ void up_irqinitialize(void)
}
#endif
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
arch/arm/src/efm32/efm32_usbdev.c
+2 -2
View File
@@ -683,7 +683,7 @@ static const struct usbdev_ops_s g_devops =
.pullup = efm32_pullup,
};
/* Device error strings that may be enabled for more desciptive USB trace
/* Device error strings that may be enabled for more descriptive USB trace
* output.
*/
@@ -725,7 +725,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
};
#endif
/* Interrupt event strings that may be enabled for more desciptive USB trace
/* Interrupt event strings that may be enabled for more descriptive USB trace
* output.
*/
arch/arm/src/efm32/efm32_usbhost.c
+1 -1
View File
@@ -1171,7 +1171,7 @@ static int efm32_chan_wait(FAR struct efm32_usbhost_s *priv,
/* Loop, testing for an end of transfer condition. The channel 'result'
* was set to EBUSY and 'waiter' was set to true before the transfer; 'waiter'
* will be set to false and 'result' will be set appropriately when the
* tranfer is completed.
* transfer is completed.
*/
do
arch/arm/src/kinetis/kinetis_enet.c
+2 -2
View File
@@ -191,14 +191,14 @@ struct kinetis_driver_s
#endif
/* The DMA descriptors. A unaligned uint8_t is used to allocate the
* memory; 16 is added to assure that we can meet the desciptor alignment
* memory; 16 is added to assure that we can meet the descriptor alignment
* requirements.
*/
uint8_t desc[NENET_NBUFFERS * sizeof(struct enet_desc_s) + 16];
/* The DMA buffers. Again, A unaligned uint8_t is used to allocate the
* memory; 16 is added to assure that we can meet the desciptor alignment
* memory; 16 is added to assure that we can meet the descriptor alignment
* requirements.
*/
arch/arm/src/kinetis/kinetis_irq.c
+21 -2
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc17/kinetis_irq.c
*
* Copyright (C) 2011, 2013-14 Gregory Nutt. All rights reserved.
* Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -75,8 +75,18 @@
* Public Data
****************************************************************************/
/* This is the address of current interrupt saved state data. Used for
* context switching. Only value during interrupt handling.
*/
volatile uint32_t *current_regs;
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern uint32_t _vectors[];
/****************************************************************************
* Private Data
****************************************************************************/
@@ -341,11 +351,20 @@ void up_irqinitialize(void)
putreg32(0, regaddr);
}
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
#ifdef CONFIG_ARCH_RAMVECTORS
up_ramvec_initialize();
#endif
arch/arm/src/lpc17xx/lpc17_allocateheap.c
+22 -3
View File
@@ -155,15 +155,23 @@
/* Sanity checking */
#if !defined(CONFIG_LPC17_EXTDRAMHEAP) && !defined(CONFIG_LPC17_EXTSRAM0HEAP)
# define LPC17_EXT_MM_REGIONS 0
#elif defined(CONFIG_LPC17_EXTDRAMHEAP) && defined(CONFIG_LPC17_EXTSRAM0HEAP)
# define LPC17_EXT_MM_REGIONS 2
#else
# define LPC17_EXT_MM_REGIONS 1
#endif
#ifdef LPC17_AHB_HEAPBASE
# if CONFIG_MM_REGIONS < 2
# if CONFIG_MM_REGIONS < 2 + LPC17_EXT_MM_REGIONS
# warning "CONFIG_MM_REGIONS < 2: Available AHB SRAM Bank(s) not included in HEAP"
# endif
# if CONFIG_MM_REGIONS > 2
# if (CONFIG_MM_REGIONS > 2 + LPC17_EXT_MM_REGIONS)
# warning "CONFIG_MM_REGIONS > 2: Are additional regions handled by application?"
# endif
#else
# if CONFIG_MM_REGIONS > 1
# if CONFIG_MM_REGIONS > 1 + LPC17_EXT_MM_REGIONS
# warning "CONFIG_MM_REGIONS > 1: This configuration has no available AHB SRAM Bank0/1"
# warning "CONFIG_MM_REGIONS > 1: Are additional regions handled by application?"
# endif
@@ -340,5 +348,16 @@ void up_addregion(void)
kumm_addregion((FAR void*)LPC17_AHB_HEAPBASE, LPC17_AHB_HEAPSIZE);
#endif
#if CONFIG_MM_REGIONS >= 3
#if defined(CONFIG_LPC17_EXTDRAM) && defined(CONFIG_LPC17_EXTDRAMHEAP)
kmm_addregion((FAR void*)LPC17_EXTDRAM_CS0, CONFIG_LPC17_EXTDRAMSIZE);
#endif
#if !defined(CONFIG_LPC17_EXTDRAMHEAP) || (CONFIG_MM_REGIONS >= 4)
#if defined(CONFIG_LPC17_EXTSRAM0) && defined(CONFIG_LPC17_EXTSRAM0HEAP)
kmm_addregion((FAR void*)LPC17_EXTSRAM_CS0, CONFIG_LPC17_EXTSRAM0SIZE);
#endif
#endif
#endif
}
#endif
arch/arm/src/lpc17xx/lpc17_can.c
+9 -5
View File
@@ -750,7 +750,8 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
irqstate_t flags;
int ret = OK;
canvdbg("CAN%d ID: %d DLC: %d\n", priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
canvdbg("CAN%d ID: %d DLC: %d\n",
priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
if (msg->cm_hdr.ch_rtr)
{
@@ -971,12 +972,15 @@ static void can_interrupt(FAR struct can_dev_s *dev)
/* Construct the CAN header */
hdr.ch_id = rid;
hdr.ch_rtr = ((rfs & CAN_RFS_RTR) != 0);
hdr.ch_dlc = (rfs & CAN_RFS_DLC_MASK) >> CAN_RFS_DLC_SHIFT;
hdr.ch_id = rid;
hdr.ch_rtr = ((rfs & CAN_RFS_RTR) != 0);
hdr.ch_dlc = (rfs & CAN_RFS_DLC_MASK) >> CAN_RFS_DLC_SHIFT;
hdr.ch_error = 0;
#ifdef CONFIG_CAN_EXTID
hdr.ch_extid = ((rfs & CAN_RFS_FF) != 0);
hdr.ch_extid = ((rfs & CAN_RFS_FF) != 0);
#else
hdr.ch_unused = 0;
if ((rfs & CAN_RFS_FF) != 0)
{
canlldbg("ERROR: Received message with extended identifier. Dropped\n");
arch/arm/src/lpc17xx/lpc17_gpdma.h
+1 -1
View File
@@ -60,7 +60,7 @@ typedef FAR void *DMA_HANDLE;
* function is called at the completion of the DMA transfer. 'arg' is the
* same 'arg' value that was provided when lpc17_dmastart() was called and
* result indicates the result of the transfer: Zero indicates a successful
* tranfers. On failure, a negated errno is returned indicating the general
* transfers. On failure, a negated errno is returned indicating the general
* nature of the DMA faiure.
*/
arch/arm/src/lpc17xx/lpc17_irq.c
+23 -4
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc17/lpc17_irq.c
*
* Copyright (C) 2010-2011, 2013-2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2010-2011, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -76,11 +76,17 @@
* Public Data
****************************************************************************/
/* This is the address of current interrupt saved state data. Used for
* context switching. Only value during interrupt handling.
*/
volatile uint32_t *current_regs;
/****************************************************************************
* Private Data
****************************************************************************/
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern uint32_t _vectors[];
/****************************************************************************
* Private Functions
@@ -313,8 +319,21 @@ void up_irqinitialize(void)
putreg32(0, regaddr);
}
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*
* But even in this case NVIC_VECTAB has to point to the initial table
* because up_ramvec_initialize() initializes RAM table from table
* pointed by NVIC_VECTAB register.
*/
#ifdef CONFIG_ARCH_RAMVECTORS
arch/arm/src/lpc17xx/lpc17_usbdev.c
+1 -1
View File
@@ -2457,7 +2457,7 @@ static int lpc17_dmasetup(struct lpc17_usbdev_s *priv, uint8_t epphy,
dmadesc->size = (uint32_t)packet;
#endif
/* Enable DMA tranfer for this endpoint */
/* Enable DMA transfer for this endpoint */
putreq32(1 << epphy, LPC17_USBDEV_EPDMAEN);
arch/arm/src/lpc214x/lpc214x_usbdev.c
+2 -2
View File
@@ -212,7 +212,7 @@
/* USB RAM ********************************************************************
*
* UBS_UDCA is is list of 32 pointers to DMA desciptors located at the
* UBS_UDCA is is list of 32 pointers to DMA descriptors located at the
* beginning of USB RAM. Each pointer points to a DMA descriptor with
* assocated DMA buffer.
*/
@@ -2422,7 +2422,7 @@ static int lpc214x_dmasetup(struct lpc214x_usbdev_s *priv, uint8_t epphy,
dmadesc->size = (uint32_t)packet;
#endif
/* Enable DMA tranfer for this endpoint */
/* Enable DMA transfer for this endpoint */
putreq32(1 << epphy, LPC214X_USBDEV_EPDMAEN);
arch/arm/src/lpc43xx/lpc43_irq.c
+15 -8
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc43/lpc43_irq.c
*
* Copyright (C) 2012-2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2012-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -77,11 +77,17 @@
* Public Data
****************************************************************************/
/* This is the address of current interrupt saved state data. Used for
* context switching. Only value during interrupt handling.
*/
volatile uint32_t *current_regs;
/* This is the address of the vector table */
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern unsigned _vectors[];
extern uint32_t _vectors[];
/****************************************************************************
* Private Data
@@ -316,15 +322,16 @@ void up_irqinitialize(void)
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*
* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
#ifdef CONFIG_ARCH_RAMVECTORS
up_ramvec_initialize();
#else
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#endif
/* Set all interrupts (and exceptions) to the default priority */
arch/arm/src/moxart/Kconfig
+9
View File
@@ -7,3 +7,12 @@ comment "MoxART Configuration Options"
config UART_MOXA_MODE_REG
hex "16550 UART mode register address"
default 0x982000E0
config UART_MOXA_IRQ_STATUS_REG
hex "16550 UART shared IRQ status register address"
default 0x982000C0
config UART_MOXA_SHARED_IRQ
int "16550 UART shared IRQ number"
default 31
arch/arm/src/moxart/moxart_16550.c
+29 -1
View File
@@ -67,6 +67,30 @@ void uart_putreg(uart_addrwidth_t base, unsigned int offset, uart_datawidth_t va
*((volatile uart_addrwidth_t *)base + offset) = value;
}
void uart_decodeirq(int irq, FAR void *context)
{
int i;
uint32_t status;
static int os = 0;
status = *((volatile uart_addrwidth_t *)CONFIG_UART_MOXA_IRQ_STATUS_REG);
if ((status & 0x3f) == 0x3f)
{
return;
}
i = 0;
do
{
if (!(status & 0x1)) {
irq_dispatch(VIRQ_START + i, context);
}
status >>= 1;
}
while (++i <= 4);
}
#ifdef CONFIG_SERIAL_UART_ARCH_IOCTL
int uart_ioctl(struct file *filep, int cmd, unsigned long arg)
{
@@ -109,9 +133,12 @@ int uart_ioctl(struct file *filep, int cmd, unsigned long arg)
/* Update mode register with requested mode */
vmode = getreg32(CONFIG_UART_MOXA_MODE_REG);
putreg32(CONFIG_UART_MOXA_MODE_REG, (vmode & ~(OP_MODE_MASK << 2 * bitm_off)) | ((opmode << 2 * bitm_off) & 0xffff));
putreg32(vmode & ~(OP_MODE_MASK << 2 * bitm_off), CONFIG_UART_MOXA_MODE_REG);
vmode = opmode << 2 * bitm_off;
putreg32(getreg32(CONFIG_UART_MOXA_MODE_REG) | vmode, CONFIG_UART_MOXA_MODE_REG);
irqrestore(flags);
ret = OK;
break;
}
@@ -126,6 +153,7 @@ int uart_ioctl(struct file *filep, int cmd, unsigned long arg)
irqrestore(flags);
*(unsigned long *)arg = opmode;
ret = OK;
break;
}
}
arch/arm/src/moxart/moxart_irq.c
+13
View File
@@ -81,6 +81,8 @@ volatile uint32_t *current_regs;
* Public Functions
****************************************************************************/
extern void uart_decodeirq(int irq, uint32_t *regs);
/****************************************************************************
* Name: up_irqinitialize
*
@@ -93,6 +95,10 @@ void up_irqinitialize(void)
{
/* Prepare hardware */
*(volatile int *)0x98700000 |= 0x3f;
/* PMU setup */
(*(volatile uint32_t *)0x98100008) &= ~0x9;
while (!((*(volatile uint32_t *)0x98100008) & 0x2)) { ; }
@@ -101,6 +107,8 @@ void up_irqinitialize(void)
(*(volatile uint32_t *)0x98800100) = 0xDFF8003F;
/* Check board type */
/* Mask all interrupts off */
putreg32(0, IRQ_REG(IRQ__MASK));
@@ -119,6 +127,11 @@ void up_irqinitialize(void)
current_regs = NULL;
/* Setup UART shared interrupt */
irq_attach(CONFIG_UART_MOXA_SHARED_IRQ, uart_decodeirq);
up_enable_irq(CONFIG_UART_MOXA_SHARED_IRQ);
/* And finally, enable interrupts */
#if 1
arch/arm/src/moxart/moxart_timer.c
-3
View File
@@ -132,9 +132,6 @@ void up_timer_initialize(void)
uint32_t tmp;
// up_disable_irq(IRQ_SYSTIMER);
*(volatile int *)0x98700000 = 0x3f;
putreg32(0, TM1_ADDR + CNTL_TIMER);
putreg32(0, TM1_ADDR + INTR_STATE_TIMER);
putreg32(0x1ff, TM1_ADDR + INTR_MASK_TIMER);
arch/arm/src/nuc1xx/chip/nuc_gcr.h
+1 -1
View File
@@ -356,7 +356,7 @@
# define GCR_REGWRPROT_2 (0x16)
# define GCR_REGWRPROT_3 (0x88)
/* Read: */
#define GCR_REGWRPROT_DIS (1 << 0) /* Bit 0: Register write protectino disable index */
#define GCR_REGWRPROT_DIS (1 << 0) /* Bit 0: Register write protection disable index */
/********************************************************************************************
* Public Types
arch/arm/src/sam34/sam_dmac.c
+1 -1
View File
@@ -1225,7 +1225,7 @@ static inline int sam_multiple(struct sam_dma_s *dmach)
* Additionally, the CTRLA DONE bit is asserted when the buffer transfer has completed.
*
* The DMAC transfer continues until the CTRLB register disables the descriptor
* (DSCR bits) registers at the final buffer tranfer.
* (DSCR bits) registers at the final buffer transfer.
*
* Enable error, buffer complete and transfer complete interrupts. We
* don't really need the buffer complete interrupts, but we will take them
arch/arm/src/sam34/sam_irq.c
+20 -6
View File
@@ -78,7 +78,16 @@
* Public Data
****************************************************************************/
/* This is the address of current interrupt saved state data. Used for
* context switching. Only value during interrupt handling.
*/
volatile uint32_t *current_regs;
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern uint32_t _vectors[];
/****************************************************************************
@@ -378,16 +387,21 @@ void up_irqinitialize(void)
}
#endif
/* Set up the vector table address.
*
* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
#if defined(CONFIG_ARCH_RAMVECTORS)
up_ramvec_initialize();
#elif defined(CONFIG_SAM_BOOTLOADER)
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#endif
/* Set all interrupts (and exceptions) to the default priority */
arch/arm/src/sam34/sam_udp.c
+2 -2
View File
@@ -500,7 +500,7 @@ static const struct usb_epdesc_s g_ep0desc =
.interval = 0
};
/* Device error strings that may be enabled for more desciptive USB trace
/* Device error strings that may be enabled for more descriptive USB trace
* output.
*/
@@ -540,7 +540,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
};
#endif
/* Interrupt event strings that may be enabled for more desciptive USB trace
/* Interrupt event strings that may be enabled for more descriptive USB trace
* output.
*/
arch/arm/src/sama5/sam_can.c
+17 -9
View File
@@ -733,7 +733,10 @@ static int can_recvsetup(FAR struct sam_can_s *priv)
canvdbg("CAN%d Mailbox %d: Index=%d rxmbset=%02x\n",
config->port, mbno, mbndx, priv->rxmbset);
/* Set up the message ID and filter mask */
/* Set up the message ID and filter mask
* REVISIT: This logic should be capable of setting up standard
* filters when CONFIG_CAN_EXTID is selected.
*/
#ifdef CONFIG_CAN_EXTID
can_putreg(priv, SAM_CAN_MnID_OFFSET(mbndx),
@@ -1125,14 +1128,16 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
canvdbg("Mailbox Index=%d txmbset=%02x\n", mbndx, priv->txmbset);
/* Set up the ID and mask, standard 11-bit or extended 29-bit. */
/* Set up the ID and mask, standard 11-bit or extended 29-bit.
* REVISIT: This logic should be capable of sending standard messages
* when CONFIG_CAN_EXTID is selected.
*/
#ifdef CONFIG_CAN_EXTID
DEBUGASSERT(msg->cm_hdr.ch_extid);
DEBUGASSERT(msg->cm_hdr.ch_id < (1 << 29));
can_putreg(priv, SAM_CAN_MnID_OFFSET(mbndx), CAN_MID_EXTID(msg->cm_hdr.ch_id));
#else
DEBUGASSERT(!msg->cm_hdr.ch_extid);
DEBUGASSERT(msg->cm_hdr.ch_id < (1 << 11));
can_putreg(priv, SAM_CAN_MnID_OFFSET(mbndx), CAN_MID_STDID(msg->cm_hdr.ch_id));
#endif
@@ -1309,24 +1314,27 @@ static inline void can_rxinterrupt(FAR struct can_dev_s *dev, int mbndx,
mid = can_getreg(priv, SAM_CAN_MnID_OFFSET(mbndx));
/* Format the CAN header */
/* Format the CAN header.
* REVISIT: This logic should be capable of receiving standard messages
* when CONFIG_CAN_EXTID is selected.
*/
#ifdef CONFIG_CAN_EXTID
/* Save the extended ID of the newly received message */
hdr.ch_id = (mid & CAN_MAM_EXTID_MASK) >> CAN_MAM_EXTID_SHIFT;
hdr.ch_dlc = (msr & CAN_MSR_MDLC_MASK) >> CAN_MSR_MDLC_SHIFT;
hdr.ch_rtr = 0;
hdr.ch_extid = true;
hdr.ch_unused = 0;
#else
/* Save the standard ID of the newly received message */
hdr.ch_dlc = (msr & CAN_MSR_MDLC_MASK) >> CAN_MSR_MDLC_SHIFT;
hdr.ch_rtr = 0;
hdr.ch_id = (mid & CAN_MAM_STDID_MASK) >> CAN_MAM_STDID_SHIFT;
#endif
hdr.ch_dlc = (msr & CAN_MSR_MDLC_MASK) >> CAN_MSR_MDLC_SHIFT;
hdr.ch_rtr = 0;
hdr.ch_error = 0;
hdr.ch_unused = 0;
/* And provide the CAN message to the upper half logic */
ret = can_receive(dev, &hdr, (FAR uint8_t *)md);
arch/arm/src/sama5/sam_dmac.c
+2 -2
View File
@@ -1721,7 +1721,7 @@ static inline int sam_multiple(struct sam_dmach_s *dmach)
* buffer transfer has completed.
*
* The DMAC transfer continues until the CTRLB register disables the
* descriptor (DSCR bits) registers at the final buffer tranfer.
* descriptor (DSCR bits) registers at the final buffer transfer.
*
* Enable error, buffer complete and transfer complete interrupts. We
* don't really need the buffer complete interrupts, but we will take them
@@ -2309,7 +2309,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
dmach->callback = callback;
dmach->arg = arg;
/* Is this a single block transfer? Or a multiple block tranfer? */
/* Is this a single block transfer? Or a multiple block transfer? */
if (dmach->llhead == dmach->lltail)
{
arch/arm/src/sama5/sam_udphs.c
+5 -5
View File
@@ -555,7 +555,7 @@ static const struct usb_epdesc_s g_ep0desc =
#ifdef CONFIG_SAMA5_UDPHS_SCATTERGATHER
#ifdef CONFIG_SAMA5_UDPHS_PREALLOCATE
/* This is a properly aligned pool of preallocated DMA transfer desciptors */
/* This is a properly aligned pool of preallocated DMA transfer descriptors */
static struct sam_dtd_s g_dtdpool[CONFIG_SAMA5_UDPHS_NDTDS]
__attribute__ ((aligned(16)));
@@ -563,7 +563,7 @@ static struct sam_dtd_s g_dtdpool[CONFIG_SAMA5_UDPHS_NDTDS]
#endif
/* Device error strings that may be enabled for more desciptive USB trace
/* Device error strings that may be enabled for more descriptive USB trace
* output.
*/
@@ -604,7 +604,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
};
#endif
/* Interrupt event strings that may be enabled for more desciptive USB trace
/* Interrupt event strings that may be enabled for more descriptive USB trace
* output.
*/
@@ -1280,7 +1280,7 @@ static void sam_req_wrsetup(struct sam_usbdev_s *priv,
* When a request is queued, the request 'len' is the number of bytes
* to transfer and 'xfrd' and 'inflight' must be zero.
*
* When this function starts a tranfer it will update the request
* When this function starts a transfer it will update the request
* 'inflight' field to indicate the size of the transfer.
*
* When the transfer completes, the the 'inflight' field must hold the
@@ -1547,7 +1547,7 @@ static void sam_req_rddisable(uint8_t epno)
* - When receiving data via DMA, then data has already been transferred
* and this function is called on the terminating event. The transfer
* is complete and we just need to check for end of request events and
* if we need to setup the tranfer for the next request.
* if we need to setup the transfer for the next request.
* - When receiving via the FIFO, the transfer is not complete. The
* data is in the FIFO and must be transferred from the FIFO to the
* request buffer. No setup is needed for the next transfer other than
arch/arm/src/sama5/sam_xdmac.c
+1 -1
View File
@@ -2355,7 +2355,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
xdmach->callback = callback;
xdmach->arg = arg;
/* Is this a single block transfer? Or a multiple block tranfer? */
/* Is this a single block transfer? Or a multiple block transfer? */
if (xdmach->llhead == xdmach->lltail)
{
arch/arm/src/samdl/chip/saml_eic.h
+1 -1
View File
@@ -106,7 +106,7 @@
# define EIC_NVMICTRL_NMISENSE_HIGH (4 << EIC_NVMICTRL_NMISENSE_SHIFT) /* High level detection */
# define EIC_NVMICTRL_NMISENSE_LOW (5 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Low level detection */
#define EIC_NVMICTRL_NMIFLTEN (1 << 3) /* Bit 3: Non-maskable interrupt filter enable */
#define EIC_NVMICTRL_ASYNC (1 << 4) /* Bit 4: Asynchronous edge detectino mode */
#define EIC_NVMICTRL_ASYNC (1 << 4) /* Bit 4: Asynchronous edge detection mode */
/* Non-maskable interrupt flas status and clear register */
arch/arm/src/samdl/sam_lowputc.c
+15 -2
View File
@@ -296,6 +296,9 @@ sam_pad_configure(const struct sam_usart_config_s * const config)
#ifdef SAMDL_HAVE_USART
int sam_usart_internal(const struct sam_usart_config_s * const config)
{
#ifdef CONFIG_ARCH_FAMILY_SAML21
int channel;
#endif
int ret;
/* Enable clocking to the SERCOM module */
@@ -306,10 +309,20 @@ int sam_usart_internal(const struct sam_usart_config_s * const config)
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
sercom_coreclk_configure(config->sercom, config->gclkgen, false);
#elif defined(CONFIG_ARCH_FAMILY_SAML21)
sam_gclk_chan_enable(config->sercom + GCLK_CHAN_SERCOM0_CORE,
config->gclkgen);
if (config->sercom == 5)
{
channel = GCLK_CHAN_SERCOM5_CORE;
}
else
{
channel = config->sercom + GCLK_CHAN_SERCOM0_CORE;
}
sam_gclk_chan_enable(channel, config->gclkgen);
#endif
sercom_slowclk_configure(config->sercom, config->slowgen);
/* Set USART configuration according to the board configuration */
arch/arm/src/samdl/sam_port.c
+6 -6
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/samdl/sam_port.c
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* References:
@@ -94,7 +94,7 @@ static inline uintptr_t sam_portbase(port_pinset_t pinset)
* Name: sam_portpin
*
* Description:
* Returun the base address of the PORT register set
* Return the bit associated with the pin
*
****************************************************************************/
@@ -330,7 +330,7 @@ static inline void sam_configperiph(uintptr_t base, port_pinset_t pinset)
regval |= PORT_WRCONFIG_INEN;
}
if (pin > 16)
if (pin >= 16)
{
/* Select the upper half word and adjust the bit setting */
@@ -538,15 +538,15 @@ int sam_dumpport(uint32_t pinset, const char *msg)
/* Get the base address associated with the PIO port */
pin = sam_portpin(pinset);
pin = (pinset & PORT_PIN_MASK) >> PORT_PIN_SHIFT;
port = (pinset & PORT_MASK) >> PORT_SHIFT;
base = SAM_PORTN_BASE(port);
/* The following requires exclusive access to the PORT registers */
flags = irqsave();
lldbg("PORT%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
lldbg("PORT%c pin: %d pinset: %08x base: %08x -- %s\n",
g_portchar[port], pin, pinset, base, msg);
lldbg(" DIR: %08x OUT: %08x IN: %08x\n",
getreg32(base + SAM_PORT_DIR_OFFSET),
getreg32(base + SAM_PORT_OUT_OFFSET),
arch/arm/src/samdl/sam_port.h
+1 -1
View File
@@ -380,7 +380,7 @@ bool sam_portread(port_pinset_t pinset);
****************************************************************************/
#ifdef CONFIG_DEBUG
void sam_dumpport(port_pinset_t pinset, const char *msg);
int sam_dumpport(port_pinset_t pinset, const char *msg);
#else
# define sam_dumpport(p,m)
#endif
arch/arm/src/samdl/sam_spi.c
+18
View File
@@ -1467,6 +1467,9 @@ struct spi_dev_s *up_spiinitialize(int port)
struct sam_spidev_s *priv;
irqstate_t flags;
uint32_t regval;
#ifdef CONFIG_ARCH_FAMILY_SAML21
int channel;
#endif
#if 0 /* Not used */
int ret;
#endif
@@ -1534,7 +1537,22 @@ struct spi_dev_s *up_spiinitialize(int port)
/* Configure the GCLKs for the SERCOM module */
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
sercom_coreclk_configure(priv->sercom, priv->gclkgen, false);
#elif defined(CONFIG_ARCH_FAMILY_SAML21)
if (priv->sercom == 5)
{
channel = GCLK_CHAN_SERCOM5_CORE;
}
else
{
channel = priv->sercom + GCLK_CHAN_SERCOM0_CORE;
}
sam_gclk_chan_enable(channel, config->gclkgen);
#endif
sercom_slowclk_configure(priv->sercom, priv->slowgen);
/* Set the SERCOM in SPI master mode (no address) */
arch/arm/src/samv7/Kconfig
+770 -20
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/samv7/Make.defs
+13 -3
View File
@@ -124,12 +124,18 @@ ifeq ($(CONFIG_SAMV7_XDMAC),y)
CHIP_CSRCS += sam_xdmac.c
endif
ifeq ($(CONFIG_SAMV7_SPI0),y)
CHIP_CSRCS += sam_spi.c
else ifeq ($(CONFIG_SAMV7_SPI1),y)
ifeq ($(CONFIG_SAMV7_SPI_MASTER),y)
CHIP_CSRCS += sam_spi.c
endif
ifeq ($(CONFIG_SAMV7_SPI_SLAVE),y)
CHIP_CSRCS += sam_spi_slave.c
endif
ifeq ($(CONFIG_SAMV7_QSPI),y)
CHIP_CSRCS += sam_qspi.c
endif
ifeq ($(CONFIG_SAMV7_TWIHS0),y)
CHIP_CSRCS += sam_twihs.c
else ifeq ($(CONFIG_SAMV7_TWIHS1),y)
@@ -150,6 +156,10 @@ ifeq ($(CONFIG_SAMV7_EMAC),y)
CHIP_CSRCS += sam_emac.c sam_ethernet.c
endif
ifeq ($(CONFIG_SAMV7_MCAN),y)
CHIP_CSRCS += sam_mcan.c
endif
ifeq ($(CONFIG_SAMV7_USBDEVHS),y)
CHIP_CSRCS += sam_usbdevhs.c
endif
arch/arm/src/samv7/chip/sam_matrix.h
+2 -1
View File
@@ -258,6 +258,7 @@
/* CAN0 Configuration Register */
#define MATRIX_CAN0_RESERVED 0x000001ff /* Bits 0-9: Reserved */
#define MATRIX_CAN0_CAN0DMABA_MASK 0xffff0000 /* Bits 16-31: CAN0 DMA Base Address */
/* System I/O and CAN1 Configuration Register */
@@ -268,7 +269,7 @@
# define MATRIX_CCFG_SYSIO_SYSIO6 (1 << 6) /* Bit 6: PB6 or TMS/SWDIO Assignment */
# define MATRIX_CCFG_SYSIO_SYSIO7 (1 << 7) /* Bit 7: PB7 or TCK/SWCLK Assignment */
# define MATRIX_CCFG_SYSIO_SYSIO12 (1 << 12) /* Bit 12: PB12 or ERASE Assignment */
#define MATRIX_CAN0_CAN1DMABA_MASK 0xffff0000 /* Bits 16-31: CAN1 DMA Base Address */
#define MATRIX_CCFG_CAN1DMABA_MASK 0xffff0000 /* Bits 16-31: CAN1 DMA Base Address */
/* SMC Chip Select NAND Flash Assignment Register */
arch/arm/src/samv7/chip/sam_mcan.h
+146 -9
View File
@@ -67,7 +67,7 @@
#define SAM_MCAN_ECR_OFFSET 0x0040 /* Error Counter Register */
#define SAM_MCAN_PSR_OFFSET 0x0044 /* Protocol Status Register */
/* 0x0048-0x004c Reserved */
#define SAM_MCAN_IR_OFFSET 0x0050 /* Interrupt Register*/
#define SAM_MCAN_IR_OFFSET 0x0050 /* Interrupt Register*/
#define SAM_MCAN_IE_OFFSET 0x0054 /* Interrupt Enable Register */
#define SAM_MCAN_ILS_OFFSET 0x0058 /* Interrupt Line Select Register */
#define SAM_MCAN_ILE_OFFSET 0x005c /* Interrupt Line Enable Register */
@@ -214,7 +214,7 @@
#define MCAN_FBTP_FBRP_SHIFT (16) /* Bits 16-20: Fast Baud Rate Prescaler */
#define MCAN_FBTP_FBRP_MASK (31 << MCAN_FBTP_FBRP_SHIFT)
# define MCAN_FBTP_FBRP(n) ((uint32_t)(n) << MCAN_FBTP_FBRP_SHIFT)
#define MCAN_FBTP_TDCO (1 << 23) /* Bit: 23: Transceiver Delay Compensation */
#define MCAN_FBTP_TDC (1 << 23) /* Bit: 23: Transceiver Delay Compensation */
#define MCAN_FBTP_TDCO_SHIFT (24) /* Bits 24-28: Transceiver Delay Compensation Offset */
#define MCAN_FBTP_TDCO_MASK (31 << MCAN_FBTP_TDC_SHIFT)
# define MCAN_FBTP_TDCO(n) ((uint32_t)(n) << MCAN_FBTP_TDC_SHIFT)
@@ -360,7 +360,7 @@
/* Common bit definitions for Interrupt Register, Interrupt Enable Register, Interrupt
* Line Select Register
*/
*/
#define MCAN_INT_RF0N (1 << 0) /* Bit 0: Receive FIFO 0 New Message */
#define MCAN_INT_RF0W (1 << 1) /* Bit 1: Receive FIFO 0 Watermark Reached */
@@ -370,7 +370,7 @@
#define MCAN_INT_RF1W (1 << 5) /* Bit 5: Receive FIFO 1 Watermark Reached */
#define MCAN_INT_RF1F (1 << 6) /* Bit 6: Receive FIFO 1 Full */
#define MCAN_INT_RF1L (1 << 7) /* Bit 7: Receive FIFO 1 Message Lost */
#define MCAN_INT_HPM (1 << 8) /* Bit 8: High Priority Message */
#define MCAN_INT_HPM (1 << 8) /* Bit 8: High Priority Message Received */
#define MCAN_INT_TC (1 << 9) /* Bit 9: Transmission Completed */
#define MCAN_INT_TCF (1 << 10) /* Bit 10: Transmission Cancellation Finished */
#define MCAN_INT_TFE (1 << 11) /* Bit 11: Tx FIFO Empty */
@@ -387,12 +387,14 @@
#define MCAN_INT_EW (1 << 24) /* Bit 24: Warning Status */
#define MCAN_INT_BO (1 << 25) /* Bit 25: Bus_Off Status */
#define MCAN_INT_WDI (1 << 26) /* Bit 26: Watchdog Interrupt */
#define MCAN_INT_CRCE (1 << 27) /* Bit 27: CRC Error */
#define MCAN_INT_CRCE (1 << 27) /* Bit 27: Receive CRC Error */
#define MCAN_INT_BE (1 << 28) /* Bit 28: Bit Error */
#define MCAN_INT_ACKE (1 << 29) /* Bit 29: Acknowledge Error */
#define MCAN_INT_FOE (1 << 30) /* Bit 30: Format Error */
#define MCAN_INT_STE (1 << 31) /* Bit 31: Stuff Error */
#define MCAN_INT_ALL (0xffcfffff)
/* Interrupt Line Enable Register */
#define MCAN_ILE_EINT0 (1 << 0) /* Bit 0: Enable Interrupt Line 0 */
@@ -442,10 +444,10 @@
# define MCAN_HPMS_BIDX(n) ((uint32_t)(n) << MCAN_HPMS_BIDX_SHIFT)
#define MCAN_HPMS_MSI_SHIFT (6) /* Bits 6-7: Message Storage Indicator */
#define MCAN_HPMS_MSI_MASK (3 << MCAN_HPMS_MSI_SHIFT)
# define MCAN_HPMS_MSI_ NOFIFO (0 << MCAN_HPMS_MSI_SHIFT) /* No FIFO selected. */
# define MCAN_HPMS_MSI_ LOST (1 << MCAN_HPMS_MSI_SHIFT) /* FIFO message. */
# define MCAN_HPMS_MSI_ FIFO0 (2 << MCAN_HPMS_MSI_SHIFT) /* Message stored in FIFO 0. */
# define MCAN_HPMS_MSI_ FIFO1 (3 << MCAN_HPMS_MSI_SHIFT) /* Message stored in FIFO 1. */
# define MCAN_HPMS_MSI_NOFIFO (0 << MCAN_HPMS_MSI_SHIFT) /* No FIFO selected. */
# define MCAN_HPMS_MSI_LOST (1 << MCAN_HPMS_MSI_SHIFT) /* FIFO message. */
# define MCAN_HPMS_MSI_FIFO0 (2 << MCAN_HPMS_MSI_SHIFT) /* Message stored in FIFO 0. */
# define MCAN_HPMS_MSI_FIFO1 (3 << MCAN_HPMS_MSI_SHIFT) /* Message stored in FIFO 1. */
#define MCAN_HPMS_FIDX_SHIFT (8) /* Bits 8-14: Filter Index */
#define MCAN_HPMS_FIDX_MASK (0x7f << MCAN_HPMS_FIDX_SHIFT)
# define MCAN_HPMS_FIDX(n) ((uint32_t)(n) << MCAN_HPMS_FIDX_SHIFT)
@@ -535,6 +537,7 @@
#define MCAN_RXESC_F0DS_SHIFT (0) /* Bits 0-2: Receive FIFO 0 Data Field Size */
#define MCAN_RXESC_F0DS_MASK (7 << MCAN_RXESC_F0DS_SHIFT)
# define MCAN_RXESC_F0DS(n) ((uint32_t)(n) << MCAN_RXESC_F0DS_SHIFT)
# define MCAN_RXESC_F0DS_8B (0 << MCAN_RXESC_F0DS_SHIFT) /* 8-byte data field */
# define MCAN_RXESC_F0DS_12B (1 << MCAN_RXESC_F0DS_SHIFT) /* 12-byte data field */
# define MCAN_RXESC_F0DS_16B (2 << MCAN_RXESC_F0DS_SHIFT) /* 16-byte data field */
@@ -545,6 +548,7 @@
# define MCAN_RXESC_F0DS_64B (7 << MCAN_RXESC_F0DS_SHIFT) /* 64-byte data field */
#define MCAN_RXESC_F1DS_SHIFT (4) /* Bits 4-6: Receive FIFO 1 Data Field Size */
#define MCAN_RXESC_F1DS_MASK (7 << MCAN_RXESC_F1DS_SHIFT)
# define MCAN_RXESC_F1DS(n) ((uint32_t)(n) << MCAN_RXESC_F1DS_SHIFT)
# define MCAN_RXESC_F1DS_8B (0 << MCAN_RXESC_F1DS_SHIFT) /* 8-byte data field */
# define MCAN_RXESC_F1DS_12B (1 << MCAN_RXESC_F1DS_SHIFT) /* 12-byte data field */
# define MCAN_RXESC_F1DS_16B (2 << MCAN_RXESC_F1DS_SHIFT) /* 16-byte data field */
@@ -555,6 +559,7 @@
# define MCAN_RXESC_F1DS_64B (7 << MCAN_RXESC_F1DS_SHIFT) /* 64-byte data field */
#define MCAN_RXESC_RBDS_SHIFT (8) /* Bits 8-10: Receive Buffer Data Field Size */
#define MCAN_RXESC_RBDS_MASK (7 << MCAN_RXESC_RBDS_SHIFT)
# define MCAN_RXESC_RBDS(n) ((uint32_t)(n) << MCAN_RXESC_RBDS_SHIFT)
# define MCAN_RXESC_RBDS_8B (0 << MCAN_RXESC_RBDS_SHIFT) /* 8-byte data field */
# define MCAN_RXESC_RBDS_12B (1 << MCAN_RXESC_RBDS_SHIFT) /* 12-byte data field */
# define MCAN_RXESC_RBDS_16B (2 << MCAN_RXESC_RBDS_SHIFT) /* 16-byte data field */
@@ -594,6 +599,7 @@
#define MCAN_TXESC_TBDS_SHIFT (0) /* Bits 0-2: Tx Buffer Data Field Size */
#define MCAN_TXESC_TBDS_MASK (7 << MCAN_TXESC_TBDS_SHIFT)
# define MCAN_TXESC_TBDS(n) ((uint32_t)(n) << MCAN_TXESC_TBDS_SHIFT)
# define MCAN_TXESC_TBDS_8B (0 << MCAN_TXESC_TBDS_SHIFT) /* 8-byte data field */
# define MCAN_TXESC_TBDS_12B (1 << MCAN_TXESC_TBDS_SHIFT) /* 12-byte data field */
# define MCAN_TXESC_TBDS_16B (2 << MCAN_TXESC_TBDS_SHIFT) /* 16-byte data field */
@@ -661,6 +667,137 @@
#define MCAN_TXEFA_MASK 0x0000001f /* Event fifo acknowledge index mask */
/* Message RAM Definitions **************************************************************/
/* Common Buffer and FIFO element bit definitions:
*
* --------------- ------------------- --------------------------------
* RESOURCE R0 R1
* --------------- ------------------- --------------------------------
* RX Buffer: ESI, XTD, RTR, ID, ANMF, FIDX, EDL, BRS, DLC, RXTS
* RX FIFO: ESI, XTD, RTR, ID, ANMF, FIDX, EDL, BRS, DLC, RXTS
* TX buffer: XTD, RTR, ID, MM, EFC, DLC
* TX Event FIFO: ESI, XTD, RTR, ID, MM, ET, EDL, BRS, DLC, TXTS
* --------------- ------------------- --------------------------------
*/
/* Common */
#define BUFFER_R0_EXTID_SHIFT (0) /* Bits 0-28: Extended identifer */
#define BUFFER_R0_EXTID_MASK (0x1fffffff << BUFFER_R0_EXTID_SHIFT)
# define BUFFER_R0_EXTID(n) ((uint32_t)(n) << BUFFER_R0_EXTID_SHIFT)
#define BUFFER_R0_STDID_SHIFT (18) /* Bits 18-28: Standard idendifier */
#define BUFFER_R0_STDID_MASK (0x7ff << BUFFER_R0_STDID_SHIFT)
# define BUFFER_R0_STDID(n) ((uint32_t)(n) << BUFFER_R0_STDID_SHIFT)
#define BUFFER_R0_RTR (1 << 29) /* Bit 29: Remote Transmission Request */
#define BUFFER_R0_XTD (1 << 30) /* Bit 30: Extended Identifier */
#define BUFFER_R0_ESI (1 << 31) /* Bit 31: Error State Indicator */
/* Common */
#define BUFFER_R1_DLC_SHIFT (16) /* Bits 16-19: Date length code */
#define BUFFER_R1_DLC_MASK (15 << BUFFER_R1_DLC_SHIFT)
# define BUFFER_R1_DLC(n) ((uint32_t)(n) << BUFFER_R1_DLC_SHIFT)
#define BUFFER_R1_BRS (1 << 20) /* Bit 20: Bit Rate Switch */
#define BUFFER_R1_EDL (1 << 21) /* Bit 21: Extended Data Length */
/* RX buffer/RX FIFOs */
#define BUFFER_R1_RXTS_SHIFT (0) /* Bits 0-15: RX Timestamp */
#define BUFFER_R1_RXTS_MASK (0xffff << BUFFER_R1_RXTS_SHIFT)
# define BUFFER_R1_RXTS(n) ((uint32_t)(n) << BUFFER_R1_RXTS_SHIFT)
#define BUFFER_R1_FIDX_SHIFT (24) /* Bits 24-30: Filter index */
#define BUFFER_R1_FIDX_MASK (0x7f << BUFFER_R1_FIDX_SHIFT)
# define BUFFER_R1_FIDX(n) ((uint32_t)(n) << BUFFER_R1_FIDX_SHIFT)
#define BUFFER_R1_ANMF (1 << 31) /* Bit 31: Accepted Non-matching Frame */
/* TX buffer/TX Event FIFO */
#define BUFFER_R1_MM_SHIFT (24) /* Bits 24-31: Message Marker */
#define BUFFER_R1_MM_MASK (0xffff << BUFFER_R1_MM_SHIFT)
# define BUFFER_R1_MM(n) ((uint32_t)(n) << BUFFER_R1_MM_SHIFT)
/* TX buffer */
#define BUFFER_R1_EFC (1 << 23) /* Bit 23: Event FIFO Control */
/* TX Event FIFO */
#define BUFFER_R1_TXTS_SHIFT (0) /* Bits 0-15: TX Timestamp */
#define BUFFER_R1_TXTS_MASK (0xffff << BUFFER_R1_TXTS_SHIFT)
# define BUFFER_R1_TXTS(n) ((uint32_t)(n) << BUFFER_R1_TXTS_SHIFT)
#define BUFFER_R1_ET_SHIFT (22) /* Bits 22-23: Event Type */
#define BUFFER_R1_ET_MASK (15 << BUFFER_R1_ET_SHIFT)
# define BUFFER_R1_ET_TXEVENT (1 << BUFFER_R1_ET_SHIFT) /* Tx event */
# define BUFFER_R1_ET_TXCANCEL (2 << BUFFER_R1_ET_SHIFT) /* Transmission despite cancellation */
/* Standard Message ID Filter Element */
#define STDFILTER_S0_SFID2_SHIFT (0) /* Bits 0-10: Standard Filter ID 2 */
#define STDFILTER_S0_SFID2_MASK (0x3ff << STDFILTER_S0_SFID2_SHIFT)
# define STDFILTER_S0_SFID2(n) ((uint32_t)(n) << STDFILTER_S0_SFID2_SHIFT)
#define STDFILTER_S0_BUFFER_SHIFT (0) /* Bits 0-5: RX buffer start address */
#define STDFILTER_S0_BUFFER_MASK (0x3f << STDFILTER_S0_BUFFER_SHIFT)
# define STDFILTER_S0_BUFFER(n) ((uint32_t)(n) << STDFILTER_S0_BUFFER_SHIFT)
#define STDFILTER_S0_ACTION_SHIFT (9) /* Bits 9-10: Action taken */
#define STDFILTER_S0_ACTION_MASK (3 << STDFILTER_S0_ACTION_SHIFT)
# define STDFILTER_S0_RXBUFFER (0 << STDFILTER_S0_ACTION_SHIFT) /* Store message in a Rx buffer */
# define STDFILTER_S0_DEBUGA (1 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message A */
# define STDFILTER_S0_DEBUGB (2 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message B */
# define STDFILTER_S0_DEBUGC (3 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message C */
#define STDFILTER_S0_SFID1_SHIFT (16) /* Bits 16-26: Standard Filter ID 2 */
#define STDFILTER_S0_SFID1_MASK (0x3ff << STDFILTER_S0_SFID1_SHIFT)
# define STDFILTER_S0_SFID1(n) ((uint32_t)(n) << STDFILTER_S0_SFID1_SHIFT)
#define STDFILTER_S0_SFEC_SHIFT (17) /* Bits 27-29: Standard Filter Element Configuration */
#define STDFILTER_S0_SFEC_MASK (7 << STDFILTER_S0_SFEC_SHIFT)
# define STDFILTER_S0_SFEC_DISABLE (0 << STDFILTER_S0_SFEC_SHIFT) /* Disable filter element */
# define STDFILTER_S0_SFEC_FIFO0 (1 << STDFILTER_S0_SFEC_SHIFT) /* Store in Rx FIFO 0 on match */
# define STDFILTER_S0_SFEC_FIFO1 (2 << STDFILTER_S0_SFEC_SHIFT) /* Store in Rx FIFO 1 on match */
# define STDFILTER_S0_SFEC_REJECT (3 << STDFILTER_S0_SFEC_SHIFT) /* Reject ID on match */
# define STDFILTER_S0_SFEC_PRIORITY (4 << STDFILTER_S0_SFEC_SHIFT) /* Set priority ion match */
# define STDFILTER_S0_SFEC_PRIOFIFO0 (5 << STDFILTER_S0_SFEC_SHIFT) /* Set priority and store in FIFO 0 on match */
# define STDFILTER_S0_SFEC_PRIOFIFO1 (6 << STDFILTER_S0_SFEC_SHIFT) /* Set priority and store in FIFO 1 on match */
# define STDFILTER_S0_SFEC_BUFFER (7 << STDFILTER_S0_SFEC_SHIFT) /* Store into Rx Buffer or as debug message */
#define STDFILTER_S0_SFT_SHIFT (30) /* Bits 30-31: Standard Filter Type */
#define STDFILTER_S0_SFT_MASK (3 << STDFILTER_S0_SFT_SHIFT)
# define STDFILTER_S0_SFT_RANGE (0 << STDFILTER_S0_SFT_SHIFT) /* Range filter from SF1ID to SF2ID */
# define STDFILTER_S0_SFT_DUAL (1 << STDFILTER_S0_SFT_SHIFT) /* Dual ID filter for SF1ID or SF2ID */
# define STDFILTER_S0_SFT_CLASSIC (2 << STDFILTER_S0_SFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */
/* Extended Message ID Filter Element */
#define EXTFILTER_F0_EFID1_SHIFT (0) /* Bits 0-28: Extended Filter ID 1 */
#define EXTFILTER_F0_EFID1_MASK (0x1fffffff << EXTFILTER_F0_EFID1_SHIFT)
# define EXTFILTER_F0_EFID1(n) ((uint32_t)(n) << EXTFILTER_F0_EFID1_SHIFT)
#define EXTFILTER_F0_EFEC_SHIFT (29) /* Bits 29-31: Extended Filter Element Configuration */
#define EXTFILTER_F0_EFEC_MASK (7 << EXTFILTER_F0_EFEC_SHIFT)
# define EXTFILTER_F0_EFEC_DISABLE (0 << EXTFILTER_F0_EFEC_SHIFT) /* Disable filter element */
# define EXTFILTER_F0_EFEC_FIFO0 (1 << EXTFILTER_F0_EFEC_SHIFT) /* Store in Rx FIFO 0 on match */
# define EXTFILTER_F0_EFEC_FIFO1 (2 << EXTFILTER_F0_EFEC_SHIFT) /* Store in Rx FIFO 1 on match */
# define EXTFILTER_F0_EFEC_REJECT (3 << EXTFILTER_F0_EFEC_SHIFT) /* Reject ID on match */
# define EXTFILTER_F0_EFEC_PRIORITY (4 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority on match */
# define EXTFILTER_F0_EFEC_PRIOFIFO0 (5 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority and store in FIFO 0 on match */
# define EXTFILTER_F0_EFEC_PRIOFIFO1 (6 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority and store in FIFO 1 on match */
# define EXTFILTER_F0_EFEC_BUFFER (7 << EXTFILTER_F0_EFEC_SHIFT) /* Store into Rx Buffer or as debug message */
#define EXTFILTER_F1_EFID2_SHIFT (0) /* Bits 0-28: Extended Filter ID 2 */
#define EXTFILTER_F1_EFID2_MASK (0x1fffffff << EXTFILTER_F1_EFID2_SHIFT)
# define EXTFILTER_F1_EFID2(n) ((uint32_t)(n) << EXTFILTER_F1_EFID2_SHIFT)
#define EXTFILTER_F1_BUFFER_SHIFT (0) /* Bits 0-5: RX buffer start address */
#define EXTFILTER_F1_BUFFER_MASK (0x3f << EXTFILTER_F1_BUFFER_SHIFT)
# define EXTFILTER_F1_BUFFER(n) ((uint32_t)(n) << EXTFILTER_F1_BUFFER_SHIFT)
#define EXTFILTER_F1_ACTION_SHIFT (9) /* Bits 9-10: Action taken */
#define EXTFILTER_F1_ACTION_MASK (3 << EXTFILTER_F1_ACTION_SHIFT)
# define EXTFILTER_F1_RXBUFFER (0 << EXTFILTER_F1_ACTION_SHIFT) /* Store message in a Rx buffer */
# define EXTFILTER_F1_DEBUGA (1 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message A */
# define EXTFILTER_F1_DEBUGB (2 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message B */
# define EXTFILTER_F1_DEBUGC (3 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message C */
#define EXTFILTER_F1_EFT_SHIFT (30) /* Bits 30-31: Extended Filter Type */
#define EXTFILTER_F1_EFT_MASK (3 << EXTFILTER_F1_EFT_SHIFT)
# define EXTFILTER_F1_EFT_RANGE (0 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from SF1ID to SF2ID */
# define EXTFILTER_F1_EFT_DUAL (1 << EXTFILTER_F1_EFT_SHIFT) /* Dual ID filter for SF1ID or SF2ID */
# define EXTFILTER_F1_EFT_CLASSIC (2 << EXTFILTER_F1_EFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */
# define EXTFILTER_F1_EFT_NOXIDAM (2 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from EF1ID to EF2ID, no XIDAM */
/****************************************************************************************
* Public Types
****************************************************************************************/
arch/arm/src/samv7/chip/sam_qspi.h
+272
View File
@@ -0,0 +1,272 @@
/****************************************************************************************
* arch/arm/src/samv7/chip/sam_qspi.h
* Quad SPI (QSPI) definitions for the SAMV71
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_QSPI_H
#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_QSPI_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include <arch/samv7/chip.h>
#include "chip/sam_memorymap.h"
#if SAMV7_NQSPI > 0
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* General Characteristics **************************************************************/
#define SAM_QSPI_MINBITS 8 /* Minimum word width */
#define SAM_QSPI_MAXBITS 16 /* Maximum word width */
/* QSPI register offsets ****************************************************************/
#define SAM_QSPI_CR_OFFSET 0x0000 /* Control Register */
#define SAM_QSPI_MR_OFFSET 0x0004 /* Mode Register */
#define SAM_QSPI_RDR_OFFSET 0x0008 /* Receive Data Register */
#define SAM_QSPI_TDR_OFFSET 0x000c /* Transmit Data Register */
#define SAM_QSPI_SR_OFFSET 0x0010 /* Status Register */
#define SAM_QSPI_IER_OFFSET 0x0014 /* Interrupt Enable Register */
#define SAM_QSPI_IDR_OFFSET 0x0018 /* Interrupt Disable Register */
#define SAM_QSPI_IMR_OFFSET 0x001c /* Interrupt Mask Register */
#define SAM_QSPI_SCR_OFFSET 0x0020 /* Serial Clock Register */
#define SAM_QSPI_IAR_OFFSET 0x0030 /* Instruction Address Register */
#define SAM_QSPI_ICR_OFFSET 0x0034 /* Instruction Code Register */
#define SAM_QSPI_IFR_OFFSET 0x0038 /* Instruction Frame Register */
/* 0x003c Reserved */
#define SAM_QSPI_SMR_OFFSET 0x0040 /* Scrambling Mode Register */
#define SAM_QSPI_SKR_OFFSET 0x0044 /* Scrambling Key Register */
/* 0x0048–0x00e0 Reserved */
#define SAM_QSPI_WPCR_OFFSET 0x00e4 /* Write Protection Control Register */
#define SAM_QSPI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */
/* 0xec-0xfc: Reserved */
/* QSPI register addresses **************************************************************/
#define SAM_QSPI0_CR (SAM_QSPI0_BASE+SAM_QSPI_CR_OFFSET) /* Control Register */
#define SAM_QSPI0_MR (SAM_QSPI0_BASE+SAM_QSPI_MR_OFFSET) /* Mode Register */
#define SAM_QSPI0_RDR (SAM_QSPI0_BASE+SAM_QSPI_RDR_OFFSET) /* Receive Data Register */
#define SAM_QSPI0_TDR (SAM_QSPI0_BASE+SAM_QSPI_TDR_OFFSET) /* Transmit Data Register */
#define SAM_QSPI0_SR (SAM_QSPI0_BASE+SAM_QSPI_SR_OFFSET) /* Status Register */
#define SAM_QSPI0_IER (SAM_QSPI0_BASE+SAM_QSPI_IER_OFFSET) /* Interrupt Enable Register */
#define SAM_QSPI0_IDR (SAM_QSPI0_BASE+SAM_QSPI_IDR_OFFSET) /* Interrupt Disable Register */
#define SAM_QSPI0_IMR (SAM_QSPI0_BASE+SAM_QSPI_IMR_OFFSET) /* Interrupt Mask Register */
#define SAM_QSPI0_SCR (SAM_QSPI0_BASE+SAM_QSPI_SCR_OFFSET) /* Serial Clock Register */
#define SAM_QSPI0_IAR (SAM_QSPI0_BASE+SAM_QSPI_IAR_OFFSET) /* Instruction Address Register */
#define SAM_QSPI0_ICR (SAM_QSPI0_BASE+SAM_QSPI_ICR_OFFSET) /* Instruction Code Register */
#define SAM_QSPI0_IFR (SAM_QSPI0_BASE+SAM_QSPI_IFR_OFFSET) /* Instruction Frame Register */
#define SAM_QSPI0_SMR (SAM_QSPI0_BASE+SAM_QSPI_SMR_OFFSET) /* Scrambling Mode Register */
#define SAM_QSPI0_SKR (SAM_QSPI0_BASE+SAM_QSPI_SKR_OFFSET) /* Scrambling Key Register */
#define SAM_QSPI0_WPCR (SAM_QSPI0_BASE+SAM_QSPI_WPCR_OFFSET) /* Write Protection Control Register */
#define SAM_QSPI0_WPSR (SAM_QSPI0_BASE+SAM_QSPI_WPSR_OFFSET) /* Write Protection Status Register */
#if SAMV7_NQSPI > 1
# define SAM_QSPI1_CR (SAM_QSPI1_BASE+SAM_QSPI_CR_OFFSET) /* Control Register */
# define SAM_QSPI1_MR (SAM_QSPI1_BASE+SAM_QSPI_MR_OFFSET) /* Mode Register */
# define SAM_QSPI1_RDR (SAM_QSPI1_BASE+SAM_QSPI_RDR_OFFSET) /* Receive Data Register */
# define SAM_QSPI1_TDR (SAM_QSPI1_BASE+SAM_QSPI_TDR_OFFSET) /* Transmit Data Register */
# define SAM_QSPI1_SR (SAM_QSPI1_BASE+SAM_QSPI_SR_OFFSET) /* Status Register */
# define SAM_QSPI1_IER (SAM_QSPI1_BASE+SAM_QSPI_IER_OFFSET) /* Interrupt Enable Register */
# define SAM_QSPI1_IDR (SAM_QSPI1_BASE+SAM_QSPI_IDR_OFFSET) /* Interrupt Disable Register */
# define SAM_QSPI1_IMR (SAM_QSPI1_BASE+SAM_QSPI_IMR_OFFSET) /* Interrupt Mask Register */
# define SAM_QSPI1_SCR (SAM_QSPI1_BASE+SAM_QSPI_SCR_OFFSET) /* Serial Clock Register */
# define SAM_QSPI1_IAR (SAM_QSPI1_BASE+SAM_QSPI_IAR_OFFSET) /* Instruction Address Register */
# define SAM_QSPI1_ICR (SAM_QSPI1_BASE+SAM_QSPI_ICR_OFFSET) /* Instruction Code Register */
# define SAM_QSPI1_IFR (SAM_QSPI1_BASE+SAM_QSPI_IFR_OFFSET) /* Instruction Frame Register */
# define SAM_QSPI1_SMR (SAM_QSPI1_BASE+SAM_QSPI_SMR_OFFSET) /* Scrambling Mode Register */
# define SAM_QSPI1_SKR (SAM_QSPI1_BASE+SAM_QSPI_SKR_OFFSET) /* Scrambling Key Register */
# define SAM_QSPI1_WPCR (SAM_QSPI1_BASE+SAM_QSPI_WPCR_OFFSET) /* Write Protection Control Register */
# define SAM_QSPI1_WPSR (SAM_QSPI1_BASE+SAM_QSPI_WPSR_OFFSET) /* Write Protection Status Register */
#endif
/* QSPI register bit definitions ********************************************************/
/* QSPI Control Register */
#define QSPI_CR_QSPIEN (1 << 0) /* Bit 0: QSPI Enable */
#define QSPI_CR_QSPIDIS (1 << 1) /* Bit 1: QSPI Disable */
#define QSPI_CR_SWRST (1 << 7) /* Bit 7: QSPI Software Reset */
#define QSPI_CR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
/* QSPI Mode Register */
#define QSPI_MR_SMM (1 << 0) /* Bit 0: Serial Memory Mode */
#define QSPI_MR_LLB (1 << 1) /* Bit 1: Local Loopback Enable */
#define QSPI_MR_WDRBT (1 << 2) /* Bit 2: Wait Data Read Before Transfer */
#define QSPI_MR_CSMODE_SHIFT (4) /* Bits 4-5: Chip Select Mode */
#define QSPI_MR_CSMODE_MASK (3 << QSPI_MR_PCS_SHIFT)
# define QSPI_MR_CSMODE_NRELOAD (0 << QSPI_MR_PCS_SHIFT) /* CS deasserted if TD not reloaded */
# define QSPI_MR_CSMODE_LASTXFER (1 << QSPI_MR_PCS_SHIFT) /* CS deasserted when LASTXFER transferred */
# define QSPI_MR_CSMODE_SYSTEM (2 << QSPI_MR_PCS_SHIFT) /* CS deasserted after each transfer */
#define QSPI_MR_NBBITS_SHIFT (8) /* Bits 8-11: Number Of Bits Per Transfer */
#define QSPI_MR_NBBITS_MASK (15 << QSPI_MR_NBBITS_SHIFT)
# define QSPI_MR_NBBITS(n) ((uint32_t)((n)-SAM_QSPI_MINBITS) << QSPI_MR_NBBITS_SHIFT)
# define QSPI_MR_NBBITS_8BIT (0 << QSPI_MR_NBBITS_SHIFT) /* 8 bits for transfer */
# define QSPI_MR_NBBITS_9BIT (1 << QSPI_MR_NBBITS_SHIFT) /* 9 bits for transfer */
# define QSPI_MR_NBBITS_10BIT (2 << QSPI_MR_NBBITS_SHIFT) /* 10 bits for transfer */
# define QSPI_MR_NBBITS_11BIT (3 << QSPI_MR_NBBITS_SHIFT) /* 11 bits for transfer */
# define QSPI_MR_NBBITS_12BIT (4 << QSPI_MR_NBBITS_SHIFT) /* 12 bits for transfer */
# define QSPI_MR_NBBITS_13BIT (5 << QSPI_MR_NBBITS_SHIFT) /* 13 bits for transfer */
# define QSPI_MR_NBBITS_14BIT (6 << QSPI_MR_NBBITS_SHIFT) /* 14 bits for transfer */
# define QSPI_MR_NBBITS_15BIT (7 << QSPI_MR_NBBITS_SHIFT) /* 15 bits for transfer */
# define QSPI_MR_NBBITS_16BIT (8 << QSPI_MR_NBBITS_SHIFT) /* 16 bits for transfer */
#define QSPI_MR_DLYBCT_SHIFT (16) /* Bits 16-23: Delay Between Consecutive Transfers */
#define QSPI_MR_DLYBCT_MASK (0xff << QSPI_MR_DLYBCT_SHIFT)
# define QSPI_MR_DLYBCT(n) ((uint32_t)(n) << QSPI_MR_DLYBCT_SHIFT)
#define QSPI_MR_DLYCS_SHIFT (24) /* Bits 24-31: Minimum Inactive QCS Delay */
#define QSPI_MR_DLYCS_MASK (0xff << QSPI_MR_DLYCS_SHIFT)
# define QSPI_MR_DLYCS(n) ((uint32_t)(n) << QSPI_MR_DLYCS_SHIFT)
/* QSPI Receive Data Register */
#define QSPI_RDR_RD_SHIFT (0) /* Bits 0-15: Receive Data */
#define QSPI_RDR_RD_MASK (0xffff << QSPI_RDR_RD_SHIFT)
/* QSPI Transmit Data Register */
#define QSPI_TDR_TD_SHIFT (0) /* Bits 0-15: Transmit Data */
#define QSPI_TDR_TD_MASK (0xffff << QSPI_TDR_TD_SHIFT)
/* QSPI Status Register, QSPI Interrupt Enable Register, QSPI Interrupt Disable Register,
* and QSPI Interrupt Mask Register (common bit fields)
*/
#define QSPI_INT_RDRF (1 << 0) /* Bit 0: Receive Data Register Full Interrupt */
#define QSPI_INT_TDRE (1 << 1) /* Bit 1: Transmit Data Register Empty Interrupt */
#define QSPI_INT_TXEMPTY (1 << 2) /* Bit 2: Transmission Registers Empty Interrupt */
#define QSPI_INT_OVRES (1 << 3) /* Bit 3: Overrun Error Interrupt */
#define QSPI_INT_CSR (1 << 8) /* Bit 8: Chip Select Rise Interrupt */
#define QSPI_SR_CSS (1 << 9) /* Bit 9: Chip Select Status Interrupt */
#define QSPI_SR_INTSTRE (1 << 10) /* Bit 10: Instruction End Status Interrupt */
#define QSPI_SR_QSPIENS (1 << 24) /* Bit 24: QSPI Enable Status (SR only) */
#define QSPI_INT_ALL (0x0000070f)
/* Serial Clock Register */
#define QSPI_SCR_CPOL (1 << 0) /* Bit 0: Clock Polarity */
#define QSPI_SCR_NCPHA (1 << 1) /* Bit 1: Clock Phase */
#define QSPI_SCR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */
#define QSPI_SCR_SCBR_MASK (0xff << QSPI_SCR_SCBR_SHIFT)
# define QSPI_SCR_SCBR(n) ((uint32_t)(n) << QSPI_SCR_SCBR_SHIFT)
#define QSPI_SCR_DLYBS_SHIFT (16) /* Bits 16-23: Delay Before QSCK */
#define QSPI_SCR_DLYBS_MASK (0xff << QSPI_SCR_DLYBS_SHIFT)
# define QSPI_SCR_DLYBS(n) ((uint32_t)(n) << QSPI_SCR_DLYBS_SHIFT)
/* Instruction Address Register (32-bit value) */
/* Instruction Code Register */
#define QSPI_ICR_INST_SHIFT (0) /* Bits 0-7: Instruction Code */
#define QSPI_ICR_INST_MASK (0xff << QSPI_ICR_INST_SHIFT)
# define QSPI_ICR_INST(n) ((uint32_t)(n) << QSPI_ICR_INST_SHIFT)
#define QSPI_ICR_OPT_SHIFT (16) /* Bits 16-23: Option Code */
#define QSPI_ICR_OPT_MASK (0xff << QSPI_ICR_OPT_SHIFT)
# define QSPI_ICR_OPT(n) ((uint32_t)(n) << QSPI_ICR_OPT_SHIFT)
/* Instruction Frame Register */
#define QSPI_IFR_WIDTH_SHIFT (0) /* Bits 0-2: Width of Instruction Code,
* Address, Option Code and Data */
#define QSPI_IFR_WIDTH_MASK (7 << QSPI_IFR_WIDTH_SHIFT)
/* Instruction Address-Option Data */
# define QSPI_IFR_WIDTH_SINGLE (0 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Single-bit Single-bit */
# define QSPI_IFR_WIDTH_DUALOUT (1 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Single-bit Dual */
# define QSPI_IFR_WIDTH_QUADOUT (2 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Single-bit Quad */
# define QSPI_IFR_WIDTH_DUALIO (3 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Dual Dual */
# define QSPI_IFR_WIDTH_QUADIO (4 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Quad Quad */
# define QSPI_IFR_WIDTH_DUALCMD (5 << QSPI_IFR_WIDTH_SHIFT) /* Dual Dual Dual */
# define QSPI_IFR_WIDTH_QUADCMD (6 << QSPI_IFR_WIDTH_SHIFT) /* Quad Quad Quad */
#define QSPI_IFR_INSTEN (1 << 4) /* Bit 4: Instruction Enable */
#define QSPI_IFR_ADDREN (1 << 5) /* Bit 5: Address Enable */
#define QSPI_IFR_OPTEN (1 << 6) /* Bit 6: Option Enable */
#define QSPI_IFR_DATAEN (1 << 7) /* Bit 7: Data Enable */
#define QSPI_IFR_OPTL_SHIFT (8) /* Bits 8-9: Option Code Length */
#define QSPI_IFR_OPTL_MASK (3 << QSPI_IFR_OPTL_SHIFT)
# define QSPI_IFR_OPTL_1BIT (0 << QSPI_IFR_OPTL_SHIFT) /* Option is 1 bit */
# define QSPI_IFR_OPTL_2BIT (1 << QSPI_IFR_OPTL_SHIFT) /* Option is 2 bits */
# define QSPI_IFR_OPTL_4BIT (2 << QSPI_IFR_OPTL_SHIFT) /* Option is 4 bits */
# define QSPI_IFR_OPTL_8BIT (3 << QSPI_IFR_OPTL_SHIFT) /* Option is 8 bits */
#define QSPI_IFR_ADDRL (1 << 10) /* Bit 10: Address Length */
#define QSPI_IFR_TFRTYP_SHIFT (12) /* Bits 12-13: Data Transfer Type */
#define QSPI_IFR_TFRTYP_MASK (3 << QSPI_IFR_TFRTYP_SHIFT)
# define QSPI_IFR_TFRTYP_READ (0 << QSPI_IFR_TFRTYP_SHIFT) /* Read transfer from serial memory */
# define QSPI_IFR_TFRTYP_RDMEM (1 << QSPI_IFR_TFRTYP_SHIFT) /* Read data transfer from serial memory */
# define QSPI_IFR_TFRTYP_WRITE (2 << QSPI_IFR_TFRTYP_SHIFT) /* Write transfer into serial memory */
# define QSPI_IFR_TFRTYP_WRMEM (3 << QSPI_IFR_TFRTYP_SHIFT) /* Write data transfer the serial memory */
#define QSPI_IFR_CRM (1 << 14) /* Bit 14: Continuous Read Mode */
#define QSPI_IFR_NBDUM_SHIFT (16) /* Bits 16-20: Number Of Dummy Cycles */
#define QSPI_IFR_NBDUM_MASK (31 << QSPI_IFR_NBDUM_SHIFT)
# define QSPI_IFR_NBDUM(n) ((uint32_t)(n) << QSPI_IFR_NBDUM_SHIFT)
/* Scrambling Mode Register */
#define QSPI_SMR_SCREN (1 << 0) /* Bit 0: Scrambling/Unscrambling Enable */
#define QSPI_SMR_RVDIS (1 << 1) /* Bit 1: Scrambling/Unscrambling Random Value Disable */
/* Scrambling Key Register (32-bit value) */
/* QSPI Write Protection Control Register */
#define QSPI_WPCR_WPEN (1 << 0) /* Bit 0: QSPI Write Protection Enable */
#define QSPI_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: QSPI Write Protection Key Password */
#define QSPI_WPCR_WPKEY_MASK (0x00ffffff << QSPI_WPCR_WPKEY_SHIFT)
# define QSPI_WPCR_WPKEY (0x00515350 << QSPI_WPCR_WPKEY_SHIFT)
/* QSPI Write Protection Status Register */
#define QSPI_WPSR_WPVS (1 << 0) /* Bit 0: QSPI Write Protection Violation Status */
#define QSPI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-15: QSPI Write Protection Violation Source */
#define QSPI_WPSR_WPVSRC_MASK (0xff << QSPI_WPSR_WPVSRC_SHIFT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* SAMV7_NQSPI > 0 */
#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_QSPI_H */
arch/arm/src/samv7/chip/sam_spi.h
+5 -2
View File
@@ -120,7 +120,8 @@
/* SPI Mode Register */
#define SPI_MR_MSTR (1 << 0) /* Bit 0: Master/Slave Mode */
#define SPI_MR_MSTR (1 << 0) /* Bit 0: 1=Master Mode */
# define SPI_MR_SLAVE (0) /* 0=Slave Mode */
#define SPI_MR_PS (1 << 1) /* Bit 1: Peripheral Select */
#define SPI_MR_PCSDEC (1 << 2) /* Bit 2: Chip Select Decode */
#define SPI_MR_MODFDIS (1 << 4) /* Bit 4: Mode Fault Detection */
@@ -170,7 +171,9 @@
#define SPI_INT_NSSR (1 << 8) /* Bit 8: NSS Rising Interrupt */
#define SPI_INT_TXEMPTY (1 << 9) /* Bit 9: Transmission Registers Empty Interrupt */
#define SPI_INT_UNDES (1 << 10) /* Bit 10: Underrun Error Status Interrupt (slave) */
#define SPI_SR_SPIENS (1 << 16) /* Bit 16: SPI Enable Status (SR only) */
#define SPI_SR_SPIENS (1 << 16) /* Bit 16: SPI Enable Status (SR only) */
#define SPI_INT_ALL (0x0000070f)
/* SPI Chip Select Registers 0-3 */
arch/arm/src/samv7/chip/sam_usbhs.h
+3
View File
@@ -746,6 +746,9 @@
#define USBHS_CTRL_RDERRE (1 << 4) /* Bit 4: Remote Device Connection Error Interrupt Enable */
#define USBHS_CTRL_FRZCLK (1 << 14) /* Bit 14: Freeze USB Clock */
#define USBHS_CTRL_USBE (1 << 15) /* Bit 15: USBHS Enable */
#define USBHS_CTRL_UIDE (1 << 24) /* Bit 24: UOTGID Pin Enable */
# define USBHS_CTRL_UIDE_UIMOD (0 << 24) /* 0=USB mode selected UIMOD bit. */
# define USBHS_CTRL_UIDE_UOTGID (1 << 24) /* 1=USB mode selected by UOTGID */
#define USBHS_CTRL_UIMOD_MASK (1 << 25) /* Bit 25: USBHS Mode */
# define USBHS_CTRL_UIMOD_HOST (0 << 25) /* 0=Host mode */
# define USBHS_CTRL_UIMOD_DEVICE (1 << 25) /* 1=Device mode */
arch/arm/src/samv7/chip/samv71_memorymap.h
+1 -1
View File
@@ -55,7 +55,7 @@
#define SAM_MEMORY_BASE 0x60000000 /* 0x60000000-0x7fffffff: Memories */
#define SAM_QSPIMEM_BASE 0x80000000 /* 0x80000000-0x9fffffff: QSPI memory */
#define SAM_AXIMX_BASE 0xa0000000 /* 0xa0000000-0x9fffffff: AXIMX */
#define SAM_USBHSRAM_BASE 0xa0010000 /* 0xa0100000-0xa01fffff: USBHS RAM */
#define SAM_USBHSRAM_BASE 0xa0100000 /* 0xa0100000-0xa01fffff: USBHS RAM */
/* 0xa0200000-0xdfffffff: Reserved */
#define SAM_SYSTEM_BASE 0xe0000000 /* 0xe0000000-0xffffffff: System */
arch/arm/src/samv7/chip/samv71_pinmap.h
+9 -7
View File
@@ -152,14 +152,14 @@
#define GPIO_AFE0_ADTRG (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8)
#define GPIO_AFE1_ADTRG (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN9)
/* CAN */
/* MCAN */
#define GPIO_CAN0_RX (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3)
#define GPIO_CAN0_TX (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2)
#define GPIO_CAN1_RX_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN28)
#define GPIO_CAN1_RX_2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12)
#define GPIO_CAN1_TX_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN12)
#define GPIO_CAN1_TX_2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14)
#define GPIO_MCAN0_RX (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3)
#define GPIO_MCAN0_TX (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2)
#define GPIO_MCAN1_RX_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN28)
#define GPIO_MCAN1_RX_2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12)
#define GPIO_MCAN1_TX_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN12)
#define GPIO_MCAN1_TX_2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14)
/* Digital-to-Analog Convert (DAC) */
@@ -399,6 +399,7 @@
#define GPIO_SPI0_MOSI (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN21)
#define GPIO_SPI0_SPCK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN22)
#define GPIO_SPI0_NSS (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2)
#define GPIO_SPI0_NPCS0 (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2)
#define GPIO_SPI0_NPCS1_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31)
#define GPIO_SPI0_NPCS1_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN25)
@@ -409,6 +410,7 @@
#define GPIO_SPI1_MOSI (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27)
#define GPIO_SPI1_SPCK (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24)
#define GPIO_SPI1_NSS (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25)
#define GPIO_SPI1_NPCS0 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25)
#define GPIO_SPI1_NPCS1_1 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28)
#define GPIO_SPI1_NPCS1_2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN0)
arch/arm/src/samv7/sam_clockconfig.c
+56 -20
View File
@@ -224,30 +224,27 @@ static inline void sam_pmcsetup(void)
putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR);
sam_pmcwait(PMC_INT_LOCKA);
#ifdef CONFIG_USBDEV
#ifdef CONFIG_SAMV7_USBDEVHS
/* UTMI configuration: Enable port0, select 12/16 MHz MAINOSC crystal source */
#if 0 /* REVISIT: Does this apply only to OHCI? */
putreg32(UTMI_OHCIICR_RES0, SAM_UTMI_OHCIICR);
#endif
#if BOARD_MAINOSC_FREQUENCY == 12000000
putreg32(UTMI_CKTRIM_FREQ_XTAL12, SAM_UTMI_CKTRIM);
#elif BOARD_MAINOSC_FREQUENCY == 12000000
#elif BOARD_MAINOSC_FREQUENCY == 16000000
putreg32(UTMI_CKTRIM_FREQ_XTAL16, SAM_UTMI_CKTRIM);
#else
# error ERROR: Unrecognized MAINSOSC frequency
#endif
#ifdef CONFIG_SAMV7_USBDEVHS_LOWPOWER
/* Enable UTMI Clocking. The USBHS can work in two modes:
*
* - Normal mode where High speed, Full speed and Low speed are available.
* - Low-power mode where only Full speed and Low speed are available.
*
* Only the normal mode is supported by this logic.
* Only the Low-power mode is mode is supported by the logic here. Normal
* mode logic is handled in the function sam_usbclock().
*/
#ifdef CONFIG_SAMV7_USBDEVHS_LOWPOWER
/* UTMI Low-power mode, Full/Low Speed mode
*
* Enable the 48MHz FS Clock.
@@ -255,15 +252,6 @@ static inline void sam_pmcsetup(void)
putreg32(PMC_USBCLK, SAM_PMC_SCER);
#else
/* UTMI normal mode, High/Full/Low Speed
*
* Disable the 48MHz USB FS Clock. It is not used in this configuration
*/
putreg32(PMC_USBCLK, SAM_PMC_SCDR);
#endif
/* Select the UTMI PLL as the USB PLL clock input (480MHz) with divider
* to get to 48MHz. UPLL output frequency is determined only by the
* 12/16MHz crystal selection above.
@@ -271,7 +259,6 @@ static inline void sam_pmcsetup(void)
regval = PMC_USB_USBS_UPLL;
#ifdef CONFIG_SAMV7_USBDEVHS_LOWPOWER
if ((getreg32(SAM_PMC_MCKR) & PMC_MCKR_PLLADIV2) != 0)
{
/* Divider = 480 Mhz / 2 / 48 Mhz = 5 */
@@ -284,7 +271,6 @@ static inline void sam_pmcsetup(void)
regval |= PMC_USB_USBDIV(9);
}
#endif
putreg32(regval, SAM_PMC_USB);
@@ -296,7 +282,9 @@ static inline void sam_pmcsetup(void)
/* Wait for LOCKU */
sam_pmcwait(PMC_INT_LOCKU);
#endif
#endif /* CONFIG_SAMV7_USBDEVHS_LOWPOWER */
#endif /* CONFIG_SAMV7_USBDEVHS */
/* Switch to the fast clock and wait for MCKRDY */
@@ -405,3 +393,51 @@ void sam_clockconfig(void)
sam_enabledefaultmaster();
}
/****************************************************************************
* Name: sam_usbclock
*
* Description:
* Enable USBHS clocking.
*
****************************************************************************/
#if defined(CONFIG_SAMV7_USBDEVHS) && !defined(CONFIG_SAMV7_USBDEVHS_LOWPOWER)
void sam_usbclock(void)
{
uint32_t regval;
/* Enable UTMI Clocking. The USBHS can work in two modes:
*
* - Normal mode where High speed, Full speed and Low speed are available.
* - Low-power mode where only Full speed and Low speed are available.
*
* Only the normal mode is supported by this logic of this function. Low-
* power mode was handled in the sam_clockconfig().
*/
/* UTMI normal mode, High/Full/Low Speed
*
* Disable the 48MHz USB FS Clock. It is not used in this configuration
*/
putreg32(PMC_USBCLK, SAM_PMC_SCDR);
/* Select the UTMI PLL as the USB PLL clock input (480MHz) with a divider
* of 1. UPLL output frequency is determined only by the 12/16MHz crystal
* selection set in sam_clockconfig().
*/
putreg32(PMC_USB_USBS_UPLL, SAM_PMC_USB);
/* Enable the UTMI PLL with the maximum start-up time */
regval = PMC_CKGR_UCKR_UPLLEN | PMC_CKGR_UCKR_UPLLCOUNT_MAX;
putreg32(regval, SAM_PMC_CKGR_UCKR);
/* Wait for LOCKU */
sam_pmcwait(PMC_INT_LOCKU);
}
#endif /* CONFIG_SAMV7_USBDEVHS && !CONFIG_SAMV7_USBDEVHS_LOWPOWER */
arch/arm/src/samv7/sam_clockconfig.h
+14
View File
@@ -85,6 +85,20 @@ extern "C"
void sam_clockconfig(void);
/****************************************************************************
* Name: sam_usbclock
*
* Description:
* Enable USBHS clocking.
*
****************************************************************************/
#if defined(CONFIG_SAMV7_USBDEVHS) && !defined(CONFIG_SAMV7_USBDEVHS_LOWPOWER)
void sam_usbclock(void);
#else
# define sam_usbclock()
#endif
#undef EXTERN
#if defined(__cplusplus)
}
arch/arm/src/samv7/sam_config.h
+42 -4
View File
@@ -255,22 +255,60 @@
/* SPI ******************************************************************************/
/* Don't enable SPI peripherals not supported by the chip. */
#if CHIP_NSPI < 1
#if SAMV7_NSPI < 1
# undef CONFIG_SAMV7_SPI0
# undef CONFIG_SAMV7_SPI0_MASTER
# undef CONFIG_SAMV7_SPI0_SLAVE
# undef CONFIG_SAMV7_SPI1
#elif CHIP_NSPI < 2
# undef CONFIG_SAMV7_SPI1_MASTER
# undef CONFIG_SAMV7_SPI1_SLAVE
#elif SAMV7_NSPI < 2
# undef CONFIG_SAMV7_SPI1
# undef CONFIG_SAMV7_SPI1_MASTER
# undef CONFIG_SAMV7_SPI1_SLAVE
#endif
#ifndef CONFIG_SAMV7_HAVE_SPI
#ifndef CONFIG_SAMV7_SPI
# undef CONFIG_SAMV7_SPI0
# undef CONFIG_SAMV7_SPI0_MASTER
# undef CONFIG_SAMV7_SPI0_SLAVE
# undef CONFIG_SAMV7_SPI1
# undef CONFIG_SAMV7_SPI1_MASTER
# undef CONFIG_SAMV7_SPI1_SLAVE
#endif
/* Are any SPI peripherals enabled? */
#if !defined(CONFIG_SAMV7_SPI0) && !defined(CONFIG_SAMV7_SPI0)
# undef CONFIG_SAMV7_HAVE_SPI
# undef CONFIG_SAMV7_SPI
# undef CONFIG_SAMV7_SPI_MASTER
# undef CONFIG_SAMV7_SPI_SLAVE
#endif
/* Each SPI peripheral must be enabled as a MASTER or as a SLAVE */
#ifndef CONFIG_SAMV7_SPI_MASTER
# undef CONFIG_SAMV7_SPI0_MASTER
# undef CONFIG_SAMV7_SPI1_MASTER
#endif
#if !defined(CONFIG_SAMV7_SPI0_MASTER) && !defined(CONFIG_SAMV7_SPI1_MASTER)
# undef CONFIG_SAMV7_SPI_MASTER
#endif
#ifndef CONFIG_SAMV7_SPI_SLAVE
# undef CONFIG_SAMV7_SPI0_SLAVE
# undef CONFIG_SAMV7_SPI1_SLAVE
#endif
#if !defined(CONFIG_SAMV7_SPI0_SLAVE) && !defined(CONFIG_SAMV7_SPI1_SLAVE)
# undef CONFIG_SAMV7_SPI_SLAVE
#endif
#if !defined(CONFIG_SAMV7_SPI_MASTER) && !defined(CONFIG_SAMV7_SPI_SLAVE)
# undef CONFIG_SAMV7_SPI
# undef CONFIG_SAMV7_SPI0
# undef CONFIG_SAMV7_SPI1
#endif
/****************************************************************************
arch/arm/src/samv7/sam_emac.c
+3 -3
View File
@@ -350,7 +350,7 @@
* the 8-byte (2 word boundaries). However, if the data cache is enabled
* the a higher level of alignment is required. That is because the data
* will need to be invalidated and that cache invalidation will occur in
* multiples of full change lines.
* multiples of full cache lines.
*
* In addition, padding may be required at the ends of the descriptors and
* buffers to protect data after the end of from invalidation.
@@ -2103,7 +2103,7 @@ static void sam_txdone(struct sam_emac_s *priv, int qid)
*
* Parameters:
* priv - Reference to the driver state structure
* quid - Index of the tranfer queue that generated the interrupt
* quid - Index of the transfer queue that generated the interrupt
*
* Returned Value:
* None
@@ -2230,7 +2230,7 @@ static void sam_txerr_interrupt(FAR struct sam_emac_s *priv, int qid)
*
* Parameters:
* priv - Reference to the driver state structure
* quid - Index of the tranfer queue that generated the interrupt
* quid - Index of the transfer queue that generated the interrupt
*
* Returned Value:
* None
arch/arm/src/samv7/sam_irq.c
+20 -6
View File
@@ -78,7 +78,16 @@
* Public Data
****************************************************************************/
/* This is the address of current interrupt saved state data. Used for
* context switching. Only value during interrupt handling.
*/
volatile uint32_t *current_regs;
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern uint32_t _vectors[];
/****************************************************************************
@@ -378,16 +387,21 @@ void up_irqinitialize(void)
}
#endif
/* Set up the vector table address.
*
* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
#if defined(CONFIG_ARCH_RAMVECTORS)
up_ramvec_initialize();
#elif defined(CONFIG_SAM_BOOTLOADER)
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#endif
/* Set all interrupts (and exceptions) to the default priority */
arch/arm/src/samv7/sam_mcan.c
Executable
+3788
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/samv7/sam_mcan.h
+110
View File
@@ -0,0 +1,110 @@
/****************************************************************************
* arch/arm/src/samv7/sam_mcan.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMV7_SAM_MCAN_H
#define __ARCH_ARM_SRC_SAMV7_SAM_MCAN_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam_mcan.h"
#include <nuttx/can.h>
#if defined(CONFIG_CAN) && (defined(CONFIG_SAMV7_MCAN0) || \
defined(CONFIG_SAMV7_MCAN1))
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Port numbers for use with sam_mcan_initialize() */
#define MCAN0 0
#define MCAN1 1
/***************************************************************************
* Public Types
***************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/***************************************************************************
* Public Functions
***************************************************************************/
/****************************************************************************
* Name: sam_mcan_initialize
*
* Description:
* Initialize the selected MCAN port
*
* Input Parameter:
* port - Port number (for hardware that has multiple CAN interfaces),
* 0=MCAN0, 1=NCAN1
*
* Returned Value:
* Valid CAN device structure reference on success; a NULL on failure
*
****************************************************************************/
struct can_dev_s;
FAR struct can_dev_s *sam_mcan_initialize(int port);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_CAN && (CONFIG_SAMV7_MCAN0 || CONFIG_SAMV7_MCAN1) */
#endif /* __ARCH_ARM_SRC_SAMV7_SAM_MCAN_H */

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