mirror of
https://github.com/apache/nuttx.git
synced 2026-09-21 21:47:28 +08:00
Squashed commit of the following:
arch/mips/src/pic32mz: Commits the basic architecture port for the PIC32MZEF.
arch/mips/src/pic32mz: Begin adding PIC32MZEF files. Initial commit are simply PIC32MZEC files with name changes.
arch/mips/include/pic32mz: Add support for the PIC32MZEF family.
This commit is contained in:
Gregory Nutt
@@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/mips/include/pic32mz/chip.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
|
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* Author: Gregory Nutt <gnutt@nuttx.org>
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||||
*
|
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* Redistribution and use in source and binary forms, with or without
|
||||
@@ -52,7 +52,8 @@
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*/
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#if defined(CONFIG_ARCH_CHIP_PIC32MZ2048ECH)
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# define CHIP_PIC32MZEC 1
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# define CHIP_PIC32MZEC 1 /* PIC32MZEC family */
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# undef CHIP_PIC32MZEF /* Not PIC32MZEF family */
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# define CHIP_BOOTFLASH_KB 160 /* 160Kb boot FLASH */
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# define CHIP_PROGFLASH_KB 2048 /* 2048Kb program FLASH */
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# define CHIP_DATAMEM_KB 512 /* 512Kb data memory */
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@@ -63,7 +64,7 @@
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# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
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# define CHIP_NSPI 6 /* 6 SPI/I2S interfaces */
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# define CHIP_NCAN 2 /* 2 CAN interfaces */
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# define CHIP_NCRTYPO 0 /* No crtypo support */
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# define CHIP_NCRTYPO 0 /* No crypto support */
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# define CHIP_RNG 1 /* 1 Random number generator */
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# define CHIP_NDMACH 8 /* 8 programmable DMA channels */
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# define CHIP_NUSBDMACHAN 16 /* 16 dedicated DMA channels */
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@@ -86,7 +87,8 @@
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*/
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#elif defined(CONFIG_ARCH_CHIP_PIC32MZ2048ECM)
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# define CHIP_PIC32MZEC 1
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# define CHIP_PIC32MZEC 1 /* PIC32MZEC family */
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# undef CHIP_PIC32MZEF /* Not PIC32MZEF family */
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# define CHIP_BOOTFLASH_KB 160 /* 160Kb boot FLASH */
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# define CHIP_PROGFLASH_KB 2048 /* 2048Kb program FLASH */
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# define CHIP_DATAMEM_KB 512 /* 512Kb data memory */
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@@ -97,7 +99,85 @@
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# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
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# define CHIP_NSPI 6 /* 6 SPI/I2S interfaces */
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# define CHIP_NCAN 2 /* 2 CAN interfaces */
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# define CHIP_NCRTYPO 1 /* Has crtypo support */
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# define CHIP_NCRTYPO 1 /* Has crypto support */
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# define CHIP_RNG 1 /* 1 Random number generator */
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# define CHIP_NDMACH 8 /* 8 programmable DMA channels */
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# define CHIP_NUSBDMACHAN 18 /* 18 dedicated DMA channels */
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# define CHIP_NADC10 48 /* 48 ADC channels */
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# define CHIP_NCM 2 /* 2 Analog comparators */
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# define CHIP_USBHSOTG 1 /* 1 USB 2.0 HSOTG */
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# define CHIP_NI2C 5 /* 5 I2C interfaces */
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# define CHIP_NPMP 1 /* Have parallel master port */
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# define CHIP_NEBI 1 /* Have eternal bus interface */
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# define CHIP_NSQI 1 /* 1 Serial quad interface */
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# define CHIP_NRTCC 1 /* Has RTCC */
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# define CHIP_NETHERNET 1 /* 1 Ethernet MAC */
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# define CHIP_NPORTS 10 /* 10 ports (A-H, J-K) */
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# define CHIP_NJTAG 1 /* Has JTAG */
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# define CHIP_NTRACE 1 /* Has trace capability */
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/* Available in 64/100/124/144 pin packages. Description here is specifically
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* for the 124 and 144 pin packages (PIC32MZ2048EFH1100, and
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* PIC32MZ2048EFH144). The PIC32MZ2048EFH1100 differs in that it has only
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* 40 ADC channels. The PIC32MZ2048EFH1064 differs in that it has only 24 ADC
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* channels, two fewer SPI/I2S, one fewer I2C, and no EBI. There are
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* additional differences between all family members in the number of pins
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* how they may be mapped.
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*/
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#elif defined(CONFIG_ARCH_CHIP_PIC32MZ2048EFH)
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# undef CHIP_PIC32MZEC /* Not PIC32MZEC family */
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# define CHIP_PIC32MZEF 1 /* PIC32MZEF family */
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# define CHIP_BOOTFLASH_KB 160 /* 160Kb boot FLASH */
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# define CHIP_PROGFLASH_KB 2048 /* 2048Kb program FLASH */
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# define CHIP_DATAMEM_KB 512 /* 512Kb data memory */
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# define CHIP_NTIMERS 9 /* 5 timers */
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# define CHIP_NIC 9 /* 5 input capture */
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# define CHIP_NOC 9 /* 5 output compare */
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# define CHIP_NUARTS 6 /* 6 UARTS */
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# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
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# define CHIP_NSPI 6 /* 6 SPI/I2S interfaces */
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# define CHIP_NCAN 2 /* 2 CAN 2.0B interfaces */
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# define CHIP_NCRTYPO 0 /* No crypto support */
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# define CHIP_RNG 1 /* 1 Random number generator */
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# define CHIP_NDMACH 8 /* 8 programmable DMA channels */
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# define CHIP_NUSBDMACHAN 16 /* 16 dedicated DMA channels */
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# define CHIP_NADC10 48 /* 48 ADC channels */
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# define CHIP_NCM 2 /* 2 Analog comparators */
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# define CHIP_USBHSOTG 1 /* 1 USB 2.0 HSOTG */
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# define CHIP_NI2C 5 /* 5 I2C interfaces */
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# define CHIP_NPMP 1 /* Have parallel master port */
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# define CHIP_NEBI 1 /* Have eternal bus interface */
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# define CHIP_NSQI 1 /* 1 Serial quad interface */
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# define CHIP_NRTCC 1 /* Has RTCC */
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# define CHIP_NETHERNET 1 /* 1 Ethernet MAC */
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# define CHIP_NPORTS 10 /* 10 ports (A-H, J-K) */
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# define CHIP_NJTAG 1 /* Has JTAG */
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# define CHIP_NTRACE 1 /* Has trace capability */
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/* Available in 64/100/124/144 pin packages. Description here is specifically
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* for the 124, and 144 pin packages (PIC32MZ2048EFM124, and
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* PIC32MZ2048EFH144). The PIC32MZ2048EFM100 differs in that it has only 40
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* ADC channels. The PIC32MZ2048EFM064 differs in that it has only 24 ADC
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* channels, two fewer SPI/I2S, one fewer I2C, and no EBI. There are
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* additional differences between all family members in the number of pins
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* how they may be mapped.
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*/
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#elif defined(CONFIG_ARCH_CHIP_PIC32MZ2048EFM)
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# undef CHIP_PIC32MZEC /* Not PIC32MZEC family */
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# define CHIP_PIC32MZEF 1 /* PIC32MZEF family */
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# define CHIP_BOOTFLASH_KB 160 /* 160Kb boot FLASH */
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# define CHIP_PROGFLASH_KB 2048 /* 2048Kb program FLASH */
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# define CHIP_DATAMEM_KB 512 /* 512Kb data memory */
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# define CHIP_NTIMERS 9 /* 5 timers */
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# define CHIP_NIC 9 /* 5 input capture */
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# define CHIP_NOC 9 /* 5 output compare */
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# define CHIP_NUARTS 6 /* 6 UARTS */
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# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
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# define CHIP_NSPI 6 /* 6 SPI/I2S interfaces */
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# define CHIP_NCAN 2 /* 2 CAN 2.0B interfaces */
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# define CHIP_NCRTYPO 1 /* Has crypto support */
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# define CHIP_RNG 1 /* 1 Random number generator */
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# define CHIP_NDMACH 8 /* 8 programmable DMA channels */
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# define CHIP_NUSBDMACHAN 18 /* 18 dedicated DMA channels */
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@@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/mips/include/pic32mz/irq.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -49,6 +49,8 @@
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#if defined(CHIP_PIC32MZEC)
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# include <arch/pic32mz/irq_pic32mzxxxec.h>
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#elif defined(CHIP_PIC32MZEF)
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# include <arch/pic32mz/irq_pic32mzxxxef.h>
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#else
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# error "Unknown PIC32MZ family
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#endif
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@@ -62,6 +62,7 @@
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#define PIC32MZ_IRQ_OC1 7 /* Vector: 7, Output Compare 1 */
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#define PIC32MZ_IRQ_INT1 8 /* Vector: 8, External Interrupt 1 */
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#define PIC32MZ_IRQ_T2 9 /* Vector: 9, Timer 2 */
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#define PIC32MZ_IRQ_ICE2 10 /* Vector: 10, Input Capture 2 Error */
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#define PIC32MZ_IRQ_IC2 11 /* Vector: 11, Input Capture 2 */
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#define PIC32MZ_IRQ_OC2 12 /* Vector: 12, Output Compare 2 */
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@@ -72,6 +73,7 @@
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#define PIC32MZ_IRQ_OC3 17 /* Vector: 17, Output Compare 3 */
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#define PIC32MZ_IRQ_INT3 18 /* Vector: 18, External Interrupt 3 */
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#define PIC32MZ_IRQ_T4 19 /* Vector: 19, Timer 4 */
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#define PIC32MZ_IRQ_ICE4 20 /* Vector: 20, Input Capture 4 Error */
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#define PIC32MZ_IRQ_IC4 21 /* Vector: 21, Input Capture 4 */
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#define PIC32MZ_IRQ_OC4 22 /* Vector: 22, Output Compare 4 */
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@@ -82,6 +84,7 @@
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#define PIC32MZ_IRQ_OC5 27 /* Vector: 27, Output Compare 5 */
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#define PIC32MZ_IRQ_T6 28 /* Vector: 28, Timer 6 */
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#define PIC32MZ_IRQ_ICE6 29 /* Vector: 29, Input Capture 6 Error */
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#define PIC32MZ_IRQ_IC6 30 /* Vector: 30, Input Capture 6 */
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#define PIC32MZ_IRQ_OC6 31 /* Vector: 31, Output Compare 6 */
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#define PIC32MZ_IRQ_T7 32 /* Vector: 32, Timer 7 */
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@@ -92,6 +95,7 @@
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#define PIC32MZ_IRQ_ICE8 37 /* Vector: 37, Input Capture 8 Error */
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#define PIC32MZ_IRQ_IC8 38 /* Vector: 38, Input Capture 8 */
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#define PIC32MZ_IRQ_OC8 39 /* Vector: 39, Output Compare 8 */
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#define PIC32MZ_IRQ_T9 40 /* Vector: 40, Timer 9 */
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#define PIC32MZ_IRQ_ICE9 41 /* Vector: 41, Input Capture 9 Error */
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#define PIC32MZ_IRQ_IC9 42 /* Vector: 42, Input Capture 9 */
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@@ -102,6 +106,7 @@
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#define PIC32MZ_IRQ_AD1CMP2 47 /* Vector: 47, ADC1 Digital Comparator 2 */
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#define PIC32MZ_IRQ_AD1CMP3 48 /* Vector: 48, ADC1 Digital Comparator 3 */
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#define PIC32MZ_IRQ_AD1CMP4 49 /* Vector: 49, ADC1 Digital Comparator 4 */
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#define PIC32MZ_IRQ_AD1CMP5 50 /* Vector: 50, ADC1 Digital Comparator 5 */
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#define PIC32MZ_IRQ_AD1CMP6 51 /* Vector: 51, ADC1 Digital Comparator 6 */
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#define PIC32MZ_IRQ_AD1FLT1 52 /* Vector: 52, ADC1 Digital Filter 1 */
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@@ -112,6 +117,7 @@
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#define PIC32MZ_IRQ_AD1FLT6 57 /* Vector: 57, ADC1 Digital Filter 6 */
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/* Vector: 58, Reserved */
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#define PIC32MZ_IRQ_AD1DAT0 59 /* Vector: 59, ADC1 Data 0 */
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#define PIC32MZ_IRQ_AD1DAT1 60 /* Vector: 60, ADC1 Data 1 */
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#define PIC32MZ_IRQ_AD1DAT2 61 /* Vector: 61, ADC1 Data 2 */
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#define PIC32MZ_IRQ_AD1DAT3 62 /* Vector: 62, ADC1 Data 3 */
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@@ -122,6 +128,7 @@
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#define PIC32MZ_IRQ_AD1DAT8 67 /* Vector: 67, ADC1 Data 8 */
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#define PIC32MZ_IRQ_AD1DAT9 68 /* Vector: 68, ADC1 Data 9 */
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#define PIC32MZ_IRQ_AD1DAT10 69 /* Vector: 69, ADC1 Data 10 */
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#define PIC32MZ_IRQ_AD1DAT11 70 /* Vector: 70, ADC1 Data 11 */
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#define PIC32MZ_IRQ_AD1DAT12 71 /* Vector: 71, ADC1 Data 12 */
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#define PIC32MZ_IRQ_AD1DAT13 72 /* Vector: 72, ADC1 Data 13 */
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@@ -132,6 +139,7 @@
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#define PIC32MZ_IRQ_AD1DAT18 77 /* Vector: 77, ADC1 Data 18 */
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#define PIC32MZ_IRQ_AD1DAT19 78 /* Vector: 78, ADC1 Data 19 */
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#define PIC32MZ_IRQ_AD1DAT20 79 /* Vector: 79, ADC1 Data 20 */
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#define PIC32MZ_IRQ_AD1DAT21 80 /* Vector: 80, ADC1 Data 21 */
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#define PIC32MZ_IRQ_AD1DAT22 81 /* Vector: 81, ADC1 Data 22 */
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#define PIC32MZ_IRQ_AD1DAT23 82 /* Vector: 82, ADC1 Data 23 */
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@@ -142,6 +150,7 @@
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#define PIC32MZ_IRQ_AD1DAT28 87 /* Vector: 87, ADC1 Data 28 */
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#define PIC32MZ_IRQ_AD1DAT29 88 /* Vector: 88, ADC1 Data 29 */
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#define PIC32MZ_IRQ_AD1DAT30 89 /* Vector: 89, ADC1 Data 30 */
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#define PIC32MZ_IRQ_AD1DAT31 90 /* Vector: 90, ADC1 Data 31 */
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#define PIC32MZ_IRQ_AD1DAT32 91 /* Vector: 91, ADC1 Data 32 */
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#define PIC32MZ_IRQ_AD1DAT33 92 /* Vector: 92, ADC1 Data 33 */
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@@ -152,6 +161,7 @@
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#define PIC32MZ_IRQ_AD1DAT38 97 /* Vector: 97, ADC1 Data 38 */
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#define PIC32MZ_IRQ_AD1DAT39 98 /* Vector: 98, ADC1 Data 39 */
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#define PIC32MZ_IRQ_AD1DAT40 99 /* Vector: 99, ADC1 Data 40 */
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#define PIC32MZ_IRQ_AD1DAT41 100 /* Vector: 100, ADC1 Data 41 */
|
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#define PIC32MZ_IRQ_AD1DAT42 101 /* Vector: 101, ADC1 Data 42 */
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#define PIC32MZ_IRQ_AD1DAT43 102 /* Vector: 102, ADC1 Data 43 */
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@@ -162,6 +172,7 @@
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#define PIC32MZ_IRQ_CTYPTO 107 /* Vector: 107, Crypto Engine Event */
|
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/* Vector: 108, Reserved */
|
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#define PIC32MZ_IRQ_SPI1F 109 /* Vector: 109, SPI1 Fault */
|
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#define PIC32MZ_IRQ_SPI1RX 110 /* Vector: 110, SPI1 Receive Done */
|
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#define PIC32MZ_IRQ_SPI1TX 111 /* Vector: 111, SPI1 Transfer Done */
|
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#define PIC32MZ_IRQ_U1E 112 /* Vector: 112, UART1 Fault */
|
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@@ -172,6 +183,7 @@
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#define PIC32MZ_IRQ_I2C1M 117 /* Vector: 117, I2C1 Master Event */
|
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#define PIC32MZ_IRQ_PORTA 118 /* Vector: 118, PORTA Input Change Interrupt */
|
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#define PIC32MZ_IRQ_PORTB 119 /* Vector: 119, PORTB Input Change Interrupt */
|
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|
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#define PIC32MZ_IRQ_PORTC 120 /* Vector: 120, PORTC Input Change Interrupt */
|
||||
#define PIC32MZ_IRQ_PORTD 121 /* Vector: 121, PORTD Input Change Interrupt */
|
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#define PIC32MZ_IRQ_PORTE 122 /* Vector: 122, PORTE Input Change Interrupt */
|
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@@ -182,6 +194,7 @@
|
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#define PIC32MZ_IRQ_PORTK 127 /* Vector: 127, PORTK Input Change Interrupt */
|
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#define PIC32MZ_IRQ_PMP 128 /* Vector: 128, Parallel Master Port */
|
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#define PIC32MZ_IRQ_PMPE 129 /* Vector: 129, Parallel Master Port Error */
|
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|
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#define PIC32MZ_IRQ_CMP1 130 /* Vector: 130, Comparator 1 Interrupt */
|
||||
#define PIC32MZ_IRQ_CMP2 131 /* Vector: 131, Comparator 2 Interrupt */
|
||||
#define PIC32MZ_IRQ_USBGEN 132 /* Vector: 132, USB General Event */
|
||||
@@ -192,6 +205,7 @@
|
||||
#define PIC32MZ_IRQ_DMA3 137 /* Vector: 137, DMA Channel 3 */
|
||||
#define PIC32MZ_IRQ_DMA4 138 /* Vector: 138, DMA Channel 4 */
|
||||
#define PIC32MZ_IRQ_DMA5 139 /* Vector: 139, DMA Channel 5 */
|
||||
|
||||
#define PIC32MZ_IRQ_DMA6 140 /* Vector: 140, DMA Channel 6 */
|
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#define PIC32MZ_IRQ_DMA7 141 /* Vector: 141, DMA Channel 7 */
|
||||
#define PIC32MZ_IRQ_SPI2F 142 /* Vector: 142, SPI2 Fault */
|
||||
@@ -202,6 +216,7 @@
|
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#define PIC32MZ_IRQ_U2TX 147 /* Vector: 147, UART2 Transfer Done */
|
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#define PIC32MZ_IRQ_I2C2COL 148 /* Vector: 148, I2C2 Bus Collision Event */
|
||||
#define PIC32MZ_IRQ_I2C2S 149 /* Vector: 149, I2C2 Slave Event */
|
||||
|
||||
#define PIC32MZ_IRQ_I2C2M 150 /* Vector: 150, I2C2 Master Event */
|
||||
#define PIC32MZ_IRQ_CAN1 151 /* Vector: 151, Control Area Network 1 */
|
||||
#define PIC32MZ_IRQ_CAN2 152 /* Vector: 152, Control Area Network 2 */
|
||||
@@ -212,7 +227,8 @@
|
||||
#define PIC32MZ_IRQ_U3E 157 /* Vector: 157, UART3 Fault */
|
||||
#define PIC32MZ_IRQ_U3RX 158 /* Vector: 158, UART3 Receive Done */
|
||||
#define PIC32MZ_IRQ_U3TX 159 /* Vector: 159, UART3 Transfer Done */
|
||||
#define PIC32MZ_IRQ_I2C3COL 160 /* Vector: 160, I2C3 Bus Collision Event */
|
||||
|
||||
#define PIC32MZ_IRQ_I2C3COL 160 /* Vector: 160, I2C3 Bus Collision Event */
|
||||
#define PIC32MZ_IRQ_I2C3S 161 /* Vector: 161, I2C3 Slave Event */
|
||||
#define PIC32MZ_IRQ_I2C3M 162 /* Vector: 162, I2C3 Master Event */
|
||||
#define PIC32MZ_IRQ_SPI4F 163 /* Vector: 163, SPI4 Fault */
|
||||
@@ -222,6 +238,7 @@
|
||||
#define PIC32MZ_IRQ_FCE 167 /* Vector: 167, Flash Control Event */
|
||||
#define PIC32MZ_IRQ_PMSEC 168 /* Vector: 168, Prefetch Module SEC Event */
|
||||
#define PIC32MZ_IRQ_SQI1 169 /* Vector: 169, SQI1 Event */
|
||||
|
||||
#define PIC32MZ_IRQ_U4E 170 /* Vector: 170, UART4 Fault */
|
||||
#define PIC32MZ_IRQ_U4RX 171 /* Vector: 171, UART4 Receive Done */
|
||||
#define PIC32MZ_IRQ_U4TX 172 /* Vector: 172, UART4 Transfer Done */
|
||||
@@ -232,6 +249,7 @@
|
||||
#define PIC32MZ_IRQ_SPI5RX 177 /* Vector: 177, SPI5 Receive Done */
|
||||
#define PIC32MZ_IRQ_SPI5TX 178 /* Vector: 178, SPI5 Transfer Done */
|
||||
#define PIC32MZ_IRQ_U5E 179 /* Vector: 179, UART5 Fault */
|
||||
|
||||
#define PIC32MZ_IRQ_U5RX 180 /* Vector: 180, UART5 Receive Done */
|
||||
#define PIC32MZ_IRQ_U5TX 181 /* Vector: 181, UART5 Transfer Done */
|
||||
#define PIC32MZ_IRQ_I2C5COL 182 /* Vector: 182, I2C5 Bus Collision Event */
|
||||
@@ -242,6 +260,7 @@
|
||||
#define PIC32MZ_IRQ_SPI6TX 187 /* Vector: 187, SPI6 Transfer Done */
|
||||
#define PIC32MZ_IRQ_U6E 188 /* Vector: 188, UART6 Fault */
|
||||
#define PIC32MZ_IRQ_U6RX 189 /* Vector: 189, UART6 Receive Done */
|
||||
|
||||
#define PIC32MZ_IRQ_U6TX 190 /* Vector: 190, UART6 Transfer Done */
|
||||
|
||||
#define PIC32MZ_IRQ_BAD 191 /* Not a real IRQ number */
|
||||
|
||||
@@ -0,0 +1,325 @@
|
||||
/****************************************************************************
|
||||
* arch/mips/include/pic32mz/irq_pic32mzxxxef.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* This file should never be included directed but, rather, only indirectly
|
||||
* through nuttx/irq.h
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_MIPS_INCLUDE_PIC32MZ_IRQ_PIC32MZXXXEF_H
|
||||
#define __ARCH_MIPS_INCLUDE_PIC32MZ_IRQ_PIC32MZXXXEF_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Interrupt vector numbers. These should be used to attach to interrupts
|
||||
* and to change interrupt priorities.
|
||||
*/
|
||||
|
||||
#define PIC32MZ_IRQ_CT 0 /* Vector: 0, Core Timer Interrupt */
|
||||
#define PIC32MZ_IRQ_CS0 1 /* Vector: 1, Core Software Interrupt 0 */
|
||||
#define PIC32MZ_IRQ_CS1 2 /* Vector: 2, Core Software Interrupt 1 */
|
||||
#define PIC32MZ_IRQ_INT0 3 /* Vector: 3, External Interrupt 0 */
|
||||
#define PIC32MZ_IRQ_T1 4 /* Vector: 4, Timer 1 */
|
||||
#define PIC32MZ_IRQ_ICE1 5 /* Vector: 5, Input Capture 1 Error */
|
||||
#define PIC32MZ_IRQ_IC1 6 /* Vector: 6, Input Capture 1 */
|
||||
#define PIC32MZ_IRQ_OC1 7 /* Vector: 7, Output Compare 1 */
|
||||
#define PIC32MZ_IRQ_INT1 8 /* Vector: 8, External Interrupt 1 */
|
||||
#define PIC32MZ_IRQ_T2 9 /* Vector: 9, Timer 2 */
|
||||
|
||||
#define PIC32MZ_IRQ_ICE2 10 /* Vector: 10, Input Capture 2 Error */
|
||||
#define PIC32MZ_IRQ_IC2 11 /* Vector: 11, Input Capture 2 */
|
||||
#define PIC32MZ_IRQ_OC2 12 /* Vector: 12, Output Compare 2 */
|
||||
#define PIC32MZ_IRQ_INT2 13 /* Vector: 13, External Interrupt 2 */
|
||||
#define PIC32MZ_IRQ_T3 14 /* Vector: 14, Timer 3 */
|
||||
#define PIC32MZ_IRQ_ICE3 15 /* Vector: 15, Input Capture 3 Error */
|
||||
#define PIC32MZ_IRQ_IC3 16 /* Vector: 16, Input Capture 3 */
|
||||
#define PIC32MZ_IRQ_OC3 17 /* Vector: 17, Output Compare 3 */
|
||||
#define PIC32MZ_IRQ_INT3 18 /* Vector: 18, External Interrupt 3 */
|
||||
#define PIC32MZ_IRQ_T4 19 /* Vector: 19, Timer 4 */
|
||||
|
||||
#define PIC32MZ_IRQ_ICE4 20 /* Vector: 20, Input Capture 4 Error */
|
||||
#define PIC32MZ_IRQ_IC4 21 /* Vector: 21, Input Capture 4 */
|
||||
#define PIC32MZ_IRQ_OC4 22 /* Vector: 22, Output Compare 4 */
|
||||
#define PIC32MZ_IRQ_INT4 23 /* Vector: 23, External Interrupt 4 */
|
||||
#define PIC32MZ_IRQ_T5 24 /* Vector: 24, Timer 5 */
|
||||
#define PIC32MZ_IRQ_ICE5 25 /* Vector: 25, Input Capture 5 Error */
|
||||
#define PIC32MZ_IRQ_IC5 26 /* Vector: 26, Input Capture 5 */
|
||||
#define PIC32MZ_IRQ_OC5 27 /* Vector: 27, Output Compare 5 */
|
||||
#define PIC32MZ_IRQ_T6 28 /* Vector: 28, Timer 6 */
|
||||
#define PIC32MZ_IRQ_ICE6 29 /* Vector: 29, Input Capture 6 Error */
|
||||
|
||||
#define PIC32MZ_IRQ_IC6 30 /* Vector: 30, Input Capture 6 */
|
||||
#define PIC32MZ_IRQ_OC6 31 /* Vector: 31, Output Compare 6 */
|
||||
#define PIC32MZ_IRQ_T7 32 /* Vector: 32, Timer 7 */
|
||||
#define PIC32MZ_IRQ_ICE7 33 /* Vector: 33, Input Capture 7 Error */
|
||||
#define PIC32MZ_IRQ_IC7 34 /* Vector: 34, Input Capture 7 */
|
||||
#define PIC32MZ_IRQ_OC7 35 /* Vector: 35, Output Compare 7 */
|
||||
#define PIC32MZ_IRQ_T8 36 /* Vector: 36, Timer 8 */
|
||||
#define PIC32MZ_IRQ_ICE8 37 /* Vector: 37, Input Capture 8 Error */
|
||||
#define PIC32MZ_IRQ_IC8 38 /* Vector: 38, Input Capture 8 */
|
||||
#define PIC32MZ_IRQ_OC8 39 /* Vector: 39, Output Compare 8 */
|
||||
|
||||
#define PIC32MZ_IRQ_T9 40 /* Vector: 40, Timer 9 */
|
||||
#define PIC32MZ_IRQ_ICE9 41 /* Vector: 41, Input Capture 9 Error */
|
||||
#define PIC32MZ_IRQ_IC9 42 /* Vector: 42, Input Capture 9 */
|
||||
#define PIC32MZ_IRQ_OC9 43 /* Vector: 43, Output Compare 9 */
|
||||
#define PIC32MZ_IRQ_AD1 44 /* Vector: 44, ADC1 Global Interrupt */
|
||||
#define PIC32MZ_IRQ_AD1FIFO 45 /* Vector: 45, ADC1 FIFO Data Ready Interrupt */
|
||||
#define PIC32MZ_IRQ_AD1CMP1 46 /* Vector: 46, ADC1 Digital Comparator 1 */
|
||||
#define PIC32MZ_IRQ_AD1CMP2 47 /* Vector: 47, ADC1 Digital Comparator 2 */
|
||||
#define PIC32MZ_IRQ_AD1CMP3 48 /* Vector: 48, ADC1 Digital Comparator 3 */
|
||||
#define PIC32MZ_IRQ_AD1CMP4 49 /* Vector: 49, ADC1 Digital Comparator 4 */
|
||||
|
||||
#define PIC32MZ_IRQ_AD1CMP5 50 /* Vector: 50, ADC1 Digital Comparator 5 */
|
||||
#define PIC32MZ_IRQ_AD1CMP6 51 /* Vector: 51, ADC1 Digital Comparator 6 */
|
||||
#define PIC32MZ_IRQ_AD1FLT1 52 /* Vector: 52, ADC1 Digital Filter 1 */
|
||||
#define PIC32MZ_IRQ_AD1FLT2 53 /* Vector: 53, ADC1 Digital Filter 2 */
|
||||
#define PIC32MZ_IRQ_AD1FLT3 54 /* Vector: 54, ADC1 Digital Filter 3 */
|
||||
#define PIC32MZ_IRQ_AD1FLT4 55 /* Vector: 55, ADC1 Digital Filter 4 */
|
||||
#define PIC32MZ_IRQ_AD1FLT5 56 /* Vector: 56, ADC1 Digital Filter 5 */
|
||||
#define PIC32MZ_IRQ_AD1FLT6 57 /* Vector: 57, ADC1 Digital Filter 6 */
|
||||
#define PIC32MZ_IRQ_AD1FAULT 59 /* Vector: 58, ADC1 Fault */
|
||||
#define PIC32MZ_IRQ_AD1DAT0 59 /* Vector: 59, ADC1 Data 0 */
|
||||
|
||||
#define PIC32MZ_IRQ_AD1DAT1 60 /* Vector: 60, ADC1 Data 1 */
|
||||
#define PIC32MZ_IRQ_AD1DAT2 61 /* Vector: 61, ADC1 Data 2 */
|
||||
#define PIC32MZ_IRQ_AD1DAT3 62 /* Vector: 62, ADC1 Data 3 */
|
||||
#define PIC32MZ_IRQ_AD1DAT4 63 /* Vector: 63, ADC1 Data 4 */
|
||||
#define PIC32MZ_IRQ_AD1DAT5 64 /* Vector: 64, ADC1 Data 5 */
|
||||
#define PIC32MZ_IRQ_AD1DAT6 65 /* Vector: 65, ADC1 Data 6 */
|
||||
#define PIC32MZ_IRQ_AD1DAT7 66 /* Vector: 66, ADC1 Data 7 */
|
||||
#define PIC32MZ_IRQ_AD1DAT8 67 /* Vector: 67, ADC1 Data 8 */
|
||||
#define PIC32MZ_IRQ_AD1DAT9 68 /* Vector: 68, ADC1 Data 9 */
|
||||
#define PIC32MZ_IRQ_AD1DAT10 69 /* Vector: 69, ADC1 Data 10 */
|
||||
|
||||
#define PIC32MZ_IRQ_AD1DAT11 70 /* Vector: 70, ADC1 Data 11 */
|
||||
#define PIC32MZ_IRQ_AD1DAT12 71 /* Vector: 71, ADC1 Data 12 */
|
||||
#define PIC32MZ_IRQ_AD1DAT13 72 /* Vector: 72, ADC1 Data 13 */
|
||||
#define PIC32MZ_IRQ_AD1DAT14 73 /* Vector: 73, ADC1 Data 14 */
|
||||
#define PIC32MZ_IRQ_AD1DAT15 74 /* Vector: 74, ADC1 Data 15 */
|
||||
#define PIC32MZ_IRQ_AD1DAT16 75 /* Vector: 75, ADC1 Data 16 */
|
||||
#define PIC32MZ_IRQ_AD1DAT17 76 /* Vector: 76, ADC1 Data 17 */
|
||||
#define PIC32MZ_IRQ_AD1DAT18 77 /* Vector: 77, ADC1 Data 18 */
|
||||
#define PIC32MZ_IRQ_AD1DAT19 78 /* Vector: 78, ADC1 Data 19 */
|
||||
#define PIC32MZ_IRQ_AD1DAT20 79 /* Vector: 79, ADC1 Data 20 */
|
||||
|
||||
#define PIC32MZ_IRQ_AD1DAT21 80 /* Vector: 80, ADC1 Data 21 */
|
||||
#define PIC32MZ_IRQ_AD1DAT22 81 /* Vector: 81, ADC1 Data 22 */
|
||||
#define PIC32MZ_IRQ_AD1DAT23 82 /* Vector: 82, ADC1 Data 23 */
|
||||
#define PIC32MZ_IRQ_AD1DAT24 83 /* Vector: 83, ADC1 Data 24 */
|
||||
#define PIC32MZ_IRQ_AD1DAT25 84 /* Vector: 84, ADC1 Data 25 */
|
||||
#define PIC32MZ_IRQ_AD1DAT26 85 /* Vector: 85, ADC1 Data 26 */
|
||||
#define PIC32MZ_IRQ_AD1DAT27 86 /* Vector: 86, ADC1 Data 27 */
|
||||
#define PIC32MZ_IRQ_AD1DAT28 87 /* Vector: 87, ADC1 Data 28 */
|
||||
#define PIC32MZ_IRQ_AD1DAT29 88 /* Vector: 88, ADC1 Data 29 */
|
||||
#define PIC32MZ_IRQ_AD1DAT30 89 /* Vector: 89, ADC1 Data 30 */
|
||||
|
||||
#define PIC32MZ_IRQ_AD1DAT31 90 /* Vector: 90, ADC1 Data 31 */
|
||||
#define PIC32MZ_IRQ_AD1DAT32 91 /* Vector: 91, ADC1 Data 32 */
|
||||
#define PIC32MZ_IRQ_AD1DAT33 92 /* Vector: 92, ADC1 Data 33 */
|
||||
#define PIC32MZ_IRQ_AD1DAT34 93 /* Vector: 93, ADC1 Data 34 */
|
||||
#define PIC32MZ_IRQ_AD1DAT35 94 /* Vector: 94, ADC1 Data 35 */
|
||||
#define PIC32MZ_IRQ_AD1DAT36 95 /* Vector: 95, ADC1 Data 36 */
|
||||
#define PIC32MZ_IRQ_AD1DAT37 96 /* Vector: 96, ADC1 Data 37 */
|
||||
#define PIC32MZ_IRQ_AD1DAT38 97 /* Vector: 97, ADC1 Data 38 */
|
||||
#define PIC32MZ_IRQ_AD1DAT39 98 /* Vector: 98, ADC1 Data 39 */
|
||||
#define PIC32MZ_IRQ_AD1DAT40 99 /* Vector: 99, ADC1 Data 40 */
|
||||
|
||||
#define PIC32MZ_IRQ_AD1DAT41 100 /* Vector: 100, ADC1 Data 41 */
|
||||
#define PIC32MZ_IRQ_AD1DAT42 101 /* Vector: 101, ADC1 Data 42 */
|
||||
#define PIC32MZ_IRQ_AD1DAT43 102 /* Vector: 102, ADC1 Data 43 */
|
||||
#define PIC32MZ_IRQ_AD1DAT44 103 /* Vector: 103, ADC1 Data 44 */
|
||||
#define PIC32MZ_IRQ_COREPERF 104 /* Vector: 104, Core Performance Counter Interrupt */
|
||||
#define PIC32MZ_IRQ_COREFDBG 105 /* Vector: 105, Core Fast Debug Channel Interrupt */
|
||||
#define PIC32MZ_IRQ_BUSPROT 106 /* Vector: 106, System Bus Protection Violation */
|
||||
#define PIC32MZ_IRQ_CTYPTO 107 /* Vector: 107, Crypto Engine Event */
|
||||
/* Vector: 108, Reserved */
|
||||
#define PIC32MZ_IRQ_SPI1F 109 /* Vector: 109, SPI1 Fault */
|
||||
|
||||
#define PIC32MZ_IRQ_SPI1RX 110 /* Vector: 110, SPI1 Receive Done */
|
||||
#define PIC32MZ_IRQ_SPI1TX 111 /* Vector: 111, SPI1 Transfer Done */
|
||||
#define PIC32MZ_IRQ_U1E 112 /* Vector: 112, UART1 Fault */
|
||||
#define PIC32MZ_IRQ_U1RX 113 /* Vector: 113, UART1 Receive Done */
|
||||
#define PIC32MZ_IRQ_U1TX 114 /* Vector: 114, UART1 Transfer Done */
|
||||
#define PIC32MZ_IRQ_I2C1COL 115 /* Vector: 115, I2C1 Bus Collision Event */
|
||||
#define PIC32MZ_IRQ_I2C1S 116 /* Vector: 116, I2C1 Slave Event */
|
||||
#define PIC32MZ_IRQ_I2C1M 117 /* Vector: 117, I2C1 Master Event */
|
||||
#define PIC32MZ_IRQ_PORTA 118 /* Vector: 118, PORTA Input Change Interrupt */
|
||||
#define PIC32MZ_IRQ_PORTB 119 /* Vector: 119, PORTB Input Change Interrupt */
|
||||
|
||||
#define PIC32MZ_IRQ_PORTC 120 /* Vector: 120, PORTC Input Change Interrupt */
|
||||
#define PIC32MZ_IRQ_PORTD 121 /* Vector: 121, PORTD Input Change Interrupt */
|
||||
#define PIC32MZ_IRQ_PORTE 122 /* Vector: 122, PORTE Input Change Interrupt */
|
||||
#define PIC32MZ_IRQ_PORTF 123 /* Vector: 123, PORTF Input Change Interrupt */
|
||||
#define PIC32MZ_IRQ_PORTG 124 /* Vector: 124, PORTG Input Change Interrupt */
|
||||
#define PIC32MZ_IRQ_PORTH 125 /* Vector: 125, PORTH Input Change Interrupt */
|
||||
#define PIC32MZ_IRQ_PORTJ 126 /* Vector: 126, PORTJ Input Change Interrupt */
|
||||
#define PIC32MZ_IRQ_PORTK 127 /* Vector: 127, PORTK Input Change Interrupt */
|
||||
#define PIC32MZ_IRQ_PMP 128 /* Vector: 128, Parallel Master Port */
|
||||
#define PIC32MZ_IRQ_PMPE 129 /* Vector: 129, Parallel Master Port Error */
|
||||
|
||||
#define PIC32MZ_IRQ_CMP1 130 /* Vector: 130, Comparator 1 Interrupt */
|
||||
#define PIC32MZ_IRQ_CMP2 131 /* Vector: 131, Comparator 2 Interrupt */
|
||||
#define PIC32MZ_IRQ_USBGEN 132 /* Vector: 132, USB General Event */
|
||||
#define PIC32MZ_IRQ_USBDMA 133 /* Vector: 133, USB DMA Event */
|
||||
#define PIC32MZ_IRQ_DMA0 134 /* Vector: 134, DMA Channel 0 */
|
||||
#define PIC32MZ_IRQ_DMA1 135 /* Vector: 135, DMA Channel 1 */
|
||||
#define PIC32MZ_IRQ_DMA2 136 /* Vector: 136, DMA Channel 2 */
|
||||
#define PIC32MZ_IRQ_DMA3 137 /* Vector: 137, DMA Channel 3 */
|
||||
#define PIC32MZ_IRQ_DMA4 138 /* Vector: 138, DMA Channel 4 */
|
||||
#define PIC32MZ_IRQ_DMA5 139 /* Vector: 139, DMA Channel 5 */
|
||||
|
||||
#define PIC32MZ_IRQ_DMA6 140 /* Vector: 140, DMA Channel 6 */
|
||||
#define PIC32MZ_IRQ_DMA7 141 /* Vector: 141, DMA Channel 7 */
|
||||
#define PIC32MZ_IRQ_SPI2F 142 /* Vector: 142, SPI2 Fault */
|
||||
#define PIC32MZ_IRQ_SPI2RX 143 /* Vector: 143, SPI2 Receive Done */
|
||||
#define PIC32MZ_IRQ_SPI2TX 144 /* Vector: 144, SPI2 Transfer Done */
|
||||
#define PIC32MZ_IRQ_U2E 145 /* Vector: 145, UART2 Fault */
|
||||
#define PIC32MZ_IRQ_U2RX 146 /* Vector: 146, UART2 Receive Done */
|
||||
#define PIC32MZ_IRQ_U2TX 147 /* Vector: 147, UART2 Transfer Done */
|
||||
#define PIC32MZ_IRQ_I2C2COL 148 /* Vector: 148, I2C2 Bus Collision Event */
|
||||
#define PIC32MZ_IRQ_I2C2S 149 /* Vector: 149, I2C2 Slave Event */
|
||||
|
||||
#define PIC32MZ_IRQ_I2C2M 150 /* Vector: 150, I2C2 Master Event */
|
||||
#define PIC32MZ_IRQ_CAN1 151 /* Vector: 151, Control Area Network 1 */
|
||||
#define PIC32MZ_IRQ_CAN2 152 /* Vector: 152, Control Area Network 2 */
|
||||
#define PIC32MZ_IRQ_ETH 153 /* Vector: 153, Ethernet interrupt */
|
||||
#define PIC32MZ_IRQ_SPI3F 154 /* Vector: 154, SPI3 Fault */
|
||||
#define PIC32MZ_IRQ_SPI3RX 155 /* Vector: 155, SPI3 Receive Done */
|
||||
#define PIC32MZ_IRQ_SPI3TX 156 /* Vector: 156, SPI3 Transfer Done */
|
||||
#define PIC32MZ_IRQ_U3E 157 /* Vector: 157, UART3 Fault */
|
||||
#define PIC32MZ_IRQ_U3RX 158 /* Vector: 158, UART3 Receive Done */
|
||||
#define PIC32MZ_IRQ_U3TX 159 /* Vector: 159, UART3 Transfer Done */
|
||||
|
||||
#define PIC32MZ_IRQ_I2C3COL 160 /* Vector: 160, I2C3 Bus Collision Event */
|
||||
#define PIC32MZ_IRQ_I2C3S 161 /* Vector: 161, I2C3 Slave Event */
|
||||
#define PIC32MZ_IRQ_I2C3M 162 /* Vector: 162, I2C3 Master Event */
|
||||
#define PIC32MZ_IRQ_SPI4F 163 /* Vector: 163, SPI4 Fault */
|
||||
#define PIC32MZ_IRQ_SPI4RX 164 /* Vector: 164, SPI4 Receive Done */
|
||||
#define PIC32MZ_IRQ_SPI4TX 165 /* Vector: 165, SPI4 Transfer Done */
|
||||
#define PIC32MZ_IRQ_RTCC 166 /* Vector: 166, Real-Time Clock and Calendar */
|
||||
#define PIC32MZ_IRQ_FCE 167 /* Vector: 167, Flash Control Event */
|
||||
#define PIC32MZ_IRQ_PMSEC 168 /* Vector: 168, Prefetch Module SEC Event */
|
||||
#define PIC32MZ_IRQ_SQI1 169 /* Vector: 169, SQI1 Event */
|
||||
|
||||
#define PIC32MZ_IRQ_U4E 170 /* Vector: 170, UART4 Fault */
|
||||
#define PIC32MZ_IRQ_U4RX 171 /* Vector: 171, UART4 Receive Done */
|
||||
#define PIC32MZ_IRQ_U4TX 172 /* Vector: 172, UART4 Transfer Done */
|
||||
#define PIC32MZ_IRQ_I2C4COL 173 /* Vector: 173, I2C4 Bus Collision Event */
|
||||
#define PIC32MZ_IRQ_I2C4S 174 /* Vector: 174, I2C4 Slave Event */
|
||||
#define PIC32MZ_IRQ_I2C4M 175 /* Vector: 175, I2C4 Master Event */
|
||||
#define PIC32MZ_IRQ_SPI5F 176 /* Vector: 176, SPI5 Fault */
|
||||
#define PIC32MZ_IRQ_SPI5RX 177 /* Vector: 177, SPI5 Receive Done */
|
||||
#define PIC32MZ_IRQ_SPI5TX 178 /* Vector: 178, SPI5 Transfer Done */
|
||||
#define PIC32MZ_IRQ_U5E 179 /* Vector: 179, UART5 Fault */
|
||||
|
||||
#define PIC32MZ_IRQ_U5RX 180 /* Vector: 180, UART5 Receive Done */
|
||||
#define PIC32MZ_IRQ_U5TX 181 /* Vector: 181, UART5 Transfer Done */
|
||||
#define PIC32MZ_IRQ_I2C5COL 182 /* Vector: 182, I2C5 Bus Collision Event */
|
||||
#define PIC32MZ_IRQ_I2C5S 183 /* Vector: 183, I2C5 Slave Event */
|
||||
#define PIC32MZ_IRQ_I2C5M 184 /* Vector: 184, I2C5 Master Event */
|
||||
#define PIC32MZ_IRQ_SPI6F 185 /* Vector: 185, SPI6 Fault */
|
||||
#define PIC32MZ_IRQ_SPI6RX 186 /* Vector: 186, SPI6 Receive Done */
|
||||
#define PIC32MZ_IRQ_SPI6TX 187 /* Vector: 187, SPI6 Transfer Done */
|
||||
#define PIC32MZ_IRQ_U6E 188 /* Vector: 188, UART6 Fault */
|
||||
#define PIC32MZ_IRQ_U6RX 189 /* Vector: 189, UART6 Receive Done */
|
||||
|
||||
#define PIC32MZ_IRQ_U6TX 190 /* Vector: 190, UART6 Transfer Done */
|
||||
/* Vector: 191, Reserved */
|
||||
#define PIC32MZ_IRQ_ADCESR 192 /* Vector: ADC End of Scan Ready */
|
||||
#define PIC32MZ_IRQ_ADCACR 193 /* Vector: ADC Analog Circuits Ready */
|
||||
#define PIC32MZ_IRQ_ADCUR 194 /* Vector: ADC Update Ready */
|
||||
/* Vector: 195, Reserved */
|
||||
#define PIC32MZ_IRQ_ADCGEIR 196 /* Vector: ADC Group Early Interrupt Request */
|
||||
/* Vector: 197, Reserved */
|
||||
#define PIC32MZ_IRQ_ADC0ER 198 /* Vector: ADC0 Early Interrupt */
|
||||
#define PIC32MZ_IRQ_ADC1ER 199 /* Vector: ADC1 Early Interrupt */
|
||||
#define PIC32MZ_IRQ_ADC2ER 200 /* Vector: ADC2 Early Interrupt */
|
||||
#define PIC32MZ_IRQ_ADC3ER 201 /* Vector: ADC3 Early Interrupt */
|
||||
#define PIC32MZ_IRQ_ADC4ER 202 /* Vector: ADC4 Early Interrupt */
|
||||
/* Vector: 203, Reserved */
|
||||
/* Vector: 204, Reserved */
|
||||
#define PIC32MZ_IRQ_ADC7ER 205 /* Vector: ADC7 Early Interrupt */
|
||||
#define PIC32MZ_IRQ_ADC0WI 206 /* Vector: ADC0 Warm Interrupt */
|
||||
#define PIC32MZ_IRQ_ADC1WI 207 /* Vector: ADC1 Warm Interrupt */
|
||||
#define PIC32MZ_IRQ_ADC2WI 208 /* Vector: ADC2 Warm Interrupt */
|
||||
#define PIC32MZ_IRQ_ADC3WI 209 /* Vector: ADC3 Warm Interrupt */
|
||||
#define PIC32MZ_IRQ_ADC4WI 210 /* Vector: ADC4 Warm Interrupt */
|
||||
/* Vector: 211, Reserved */
|
||||
/* Vector: 212, Reserved */
|
||||
#define PIC32MZ_IRQ_ADC7WI 213 /* Vector: ADC7 Warm Interrupt */
|
||||
|
||||
#define PIC32MZ_IRQ_BAD 214 /* Not a real IRQ number */
|
||||
#define NR_IRQS 214
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Inline functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_MIPS_INCLUDE_PIC32MZ_IRQ_PIC32MZXXXEF_H */
|
||||
|
||||
@@ -14,13 +14,32 @@ config ARCH_CHIP_PIC32MZ2048ECH
|
||||
bool "PIC32MZ2048ECH"
|
||||
select ARCH_CHIP_PIC32MZEC
|
||||
---help---
|
||||
Microchip PIC32MZ2048ECH (MIPS32 M14K)
|
||||
Microchip PIC32MZ2048ECH (MIPS32 M14K) such as the
|
||||
PIC32MZ2048ECH144-I/PH used with the PIC32MZ EC STARTER KIT
|
||||
DM320006 (no longer available)
|
||||
|
||||
config ARCH_CHIP_PIC32MZ2048ECM
|
||||
bool "PIC32MZ2048ECM"
|
||||
select ARCH_CHIP_PIC32MZEC
|
||||
---help---
|
||||
Microchip PIC32MZ2048ECM with Crypto Engine (MIPS32 M14K)
|
||||
Microchip PIC32MZ2048ECM with Crypto Engine (MIPS32 M14K) such as
|
||||
the ARCH_CHIP_PIC32MZ2048ECM144-I/PH used with the PIC32MZ EC
|
||||
STARTER KIT DM320006-C (no longer available)
|
||||
|
||||
config ARCH_CHIP_PIC32MZ2048EFH
|
||||
bool "PIC32MZ2048EFH"
|
||||
select ARCH_CHIP_PIC32MZEF
|
||||
---help---
|
||||
Microchip PIC32MZ2048EFH (MIPS32 M14K) such as the
|
||||
PIC32MZ2048EFH144-I/PH used in the PIC32MZ EF STARTER KIT or as the
|
||||
PIC32MZ2048EFH100 used with the Mikro Flip&Clip for PIC32MZ.
|
||||
|
||||
config ARCH_CHIP_PIC32MZ2048EFM
|
||||
bool "PIC32MZ2048EFM"
|
||||
select ARCH_CHIP_PIC32MZEF
|
||||
---help---
|
||||
Microchip PIC32MZ2048EFH with Crypto Engine (MIPS32 M14K) such as
|
||||
the PIC32MZ2048EFM144-I/PH used in the PIC32MZ EF STARTER KIT
|
||||
|
||||
endchoice
|
||||
|
||||
@@ -29,6 +48,11 @@ config ARCH_CHIP_PIC32MZEC
|
||||
default n
|
||||
select ARCH_MIPS_M14K
|
||||
|
||||
config ARCH_CHIP_PIC32MZEF
|
||||
bool
|
||||
default n
|
||||
select ARCH_MIPS_M14K
|
||||
|
||||
config PIC32MZ_MVEC
|
||||
bool
|
||||
default n
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/mips/src/pic32mz/chip/pic32mz-features.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -44,6 +44,8 @@
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_PIC32MZEC)
|
||||
# include <chip/pic32mzec-features.h>
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MZEF)
|
||||
# include <chip/pic32mzef-features.h>
|
||||
#else
|
||||
# error Unknown PIC32MZ family
|
||||
#endif
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/mips/src/pic32mz/chip/pic32mz-memorymap.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -44,6 +44,8 @@
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_PIC32MZEC)
|
||||
# include "chip/pic32mzec-memorymap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MZEF)
|
||||
# include "chip/pic32mzef-memorymap.h"
|
||||
#else
|
||||
# error Unknown PIC32MZ family
|
||||
#endif
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/********************************************************************************************
|
||||
* arch/mips/src/pic32mz/pic32mz-pps.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -51,6 +51,8 @@
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_PIC32MZEC)
|
||||
# include "chip/pic32mzec-pps.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MZEF)
|
||||
# include "chip/pic32mzef-pps.h"
|
||||
#else
|
||||
# error Unknown PIC32MZ family
|
||||
#endif
|
||||
|
||||
@@ -432,10 +432,10 @@
|
||||
# define DEVCFG1_FWDT_DISABLED (0 << 23) /* Bit 23=0: Watchdog disabled, can be enabled */
|
||||
#define DEVCFG1_FWDTWINSZ_SHIFT (24) /* Bits 24-25: Watchdog Timer Window Size bits */
|
||||
#define DEVCFG1_FWDTWINSZ_MASK (3 << DEVCFG1_FWDTWINSZ_SHIFT)
|
||||
# define DEVCFG1_FWDTWINSZ_75 (0 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 75% */
|
||||
# define DEVCFG1_FWDTWINSZ_50 (1 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 50% */
|
||||
# define DEVCFG1_FWDTWINSZ_37p5 (2 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 37.5% */
|
||||
# define DEVCFG1_FWDTWINSZ_25 (3 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 25% */
|
||||
# define DEVCFG1_FWDTWINSZ_75 (0 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 75% */
|
||||
# define DEVCFG1_FWDTWINSZ_50 (1 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 50% */
|
||||
# define DEVCFG1_FWDTWINSZ_37p5 (2 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 37.5% */
|
||||
# define DEVCFG1_FWDTWINSZ_25 (3 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 25% */
|
||||
#define DEVCFG1_DMTCNT_SHIFT (26) /* Bits 26-30: Deadman Timer Count Select bits */
|
||||
#define DEVCFG1_DMTCNT_MASK (31 << DEVCFG1_DMTCNT_SHIFT)
|
||||
# define DEVCFG1_DMTCNT(n) ((uint32_t)((n)-8) << DEVCFG1_DMTCNT_SHIFT) /* 2**n, n=8..31 */
|
||||
|
||||
@@ -117,26 +117,33 @@
|
||||
#define PIC32MZ_CVREF_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000e00) /* CVREF */
|
||||
#define PIC32MZ_OSC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00001200) /* Oscillator */
|
||||
#define PIC32MZ_PPS_K1BASE (PIC32MZ_SFR_K1BASE + 0x00001400) /* PPS */
|
||||
|
||||
#define PIC32MZ_INT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00010000) /* Interrupt Controller */
|
||||
#define PIC32MZ_DMA_K1BASE (PIC32MZ_SFR_K1BASE + 0x00011000) /* DMA */
|
||||
|
||||
#define PIC32MZ_I2C_K1BASE (PIC32MZ_SFR_K1BASE + 0x00020000) /* I2C1-I2C5 */
|
||||
#define PIC32MZ_SPI_K1BASE (PIC32MZ_SFR_K1BASE + 0x00021000) /* SPI1-SPI6 */
|
||||
#define PIC32MZ_UART_K1BASE (PIC32MZ_SFR_K1BASE + 0x00022000) /* UART1-UART6 */
|
||||
#define PIC32MZ_PMP_K1BASE (PIC32MZ_SFR_K1BASE + 0x0002e000) /* PMP */
|
||||
|
||||
#define PIC32MZ_TIMER_K1BASE (PIC32MZ_SFR_K1BASE + 0x00040000) /* Timer1-Timer9 */
|
||||
#define PIC32MZ_IC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00042000) /* IC1-IC9 */
|
||||
#define PIC32MZ_OC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00044000) /* OC1-OC9 */
|
||||
#define PIC32MZ_ADC1_K1BASE (PIC32MZ_SFR_K1BASE + 0x0004b000) /* ADC1 */
|
||||
#define PIC32MZ_CMP_K1BASE (PIC32MZ_SFR_K1BASE + 0x0004c000) /* Comparator 1, 2 */
|
||||
|
||||
#define PIC32MZ_IOPORT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00060000) /* PORTA-PORTK */
|
||||
|
||||
#define PIC32MZ_CAN_K1BASE (PIC32MZ_SFR_K1BASE + 0x00080000) /* CAN1 and CAN2 */
|
||||
#define PIC32MZ_ETH_K1BASE (PIC32MZ_SFR_K1BASE + 0x00082000) /* Ethernet */
|
||||
|
||||
#define PIC32MZ_PREFETCH_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e0000) /* Prefetch */
|
||||
#define PIC32MZ_EBI_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e1000) /* EBI */
|
||||
#define PIC32MZ_SQI1_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e2000) /* SQI1 */
|
||||
#define PIC32MZ_USB_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e3000) /* USB */
|
||||
#define PIC32MZ_CRYPTO_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e5000) /* Crypto */
|
||||
#define PIC32MZ_RNG_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e6000) /* RNG */
|
||||
|
||||
#define PIC32MZ_SYSBUS_K1BASE (PIC32MZ_SFR_K1BASE + 0x000f0000) /* System Bus */
|
||||
|
||||
#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_MEMORYMAP_H */
|
||||
|
||||
@@ -47,6 +47,8 @@
|
||||
********************************************************************************************/
|
||||
/* PPS Register Offsets *********************************************************************/
|
||||
|
||||
/* Peripheral pin select input register map */
|
||||
|
||||
#define PIC32MZ_INTnR_OFFSET(n) (0x1400 + ((n << 2)) /* n=1..4 */
|
||||
# define PIC32MZ_INT1R_OFFSET 0x1404
|
||||
# define PIC32MZ_INT2R_OFFSET 0x1408
|
||||
@@ -93,7 +95,7 @@
|
||||
# define PIC32MZ_SDI4R_OFFSET 0x14c0
|
||||
# define PIC32MZ_SDI5R_OFFSET 0x14cc
|
||||
# define PIC32MZ_SDI6R_OFFSET 0x14d8
|
||||
#define PIC32MZ_SSnR_OFFSET(n) (0x1490 + 12*(n)) /* n=1..6 */
|
||||
#define PIC32MZ_SSnR_OFFSET(n) (0x1494 + 12*(n)) /* n=1..6 */
|
||||
# define PIC32MZ_SS1R_OFFSET 0x14a0
|
||||
# define PIC32MZ_SS2R_OFFSET 0x14ac
|
||||
# define PIC32MZ_SS3R_OFFSET 0x14b8
|
||||
@@ -107,6 +109,9 @@
|
||||
# define PIC32MZ_REFCLKI1R_OFFSET 0x14e8
|
||||
# define PIC32MZ_REFCLKI3R_OFFSET 0x14f0
|
||||
# define PIC32MZ_REFCLKI4R_OFFSET 0x14f4
|
||||
|
||||
/* Peripheral pin select output register map */
|
||||
|
||||
#define PIC32MZ_RPAnR_OFFSET(n) (0x1500 + ((n) << 2)) /* n=14,15 */
|
||||
# define PIC32MZ_RPA14R_OFFSET 0x1538
|
||||
# define PIC32MZ_RPA15R_OFFSET 0x153c
|
||||
@@ -236,6 +241,9 @@
|
||||
# define PIC32MZ_REFCLKI1R (PIC32MZ_SFR_K1BASE+PIC32MZ_REFCLKI1R_OFFSET)
|
||||
# define PIC32MZ_REFCLKI3R (PIC32MZ_SFR_K1BASE+PIC32MZ_REFCLKI3R_OFFSET)
|
||||
# define PIC32MZ_REFCLKI4R (PIC32MZ_SFR_K1BASE+PIC32MZ_REFCLKI4R_OFFSET)
|
||||
|
||||
/* Peripheral pin select output register map */
|
||||
|
||||
#define PIC32MZ_RPAnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_RPAnR_OFFSET(n))
|
||||
# define PIC32MZ_RPA14R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPA14R_OFFSET)
|
||||
# define PIC32MZ_RPA15R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPA15R_OFFSET)
|
||||
@@ -764,8 +772,8 @@
|
||||
#define T2CKR_RPF1 4
|
||||
#define T2CKR_RPF4 2
|
||||
#define T2CKR_RPG1 12
|
||||
|
||||
#define T2CKR_RPG8 1
|
||||
|
||||
#define T3CKR_RPB0 5
|
||||
#define T3CKR_RPB7 7
|
||||
#define T3CKR_RPB8 2
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,147 @@
|
||||
/************************************************************************************
|
||||
* arch/mips/src/pic32mz/chip/pic32mzef-memorymap.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_MEMORYMAP_H
|
||||
#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "mips32-memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Physical Memory Map **************************************************************/
|
||||
/* Memory Regions */
|
||||
|
||||
#define PIC32MZ_DATAMEM_PBASE 0x00000000 /* Size depends on CHIP_DATAMEM_KB */
|
||||
#define PIC32MZ_PROGFLASH_PBASE 0x1d000000 /* Size depends on CHIP_PROGFLASH_KB */
|
||||
#define PIC32MZ_SFR_PBASE 0x1f800000 /* Special function registers */
|
||||
#define PIC32MZ_BOOTFLASH_PBASE 0x1fc00000 /* Size depends on CHIP_BOOTFLASH_KB */
|
||||
#define PIC32MZ_EBIMEM_PBASE 0x20000000 /* External memory via EBI */
|
||||
#define PIC32MZ_SQIMEM_PBASE 0x30000000 /* External memory via SQI */
|
||||
|
||||
/* Boot FLASH */
|
||||
|
||||
#define PIC32MZ_LOWERBOOT_PBASE 0x1fc00000 /* Lower boot alias */
|
||||
#define PIC32MZ_BOOTCFG_PBASE 0x1fc0ff00 /* Configuration space */
|
||||
#define PIC32MZ_UPPERBOOT_PBASE 0x1fc20000 /* Upper boot alias */
|
||||
#define PIC32MZ_BOOT1_PBASE 0x1fc40000 /* Boot flash 1 */
|
||||
#define PIC32MZ_SEQCFG1_PBASE 0x1fc4ff00 /* Sequence/configuration space 1 */
|
||||
#define PIC32MZ_DEVSN_PBASE 0x1fc54000 /* Device serial number */
|
||||
#define PIC32MZ_BOOT2_PBASE 0x1fc60000 /* Boot flash 2 */
|
||||
#define PIC32MZ_SEQCFG2_PBASE 0x1fc6ff00 /* Sequence/configuration space 2 */
|
||||
|
||||
/* Virtual Memory Map ***************************************************************/
|
||||
|
||||
#define PIC32MZ_DATAMEM_K0BASE (KSEG0_BASE + PIC32MZ_DATAMEM_PBASE)
|
||||
#define PIC32MZ_PROGFLASH_K0BASE (KSEG0_BASE + PIC32MZ_PROGFLASH_PBASE)
|
||||
#define PIC32MZ_SFR_K0BASE (KSEG0_BASE + PIC32MZ_SFR_PBASE)
|
||||
#define PIC32MZ_BOOTFLASH_K0BASE (KSEG0_BASE + PIC32MZ_BOOTFLASH_PBASE)
|
||||
#define PIC32MZ_EBIMEM_K0BASE (KSEG0_BASE + PIC32MZ_EBIMEM_PBASE)
|
||||
#define PIC32MZ_SQIMEM_K0BASE (KSEG0_BASE + PIC32MZ_SQIMEM_PBASE)
|
||||
|
||||
#define PIC32MZ_DATAMEM_K1BASE (KSEG1_BASE + PIC32MZ_DATAMEM_PBASE)
|
||||
#define PIC32MZ_PROGFLASH_K1BASE (KSEG1_BASE + PIC32MZ_PROGFLASH_PBASE)
|
||||
#define PIC32MZ_SFR_K1BASE (KSEG1_BASE + PIC32MZ_SFR_PBASE)
|
||||
#define PIC32MZ_BOOTFLASH_K1BASE (KSEG1_BASE + PIC32MZ_BOOTFLASH_PBASE)
|
||||
#define PIC32MZ_EBIMEM_K1BASE (KSEG1_BASE + PIC32MZ_EBIMEM_PBASE)
|
||||
#define PIC32MZ_SQIMEM_K1BASE (KSEG1_BASE + PIC32MZ_SQIMEM_PBASE)
|
||||
|
||||
/* Boot FLASH */
|
||||
|
||||
#define PIC32MZ_LOWERBOOT_K0BASE (KSEG0_BASE + PIC32MZ_LOWERBOOT_PBASE)
|
||||
#define PIC32MZ_BOOTCFG_K0BASE (KSEG0_BASE + PIC32MZ_BOOTCFG_PBASE)
|
||||
#define PIC32MZ_UPPERBOOT_K0BASE (KSEG0_BASE + PIC32MZ_UPPERBOOT_PBASE)
|
||||
#define PIC32MZ_BOOT1_K0BASE (KSEG0_BASE + PIC32MZ_BOOT1_PBASE)
|
||||
#define PIC32MZ_SEQCFG1_K0BASE (KSEG0_BASE + PIC32MZ_SEQCFG1_PBASE)
|
||||
#define PIC32MZ_DEVSN_K0BASE (KSEG0_BASE + PIC32MZ_DEVSN_PBASE)
|
||||
#define PIC32MZ_BOOT2_K0BASE (KSEG0_BASE + PIC32MZ_BOOT2_PBASE)
|
||||
#define PIC32MZ_SEQCFG2_K0BASE (KSEG0_BASE + PIC32MZ_SEQCFG2_PBASE)
|
||||
|
||||
#define PIC32MZ_LOWERBOOT_K1BASE (KSEG1_BASE + PIC32MZ_LOWERBOOT_PBASE)
|
||||
#define PIC32MZ_BOOTCFG_K1BASE (KSEG1_BASE + PIC32MZ_BOOTCFG_PBASE)
|
||||
#define PIC32MZ_UPPERBOOT_K1BASE (KSEG1_BASE + PIC32MZ_UPPERBOOT_PBASE)
|
||||
#define PIC32MZ_BOOT1_K1BASE (KSEG1_BASE + PIC32MZ_BOOT1_PBASE)
|
||||
#define PIC32MZ_SEQCFG1_K1BASE (KSEG1_BASE + PIC32MZ_SEQCFG1_PBASE)
|
||||
#define PIC32MZ_DEVSN_K1BASE (KSEG1_BASE + PIC32MZ_DEVSN_PBASE)
|
||||
#define PIC32MZ_BOOT2_K1BASE (KSEG1_BASE + PIC32MZ_BOOT2_PBASE)
|
||||
#define PIC32MZ_SEQCFG2_K1BASE (KSEG1_BASE + PIC32MZ_SEQCFG2_PBASE)
|
||||
|
||||
/* Register Base Addresses **********************************************************/
|
||||
|
||||
#define PIC32MZ_CONFIG_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000000) /* Configuration */
|
||||
#define PIC32MZ_FLASHC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000600) /* Flash Controller */
|
||||
#define PIC32MZ_WDT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000800) /* Watchdog Timer */
|
||||
#define PIC32MZ_DMT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000a00) /* Deadman Timer */
|
||||
#define PIC32MZ_RTCC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000c00) /* RTCC */
|
||||
#define PIC32MZ_CVREF_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000e00) /* CVREF */
|
||||
#define PIC32MZ_OSC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00001200) /* Oscillator */
|
||||
#define PIC32MZ_PPS_K1BASE (PIC32MZ_SFR_K1BASE + 0x00001400) /* PPS */
|
||||
|
||||
#define PIC32MZ_INT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00010000) /* Interrupt Controller */
|
||||
#define PIC32MZ_DMA_K1BASE (PIC32MZ_SFR_K1BASE + 0x00011000) /* DMA */
|
||||
|
||||
#define PIC32MZ_I2C_K1BASE (PIC32MZ_SFR_K1BASE + 0x00020000) /* I2C1-I2C5 */
|
||||
#define PIC32MZ_SPI_K1BASE (PIC32MZ_SFR_K1BASE + 0x00021000) /* SPI1-SPI6 */
|
||||
#define PIC32MZ_UART_K1BASE (PIC32MZ_SFR_K1BASE + 0x00022000) /* UART1-UART6 */
|
||||
#define PIC32MZ_PMP_K1BASE (PIC32MZ_SFR_K1BASE + 0x0002e000) /* PMP */
|
||||
|
||||
#define PIC32MZ_TIMER_K1BASE (PIC32MZ_SFR_K1BASE + 0x00040000) /* Timer1-Timer9 */
|
||||
#define PIC32MZ_IC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00042000) /* IC1-IC9 */
|
||||
#define PIC32MZ_OC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00044000) /* OC1-OC9 */
|
||||
#define PIC32MZ_ADC1_K1BASE (PIC32MZ_SFR_K1BASE + 0x0004b000) /* ADC1 */
|
||||
#define PIC32MZ_CMP_K1BASE (PIC32MZ_SFR_K1BASE + 0x0004c000) /* Comparator 1, 2 */
|
||||
|
||||
#define PIC32MZ_IOPORT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00060000) /* PORTA-PORTK */
|
||||
|
||||
#define PIC32MZ_CAN_K1BASE (PIC32MZ_SFR_K1BASE + 0x00080000) /* CAN1 and CAN2 */
|
||||
#define PIC32MZ_ETH_K1BASE (PIC32MZ_SFR_K1BASE + 0x00082000) /* Ethernet */
|
||||
#define PIC32MZ_USBCR_K1BASE (PIC32MZ_SFR_K1BASE + 0x00084000) /* USBCR */
|
||||
|
||||
#define PIC32MZ_PREFETCH_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e0000) /* Prefetch */
|
||||
#define PIC32MZ_EBI_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e1000) /* EBI */
|
||||
#define PIC32MZ_SQI1_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e2000) /* SQI1 */
|
||||
#define PIC32MZ_USB_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e3000) /* USB */
|
||||
#define PIC32MZ_CRYPTO_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e5000) /* Crypto */
|
||||
#define PIC32MZ_RNG_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e6000) /* RNG */
|
||||
|
||||
#define PIC32MZ_SYSBUS_K1BASE (PIC32MZ_SFR_K1BASE + 0x000f0000) /* System Bus */
|
||||
|
||||
#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_MEMORYMAP_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -537,6 +537,20 @@
|
||||
|
||||
/* Not yet configurable settings */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_PIC32MZEC)
|
||||
# define CONFIG_PIC32MX_SMCLR 0
|
||||
# define CONFIG_PIC32MX_SOSCGAIN 0
|
||||
# define CONFIG_PIC32MX_SOSCBOOST 0
|
||||
# define CONFIG_PIC32MX_POSCGAIN 0
|
||||
# define CONFIG_PIC32MX_POSCBOOST 0
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MZEF)
|
||||
# define CONFIG_PIC32MX_SMCLR DEVCFG0_SMCLR
|
||||
# define CONFIG_PIC32MX_SOSCGAIN DEVCFG0_SOSCGAIN_HIGH
|
||||
# define CONFIG_PIC32MX_SOSCBOOST DEVCFG0_SOSCBOOST
|
||||
# define CONFIG_PIC32MX_POSCGAIN DEVCFG0_POSCGAIN_HIGH
|
||||
# define CONFIG_PIC32MX_POSCBOOST DEVCFG0_POSCBOOST
|
||||
#endif
|
||||
|
||||
#define CONFIG_PIC32MZ_FSLEEP DEVCFG0_FSLEEP_OFF
|
||||
#define CONFIG_PIC32MZ_DBGPER DEVCFG0_DBGPER_ALL
|
||||
#define CONFIG_PIC32MZ_EJTAGBEN DEVCFG0_EJTAG_NORMAL
|
||||
|
||||
@@ -690,29 +690,31 @@ devcfg3:
|
||||
DEVCFG3_RWO
|
||||
|
||||
devcfg2:
|
||||
.long CONFIG_PIC32MZ_PLLIDIV | CONFIG_PIC32MZ_FPLLRNG | \
|
||||
CONFIG_PIC32MZ_FPLLICLK | CONFIG_PIC32MZ_PLLMULT | \
|
||||
CONFIG_PIC32MZ_PLLODIV | CONFIG_PIC32MZ_UPLLFSEL | \
|
||||
.long CONFIG_PIC32MZ_PLLIDIV | CONFIG_PIC32MZ_FPLLRNG | \
|
||||
CONFIG_PIC32MZ_FPLLICLK | CONFIG_PIC32MZ_PLLMULT | \
|
||||
CONFIG_PIC32MZ_PLLODIV | CONFIG_PIC32MZ_UPLLFSEL | \
|
||||
DEVCFG2_RWO
|
||||
|
||||
devcfg1:
|
||||
.long CONFIG_PIC32MZ_FNOSC | CONFIG_PIC32MZ_DMTINV |\
|
||||
CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_IESO | \
|
||||
CONFIG_PIC32MZ_POSCMOD | CONFIG_PIC32MZ_OSCIOFNC | \
|
||||
CONFIG_PIC32MZ_FCKSM | CONFIG_PIC32MZ_WDTPS | \
|
||||
CONFIG_PIC32MZ_WDTSPGM | CONFIG_PIC32MZ_WINDIS | \
|
||||
CONFIG_PIC32MZ_FWDTEN | CONFIG_PIC32MZ_FWDTWINSZ | \
|
||||
CONFIG_PIC32MZ_DMTCNT | CONFIG_PIC32MZ_FSOSCEN | \
|
||||
CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_FDMTEN | \
|
||||
.long CONFIG_PIC32MZ_FNOSC | CONFIG_PIC32MZ_DMTINV |\
|
||||
CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_IESO | \
|
||||
CONFIG_PIC32MZ_POSCMOD | CONFIG_PIC32MZ_OSCIOFNC | \
|
||||
CONFIG_PIC32MZ_FCKSM | CONFIG_PIC32MZ_WDTPS | \
|
||||
CONFIG_PIC32MZ_WDTSPGM | CONFIG_PIC32MZ_WINDIS | \
|
||||
CONFIG_PIC32MZ_FWDTEN | CONFIG_PIC32MZ_FWDTWINSZ | \
|
||||
CONFIG_PIC32MZ_DMTCNT | CONFIG_PIC32MZ_FSOSCEN | \
|
||||
CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_FDMTEN | \
|
||||
DEVCFG1_RWO
|
||||
|
||||
devcfg0:
|
||||
.long CONFIG_PIC32MZ_DEBUGGER | CONFIG_PIC32MZ_JTAGEN | \
|
||||
CONFIG_PIC32MZ_ICESEL | CONFIG_PIC32MZ_TRCEN | \
|
||||
CONFIG_PIC32MZ_BOOTISA | CONFIG_PIC32MZ_FECCCON | \
|
||||
CONFIG_PIC32MZ_FSLEEP | CONFIG_PIC32MZ_DBGPER | \
|
||||
CONFIG_PIC32MZ_EJTAGBEN | DEVCFG0_RW0
|
||||
|
||||
.long CONFIG_PIC32MZ_DEBUGGER | CONFIG_PIC32MZ_JTAGEN | \
|
||||
CONFIG_PIC32MZ_ICESEL | CONFIG_PIC32MZ_TRCEN | \
|
||||
CONFIG_PIC32MZ_BOOTISA | CONFIG_PIC32MZ_FECCCON | \
|
||||
CONFIG_PIC32MZ_FSLEEP | CONFIG_PIC32MZ_DBGPER | \
|
||||
CONFIG_PIC32MX_SMCLR | CONFIG_PIC32MX_SOSCGAIN | \
|
||||
CONFIG_PIC32MX_SOSCBOOST | CONFIG_PIC32MX_POSCGAIN | \
|
||||
CONFIG_PIC32MX_POSCBOOST | CONFIG_PIC32MZ_EJTAGBEN | \
|
||||
DEVCFG0_RW0
|
||||
.size devcfg, .-devcfg
|
||||
|
||||
/* Every word in the configuration space and sequence space has an
|
||||
|
||||
@@ -28,7 +28,7 @@ STATUS
|
||||
b) Execute the following command which claims to have successfully
|
||||
written to FLASH.
|
||||
|
||||
/bossac.exe --info --debug --port COM7 --usb-port=0 --erase --write --verify -b nuttx.bin -R
|
||||
bossac.exe --info --debug --port COM7 --usb-port=0 --erase --write --verify -b nuttx.bin -R
|
||||
|
||||
But the code does not boot. There is no indication of life.
|
||||
|
||||
|
||||
Reference in New Issue
Block a user