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Fix some spacing problems

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This commit is contained in:
Gregory Nutt
2015-10-04 14:59:08 -06:00
parent 4435c1bfb7
commit 6fc6d17760
75 changed files with 404 additions and 400 deletions
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arch/arm/src/a1x/a1x_irq.c
+4 -4
View File
@@ -226,10 +226,10 @@ uint32_t *arm_decodeirq(uint32_t *regs)
#if 0 /* Use PEND registers instead */
uint32_t regval;
/* During initialization, the BASE address register was set to zero.
* Therefore, when we read the VECTOR address register, we get the IRQ number
* shifted left by two.
*/
/* During initialization, the BASE address register was set to zero.
* Therefore, when we read the VECTOR address register, we get the IRQ number
* shifted left by two.
*/
regval = getreg32(A1X_INTC_VECTOR);
arch/arm/src/a1x/a1x_pio.c
+2 -2
View File
@@ -154,9 +154,9 @@ static int a1x_pio_interrupt(int irq, void *context)
pending >>= 2;
}
/* Check for pending interrupts in any of the last bits */
/* Check for pending interrupts in any of the last bits */
else
else
{
if ((pending & 0x00000001) == 0)
{
arch/arm/src/arm/up_assert.c
+8 -8
View File
@@ -312,16 +312,16 @@ static void _up_assert(int errorcode)
if (current_regs || ((struct tcb_s*)g_readytorun.head)->pid == 0)
{
(void)irqsave();
for (;;)
{
(void)irqsave();
for (;;)
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
up_mdelay(250);
board_led_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
up_mdelay(250);
#endif
}
}
}
else
{
arch/arm/src/armv6-m/up_assert.c
+8 -8
View File
@@ -367,16 +367,16 @@ static void _up_assert(int errorcode)
if (current_regs || ((struct tcb_s*)g_readytorun.head)->pid == 0)
{
(void)irqsave();
for (;;)
{
(void)irqsave();
for (;;)
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
up_mdelay(250);
board_led_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
up_mdelay(250);
#endif
}
}
}
else
{
arch/arm/src/armv7-a/arm_assert.c
+8 -8
View File
@@ -367,16 +367,16 @@ static void _up_assert(int errorcode)
if (current_regs || ((struct tcb_s*)g_readytorun.head)->pid == 0)
{
(void)irqsave();
for (;;)
{
(void)irqsave();
for (;;)
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
up_mdelay(250);
board_led_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
up_mdelay(250);
#endif
}
}
}
else
{
arch/arm/src/armv7-a/arm_virtpgaddr.c
+1 -1
View File
@@ -47,7 +47,7 @@
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
/****************************************************************************
* Private Data
****************************************************************************/
arch/arm/src/kinetis/kinetis_enet.c
+2 -2
View File
@@ -195,7 +195,7 @@ struct kinetis_driver_s
* requirements.
*/
uint8_t desc[NENET_NBUFFERS * sizeof(struct enet_desc_s) + 16];
uint8_t desc[NENET_NBUFFERS * sizeof(struct enet_desc_s) + 16];
/* The DMA buffers. Again, A unaligned uint8_t is used to allocate the
* memory; 16 is added to assure that we can meet the descriptor alignment
@@ -883,7 +883,7 @@ static int kinetis_ifup(struct net_driver_s *dev)
ndbg("Bringing up: %d.%d.%d.%d\n",
dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
/* Initialize ENET buffers */
arch/arm/src/kinetis/kinetis_sdhc.c
+16 -16
View File
@@ -2198,14 +2198,14 @@ static int kinetis_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t r
uint32_t regval;
int ret = OK;
/* R2 CID, CSD register (136-bit)
* 135 0 Start bit
* 134 0 Transmission bit (0=from card)
* 133:128 bit5 - bit0 Reserved
* 127:1 bit127 - bit1 127-bit CID or CSD register
* (including internal CRC)
* 0 1 End bit
*/
/* R2 CID, CSD register (136-bit)
* 135 0 Start bit
* 134 0 Transmission bit (0=from card)
* 133:128 bit5 - bit0 Reserved
* 127:1 bit127 - bit1 127-bit CID or CSD register
* (including internal CRC)
* 0 1 End bit
*/
#ifdef CONFIG_DEBUG
/* Check that R1 is the correct response to this command */
@@ -2250,14 +2250,14 @@ static int kinetis_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
uint32_t regval;
int ret = OK;
/* R3 OCR (48-bit)
* 47 0 Start bit
* 46 0 Transmission bit (0=from card)
* 45:40 bit5 - bit0 Reserved
* 39:8 bit31 - bit0 32-bit OCR register
* 7:1 bit6 - bit0 Reserved
* 0 1 End bit
*/
/* R3 OCR (48-bit)
* 47 0 Start bit
* 46 0 Transmission bit (0=from card)
* 45:40 bit5 - bit0 Reserved
* 39:8 bit31 - bit0 32-bit OCR register
* 7:1 bit6 - bit0 Reserved
* 0 1 End bit
*/
/* Check that this is the correct response to this command */
arch/arm/src/kl/kl_spi.c
+5 -4
View File
@@ -499,9 +499,9 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
* from the SPI data registr
*/
while ((spi_getreg(priv, KL_SPI_S_OFFSET) & SPI_S_SPRF) == 0);
while ((spi_getreg(priv, KL_SPI_S_OFFSET) & SPI_S_SPRF) == 0);
/* Return the data */
/* Return the data */
return (uint16_t)spi_getreg(priv, KL_SPI_D_OFFSET);
}
@@ -538,7 +538,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
/* Loop, sending each word in the user-provied data buffer. */
for ( ; nwords > 0; nwords--)
for (; nwords > 0; nwords--)
{
/* Get the data to send (0xff if there is no data source) */
@@ -597,7 +597,8 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
************************************************************************************/
#ifndef CONFIG_SPI_EXCHANGE
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer, size_t nwords)
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
size_t nwords)
{
spivdbg("txbuffer=%p nwords=%d\n", txbuffer, nwords);
return spi_exchange(dev, txbuffer, NULL, nwords);
arch/arm/src/lpc11xx/lpc11_lowgetc.c
+1 -1
View File
@@ -122,7 +122,7 @@ int lpc11_lowgetc(void)
while ((getreg32(CONSOLE_BASE+LPC11_UART_LSR_OFFSET) & UART_LSR_RDR) == 0);
/* Then read a character from the UART data register */
/* Then read a character from the UART data register */
ch = getreg8(CONSOLE_BASE+LPC11_UART_RBR_OFFSET);
#endif
arch/arm/src/lpc11xx/lpc11_spi.c
+3 -3
View File
@@ -436,11 +436,11 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
* data transfer.
*/
while ((getreg32(LPC11_SPI_SR) & SPI_SR_SPIF) == 0);
while ((getreg32(LPC11_SPI_SR) & SPI_SR_SPIF) == 0);
/* Read the SPI Status Register again to clear the status bit */
/* Read the SPI Status Register again to clear the status bit */
(void)getreg32(LPC11_SPI_SR);
(void)getreg32(LPC11_SPI_SR);
return (uint16_t)getreg32(LPC11_SPI_DR);
}
arch/arm/src/lpc17xx/lpc176x_rtc.c
+1 -1
View File
@@ -199,7 +199,7 @@ static int rtc_setup(void)
putreg32((uint32_t)0xff, LPC17_RTC_AMR);
putreg32((uint32_t)0x00, LPC17_RTC_CALIB);
/* Enable power to the RTC module */
/* Enable power to the RTC module */
regval = getreg32(LPC17_SYSCON_PCONP);
regval |= SYSCON_PCONP_PCRTC;
arch/arm/src/lpc17xx/lpc17_can.c
+8 -9
View File
@@ -1192,7 +1192,7 @@ static int can_bittiming(struct up_dev_s *priv)
canllvdbg("TS1: %d TS2: %d BRP: %d SJW= %d\n", ts1, ts2, brp, sjw);
/* Configure bit timing */
/* Configure bit timing */
btr = (((brp - 1) << CAN_BTR_BRP_SHIFT) |
((ts1 - 1) << CAN_BTR_TSEG1_SHIFT) |
@@ -1290,14 +1290,14 @@ FAR struct can_dev_s *lpc17_caninitialize(int port)
lpc17_configgpio(GPIO_CAN2_TD);
candev = &g_can2dev;
}
else
}
else
#endif
{
candbg("Unsupported port: %d\n", port);
irqrestore(flags);
return NULL;
}
{
candbg("Unsupported port: %d\n", port);
irqrestore(flags);
return NULL;
}
/* Then just perform a CAN reset operation */
@@ -1306,4 +1306,3 @@ FAR struct can_dev_s *lpc17_caninitialize(int port)
return candev;
}
#endif
arch/arm/src/lpc17xx/lpc17_gpioint.c
+16 -17
View File
@@ -163,10 +163,10 @@ static void lpc17_setintedge(uint32_t intbase, unsigned int pin,
static int lpc17_irq2port(int irq)
{
/* Set 1:
* LPC176x: 12 interrupts p0.0-p0.11
* LPC178x: 16 interrupts p0.0-p0.15
*/
/* Set 1:
* LPC176x: 12 interrupts p0.0-p0.11
* LPC178x: 16 interrupts p0.0-p0.15
*/
if (irq >= LPC17_VALID_FIRST0L &&
irq < (LPC17_VALID_FIRST0L + LPC17_VALID_NIRQS0L))
@@ -364,24 +364,24 @@ static void lpc17_gpiodemux(uint32_t intbase, uint32_t intmask,
if ((intmask & bit) != 0)
{
/* This pin can support an interrupt. Is there an interrupt pending
* and enabled?
*/
/* This pin can support an interrupt. Is there an interrupt pending
* and enabled?
*/
if ((intstatus & bit) != 0)
{
/* Clear the interrupt status */
if ((intstatus & bit) != 0)
{
/* Clear the interrupt status */
putreg32(bit, intbase + LPC17_GPIOINT_INTCLR_OFFSET);
putreg32(bit, intbase + LPC17_GPIOINT_INTCLR_OFFSET);
/* And dispatch the interrupt */
/* And dispatch the interrupt */
irq_dispatch(irq, context);
}
irq_dispatch(irq, context);
}
/* Increment the IRQ number on each interrupt pin */
/* Increment the IRQ number on each interrupt pin */
irq++;
irq++;
}
/* Next bit */
@@ -544,4 +544,3 @@ void lpc17_gpioirqdisable(int irq)
}
#endif /* CONFIG_GPIO_IRQ */
arch/arm/src/lpc17xx/lpc17_sdcard.c
+16 -16
View File
@@ -2036,14 +2036,14 @@ static int lpc17_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo
uint32_t regval;
int ret = OK;
/* R2 CID, CSD register (136-bit)
* 135 0 Start bit
* 134 0 Transmission bit (0=from card)
* 133:128 bit5 - bit0 Reserved
* 127:1 bit127 - bit1 127-bit CID or CSD register
* (including internal CRC)
* 0 1 End bit
*/
/* R2 CID, CSD register (136-bit)
* 135 0 Start bit
* 134 0 Transmission bit (0=from card)
* 133:128 bit5 - bit0 Reserved
* 127:1 bit127 - bit1 127-bit CID or CSD register
* (including internal CRC)
* 0 1 End bit
*/
#ifdef CONFIG_DEBUG
/* Check that R1 is the correct response to this command */
@@ -2089,14 +2089,14 @@ static int lpc17_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r
uint32_t regval;
int ret = OK;
/* R3 OCR (48-bit)
* 47 0 Start bit
* 46 0 Transmission bit (0=from card)
* 45:40 bit5 - bit0 Reserved
* 39:8 bit31 - bit0 32-bit OCR register
* 7:1 bit6 - bit0 Reserved
* 0 1 End bit
*/
/* R3 OCR (48-bit)
* 47 0 Start bit
* 46 0 Transmission bit (0=from card)
* 45:40 bit5 - bit0 Reserved
* 39:8 bit31 - bit0 32-bit OCR register
* 7:1 bit6 - bit0 Reserved
* 0 1 End bit
*/
/* Check that this is the correct response to this command */
arch/arm/src/lpc17xx/lpc17_spi.c
+3 -4
View File
@@ -429,11 +429,11 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
* data transfer.
*/
while ((getreg32(LPC17_SPI_SR) & SPI_SR_SPIF) == 0);
while ((getreg32(LPC17_SPI_SR) & SPI_SR_SPIF) == 0);
/* Read the SPI Status Register again to clear the status bit */
/* Read the SPI Status Register again to clear the status bit */
(void)getreg32(LPC17_SPI_SR);
(void)getreg32(LPC17_SPI_SR);
return (uint16_t)getreg32(LPC17_SPI_DR);
}
@@ -610,4 +610,3 @@ FAR struct spi_dev_s *lpc17_spiinitialize(int port)
}
#endif /* CONFIG_LPC17_SPI */
arch/arm/src/lpc17xx/lpc17_usbhost.c
+2 -2
View File
@@ -181,7 +181,7 @@ struct lpc17_usbhost_s
volatile struct usbhost_hubport_s *hport;
#endif
};
};
/* This structure describes one asynchronous transfer */
@@ -691,7 +691,7 @@ static void lpc17_tdfree(struct lpc17_gtd_s *td)
* allocated tail TD.
*/
if (tdfree != NULL && td != TDTAIL)
if (tdfree != NULL && td != TDTAIL)
{
tdfree->flink = g_tdfree;
g_tdfree = tdfree;
arch/arm/src/lpc214x/lpc214x_decodeirq.c
+1 -1
View File
@@ -107,7 +107,7 @@ static uint8_t g_nibblemap[16] = { 0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1,
#ifndef CONFIG_VECTORED_INTERRUPTS
void up_decodeirq(uint32_t *regs)
#else
static void lpc214x_decodeirq( uint32_t *regs)
static void lpc214x_decodeirq(uint32_t *regs)
#endif
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
arch/arm/src/lpc214x/lpc214x_irq.c
+1 -1
View File
@@ -193,7 +193,7 @@ void up_attach_vector(int irq, int vector, vic_vector_t handler)
/* Enable the vectored interrupt */
vic_putreg(((irq << LPC214X_VECTCNTL_IRQSHIFT) | LPC214X_VECTCNTL_ENABLE),
LPC214X_VIC_VECTCNTL0_OFFSET + offset);
LPC214X_VIC_VECTCNTL0_OFFSET + offset);
irqrestore(flags);
}
}
arch/arm/src/lpc2378/lpc23xx_io.c
+8 -7
View File
@@ -58,7 +58,8 @@
* Descriptions: Initialize the target board before running the main()
*
************************************************************************/
void IO_Init( void )
void IO_Init(void)
{
uint32_t regval;
@@ -76,20 +77,20 @@ void IO_Init( void )
pinsel_putreg(0, PINSEL9_OFFSET);
pinsel_putreg(0, PINSEL10_OFFSET);
/*
regval = scb_getreg(SCB_PCONP_OFFSET) & ~(PCSDC | PCUART1 | PCI2C0 | PCSSP1 | PCEMC | );
scb_getreg(regval, SCB_PCONP_OFFSET );
*/
#if 0
regval = scb_getreg(SCB_PCONP_OFFSET) & ~(PCSDC | PCUART1 | PCI2C0 | PCSSP1 | PCEMC);
scb_getreg(regval, SCB_PCONP_OFFSET);
#endif
/* Turn off all peripheral power */
scb_putreg(0, SCB_PCONP_OFFSET );
scb_putreg(0, SCB_PCONP_OFFSET);
/* Turn on UART0/2 / Timer0 */
/* regval = PCUART0 | PCUART2 | PCTIM0 | PCRTC ; */
regval = PCUART0 | PCUART2 | PCTIM0 ;
scb_putreg(regval , SCB_PCONP_OFFSET );
scb_putreg(regval , SCB_PCONP_OFFSET);
/* Status LED P1.19 */
arch/arm/src/lpc2378/lpc23xx_pllsetup.c
+5 -5
View File
@@ -106,16 +106,16 @@ void IO_Init(void);
*/
#ifdef CONFIG_LPC2378_PLL_CLKSRC
# if ( (CONFIG_LPC2378_PLL_CLKSRC < 0) || (CONFIG_LPC2378_PLL_CLKSRC > 2) )
# error "PLL clock source not valid, check configuration "
# endif
# if ((CONFIG_LPC2378_PLL_CLKSRC < 0) || (CONFIG_LPC2378_PLL_CLKSRC > 2))
# error "PLL clock source not valid, check configuration "
# endif
#else
# error "PLL clock source not defined, check configuration file"
# error "PLL clock source not defined, check configuration file"
#endif
/* PLL provides CCLK and must always be configured */
#define PLL ( PLL_M | (PLL_N << 16) )
#define PLL (PLL_M | (PLL_N << 16))
/* Memory Accelerator Module (MAM) initialization values
*
arch/arm/src/lpc2378/lpc23xx_timerisr.c
+6 -6
View File
@@ -62,23 +62,23 @@
/* T0_PCLKDIV valid values are 1,2,4 */
#define T0_PCLK_DIV 1
#define T0_PCLK_DIV 1
/* PCKLSEL0 bits 3:2, 00=CCLK/4, 01=CCLK/1 , 10=CCLK/2 */
#ifdef T0_PCLK_DIV
# if T0_PCLK_DIV == 1
# define TIMER0_PCLKSEL (0x00000004)
# define TIMER0_PCLKSEL (0x00000004)
# elif T0_PCLK_DIV == 2
# define TIMER0_PCLKSEL (0x00000008)
# define TIMER0_PCLKSEL (0x00000008)
# elif T0_PCLK_DIV == 4
# define TIMER0_PCLKSEL (0x00000000)
# define TIMER0_PCLKSEL (0x00000000)
# endif
#endif
#define T0_PCLKSEL_MASK (0x0000000C)
#define T0_PCLKSEL_MASK (0x0000000C)
#define T0_TICKS_COUNT ( (CCLK / T0_PCLK_DIV ) / TICK_PER_SEC )
#define T0_TICKS_COUNT ((CCLK / T0_PCLK_DIV ) / TICK_PER_SEC)
/****************************************************************************
* Private Types
arch/arm/src/lpc31xx/lpc31_ehci.c
+1 -1
View File
@@ -3849,7 +3849,7 @@ static int lpc31_enumerate(FAR struct usbhost_connection_s *conn,
static int lpc31_ep0configure(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
uint8_t funcaddr, uint8_t speed, uint16_t maxpacketsize)
{
{
struct lpc31_epinfo_s *epinfo = (struct lpc31_epinfo_s *)ep0;
DEBUGASSERT(drvr != NULL && epinfo != NULL && maxpacketsize < 2048);
arch/arm/src/lpc43xx/lpc43_allocateheap.c
+9 -9
View File
@@ -266,31 +266,31 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
void up_addregion(void)
{
#if CONFIG_MM_REGIONS > 1
/* Add the next SRAM region (which should exist) */
/* Add the next SRAM region (which should exist) */
kmm_addregion((FAR void*)MM_REGION2_BASE, MM_REGION2_SIZE);
kmm_addregion((FAR void*)MM_REGION2_BASE, MM_REGION2_SIZE);
#ifdef MM_REGION3_BASE
/* Add the third SRAM region (which will not exist in configuration B) */
/* Add the third SRAM region (which will not exist in configuration B) */
#if CONFIG_MM_REGIONS > 2
/* Add the third SRAM region (which may not exist) */
/* Add the third SRAM region (which may not exist) */
kmm_addregion((FAR void*)MM_REGION3_BASE, MM_REGION3_SIZE);
kmm_addregion((FAR void*)MM_REGION3_BASE, MM_REGION3_SIZE);
#if CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE)
/* Add the DMA region (which may not be available) */
/* Add the DMA region (which may not be available) */
kmm_addregion((FAR void*)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE);
kmm_addregion((FAR void*)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE);
#endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */
#endif /* CONFIG_MM_REGIONS > 2 */
#else /* MM_REGION3_BASE */
#if CONFIG_MM_REGIONS > 2 && defined(MM_DMAHEAP_BASE)
/* Add the DMA region (which may not be available) */
/* Add the DMA region (which may not be available) */
kmm_addregion((FAR void*)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE);
kmm_addregion((FAR void*)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE);
#endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */
#endif /* MM_REGION3_BASE */
arch/arm/src/lpc43xx/lpc43_ehci.c
+1 -1
View File
@@ -3679,7 +3679,7 @@ static int lpc43_enumerate(FAR struct usbhost_connection_s *conn,
static int lpc43_ep0configure(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
uint8_t funcaddr, uint8_t speed, uint16_t maxpacketsize)
{
{
struct lpc43_epinfo_s *epinfo = (struct lpc43_epinfo_s *)ep0;
DEBUGASSERT(drvr != NULL && epinfo != NULL && maxpacketsize < 2048);
arch/arm/src/lpc43xx/lpc43_ethernet.c
+4 -4
View File
@@ -438,7 +438,7 @@
#define DMABMR_CLEAR_MASK \
(ETH_DMABMODE_SWR | ETH_DMABMODE_DA | ETH_DMABMODE_DSL_MASK | ETH_DMABMODE_ATDS | \
ETH_DMABMODE_PBL_MASK | ETH_DMABMODE_PR_MASK | ETH_DMABMODE_FB | ETH_DMABMODE_RPBL_MASK | \
ETH_DMABMODE_USP | ETH_DMABMODE_PBL8X | ETH_DMABMODE_AAL | ETH_DMABMODE_MB | ETH_DMABMODE_TXPR )
ETH_DMABMODE_USP | ETH_DMABMODE_PBL8X | ETH_DMABMODE_AAL | ETH_DMABMODE_MB | ETH_DMABMODE_TXPR)
/* The following bits are set or left zero unconditionally in all modes.
@@ -2634,7 +2634,7 @@ static int lpc43_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
/* Add the MAC address to the hardware multicast hash table */
crc = lpc43_calcethcrc( mac, 6 );
crc = lpc43_calcethcrc(mac, 6);
hashindex = (crc >> 26) & 0x3F;
@@ -2691,7 +2691,7 @@ static int lpc43_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
/* Remove the MAC address to the hardware multicast hash table */
crc = lpc43_calcethcrc( mac, 6 );
crc = lpc43_calcethcrc(mac, 6);
hashindex = (crc >> 26) & 0x3F;
@@ -2711,7 +2711,7 @@ static int lpc43_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
/* If there is no address registered any more, delete multicast filtering */
if (lpc43_getreg(LPC43_ETH_MACHTHI ) == 0 &&
if (lpc43_getreg(LPC43_ETH_MACHTHI) == 0 &&
lpc43_getreg(LPC43_ETH_MACHTLO) == 0)
{
temp = lpc43_getreg(LPC43_ETH_MACFFLT);
arch/arm/src/lpc43xx/lpc43_spi.c
+3 -3
View File
@@ -418,11 +418,11 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
* data transfer.
*/
while ((getreg32(LPC43_SPI_SR) & SPI_SR_SPIF) == 0);
while ((getreg32(LPC43_SPI_SR) & SPI_SR_SPIF) == 0);
/* Read the SPI Status Register again to clear the status bit */
/* Read the SPI Status Register again to clear the status bit */
(void)getreg32(LPC43_SPI_SR);
(void)getreg32(LPC43_SPI_SR);
return (uint16_t)getreg32(LPC43_SPI_DR);
}
arch/arm/src/lpc43xx/lpc43_spifi.c
+1 -1
View File
@@ -241,7 +241,7 @@
* Compute this from the SPIFI clock period and the minimum high time of CS
* from the serial flash data sheet:
*
* csHigh = ceiling( min CS high / SPIFI clock period ) - 1
* csHigh = ceiling(min CS high / SPIFI clock period) - 1
*
* where ceiling means round up to the next higher integer if the argument
* isn’t an integer.
arch/arm/src/lpc43xx/lpc43_uart.c
+12 -12
View File
@@ -540,18 +540,18 @@ void lpc43_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
uint32_t cdivadd; /* Candidate FDR DIVADDVAL value */
uint32_t errval; /* Error value associated with the candidate */
/* The U[S]ART buad is given by:
*
* Fbaud = Fbase * mul / (mul + divadd) / (16 * dl)
* dl = Fbase * mul / (mul + divadd) / Fbaud / 16
* = Fbase * mul / ((mul + divadd) * Fbaud * 16)
* = ((Fbase * mul) >> 4) / ((mul + divadd) * Fbaud)
*
* Where the value of MULVAL and DIVADDVAL comply with:
*
* 0 < mul < 16
* 0 <= divadd < mul
*/
/* The U[S]ART buad is given by:
*
* Fbaud = Fbase * mul / (mul + divadd) / (16 * dl)
* dl = Fbase * mul / (mul + divadd) / Fbaud / 16
* = Fbase * mul / ((mul + divadd) * Fbaud * 16)
* = ((Fbase * mul) >> 4) / ((mul + divadd) * Fbaud)
*
* Where the value of MULVAL and DIVADDVAL comply with:
*
* 0 < mul < 16
* 0 <= divadd < mul
*/
best = UINT32_MAX;
divadd = 0;
arch/arm/src/nuc1xx/nuc_gpio.c
+1 -1
View File
@@ -304,6 +304,6 @@ bool nuc_gpioread(gpio_cfgset_t pinset)
/* Return the state of the selected pin */
return (getreg32(base + NUC_GPIO_PIN_OFFSET) & (1 << pin)) != 0;
return (getreg32(base + NUC_GPIO_PIN_OFFSET) & (1 << pin)) != 0;
#endif
}
arch/arm/src/sam34/sam4l_gpio.c
+3 -3
View File
@@ -181,7 +181,7 @@ static int sam_configinput(uintptr_t base, uint32_t pin, gpio_pinset_t cfgset)
putreg32(pin, base + SAM_GPIO_STERC_OFFSET);
}
return OK;
return OK;
}
/****************************************************************************
@@ -412,7 +412,7 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
putreg32(pin, base + SAM_GPIO_IMR1S_OFFSET);
}
/* REVISIT: Should event generation be enabled now? I am assuming so */
/* REVISIT: Should event generation be enabled now? I am assuming so */
if ((cfgset & GPIO_PERIPH_EVENTS) != 0)
{
@@ -421,7 +421,7 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
putreg32(pin, base + SAM_GPIO_EVERS_OFFSET);
}
/* Finally, drive the pen from the peripheral */
/* Finally, drive the pen from the peripheral */
putreg32(pin, base + SAM_GPIO_GPERC_OFFSET);
return OK;
arch/arm/src/sam34/sam_allocateheap.c
+3 -3
View File
@@ -303,9 +303,9 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
#if CONFIG_MM_REGIONS > 1
void up_addregion(void)
{
/* The SAM3U also have SRAM1 and NFCSRAM, We will add these as regions
* the first two additional memory regions if we have them.
*/
/* The SAM3U also have SRAM1 and NFCSRAM, We will add these as regions
* the first two additional memory regions if we have them.
*/
#ifdef HAVE_SRAM1_REGION
/* Allow user access to the heap memory */
arch/arm/src/sam34/sam_gpio.c
+1 -1
View File
@@ -190,7 +190,7 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
* another, new API... perhaps sam_configfilter()
*/
return OK;
return OK;
}
/****************************************************************************
arch/arm/src/sam34/sam_hsmci.c
+13 -13
View File
@@ -1539,10 +1539,10 @@ static void sam_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
regval &= ~(HSMCI_MR_CLKDIV_MASK | HSMCI_MR_PWSDIV_MASK);
#endif
/* These clock devisor values that must be defined in the board-specific
* board.h header file: HSMCI_INIT_CLKDIV, HSMCI_MMCXFR_CLKDIV,
* HSMCI_SDXFR_CLKDIV, and HSMCI_SDWIDEXFR_CLKDIV.
*/
/* These clock devisor values that must be defined in the board-specific
* board.h header file: HSMCI_INIT_CLKDIV, HSMCI_MMCXFR_CLKDIV,
* HSMCI_SDXFR_CLKDIV, and HSMCI_SDWIDEXFR_CLKDIV.
*/
switch (rate)
{
@@ -1780,7 +1780,7 @@ static void sam_blocksetup(FAR struct sdio_dev_s *dev, unsigned int blocklen,
DEBUGASSERT(dev != NULL && nblocks > 0 && nblocks < 65535 && blocklen < 65535);
/* When TRTYP - Single or Multi, blocklen must be 1-511, 0-512 */
/* When TRTYP - Single or Multi, blocklen must be 1-511, 0-512 */
DEBUGASSERT(blocklen <= 512);
@@ -2082,14 +2082,14 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong
struct sam_dev_s *priv = (struct sam_dev_s*)dev;
int ret = OK;
/* R2 CID, CSD register (136-bit)
* 135 0 Start bit
* 134 0 Transmission bit (0=from card)
* 133:128 bit5 - bit0 Reserved
* 127:1 bit127 - bit1 127-bit CID or CSD register
* (including internal CRC)
* 0 1 End bit
*/
/* R2 CID, CSD register (136-bit)
* 135 0 Start bit
* 134 0 Transmission bit (0=from card)
* 133:128 bit5 - bit0 Reserved
* 127:1 bit127 - bit1 127-bit CID or CSD register
* (including internal CRC)
* 0 1 End bit
*/
#ifdef CONFIG_DEBUG
/* Check that R1 is the correct response to this command */
arch/arm/src/sam34/sam_serial.c
+1 -1
View File
@@ -1346,7 +1346,7 @@ static bool up_txready(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
return ((up_serialin(priv, SAM_UART_SR_OFFSET) & UART_INT_TXRDY) != 0);
}
}
/****************************************************************************
* Name: up_txempty
arch/arm/src/sam34/sam_spi.c
+3 -3
View File
@@ -938,9 +938,9 @@ static int spi_lock(struct spi_dev_s *dev, bool lock)
*
****************************************************************************/
static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid,
bool selected)
{
static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid,
bool selected)
{
struct sam_spics_s *spics = (struct sam_spics_s *)dev;
struct sam_spidev_s *spi = spi_device(spics);
uint32_t regval;
arch/arm/src/sam34/sam_udp.c
+3 -3
View File
@@ -112,7 +112,7 @@
UDPEP_CSR_STALLSENT | UDPEP_CSR_RXSETUP | \
UDPEP_CSR_TXCOMP)
#define nop() __asm__ __volatile__ ( "nop" )
#define nop() __asm__ __volatile__ ("nop")
/* USB-related masks */
@@ -2351,7 +2351,7 @@ static void sam_csr_setbits(uint8_t epno, uint32_t setbits)
* accessing DPR.
*/
for (count = 0; count < 15; count++ )
for (count = 0; count < 15; count++)
{
nop();
}
@@ -2386,7 +2386,7 @@ static void sam_csr_clrbits(uint8_t epno, uint32_t clrbits)
* accessing DPR.
*/
for (count = 0; count < 15; count++ )
for (count = 0; count < 15; count++)
{
nop();
}
arch/arm/src/sam34/sam_wdt.c
+9 -9
View File
@@ -371,7 +371,7 @@ static int sam34_stop(FAR struct watchdog_lowerhalf_s *lower)
* the watchdog timer or "petting the dog".
*
* The application program must write in the WDT_CR register at regular
* intervals during normal operation to prevent an MCU reset.
* intervals during normal operation to prevent an MCU reset.
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
@@ -385,7 +385,7 @@ static int sam34_stop(FAR struct watchdog_lowerhalf_s *lower)
static int sam34_keepalive(FAR struct watchdog_lowerhalf_s *lower)
{
wdvdbg("Entry\n");
sam34_putreg((WDT_CR_KEY | WDT_CR_WDRSTT), SAM_WDT_CR);
return OK;
}
@@ -422,7 +422,7 @@ static int sam34_getstatus(FAR struct watchdog_lowerhalf_s *lower,
{
status->flags |= WDFLAGS_ACTIVE;
}
if (priv->handler)
{
status->flags |= WDFLAGS_CAPTURE;
@@ -480,7 +480,7 @@ static int sam34_settimeout(FAR struct watchdog_lowerhalf_s *lower,
return -ERANGE;
}
reload = ((timeout * WDT_FCLK) / 1000) - 1;
/* Make sure that the final reload value is within range */
@@ -503,7 +503,7 @@ static int sam34_settimeout(FAR struct watchdog_lowerhalf_s *lower,
wdvdbg("fwdt=%d reload=%d timout=%d\n",
WDT_FCLK, reload, priv->timeout);
/* Don't commit to MR register until started! */
return OK;
@@ -560,7 +560,7 @@ static xcpt_t sam34_capture(FAR struct watchdog_lowerhalf_s *lower,
regval |= WWDG_CFR_EWI;
sam34_putreg(regval, SAM_WDT_CFR);
up_enable_irq(STM32_IRQ_WWDG);
}
else
@@ -619,7 +619,7 @@ static int sam34_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
uint32_t mintime = (uint32_t)arg;
ret = -EINVAL;
if (priv->started)
if (priv->started)
{
ret = -ENOSYS; /* can't write the MR more than once! */
}
@@ -632,7 +632,7 @@ static int sam34_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
{
uint32_t window = (((priv->timeout - mintime) * WDT_FCLK) / 1000) - 1;
DEBUGASSERT(window <= priv->reload);
priv->window = window;
priv->window = window;
ret = OK;
}
}
@@ -649,7 +649,7 @@ static int sam34_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
*
* Description:
* Initialize the WDT watchdog timer. The watchdog timer is initialized and
* registers as 'devpath'.
* registers as 'devpath'.
*
* Input Parameters:
* devpath - The full path to the watchdog. This should be of the form
arch/arm/src/sama5/sam_dbgu.c
+1 -1
View File
@@ -547,7 +547,7 @@ static void dbgu_txint(struct uart_dev_s *dev, bool enable)
static bool dbgu_txready(struct uart_dev_s *dev)
{
return ((getreg32(SAM_DBGU_SR) & DBGU_INT_TXRDY) != 0);
}
}
/****************************************************************************
* Name: dbgu_txempty
arch/arm/src/sama5/sam_emacb.c
+1 -1
View File
@@ -3961,7 +3961,7 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv)
sam_configpio(PIO_EMAC0_COL); /* Collision Detect */
}
}
else
else
#endif
#if defined(CONFIG_SAMA5_EMAC1)
arch/arm/src/sama5/sam_flexcom_serial.c
+2 -2
View File
@@ -549,7 +549,7 @@ static void flexus_disableallints(struct flexus_dev_s *priv, uint32_t *imr)
*
****************************************************************************/
static int flexus_interrupt( struct uart_dev_s *dev)
static int flexus_interrupt(struct uart_dev_s *dev)
{
struct flexus_dev_s *priv;
uint32_t pending;
@@ -1166,7 +1166,7 @@ static bool flexus_txready(struct uart_dev_s *dev)
{
struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv;
return ((flexus_serialin(priv, SAM_FLEXUS_CSR_OFFSET) & FLEXUS_INT_TXRDY) != 0);
}
}
/****************************************************************************
* Name: flexus_txempty
arch/arm/src/sama5/sam_irq.c
+29 -29
View File
@@ -590,35 +590,35 @@ static uint32_t *sam_decodeirq(uintptr_t base, uint32_t *regs)
uint32_t irqid;
uint32_t ivr;
/* Paragraph 17.8.5 Protect Mode: "The Protect Mode permits reading the
* Interrupt Vector Register without performing the associated automatic
* operations. ... Writing PROT in AIC_DCR (Debug Control Register) at 0x1
* enables the Protect Mode.
*
* "When the Protect Mode is enabled, the AIC performs interrupt stacking
* only when a write access is performed on the AIC_IVR. Therefore, the
* Interrupt Service Routines must write (arbitrary data) to the AIC_IVR
* just after reading it. The new context of the AIC, including the value
* of the Interrupt Status Register (AIC_ISR), is updated with the current
* interrupt only when AIC_IVR is written. ..."
*
* "To summarize, in normal operating mode, the read of AIC_IVR performs the
* following operations within the AIC:
*
* 1. Calculates active interrupt (higher than current or spurious).
* 2. Determines and returns the vector of the active interrupt.
* 3. Memorizes the interrupt.
* 4. Pushes the current priority level onto the internal stack.
* 5. Acknowledges the interrupt.
*
* "However, while the Protect Mode is activated, only operations 1 to 3 are
* performed when AIC_IVR is read. Operations 4 and 5 are only performed by
* the AIC when AIC_IVR is written.
*
* "Software that has been written and debugged using the Protect Mode runs
* correctly in Normal Mode without modification. However, in Normal Mode the
* AIC_IVR write has no effect and can be removed to optimize the code.
*/
/* Paragraph 17.8.5 Protect Mode: "The Protect Mode permits reading the
* Interrupt Vector Register without performing the associated automatic
* operations. ... Writing PROT in AIC_DCR (Debug Control Register) at 0x1
* enables the Protect Mode.
*
* "When the Protect Mode is enabled, the AIC performs interrupt stacking
* only when a write access is performed on the AIC_IVR. Therefore, the
* Interrupt Service Routines must write (arbitrary data) to the AIC_IVR
* just after reading it. The new context of the AIC, including the value
* of the Interrupt Status Register (AIC_ISR), is updated with the current
* interrupt only when AIC_IVR is written. ..."
*
* "To summarize, in normal operating mode, the read of AIC_IVR performs the
* following operations within the AIC:
*
* 1. Calculates active interrupt (higher than current or spurious).
* 2. Determines and returns the vector of the active interrupt.
* 3. Memorizes the interrupt.
* 4. Pushes the current priority level onto the internal stack.
* 5. Acknowledges the interrupt.
*
* "However, while the Protect Mode is activated, only operations 1 to 3 are
* performed when AIC_IVR is read. Operations 4 and 5 are only performed by
* the AIC when AIC_IVR is written.
*
* "Software that has been written and debugged using the Protect Mode runs
* correctly in Normal Mode without modification. However, in Normal Mode the
* AIC_IVR write has no effect and can be removed to optimize the code.
*/
/* Write in the IVR to support Protect Mode */
arch/arm/src/sama5/sam_nand.c
+6 -6
View File
@@ -1024,11 +1024,11 @@ static uint32_t nand_nfc_poll(void)
g_nand.cmddone = true;
}
/* If set to one, the RBEDGE0 flag indicates that an edge has been detected
* on the Ready/Busy Line x. Depending on the EDGE CTRL field located in the
* SMC_CFG register, only rising or falling edge is detected. This flag is
* reset after the status read.
*/
/* If set to one, the RBEDGE0 flag indicates that an edge has been detected
* on the Ready/Busy Line x. Depending on the EDGE CTRL field located in the
* SMC_CFG register, only rising or falling edge is detected. This flag is
* reset after the status read.
*/
if ((sr & HSMC_NFCINT_RBEDGE0) != 0)
{
@@ -1964,7 +1964,7 @@ static int nand_readpage_noecc(struct sam_nandcs_s *priv, off_t block,
/* Configure the SMC */
regval |= (HSMC_CFG_RBEDGE | HSMC_CFG_DTOCYC(15) | HSMC_CFG_DTOMUL_1048576 |
HSMC_CFG_NFCSPARESIZE((sparesize -1 ) >> 2));
HSMC_CFG_NFCSPARESIZE((sparesize - 1) >> 2));
nand_putreg(SAM_HSMC_CFG, regval);
/* Calculate actual address of the page */
arch/arm/src/sama5/sam_ohci.c
+2 -2
View File
@@ -3453,7 +3453,7 @@ static void sam_asynch_completion(struct sam_eplist_s *eplist)
void *arg;
ssize_t nbytes;
DEBUGASSERT(eplist->ed && eplist->tail && eplist->callback != NULL &&
DEBUGASSERT(eplist->ed && eplist->tail && eplist->callback != NULL &&
eplist->buffer != NULL && eplist->buflen > 0);
ed = eplist->ed;
@@ -3603,7 +3603,7 @@ static int sam_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep,
sam_givesem(&g_ohci.exclsem);
return OK;
errout:
/* Make sure that there is no outstanding request on this endpoint */
arch/arm/src/sama5/sam_pmc.c
+6 -6
View File
@@ -126,12 +126,12 @@ uint32_t sam_pllack_frequency(uint32_t mainclk)
}
#endif
/* Get the PLLA multiplier (MULA)
*
* MULA = 0: PLLA is deactivated
* MULA > 0: The PLLA Clock frequency is the PLLA input frequency
* multiplied by MULA + 1.
*/
/* Get the PLLA multiplier (MULA)
*
* MULA = 0: PLLA is deactivated
* MULA > 0: The PLLA Clock frequency is the PLLA input frequency
* multiplied by MULA + 1.
*/
mula = (regval & PMC_CKGR_PLLAR_MUL_MASK) >> PMC_CKGR_PLLAR_MUL_SHIFT;
if (mula > 0)
arch/arm/src/sama5/sam_serial.c
+1 -1
View File
@@ -1657,7 +1657,7 @@ static bool up_txready(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
return ((up_serialin(priv, SAM_UART_SR_OFFSET) & UART_INT_TXRDY) != 0);
}
}
/****************************************************************************
* Name: up_txempty
arch/arm/src/sama5/sam_spi.c
+5 -5
View File
@@ -928,9 +928,9 @@ static int spi_lock(struct spi_dev_s *dev, bool lock)
*
****************************************************************************/
static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid,
bool selected)
{
static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid,
bool selected)
{
struct sam_spics_s *spics = (struct sam_spics_s *)dev;
struct sam_spidev_s *spi = spi_device(spics);
uint32_t regval;
@@ -1313,7 +1313,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
* Get word 1;
* Send word 1; Now word 1 is "in flight"
* nwords--;
* for ( ; nwords > 0; nwords--)
* for (; nwords > 0; nwords--)
* {
* Get word N.
* Wait for TDRE meaning that word N-1 has moved to the shift
@@ -1330,7 +1330,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
* Save the final word.
*/
for ( ; nwords > 0; nwords--)
for (; nwords > 0; nwords--)
{
/* Get the data to send (0xff if there is no data source) */
arch/arm/src/samdl/sam_serial.c
+3 -3
View File
@@ -562,9 +562,9 @@ static int sam_interrupt(struct uart_dev_s *dev)
uint8_t intflag;
uint8_t inten;
/* Get the set of pending USART interrupts (we are only interested in the
* unmasked interrupts).
*/
/* Get the set of pending USART interrupts (we are only interested in the
* unmasked interrupts).
*/
intflag = sam_serialin8(priv, SAM_USART_INTFLAG_OFFSET);
inten = sam_serialin8(priv, SAM_USART_INTENCLR_OFFSET);
arch/arm/src/samdl/sam_spi.c
+5 -5
View File
@@ -804,9 +804,9 @@ static int spi_interrupt(struct sam_spidev_s *dev)
uint8_t intflag;
uint8_t inten;
/* Get the set of pending SPI interrupts (we are only interested in the
* unmasked interrupts).
*/
/* Get the set of pending SPI interrupts (we are only interested in the
* unmasked interrupts).
*/
intflag = sam_getreg8(priv, SAM_SPI_INTFLAG_OFFSET);
inten = sam_getreg8(priv, SAM_SPI_INTENCLR_OFFSET);
@@ -1263,7 +1263,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
* Get word 1;
* Send word 1; Now word 1 is "in flight"
* nwords--;
* for ( ; nwords > 0; nwords--)
* for (; nwords > 0; nwords--)
* {
* Get word N.
* Wait for DRE:: meaning that word N-1 has moved to the shift
@@ -1280,7 +1280,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
* Save the final word.
*/
for ( ; nwords > 0; nwords--)
for (; nwords > 0; nwords--)
{
/* Get the data to send (0xff if there is no data source) */
arch/arm/src/samv7/sam_gpio.c
+3 -3
View File
@@ -69,7 +69,7 @@
#ifdef CONFIG_DEBUG_GPIO
static const char g_portchar[SAMV7_NPIO] =
{
'A'
'A'
#if SAMV7_NPIO > 1
, 'B'
#endif
@@ -91,7 +91,7 @@ static const char g_portchar[SAMV7_NPIO] =
const uintptr_t g_portbase[SAMV7_NPIO] =
{
SAM_PIOA_BASE
SAM_PIOA_BASE
#if SAMV7_NPIO > 1
, SAM_PIOB_BASE
#endif
@@ -197,7 +197,7 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
* another, new API... perhaps sam_configfilter()
*/
return OK;
return OK;
}
/****************************************************************************

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