mirror of
https://github.com/apache/nuttx.git
synced 2026-06-05 15:58:59 +08:00
Merge remote-tracking branch 'remotes/parent/master'
This commit is contained in:
Lok Tep
@@ -93,7 +93,7 @@ has a similar BSD style license:
|
|||||||
IGMP
|
IGMP
|
||||||
^^^^
|
^^^^
|
||||||
|
|
||||||
IGMP support, if enabled in uIP, adds additional logic by Steve Reynolds:
|
IGMP support, if enabled, adds additional logic by Steve Reynolds:
|
||||||
|
|
||||||
Copyright (c) 2002 CITEL Technologies Ltd.
|
Copyright (c) 2002 CITEL Technologies Ltd.
|
||||||
All rights reserved.
|
All rights reserved.
|
||||||
|
|||||||
@@ -11586,7 +11586,7 @@
|
|||||||
* configs/stm32l476vg-disco: Add support for the STM32L476VG Discovery
|
* configs/stm32l476vg-disco: Add support for the STM32L476VG Discovery
|
||||||
board. From Dave (2016-03-25).
|
board. From Dave (2016-03-25).
|
||||||
|
|
||||||
7.16 2016-xx-xx Gregory Nutt <gnutt@nuttx.org>
|
7.16 2016-06-01 Gregory Nutt <gnutt@nuttx.org>
|
||||||
|
|
||||||
* PM: Add activity domain to all PM interfaces and driver callbacks. If
|
* PM: Add activity domain to all PM interfaces and driver callbacks. If
|
||||||
CONFIG_PM_NDOMAINS == 1, then the legacy behavior is preserved. If
|
CONFIG_PM_NDOMAINS == 1, then the legacy behavior is preserved. If
|
||||||
@@ -11615,7 +11615,7 @@
|
|||||||
* STM3220G-EVAL: Add support for both the IAR and uVision GCC IDEs
|
* STM3220G-EVAL: Add support for both the IAR and uVision GCC IDEs
|
||||||
From Kha Vo (2016-04-08).
|
From Kha Vo (2016-04-08).
|
||||||
* STM32F429I Discovery: Add support for the uVision GCC IDE. From
|
* STM32F429I Discovery: Add support for the uVision GCC IDE. From
|
||||||
* Kha Vo (2016-04-08).
|
Kha Vo (2016-04-08).
|
||||||
* libc/signal and include/signal.h: Rename sigset() to signal().
|
* libc/signal and include/signal.h: Rename sigset() to signal().
|
||||||
sigset() is the System V function; signal() is the obsoleted POSIX
|
sigset() is the System V function; signal() is the obsoleted POSIX
|
||||||
name. These seem to be equivalent. Neither are relevant in modern
|
name. These seem to be equivalent. Neither are relevant in modern
|
||||||
@@ -11640,7 +11640,7 @@
|
|||||||
is interpreted as a packed dual frame exchange. Sebastien Lorquet
|
is interpreted as a packed dual frame exchange. Sebastien Lorquet
|
||||||
(2016-04-13).
|
(2016-04-13).
|
||||||
* net/sockets/listen.c and accept.c and include/nuttx/net: Separate
|
* net/sockets/listen.c and accept.c and include/nuttx/net: Separate
|
||||||
out psock_listen() and psock_accepti() for internal OS usage
|
out psock_listen() and psock_accept() for internal OS usage
|
||||||
(2016-04-14).
|
(2016-04-14).
|
||||||
* fs/inode/, fs/vfs/, and sched/task/: File and socket descriptors are
|
* fs/inode/, fs/vfs/, and sched/task/: File and socket descriptors are
|
||||||
no longer allocated for kernel threads. They must use SYSLOG for
|
no longer allocated for kernel threads. They must use SYSLOG for
|
||||||
@@ -11750,3 +11750,211 @@
|
|||||||
the watchdog driver by calling the appropriate, MCU-specific driver
|
the watchdog driver by calling the appropriate, MCU-specific driver
|
||||||
configuration function from your board initialization logic
|
configuration function from your board initialization logic
|
||||||
(2016-05-18).
|
(2016-05-18).
|
||||||
|
* arch/srm/src/stm32l4: Add CAN support for STM32L4. From Sebastien
|
||||||
|
Lorquet (2016-05-19).
|
||||||
|
* arch/arm/src/samv7: Adds a JTAG config and ERASE config to Kconfig to
|
||||||
|
set the CCFG_SYSIO SYSIO Pins. From David Sidrane (2016-05-19).
|
||||||
|
* arch/sim/src: Enhance networking support for the simulation under Linux.
|
||||||
|
Includes updated support for Linux TUN/TAP, and the addition of support
|
||||||
|
for Linux bridge devices. From Steve (2016-05-20).
|
||||||
|
* configs/stm32f411e-disco: Add basic configuration for stm32f411e-disco
|
||||||
|
board with STM32F411VE chip. From Konstantin Berezenko (2016-05-20).
|
||||||
|
* i.MX6 Sabre-6Quad: Basic SMP NSH configuration is now working. But
|
||||||
|
this is probably only because the SMP NSH case does not stress the
|
||||||
|
logic. There are know outstanding SMP issues as noted in the
|
||||||
|
Sabre-6Quad README.txt file (2016-05-22).
|
||||||
|
* configs/sabre-6quad: Add an SMP configuration; Enable procfs in all
|
||||||
|
configurations (2016-05-22).
|
||||||
|
* include/nuttx/crypto/aes.h: Modifications to the crypto API needed
|
||||||
|
for LPC43xx. From Alexander Vasiljev (2016-05-23).
|
||||||
|
* arch/arm/src/lpc43xx: Add AES support. From Alexander Vasiljev
|
||||||
|
(2016-05-24).
|
||||||
|
* configs/*/src/tiva_timer.c: Tiva boards: Fix a naming collision,
|
||||||
|
rename board-specific function from tiva_timer_initialize() to
|
||||||
|
tiva_timer_configure() to remove conflict (2016-05-23).
|
||||||
|
* arch/arm/src/sam*: Ensure that the TWIHS (i2c) hw get's its clock
|
||||||
|
set when the sequence of sam_i2cbus_initialize(),
|
||||||
|
sam_i2cbus_uninitialize(), then sam_i2cbus_initialize() or twi_reset()
|
||||||
|
is called. I found this a while back in the stm32 family, so there
|
||||||
|
may be more arch-es with this sort of bug. I suppose any driver that
|
||||||
|
has the notion of "do not set the freq if it is already set" could be
|
||||||
|
suspect. From David Sidrane (2016-05-23).
|
||||||
|
* arch/arm/src/samv7: Add the up_systemreset interface to the samv7
|
||||||
|
arch. The approach is slightly different in that: 1) It enables
|
||||||
|
ARCH_HAVE_RESET and allows the user to set if, and for how long, to
|
||||||
|
drive External nRST signal. It also does not contain a default
|
||||||
|
board_reset, as that really should be done in the config's src if
|
||||||
|
CONFIG_BOARDCTL_RESET is defined. From David Sidrane (2016-05-23).
|
||||||
|
* arch/arm/include/lpc43xx and src/lpc43xx: Adds definitions for the
|
||||||
|
LPC4337jet100 chip. From Alexander Vasiljev (2016-05-24).
|
||||||
|
* Many files: board_app_initialize() now accepts an argument that may
|
||||||
|
be used to support initialization in different configurations
|
||||||
|
(2016-05-24).
|
||||||
|
* arch/arm/src/samv7: Remove disabling of whole USB on suspend of USBHS.
|
||||||
|
This fix removes the disabling of the whole USB peripheral on suspend
|
||||||
|
interrupt. Its enough to freeze the clock instead. When disabling the
|
||||||
|
whole peripheral, the next wakeup-interrupt comes up with an disabled
|
||||||
|
clocking. The unfreeze clock has no effect, because the master clock
|
||||||
|
is disabled. This makes all registers, including the IDR unwriteable
|
||||||
|
and the IRQ falls in an endless loop blocking the whole system.
|
||||||
|
Furthermore the disabling of the peripheral clock prevents hotplugging
|
||||||
|
or reconnecting the USB. From Frank Benkert (2015-05-25).
|
||||||
|
* drivers/lcd: Add support for PCF8574 LCD Backpack driver. This driver
|
||||||
|
supports an interface board that is based on the PCF8574 io expander
|
||||||
|
and supports the HD44780-based (or compatible) LCD modules. There
|
||||||
|
are a myriad of different vendors of such, but they are principally
|
||||||
|
the same, save wiring and minor features like jumpers for I2C
|
||||||
|
addresses. This driver supports known and unknown variants. From
|
||||||
|
Dave (ziggurat29, 2013-6-26).
|
||||||
|
* arch/arm/stm32: Add support for a custom 1-wire driver. The serial
|
||||||
|
driver already supports a 1-wire interface, but this driver uses the
|
||||||
|
same serial logic to implement a lower half driver much like the I2C
|
||||||
|
lower half driver. From Aleksandr Vyhovanec (2015-05-25).
|
||||||
|
* fs/: Add logic to detach a file structure from a file descriptor.
|
||||||
|
This is for use only within the OS. It permits an open file or driver
|
||||||
|
to be used across multiple threads (2016-05-26).
|
||||||
|
* arch/arm/src/stm32l4: Get I2C working for STM32L4. From Dave
|
||||||
|
(ziggurat29) (2016-05-25).
|
||||||
|
* fs/ and include/nuttx/fs: Add logic to detach a file structure from a
|
||||||
|
file descriptor. This is for use only within the OS. It permits an
|
||||||
|
open file or driver to be used across multiple threads. (2016-05-26).
|
||||||
|
* drivers/analog/adc.c, include/nuttx/analog/adc.h, and all ADC lower
|
||||||
|
half drivers: No longer uses global adc_receive() call. Added a new
|
||||||
|
bind() method to the ADC interface. Now the ADC upper half driver
|
||||||
|
will register its receipt-of-data callback. This change allows the
|
||||||
|
ADC lower half driver to be used with a differ ADC upper half
|
||||||
|
(2016-05-26).
|
||||||
|
* drivers/analog/ads1255.c: Must not do SPI access from interrupt
|
||||||
|
handler. Use the worker thread instead. Must also lock the SPI bus
|
||||||
|
before using it. (2015-05-26).
|
||||||
|
* drivers/: Several SPI-based drivers modified. All drivers that use
|
||||||
|
SPI must call SPI_LOCK and SPI_UNLOCK. This is not optional
|
||||||
|
(2016-05-26).
|
||||||
|
* drivers/sensors: Fix a bug in crc computation for ms583730.
|
||||||
|
Implement POSIX read (2016-05-27).
|
||||||
|
* arch/arm/src/samv7: This is a fix to a problem in the handling of the
|
||||||
|
oneshot timer. Due to a wrong assumption concerning the behavior
|
||||||
|
directly after the start of the timer/counter the function
|
||||||
|
sam_oneshot_cancel(…) calculates the wrong remaining time. The code
|
||||||
|
assumes that the counter register is zero directly after the start of
|
||||||
|
the timer, but this is not true. To start the time/counter a software
|
||||||
|
trigger is invoked, this trigger starts the timer/count and sets the
|
||||||
|
counter register to zero, but the reset of the counter register is not
|
||||||
|
performed instantly. According to the datasheet: "The counter can be
|
||||||
|
reset by a trigger. In this case, the counter value passes to zero on
|
||||||
|
the next valid edge of the selected clock." Thus the counter is set to
|
||||||
|
zero between 0 and USEC_PER_TICK microseconds after the clock was
|
||||||
|
started.
|
||||||
|
In my fix I use the freerun count value to determine if at least one
|
||||||
|
tick passed since the start of the timer and thus if the value of the
|
||||||
|
oneshot counter is correct. I also tried to use the function
|
||||||
|
up_timer_gettime(…) to achieve this but, at least if compiled with no
|
||||||
|
optimization the problem vanishes without using the value of the
|
||||||
|
function, the function call takes too long.
|
||||||
|
Another problem treated in the fix is that if the oneshot timer/counter
|
||||||
|
is canceled, we only know the remaining time with a precision of
|
||||||
|
USEC_PER_TICK microseconds. This means the calculated remaining time
|
||||||
|
is between 0 and USEC_PER_TICK microseconds too long. To fix this I
|
||||||
|
subtract one tick if the calculated remaining time is greater than one
|
||||||
|
tick and otherwise set the remaining time to zero. By doing so the
|
||||||
|
measured times are much more precise as without it. From Stefan Kolb
|
||||||
|
(2016-05-27).
|
||||||
|
* arch/arm/src/sama5: Stefan Kolb's change to the SAMV7 Oneshot Timer
|
||||||
|
should also be applied to the SAMA5 oneshot time since the drivers are
|
||||||
|
identical (2016-05-27).
|
||||||
|
* arch/arm/src/stm32l4: Add support for SPI 4 and 5 on stm32f411 chips.
|
||||||
|
From Konstantin Berezenko (2016-05-27).
|
||||||
|
* arch/arm/src/sam34: Stefan Kolb's change to the SAMV7 Oneshot Timer
|
||||||
|
should also be applied to the SAM3/4 oneshot time since the drivers
|
||||||
|
are identical (2016-05-29).
|
||||||
|
* arch/arm/src/stm32: Allow to not use all channel in a lower part of
|
||||||
|
PWM. From Pierre-noel Bouteville (2016-05-30).
|
||||||
|
* libc/math: Add a NAN test on 'x' in asin function of lib_asin.c.
|
||||||
|
Suggested by Pierre-noel Bouteville (2016-05-31).
|
||||||
|
* arch/arm/src/stm32: Fix logic in F4 RTCC driver that prevent ALARM
|
||||||
|
interrupt. From Neil Hancock (2016-05-31).
|
||||||
|
* arch/arm/src/stm32: Fix STM32 ValueLine ADC IRQ number selection.
|
||||||
|
From David Sidrane (2016-05-31).
|
||||||
|
* arch/arm/src/samv7: Fix missing unlock of device in MCAN
|
||||||
|
mcan_txempty(). From Frank Benkert (2016-06-01).
|
||||||
|
|
||||||
|
7.17 2016-xx-xx Gregory Nutt <gnutt@nuttx.org>
|
||||||
|
|
||||||
|
* drivers/mtd/flash_eraseall.c: Removed. This is no longer used
|
||||||
|
in the OS and is simply a wrapper around the MDIOC_BULKERASE
|
||||||
|
IOCTL command. It used to be called (only) from
|
||||||
|
apps/system/flash_eraseall, but that has been removed because it
|
||||||
|
violated the OS/application interface -- by calling flash_eraseall().
|
||||||
|
The old code can be found in the Obsoleted' repository (and a revised
|
||||||
|
version can be found at apps/fsutils/flash_eraseall) (2016-06-03).
|
||||||
|
* arch/arm/src/stm32: STM32 Timer Driver: Change calculation of per-
|
||||||
|
timer pre-scaler value. Add support for all timers (2016-6-03)
|
||||||
|
* drivers/lcd: Correct conditional compilation in ST7565 driver. From
|
||||||
|
Pierre-noel Bouteville (2016-6-03)
|
||||||
|
* arch/arm/src/stm32: Correct conditional compilation in STM32 timer
|
||||||
|
capture logic. From Pierre-noel Bouteville (2016-6-03)
|
||||||
|
* arch/arm/src/efm32: Fix EFM32 FLASH conditional compilation. From
|
||||||
|
Pierre-noel Bouteville (2016-6-03)
|
||||||
|
* arch/arm/src/lpc43xx: Fix errors in GPIO interrupt logic. From v01d
|
||||||
|
(phreakuencies) (2016-06-04)
|
||||||
|
* arch/arm/src/kl and lpc11xx: rename xyz_lowputc to up_putc. Remove
|
||||||
|
all references to up_lowputc, everywhere (2016-06-04).
|
||||||
|
* configs/stm32f103-minimum: Add minnsh configuration. From Alan
|
||||||
|
Carvalho de Assis (2016-06-04).
|
||||||
|
* arch/arm/src/stm32: Add the up_getc() function to STM32 in order to
|
||||||
|
support the minnsh configuration. From Alan Carvalho de Assis
|
||||||
|
(2016-06-04).
|
||||||
|
* include/sys/boardctl.h: Needs to be usable with C++ files (2016-06-05).
|
||||||
|
* tools/tesbuild.sh will now build NxWM configurations (2016-06-05).
|
||||||
|
* arch/arm/src/stm32: In PWM driver, just update duty if frequency is
|
||||||
|
not changed and PSM started. This removeis glitch or blinking when
|
||||||
|
only duty is frequently changed. From Pierre-noel Bouteville (2016-06-05).
|
||||||
|
* arch/arm/src/kinetis: Add a USB device controller driver. Derived from
|
||||||
|
the pic32mx usb driver, which uses the same usb controller. From kfazz
|
||||||
|
(2016-06).
|
||||||
|
* configs/teensy-3.x: Add USB support and a usbnsh configuration. From
|
||||||
|
kfazz (2016-06).
|
||||||
|
* arch/arm/src/stm32: Add support for the STM32F105R. From Konstantin
|
||||||
|
Berezenko (2016-06-06).
|
||||||
|
* include/signal.h: Change type of SIG_ERR, SIG_IGN, ... to
|
||||||
|
_sa_handler_t. They type void does not work with the IAR toolchain.
|
||||||
|
From Aleksandr Vyhovanec (2016-06-07).
|
||||||
|
* arch/arm/src/stm32f7 and include/stm32f7: Added STM32FF76xxx and
|
||||||
|
STM32FF7xx families. From David Sidrane (2016-06-08).
|
||||||
|
* Refactoring configs/nucleo-144 sub-directories to support additional
|
||||||
|
nucleo-144 board. Add support for the Nucleo-F767ZI board. From David
|
||||||
|
Sidrane (2016-06-08).
|
||||||
|
* arch/arm/src/kinetis: Add a USB device controller driver for kinetis.
|
||||||
|
Derived from pic32mx usb driver, which uses the same usb controller.
|
||||||
|
From kfazz (2016-06-06).
|
||||||
|
* configs/teensy-3.x: Add USB device support and usbnsh configuration.
|
||||||
|
From kfazz (2016-06-06.
|
||||||
|
* arch/arm/src/stm32: Add STM32F105R support. From Konstantin Berezenko
|
||||||
|
(2016-06-06).
|
||||||
|
* include/signal.h: Change type of SIG_IGN and related defines to
|
||||||
|
_sa_handler_t. From Aleksandr Vyhovanec (2016-06-07).
|
||||||
|
* configs/nucleo-144: Refactored configs/nucleo-144 sub-directories to
|
||||||
|
support additional nucleo-144 board. Add support for the Nucleo-F767ZI
|
||||||
|
board. From David Sidrane (2016-06-07).
|
||||||
|
* arch/arm/src/stm32f7: Add support for STM32FF76xxx and STM32FF7xx
|
||||||
|
families. From David Sidrane (2016-06-08).
|
||||||
|
* include/assert.h: Check if NDEBUG is defined. From Paul Alexander
|
||||||
|
Patience (2016-06-08).
|
||||||
|
* arch/arm/src/stm32: Fix STM32 DMA code and configuration for STM32F37X
|
||||||
|
chips. From Marten Svanfeldt (2016-06-08).
|
||||||
|
* drivers/mtd: Add a driver of IS25xP SPI flash devices. From Marten
|
||||||
|
Svanfeldt (2016-06-09).
|
||||||
|
* arch/arm/src/Kconfig and configs/teensy-3.x: Teensy clock fixes. The
|
||||||
|
High Gain bit in MCG_C1 was preventing teensy from booting except
|
||||||
|
after a programming session. The second change doesn't appear to
|
||||||
|
change any functionality, but complies with restrictions in the k20
|
||||||
|
family reference manual on FEI -> FBE clock transiions. From kfazz
|
||||||
|
(2016-06-09).
|
||||||
|
* configs/*/include/board.h: Fix timer input clock definitions. From
|
||||||
|
David Sidrane (2016-06-09).
|
||||||
|
* Networking: In both IPv6 and IPv4 incoming logic: (1) Should check
|
||||||
|
if the packet size is large enough before trying to access the packet
|
||||||
|
length in the IP header. (2) In the comparison between the IP length
|
||||||
|
and the full packet length, need to subtract the size of the link
|
||||||
|
layer header before making the comparison or we will get false
|
||||||
|
positives (i.e., the packet is really too small) (2016-06-09)
|
||||||
|
|||||||
+81
-27
@@ -8,7 +8,7 @@
|
|||||||
<tr align="center" bgcolor="#e4e4e4">
|
<tr align="center" bgcolor="#e4e4e4">
|
||||||
<td>
|
<td>
|
||||||
<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
|
<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
|
||||||
<p>Last Updated: April 12, 2016</p>
|
<p>Last Updated: June 1, 2016</p>
|
||||||
</td>
|
</td>
|
||||||
</tr>
|
</tr>
|
||||||
</table>
|
</table>
|
||||||
@@ -1340,11 +1340,11 @@
|
|||||||
<h2>Released Versions</h2>
|
<h2>Released Versions</h2>
|
||||||
<p>
|
<p>
|
||||||
In addition to the ever-changing GIT repository, there are frozen released versions of NuttX available.
|
In addition to the ever-changing GIT repository, there are frozen released versions of NuttX available.
|
||||||
The current release is NuttX 7.15.
|
The current release is NuttX 7.16.
|
||||||
NuttX 7.15 is the 115<sup>th</sup> release of NuttX.
|
NuttX 7.16 is the 116<sup>th</sup> release of NuttX.
|
||||||
It was released on March 27, 2016, and is available for download from the
|
It was released on June 1, 2016, and is available for download from the
|
||||||
<a href="https://bitbucket.org/nuttx/nuttx/downloads/">Bitbucket.org</a> website.
|
<a href="https://bitbucket.org/nuttx/nuttx/downloads/">Bitbucket.org</a> website.
|
||||||
Note that the release consists of two tarballs: <code>nuttx-7.15.tar.gz</code> and <code>apps-7.15.tar.gz</code>.
|
Note that the release consists of two tarballs: <code>nuttx-7.16.tar.gz</code> and <code>apps-7.16.tar.gz</code>.
|
||||||
Both may be needed (see the top-level <code>nuttx/README.txt</code> file for build information).
|
Both may be needed (see the top-level <code>nuttx/README.txt</code> file for build information).
|
||||||
</p>
|
</p>
|
||||||
|
|
||||||
@@ -1353,7 +1353,7 @@
|
|||||||
<ul>
|
<ul>
|
||||||
<li><b>nuttx</b>.
|
<li><b>nuttx</b>.
|
||||||
<ul><p>
|
<ul><p>
|
||||||
Release notes for NuttX 7.15 are available <a href="https://bitbucket.org/nuttx/nuttx/downloads/">here</a>.
|
Release notes for NuttX 7.16 are available <a href="https://bitbucket.org/nuttx/nuttx/downloads/">here</a>.
|
||||||
Release notes for all released versions on NuttX are available in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ReleaseNotes" target="_blank">Bitbucket GIT</a>.
|
Release notes for all released versions on NuttX are available in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ReleaseNotes" target="_blank">Bitbucket GIT</a>.
|
||||||
The ChangeLog for all releases of NuttX is available in the ChangeLog file that can viewed in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ChangeLog" target="_blank">Bitbucket GIT</a>.
|
The ChangeLog for all releases of NuttX is available in the ChangeLog file that can viewed in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ChangeLog" target="_blank">Bitbucket GIT</a>.
|
||||||
The ChangeLog for the current release is at the bottom of that file.
|
The ChangeLog for the current release is at the bottom of that file.
|
||||||
@@ -1361,7 +1361,7 @@
|
|||||||
</li></ul>
|
</li></ul>
|
||||||
<li><b>apps</b>.
|
<li><b>apps</b>.
|
||||||
<ul><p>
|
<ul><p>
|
||||||
Release notes for NuttX 7.15 are available <a href="https://bitbucket.org/nuttx/apps/downloads/">here</a>.
|
Release notes for NuttX 7.16 are available <a href="https://bitbucket.org/nuttx/apps/downloads/">here</a>.
|
||||||
Release notes for all released versions on NuttX are available in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ReleaseNotes" target="_blank">Bitbucket GIT</a>
|
Release notes for all released versions on NuttX are available in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ReleaseNotes" target="_blank">Bitbucket GIT</a>
|
||||||
The ChangeLog for the all releases of <code>apps/</code> is available in the ChangeLog file that can viewed in the <a href="https://bitbucket.org/nuttx/apps/src/master/ChangeLog.txt" target="_blank">Bitbucket GIT</a>.
|
The ChangeLog for the all releases of <code>apps/</code> is available in the ChangeLog file that can viewed in the <a href="https://bitbucket.org/nuttx/apps/src/master/ChangeLog.txt" target="_blank">Bitbucket GIT</a>.
|
||||||
The ChangeLog for the current release is at the bottom of that file.
|
The ChangeLog for the current release is at the bottom of that file.
|
||||||
@@ -1418,8 +1418,8 @@
|
|||||||
<li><a href="#armcortexa9">ARM Cortex-A9</a> (1)</li>
|
<li><a href="#armcortexa9">ARM Cortex-A9</a> (1)</li>
|
||||||
<li><a href="#armcortexr4">ARM Cortex-R4</a> (1)</li>
|
<li><a href="#armcortexr4">ARM Cortex-R4</a> (1)</li>
|
||||||
<li><a href="#armcortexm0">ARM Cortex-M0/M0+</a> (7)</li>
|
<li><a href="#armcortexm0">ARM Cortex-M0/M0+</a> (7)</li>
|
||||||
<li><a href="#armcortexm3">ARM Cortex-M3</a> (34)</li>
|
<li><a href="#armcortexm3">ARM Cortex-M3</a> (35)</li>
|
||||||
<li><a href="#armcortexm4">ARM Cortex-M4</a> (28)</li>
|
<li><a href="#armcortexm4">ARM Cortex-M4</a> (29)</li>
|
||||||
<li><a href="#armcortexm7">ARM Cortex-M7</a> (4)</li>
|
<li><a href="#armcortexm7">ARM Cortex-M7</a> (4)</li>
|
||||||
</ul>
|
</ul>
|
||||||
<li>Atmel AVR
|
<li>Atmel AVR
|
||||||
@@ -2257,7 +2257,7 @@
|
|||||||
<td>
|
<td>
|
||||||
<p>
|
<p>
|
||||||
<a name="freescaleimx6"><b>NXP/Freescale i.MX6</b>.</a>
|
<a name="freescaleimx6"><b>NXP/Freescale i.MX6</b>.</a>
|
||||||
A port is underway for the following i.MX6 board
|
The basic port has been completed for the following i.MX6 board
|
||||||
<p>
|
<p>
|
||||||
<ul>
|
<ul>
|
||||||
<li>
|
<li>
|
||||||
@@ -2268,9 +2268,13 @@
|
|||||||
</p>
|
</p>
|
||||||
<p>
|
<p>
|
||||||
<b>STATUS:</b>
|
<b>STATUS:</b>
|
||||||
The basic, minimal port is code complete and introduced in NuttX-7.15, but has not yet been tested.
|
The basic, minimal port is code complete and introduced in NuttX-7.15, but had not yet been tested at that time due to the inavailability of hardware.
|
||||||
I am still waiting for the reciept of the Sabre board.
|
This basic port was verified in the NuttX-7.16 release, however.
|
||||||
Expect to see the verified Sabre-6Quad support (with SMP!) in NuttX-7.16.
|
The port is still mininal and more device drivers are needed to make the port usable.
|
||||||
|
</p>
|
||||||
|
<p>
|
||||||
|
Basic support of NuttX running in SMP mode on the i.MX6Q was also accomplished in NuttX-7.16.
|
||||||
|
However, there are still known issues with SMP support on this platform as described in the <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/sabre-6quad/README.txt" target="_blank">README</a> file for the board.
|
||||||
</p>
|
</p>
|
||||||
</li>
|
</li>
|
||||||
</ul>
|
</ul>
|
||||||
@@ -2907,13 +2911,26 @@ nsh>
|
|||||||
<td>
|
<td>
|
||||||
<p>
|
<p>
|
||||||
<a name="stm32f103cx"><b>STMicro STM32F103C4/8 (STM32 F1 Low- and Medium-Density Family)</b>.</a>
|
<a name="stm32f103cx"><b>STMicro STM32F103C4/8 (STM32 F1 Low- and Medium-Density Family)</b>.</a>
|
||||||
This port is for "STM32 Tiny" development board.
|
There are two ports available for this family:
|
||||||
This board is available from several vendors on the net, and may be sold under different names.
|
|
||||||
It is based on a STM32 F103C8T6 MCU, and is bundled with a nRF24L01 wireless communication module.
|
|
||||||
</p>
|
</p>
|
||||||
<ul>
|
<ul>
|
||||||
<p>
|
<li>
|
||||||
<b>STATUS:</b>
|
<p>
|
||||||
|
One port is for "STM32 Tiny" development board.
|
||||||
|
This board is available from several vendors on the net, and may be sold under different names.
|
||||||
|
It is based on a STM32 F103C8T6 MCU, and is bundled with a nRF24L01 wireless communication module.
|
||||||
|
</p>
|
||||||
|
</li>
|
||||||
|
<li>
|
||||||
|
<p>
|
||||||
|
The other port is for a generic minimual STM32F103CBT6 "blue" board contributed by Alan Carvalho de Assis.
|
||||||
|
</p>
|
||||||
|
</li>
|
||||||
|
</ul>
|
||||||
|
<p>
|
||||||
|
<b>STATUS:</b>
|
||||||
|
</p1>
|
||||||
|
<ul>
|
||||||
The basic STM32F103C8 port was released in NuttX version 6.28.
|
The basic STM32F103C8 port was released in NuttX version 6.28.
|
||||||
This work was contributed by Laurent Latil.
|
This work was contributed by Laurent Latil.
|
||||||
Refer to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32_tiny/README.txt" target="_blank">README</a> file for further information.
|
Refer to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32_tiny/README.txt" target="_blank">README</a> file for further information.
|
||||||
@@ -3160,11 +3177,17 @@ nsh>
|
|||||||
</ul>
|
</ul>
|
||||||
</p>
|
</p>
|
||||||
<ul>
|
<ul>
|
||||||
<b>STATUS:</b>
|
<p>
|
||||||
The peripherals of the STM32 F2 family are compatible with the STM32 F4 family.
|
<b>STATUS:</b>
|
||||||
See discussion of the STM3240G-EVAL board below for further information.
|
The peripherals of the STM32 F2 family are compatible with the STM32 F4 family.
|
||||||
Refer also to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm3220g-eval/README.txt" target="_blank">README</a> file for further information.
|
See discussion of the STM3240G-EVAL board below for further information.
|
||||||
</ul>
|
Refer also to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm3220g-eval/README.txt" target="_blank">README</a> file for further information.
|
||||||
|
</p>
|
||||||
|
<p>
|
||||||
|
Support for both the IAR and uVision GCC IDEs added for the STM3220G-EVAL board in NuttX 7.16.
|
||||||
|
From Kha Vo.
|
||||||
|
</p>
|
||||||
|
</ul>
|
||||||
</td>
|
</td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
@@ -3779,6 +3802,10 @@ nsh>
|
|||||||
In Nutt-7.7, Marco Krahl included support for a framebuffer based driver using the LTDC and DMA2D.
|
In Nutt-7.7, Marco Krahl included support for a framebuffer based driver using the LTDC and DMA2D.
|
||||||
Marcos's implementation included extensions to support more advance LTDC functions through an auxiliary interface.
|
Marcos's implementation included extensions to support more advance LTDC functions through an auxiliary interface.
|
||||||
</li>
|
</li>
|
||||||
|
<li>
|
||||||
|
Support for the uVision GCC IDE added for theSTM32F429I-Discovery board in NuttX 7.16.
|
||||||
|
From Kha Vo.
|
||||||
|
</li>
|
||||||
</ul>
|
</ul>
|
||||||
<p>
|
<p>
|
||||||
Refer to the STM32F429I-Discovery board <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32f429i-disco/README.txt" target="_blank">README</a> file for further information.
|
Refer to the STM32F429I-Discovery board <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32f429i-disco/README.txt" target="_blank">README</a> file for further information.
|
||||||
@@ -3853,6 +3880,15 @@ nsh>
|
|||||||
<li>UART, USART, Serial Console</li>
|
<li>UART, USART, Serial Console</li>
|
||||||
<li>GPIO, DMA, I2C, RNG, SPI</li>
|
<li>GPIO, DMA, I2C, RNG, SPI</li>
|
||||||
</ul>
|
</ul>
|
||||||
|
<p>
|
||||||
|
<b>NuttX-7.16</b>.
|
||||||
|
Additional drivers were contributed:
|
||||||
|
</p>
|
||||||
|
<ul>
|
||||||
|
<li>QSPI with DMA and memory mapped support. From Dave (ziggurat29).</li>
|
||||||
|
<li>CAN contributed by Sebastien Lorquet.</li>
|
||||||
|
<li>I2C made functional by Dave (ziggurat29).</li>
|
||||||
|
</ul>
|
||||||
</td>
|
</td>
|
||||||
</tr>
|
</tr>
|
||||||
|
|
||||||
@@ -3968,6 +4004,13 @@ nsh>
|
|||||||
The NXP WaveShare LPC4337-WS port is was contributed by Lok Tep and first released in NuttX-7.14.
|
The NXP WaveShare LPC4337-WS port is was contributed by Lok Tep and first released in NuttX-7.14.
|
||||||
</p>
|
</p>
|
||||||
</li>
|
</li>
|
||||||
|
<li>
|
||||||
|
<p><b>NuttX-7.16</b>
|
||||||
|
Support for the LPC4337JET100 chip was contribed by Alexander Vasiljev.
|
||||||
|
Alexander also contributed an LPC43xx AES driver available in NuttX-7.16.
|
||||||
|
</p>
|
||||||
|
</li>
|
||||||
|
|
||||||
</ul>
|
</ul>
|
||||||
</td>
|
</td>
|
||||||
</tr>
|
</tr>
|
||||||
@@ -4407,13 +4450,24 @@ Mem: 29232 5920 23312 23312
|
|||||||
<td>
|
<td>
|
||||||
<p>
|
<p>
|
||||||
<a name="stm32f74x"><b>STMicro STM32 F745/F746</b>.</a>
|
<a name="stm32f74x"><b>STMicro STM32 F745/F746</b>.</a>
|
||||||
This port uses the STMicro STM32F746G-DISCO development board featuring the STM32F746NGH6 MCU. The STM32F746NGH6 is a 216MHz Cortex-M7 operation with 1024Kb Flash.
|
Two boards are supported for this MCU:
|
||||||
Refer to the <a href="http://www.st.com/stm32f7-discovery">STMicro web site</a> for further information about this board.
|
|
||||||
</p>
|
</p>
|
||||||
<ul>
|
<ul>
|
||||||
<p>
|
<p>
|
||||||
<b>STATUS:</b>
|
<b>STM32F746G Discovery</b>.
|
||||||
The basic port is complete and there are two, verified configurations available.
|
One port uses the STMicro STM32F746G-DISCO development board featuring the STM32F746NGH6 MCU. The STM32F746NGH6 is a 216MHz Cortex-M7 operation with 1024Kb Flash.
|
||||||
|
Refer to the <a href="http://www.st.com/stm32f7-discovery">STMicro web site</a> for further information about this board.
|
||||||
|
</p>
|
||||||
|
<p>
|
||||||
|
A basic port for the Nucleo-144 board with the STM32F746ZG MCU was contribued in NuttX-7.16 by Kconstantin Berezenko.
|
||||||
|
</p>
|
||||||
|
</ul>
|
||||||
|
<p>
|
||||||
|
<b>STATUS:</b>
|
||||||
|
</p>
|
||||||
|
<ul>
|
||||||
|
<p>
|
||||||
|
The basic STM32F746G-DISCO port is complete and there are two, verified configurations available.
|
||||||
Both configurations use the NuttShell (NSH) and a serial console; one includes Ethernet support.
|
Both configurations use the NuttShell (NSH) and a serial console; one includes Ethernet support.
|
||||||
DMA supports is available.
|
DMA supports is available.
|
||||||
The STM32 F7 peripherals are very similar to some members of the STM32 F4 and additional drivers can easily be ported the F7 as discussed in this Wiki page: <a href="http://www.nuttx.org/doku.php?id=wiki:howtos:port-drivers_stm32f7">Porting Drivers to the STM32 F7</a>
|
The STM32 F7 peripherals are very similar to some members of the STM32 F4 and additional drivers can easily be ported the F7 as discussed in this Wiki page: <a href="http://www.nuttx.org/doku.php?id=wiki:howtos:port-drivers_stm32f7">Porting Drivers to the STM32 F7</a>
|
||||||
|
|||||||
@@ -4901,8 +4901,7 @@ int kbd_decode(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *sta
|
|||||||
<p>
|
<p>
|
||||||
<b><code>include/nuttx/net/netdev.h</code></b>.
|
<b><code>include/nuttx/net/netdev.h</code></b>.
|
||||||
All structures and APIs needed to work with Ethernet drivers are provided in this header file.
|
All structures and APIs needed to work with Ethernet drivers are provided in this header file.
|
||||||
The structure <code>struct net_driver_s</code> defines the interface and is passed to uIP via
|
The structure <code>struct net_driver_s</code> defines the interface and is passed to the network via <code>netdev_register()</code>.
|
||||||
<code>netdev_register()</code>.
|
|
||||||
</p>
|
</p>
|
||||||
</li>
|
</li>
|
||||||
<li>
|
<li>
|
||||||
|
|||||||
@@ -8755,9 +8755,8 @@ FAR void *mmap(FAR void *start, size_t length, int prot, int flags, int fd, off_
|
|||||||
</table>
|
</table>
|
||||||
|
|
||||||
<p>
|
<p>
|
||||||
NuttX includes a simple interface layer based on uIP (see <a href="http://www.sics.se/~adam/uip/index.php/Main_Page">http://www.sics.se</a>).
|
NuttX supports a BSD-compatible socket interface layer.
|
||||||
NuttX supports subset of a standard socket interface to uIP.
|
These socket interface can be enabled by settings in the architecture <a href="NuttXConfigVariables.html">configuration file</a>.
|
||||||
These network feature can be enabled by settings in the architecture <a href="NuttXConfigVariables.html">configuration file</a>.
|
|
||||||
Those socket APIs are discussed in the following paragraphs.
|
Those socket APIs are discussed in the following paragraphs.
|
||||||
</p>
|
</p>
|
||||||
<ul>
|
<ul>
|
||||||
|
|||||||
@@ -8,7 +8,7 @@
|
|||||||
<tr align="center" bgcolor="#e4e4e4">
|
<tr align="center" bgcolor="#e4e4e4">
|
||||||
<td>
|
<td>
|
||||||
<h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
|
<h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
|
||||||
<p>Last Updated: May 20, 2016</p>
|
<p>Last Updated: May 26, 2016</p>
|
||||||
</td>
|
</td>
|
||||||
</tr>
|
</tr>
|
||||||
</table>
|
</table>
|
||||||
@@ -316,7 +316,8 @@ nuttx/
|
|||||||
| |- eeprom/
|
| |- eeprom/
|
||||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/eeprom/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/eeprom/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||||
| |- lcd/
|
| |- lcd/
|
||||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/lcd/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
| | |- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/lcd/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||||
|
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/lcd/pcf8574_lcd_backpack_readme.txt" target="_blank"><b><i>pcf8574_lcd_backpack_readme.txt</i></b></a>
|
||||||
| |- mtd/
|
| |- mtd/
|
||||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/mtd/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/mtd/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||||
| |- sensors/
|
| |- sensors/
|
||||||
|
|||||||
+13
-8
@@ -960,10 +960,13 @@ Native Windows Build
|
|||||||
In this build, you cannot use a Cygwin or MSYS shell. Rather the build must
|
In this build, you cannot use a Cygwin or MSYS shell. Rather the build must
|
||||||
be performed in a Windows console window. Here is a better terminal than the
|
be performed in a Windows console window. Here is a better terminal than the
|
||||||
standard issue, CMD.exe terminal: ConEmu which can be downloaded from:
|
standard issue, CMD.exe terminal: ConEmu which can be downloaded from:
|
||||||
http://code.google.com/p/conemu-maximus5/
|
https://sourceforge.net/projects/conemu/ or https://conemu.github.io/ .
|
||||||
|
|
||||||
Build Tools. The build still relies on some Unix-like commands. I use
|
Build Tools. The build still relies on some Unix-like commands. I use
|
||||||
the GNUWin32 tools that can be downloaded from http://gnuwin32.sourceforge.net/.
|
the GNUWin32 tools that can be downloaded from http://gnuwin32.sourceforge.net/
|
||||||
|
using the 'Download all' selection. Individual packages can be download
|
||||||
|
instead if you know what you are doing and want a faster download (No, I
|
||||||
|
can't tell you which packages you should or should not download).
|
||||||
|
|
||||||
Host Compiler: I use the MingGW GCC compiler which can be downloaded from
|
Host Compiler: I use the MingGW GCC compiler which can be downloaded from
|
||||||
http://www.mingw.org/. If you are using GNUWin32, then it is recommended
|
http://www.mingw.org/. If you are using GNUWin32, then it is recommended
|
||||||
@@ -971,12 +974,13 @@ Native Windows Build
|
|||||||
|
|
||||||
This capability should still be considered a work in progress because:
|
This capability should still be considered a work in progress because:
|
||||||
|
|
||||||
(1) It has not been verified on all targets and tools, and
|
(1) It has not been verified on all targets and tools, and
|
||||||
(2) it still lacks some of the creature-comforts of the more mature environments.
|
(2) it still lacks some of the creature-comforts of the more mature
|
||||||
|
environments.
|
||||||
|
|
||||||
There is an alternative to the setenv.sh script available for the Windows
|
There is an alternative to the setenv.sh script available for the Windows
|
||||||
native environment: tools/configure.bat. See tools/README.txt for additional
|
native environment: tools/configure.bat. See tools/README.txt for additional
|
||||||
information.
|
information.
|
||||||
|
|
||||||
Installing GNUWin32
|
Installing GNUWin32
|
||||||
-------------------
|
-------------------
|
||||||
@@ -1491,7 +1495,8 @@ nuttx/
|
|||||||
| |- eeprom/
|
| |- eeprom/
|
||||||
| | `- README.txt
|
| | `- README.txt
|
||||||
| |- lcd/
|
| |- lcd/
|
||||||
| | `- README.txt
|
| | | README.txt
|
||||||
|
| | `- pcf8574_lcd_backpack_readme.txt
|
||||||
| |- mtd/
|
| |- mtd/
|
||||||
| | `- README.txt
|
| | `- README.txt
|
||||||
| |- sensors/
|
| |- sensors/
|
||||||
|
|||||||
+364
-1
@@ -5303,7 +5303,8 @@ Additional new features and extended functionality:
|
|||||||
can be re-enabled if needed via configuration option.
|
can be re-enabled if needed via configuration option.
|
||||||
- NXFFS: Make the start up scan of the media a configuration option.
|
- NXFFS: Make the start up scan of the media a configuration option.
|
||||||
It just takes to long and is not really necessary! Those rare cases
|
It just takes to long and is not really necessary! Those rare cases
|
||||||
where the scan was helpful can be fixed using flash_eraseall().
|
where the scan was helpful can be fixed using MDIOC_BULKERASE IOCTL
|
||||||
|
command.
|
||||||
|
|
||||||
* General Drivers:
|
* General Drivers:
|
||||||
|
|
||||||
@@ -10716,3 +10717,365 @@ detailed bugfix information):
|
|||||||
- Moved C++ initialization logic out of the RTOS and into the
|
- Moved C++ initialization logic out of the RTOS and into the
|
||||||
application space, specifically to apps/platform/board, where it
|
application space, specifically to apps/platform/board, where it
|
||||||
belongs.
|
belongs.
|
||||||
|
|
||||||
|
NuttX-7.16 Release Notes
|
||||||
|
------------------------
|
||||||
|
|
||||||
|
The 116th release of NuttX, Version 7.16, was made on June 1, 2016,
|
||||||
|
and is available for download from the Bitbucket.org website. Note
|
||||||
|
that release consists of two tarballs: nuttx-7.16.tar.gz and
|
||||||
|
apps-7.16.tar.gz. These are available from:
|
||||||
|
|
||||||
|
https://bitbucket.org/nuttx/nuttx/downloads
|
||||||
|
https://bitbucket.org/nuttx/apps/downloads
|
||||||
|
|
||||||
|
Both may be needed (see the top-level nuttx/README.txt file for build
|
||||||
|
information).
|
||||||
|
|
||||||
|
Additional new features and extended functionality:
|
||||||
|
|
||||||
|
* Core OS:
|
||||||
|
|
||||||
|
- Power Management: Add activity domain to all PM interfaces and
|
||||||
|
driver callbacks. If CONFIG_PM_NDOMAINS == 1, then the legacy
|
||||||
|
behavior is preserved. If CONFIG_PM_NDOMAINS > 1, then multiple
|
||||||
|
PM domains are supported. This will allow separate control for
|
||||||
|
certain power management groups. For example, a network can be
|
||||||
|
shut down without affect an ongoing UI (and vice versa).
|
||||||
|
- board_app_initialize(): board_app_initialize() now accepts an
|
||||||
|
argument that may be used to support initialization in different
|
||||||
|
configurations.
|
||||||
|
|
||||||
|
* File System and Block and MTD Drivers:
|
||||||
|
|
||||||
|
- N25Qxxx: Add MTD support for Micron N25Qxxx family of QSPI flash.
|
||||||
|
From Dave (ziggurat29).
|
||||||
|
- SST26F: Add an MTD driver for SST26F spi/qspi flash devices (SPI
|
||||||
|
mode only). From Sebastien Lorquet.
|
||||||
|
- File Descriptor Detach: Add logic to detach a file structure from a
|
||||||
|
file descriptor. This is for use only within the OS. It permits an
|
||||||
|
open file or driver to be used across multiple threads.
|
||||||
|
|
||||||
|
* Networking and Network Drivers:
|
||||||
|
|
||||||
|
- listen()/accept(): Separate out psock_listen() and psock_accepti()
|
||||||
|
for internal, thread independent OS usage (i.e., without a socket
|
||||||
|
descriptor).
|
||||||
|
- VNC Server: Add support for a VNC server. This logic is code
|
||||||
|
complete and functional, but not well tested.
|
||||||
|
|
||||||
|
* Graphics and Graphic Drivers:
|
||||||
|
|
||||||
|
- Framebuffer driver: Add a display number to each interface in order
|
||||||
|
to support multiple display devices.
|
||||||
|
- VNC Server: Add support for a VNC server. This logic is code
|
||||||
|
complete and functional, but not well tested.
|
||||||
|
- LCD Backpack: Add support for PCF8574 LCD Backpack driver. This
|
||||||
|
driver supports an interface board that is based on the PCF8574 I/O
|
||||||
|
expander and supports the HD44780-based (or compatible) LCD modules.
|
||||||
|
There are a myriad of different vendors of such, but they are
|
||||||
|
principally the same, save wiring and minor features like jumpers
|
||||||
|
for I2C addresses. This driver supports known and unknown variants.
|
||||||
|
From Dave (ziggurat29).
|
||||||
|
|
||||||
|
* Common Device Drivers:
|
||||||
|
|
||||||
|
- RTC: Simplify the RTC interface. The old interface was way too
|
||||||
|
complex and was not fully implemented anywhere.
|
||||||
|
- BH1750FVI: Add a character driver for Rohm Ambient Light Sensor
|
||||||
|
BH1750FVI. From Alan Carvalho de Assis.
|
||||||
|
- CAN: Improve CAN error reporting. From Frank Benkert.
|
||||||
|
- aes.h: Modifications to the crypto API needed for LPC43xx. From
|
||||||
|
Alexander Vasiljev.
|
||||||
|
- ADC: Interface no longer uses global adc_receive() call. Added a
|
||||||
|
new bind() method to the ADC interface. Now the ADC upper half
|
||||||
|
driver will register its receipt-of-data callback. This change
|
||||||
|
allows the ADC lower half driver to be used with a differ ADC upper
|
||||||
|
half.
|
||||||
|
|
||||||
|
* Simulation Platform:
|
||||||
|
|
||||||
|
- Linux Host Networking: Enhance networking support for the
|
||||||
|
simulation under Linux. Includes updated support for Linux TUN/TAP,
|
||||||
|
and the addition of support for Linux bridge devices. From Steve.
|
||||||
|
|
||||||
|
* ARMv7-A, ARMv7-R, and ARMv7-M:
|
||||||
|
|
||||||
|
- ARMv7-M: Convert more assembly language files for use with the IAR
|
||||||
|
toolchain. From Kha Vo.
|
||||||
|
- ARMv7-A: Complete re-design of SMP-related logic to initialize each
|
||||||
|
CPUn, n > 0, when CONFIG_SMP=y.
|
||||||
|
|
||||||
|
* Atmel SAMV7:
|
||||||
|
|
||||||
|
- Add a JTAG config and ERASE config to Kconfig to set the
|
||||||
|
CCFG_SYSIO SYSIO Pins. From David Sidrane.
|
||||||
|
- System Reset: Add the up_systemreset interface to the samv7 arch. The
|
||||||
|
approach is slightly different in that: 1) It enables ARCH_HAVE_RESET
|
||||||
|
and allows the user to set if, and for how long, to drive External
|
||||||
|
nRST signal. It also does not contain a default board_reset, as that
|
||||||
|
really should be done in the config's src if CONFIG_BOARDCTL_RESET
|
||||||
|
is defined. From David Sidrane.
|
||||||
|
|
||||||
|
* Atmel SAMV7 Boards:
|
||||||
|
|
||||||
|
- SAMV71-XULT: Add configuration(s) that were be used to verify VNC
|
||||||
|
graphics output as well as mouse and keyboard input.
|
||||||
|
|
||||||
|
* NXP Freescale i.MX6 Boards:
|
||||||
|
|
||||||
|
- Sabre-6Quad: The basic i.MX6 port is complete. This is a minimal
|
||||||
|
port at present and probably still has some as-of-yet-undiscovered
|
||||||
|
issues.
|
||||||
|
- Sabre-6Quad: Basic SMP NSH configuration is now working. But this
|
||||||
|
is probably only because the SMP test case does not stress the
|
||||||
|
logic. There are know outstanding SMP issues as noted in the
|
||||||
|
Sabre-6Quad README.txt file.
|
||||||
|
|
||||||
|
* NXP Freescale LPC43xx:
|
||||||
|
|
||||||
|
- LPC4337jet100: Add definitions for the LPC4337jet100 chip. From
|
||||||
|
Alexander Vasiljev.
|
||||||
|
|
||||||
|
* NXP Freescale LPC43xx Drivers:
|
||||||
|
|
||||||
|
- AES: Add AES support. From Alexander Vasiljev.
|
||||||
|
|
||||||
|
* STMicro STM32:
|
||||||
|
|
||||||
|
- STM32 L4: Add configuration options to allow SRAM2 to be used for
|
||||||
|
heap, or not at all, and to zero-initialize it on OS start, or not
|
||||||
|
at all. From Dave dev@ziggurat29.com.
|
||||||
|
- STM32 L4: Add support for HSE and MSI clocks, and auto trim of MSI
|
||||||
|
to LSE (needed for USB). From Dave (ziggurat29)
|
||||||
|
- STM32 L4: Add support for unique id function to arch; modified board
|
||||||
|
to support unique id boardctl. From Dave (ziggurat29)
|
||||||
|
|
||||||
|
* STMicro STM32 Drivers:
|
||||||
|
|
||||||
|
- STM32 F4 RTC: Add a custom RTC driver with support for alarms. From
|
||||||
|
Neil Hancock.
|
||||||
|
- STM32 L4 QSPI: Add a QSPI driver with DMA support and (optional
|
||||||
|
memory mapped mode support. From Dave ziggurat29).
|
||||||
|
- STM32, STM32 L4, and STM32 F7 Serial: Add support for compliant
|
||||||
|
SD-style breaks. From David Sidrane.
|
||||||
|
- STM32 L4 CAN: Add CAN support for STM32L4. From Sebastien Lorquet.
|
||||||
|
- STM32 1-Wire: Add support for a custom 1-wire driver. The serial
|
||||||
|
driver already supports a 1-wire interface, but this driver uses the
|
||||||
|
same serial logic to implement a lower half driver much like the
|
||||||
|
I2C lower half driver. From Aleksandr Vyhovanec.
|
||||||
|
- STM32 L4 SPI: Add support for SPI 4 and 5 on stm32f411 chips. From
|
||||||
|
Konstantin Berezenko.
|
||||||
|
- STM32 ADC: Allow omitting use of channels in a lower part of PWM.
|
||||||
|
From Pierre-noel Bouteville.
|
||||||
|
- STM32 L4 I2C: Get I2C working for STM32L4. From Dave (ziggurat29).
|
||||||
|
|
||||||
|
* STMicro STM32 Boards:
|
||||||
|
|
||||||
|
- STM3220G-EVAL: Add support for both the IAR and uVision GCC IDEs.
|
||||||
|
From Kha Vo.
|
||||||
|
- STM32F429I Discovery: Add support for the uVision GCC IDE. From
|
||||||
|
Kha Vo.
|
||||||
|
- STM32F4 Discovery: Integrate BH1750FVI driver in the STM32F4 Discovery
|
||||||
|
board. From Alan Carvalho de Assis.
|
||||||
|
- STM32L476VG Discovery: Add support for QSPI based N25Qxxx flash.
|
||||||
|
From Dave (ziggurat29)
|
||||||
|
- STM32L476VG Discovery: Add board ioctls for allowing user application
|
||||||
|
to cause QSPI memory mapped mode to be engaged and disengaged. Also
|
||||||
|
partitioned QSPI flash for file system and other (eventually xip).
|
||||||
|
From Dave (ziggurat29)
|
||||||
|
- Nucleo-144: Basic port for the Nucleo-144 board with the STM32F746ZG
|
||||||
|
MCU. From Kconstantin Berezenko.
|
||||||
|
- STM32F103 Minimum: Add support for this minimual STM32F103CBT6 "blue"
|
||||||
|
board. From Alan Carvalho de Assis.
|
||||||
|
- STM32F411E Discovery: Add basic configuration for stm32f411e-disco
|
||||||
|
board with STM32F411VE chip. From Konstantin Berezenko.
|
||||||
|
|
||||||
|
* Build/Configuration System:
|
||||||
|
|
||||||
|
- Moved NuttX repository to https://bitbucket.org/nuttx/nuttx.
|
||||||
|
Eliminated use of sub-modules.
|
||||||
|
- Add support for the IAR toolchain for the limited case of the ARMv7-M
|
||||||
|
architecture and the STM32 chip. From Aleksandr Vyhovanec.
|
||||||
|
- make export: Pass top-level make to the script to allow -j greater
|
||||||
|
than 1. From David Sidrane.
|
||||||
|
- fs/Kconfig: Allow CONFIG_FS_WRITABLE to be manually selectable. This
|
||||||
|
is needed when there are no writable file systems, but write support
|
||||||
|
is still needed in BCH or FTL.
|
||||||
|
- arch/*/Makefile: Add definitions that can be overrided to use GCC
|
||||||
|
instead of LD in the final link. From Paul Alexander Patience .
|
||||||
|
|
||||||
|
* Applications: apps/netutils:
|
||||||
|
|
||||||
|
- apps/netutils/esp8266: ESP8266 driver application. From Pierre-noel
|
||||||
|
Bouteville.
|
||||||
|
|
||||||
|
* Applications: apps/examples:
|
||||||
|
|
||||||
|
- apps/examples/alarm: Add a simple test of the ALARM iotcl calls of
|
||||||
|
the RTC driver.
|
||||||
|
- apps/examples/nximage: Add a configuration option to select
|
||||||
|
greyscale.
|
||||||
|
|
||||||
|
* Platforms: apps/platform:
|
||||||
|
|
||||||
|
- apps/platform/nucleo-144: Add platform files for NUCLEO-144
|
||||||
|
(NUCLEO-F746ZG). From Mark Olsson.
|
||||||
|
- apps/examples/media: You can now override the default device driver
|
||||||
|
path by providing an alternal path on the command line. From
|
||||||
|
Sébastien Lorquet.
|
||||||
|
|
||||||
|
Works-In-Progress:
|
||||||
|
|
||||||
|
* IEEE802.14.5/6LowPAN. Hooks and framework for this effort were
|
||||||
|
introduced in NuttX-7.15. Work has continued on this effort on
|
||||||
|
forks from the main repositories, albeit with many interruptions.
|
||||||
|
The completion of this wireless feature will postponed until at
|
||||||
|
least NuttX-7.17.
|
||||||
|
|
||||||
|
* i.MX6 SMP. Partially functional, but there is more that still
|
||||||
|
needs to be done.
|
||||||
|
|
||||||
|
Bugfixes. Only the most critical bugfixes are listed here (see the
|
||||||
|
ChangeLog for the complete list of bugfixes and for additional, more
|
||||||
|
detailed bugfix information):
|
||||||
|
|
||||||
|
* Core OS:
|
||||||
|
|
||||||
|
- Various places: Search for places where a stray semicolon following
|
||||||
|
an if condition cause the if body to be executed unconditionally.
|
||||||
|
Fixes in all SAM DMA logic, unionfs, OS signalling logic, and others.
|
||||||
|
- enter/leave_critical_section() may attempt to access task lists
|
||||||
|
before they have been initialized in the SMP configuration.
|
||||||
|
|
||||||
|
* File System/Block Drivers:
|
||||||
|
|
||||||
|
- SMART MTD: Return code of smart_scan not checked, can cause success
|
||||||
|
result in failure case, leading to 'dev' pointer being invalid. From
|
||||||
|
Dave (ziggurat29)
|
||||||
|
- mount: Fix a backward debug assertion. Noted by David Sidrane.
|
||||||
|
|
||||||
|
* Common Drivers:
|
||||||
|
|
||||||
|
- NRF24L01: Fix backward calculation of relative frequency. Noted by
|
||||||
|
Henry Zhang.
|
||||||
|
- PCA9555 I/O expander: Fix an error in the PCA9555 driver: Under
|
||||||
|
certain error conditions, interrupts were not being re-enabled.
|
||||||
|
Sebastien Lorquet.
|
||||||
|
- ADS1255: Must not do SPI access from interrupt handler. Use the
|
||||||
|
worker thread instead. Must also lock the SPI bus before using it.
|
||||||
|
- Several SPI-based drivers modified. All drivers that use SPI must
|
||||||
|
call SPI_LOCK and SPI_UNLOCK. This is not optional.
|
||||||
|
- MS583730: Fix a bug in crc computation for ms583730. Implement
|
||||||
|
POSIX read.
|
||||||
|
|
||||||
|
* Atmel SAMV7:
|
||||||
|
|
||||||
|
- Fix typo in MATRIX register definitions. From Stefan Kolb.
|
||||||
|
- SAMV7 Tickless Mode: This is a fix to a problem in the handling of
|
||||||
|
the oneshot timer. Due to a wrong assumption concerning the behavior
|
||||||
|
directly after the start of the timer/counter the function
|
||||||
|
sam_oneshot_cancel(…) calculates the wrong remaining time. The code
|
||||||
|
assumes that the counter register is zero directly after the start
|
||||||
|
of the timer, but this is not true. To start the time/counter a
|
||||||
|
software trigger is invoked, this trigger starts the timer/count and
|
||||||
|
sets the counter register to zero, but the reset of the counter
|
||||||
|
register is not performed instantly. According to the datasheet:
|
||||||
|
"The counter can be reset by a trigger. In this case, the counter
|
||||||
|
value passes to zero on the next valid edge of the selected clock."
|
||||||
|
Thus the counter is set to zero between 0 and USEC_PER_TICK
|
||||||
|
microseconds after the clock was started.
|
||||||
|
In my fix I use the freerun count value to determine if at least one
|
||||||
|
tick passed since the start of the timer and thus if the value of
|
||||||
|
the oneshot counter is correct. I also tried to use the function
|
||||||
|
up_timer_gettime(…) to achieve this but, at least if compiled with
|
||||||
|
no optimization the problem vanishes without using the value of the
|
||||||
|
function, the function call takes too long.
|
||||||
|
Another problem treated in the fix is that if the oneshot timer/counter
|
||||||
|
is canceled, we only know the remaining time with a precision of
|
||||||
|
USEC_PER_TICK microseconds. This means the calculated remaining time
|
||||||
|
is between 0 and USEC_PER_TICK microseconds too long. To fix this I
|
||||||
|
subtract one tick if the calculated remaining time is greater than
|
||||||
|
one tick and otherwise set the remaining time to zero. By doing so
|
||||||
|
the measured times are much more precise as without it. From Stefan
|
||||||
|
Kolb.
|
||||||
|
|
||||||
|
* Atmel SAMA5:
|
||||||
|
|
||||||
|
- SAMA5: Stefan Kolb's change to the SAMV7 Oneshot Timer should also
|
||||||
|
be applied to the SAMA5 oneshot time since the drivers are identical.
|
||||||
|
|
||||||
|
* Atmel SAM3/4:
|
||||||
|
|
||||||
|
- SAM3/4: Stefan Kolb's change to the SAMV7 Oneshot Timer should also
|
||||||
|
be applied to the SAM3/4 oneshot time since the drivers are identical.
|
||||||
|
|
||||||
|
* Atmel SAMV7 Drivers:
|
||||||
|
|
||||||
|
- SAMV7 TWIHS (as well as SAM3/4 and SAMA5: Ensure that the TWIHS
|
||||||
|
(i2c) hw get's its clock set when the sequence of
|
||||||
|
sam_i2cbus_initialize(), sam_i2cbus_uninitialize(), then
|
||||||
|
sam_i2cbus_initialize() or twi_reset() is called. I found this a
|
||||||
|
while back in the stm32 family, so there may be more arch-es with
|
||||||
|
this sort of bug. I suppose any driver that has the notion of "do
|
||||||
|
not set the freq if it is already set" could be suspect. From David
|
||||||
|
Sidrane.
|
||||||
|
- USBHS Device: Remove disabling of whole USB on suspend of USBHS.
|
||||||
|
This fix removes the disabling of the whole USB peripheral on
|
||||||
|
suspend interrupt. Its enough to freeze the clock instead. When
|
||||||
|
disabling the whole peripheral, the next wakeup-interrupt comes up
|
||||||
|
with an disabled clocking. The unfreeze clock has no effect, because
|
||||||
|
the master clock is disabled. This makes all registers, including
|
||||||
|
the IDR unwriteable and the IRQ falls in an endless loop blocking
|
||||||
|
the whole system. Furthermore the disabling of the peripheral clock
|
||||||
|
prevents hotplugging or reconnecting the USB. From Frank Benkert.
|
||||||
|
- MCAN: Fix missing unlock of device in MCAN mcan_txempty(). From
|
||||||
|
Frank Benkert.
|
||||||
|
|
||||||
|
* STMicro STM32:
|
||||||
|
|
||||||
|
- STM32 L4 Clocking: Problem with resetting backup domain clears
|
||||||
|
clocking options set up before in *rcc.c use INITS flag to avoid
|
||||||
|
magic reg value to detect power up reset state of RTC correct a
|
||||||
|
problem clearing interrupt flags (they weren't) which prevented an
|
||||||
|
alarm from ever being used more than once per reset cycle. From
|
||||||
|
Dave (ziggurat29)
|
||||||
|
|
||||||
|
* STMicro STM32 Drivers:
|
||||||
|
|
||||||
|
- STM32L4 SPI: That STM32Lr SPI driver is quite different. They now
|
||||||
|
handle frames of arbitrary size between 4 and 16 bits. It was broken
|
||||||
|
before a new bit has to be set (RX fifo threshold) to handle <= 8-bit
|
||||||
|
transactions. If not set, the default is 16-bit packed >=8-bit
|
||||||
|
frames and the RXNE bit is never set (it is set when 16-bits are
|
||||||
|
received). weird things as always. This also add 8-bit access
|
||||||
|
routines to the data register, because a 16-bit access to the data
|
||||||
|
register when the frame size is below 9 bits is interpreted as a
|
||||||
|
packed dual frame exchange. Sebastien Lorquet.
|
||||||
|
- STM32: Correct some bad commits that broke the LTDC display example.
|
||||||
|
From Marco Krahl.
|
||||||
|
- STM32 F4 RTC: Fix logic in F4 RTCC driver that prevent ALARM
|
||||||
|
interrupt. From Neil Hancock.
|
||||||
|
- STM32 F1 ADC: Fix STM32 ValueLine ADC IRQ number selection. From
|
||||||
|
David Sidrane.
|
||||||
|
|
||||||
|
* STMicro STM32 Boards:
|
||||||
|
|
||||||
|
- STM32F429I Discovery: Correct some bad commits that broke the LTDC
|
||||||
|
display example. From Marco Krahl.
|
||||||
|
|
||||||
|
* TI Tiva:
|
||||||
|
|
||||||
|
- GPIO Interrupts: Fix a bug of GPIO falling-edge interrupt for tiva.
|
||||||
|
From Young.
|
||||||
|
|
||||||
|
* C Library:
|
||||||
|
|
||||||
|
- math: Add a NAN test on 'x' in asin function of lib_asin.c. Suggested
|
||||||
|
by Pierre-noel Bouteville.
|
||||||
|
|
||||||
|
* Build/Configuration System:
|
||||||
|
|
||||||
|
- Several Makefiles: Add .PHONY definitions to prevent 'clean up to date'
|
||||||
|
message weirdness when 'make clean' is done with no .config or
|
||||||
|
Make.defs file.
|
||||||
|
|||||||
@@ -1,20 +1,20 @@
|
|||||||
NuttX TODO List (Last updated March 31, 2016)
|
NuttX TODO List (Last updated June 6, 2016)
|
||||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
This file summarizes known NuttX bugs, limitations, inconsistencies with
|
This file summarizes known NuttX bugs, limitations, inconsistencies with
|
||||||
standards, things that could be improved, and ideas for enhancements. This
|
standards, things that could be improved, and ideas for enhancements. This
|
||||||
TODO list does not include issues associated with individual boar ports. See
|
TODO list does not include issues associated with individual boar ports. See
|
||||||
altheso individual README.txt files in the configs/ sub-directories for
|
also the individual README.txt files in the configs/ sub-directories for
|
||||||
issues reated to each board port.
|
issues related to each board port.
|
||||||
|
|
||||||
nuttx/
|
nuttx/:
|
||||||
|
|
||||||
(13) Task/Scheduler (sched/)
|
(13) Task/Scheduler (sched/)
|
||||||
(1) Memory Management (mm/)
|
(1) Memory Management (mm/)
|
||||||
(3) Signals (sched/signal, arch/)
|
(3) Signals (sched/signal, arch/)
|
||||||
(2) pthreads (sched/pthread)
|
(2) pthreads (sched/pthread)
|
||||||
(0) Message Queues (sched/mqueue)
|
(0) Message Queues (sched/mqueue)
|
||||||
(8) Kernel/Protected Build
|
(9) Kernel/Protected Build
|
||||||
(3) C++ Support
|
(3) C++ Support
|
||||||
(6) Binary loaders (binfmt/)
|
(6) Binary loaders (binfmt/)
|
||||||
(12) Network (net/, drivers/net)
|
(12) Network (net/, drivers/net)
|
||||||
@@ -23,16 +23,16 @@ nuttx/
|
|||||||
(11) Libraries (libc/, libm/)
|
(11) Libraries (libc/, libm/)
|
||||||
(11) File system/Generic drivers (fs/, drivers/)
|
(11) File system/Generic drivers (fs/, drivers/)
|
||||||
(8) Graphics subsystem (graphics/)
|
(8) Graphics subsystem (graphics/)
|
||||||
(1) Pascal add-on (pcode/)
|
(2) Build system / Toolchains
|
||||||
(1) Build system / Toolchains
|
(3) Linux/Cywgin simulation (arch/sim)
|
||||||
(4) Linux/Cywgin simulation (arch/sim)
|
|
||||||
(4) ARM (arch/arm/)
|
(4) ARM (arch/arm/)
|
||||||
|
|
||||||
apps/
|
apps/ and other Add-Ons:
|
||||||
|
|
||||||
(3) Network Utilities (apps/netutils/)
|
(3) Network Utilities (apps/netutils/)
|
||||||
(2) NuttShell (NSH) (apps/nshlib)
|
(2) NuttShell (NSH) (apps/nshlib)
|
||||||
(1) System libraries apps/system (apps/system)
|
(1) System libraries apps/system (apps/system)
|
||||||
|
(1) Pascal add-on (pcode/)
|
||||||
(4) Other Applications & Tests (apps/examples/)
|
(4) Other Applications & Tests (apps/examples/)
|
||||||
|
|
||||||
o Task/Scheduler (sched/)
|
o Task/Scheduler (sched/)
|
||||||
@@ -70,7 +70,7 @@ o Task/Scheduler (sched/)
|
|||||||
Title: GET_ENVIRON_PTR()
|
Title: GET_ENVIRON_PTR()
|
||||||
Description: get_environ_ptr() (sched/sched_getenvironptr.c) is not implemented.
|
Description: get_environ_ptr() (sched/sched_getenvironptr.c) is not implemented.
|
||||||
The representation of the environment strings selected for
|
The representation of the environment strings selected for
|
||||||
NutX is not compatible with the operation. Some significant
|
NuttX is not compatible with the operation. Some significant
|
||||||
re-design would be required to implement this function and that
|
re-design would be required to implement this function and that
|
||||||
effort is thought to be not worth the result.
|
effort is thought to be not worth the result.
|
||||||
Status: Open. No change is planned.
|
Status: Open. No change is planned.
|
||||||
@@ -81,7 +81,7 @@ o Task/Scheduler (sched/)
|
|||||||
Status: Open
|
Status: Open
|
||||||
Priority: Low -- There is no plan to implement this.
|
Priority: Low -- There is no plan to implement this.
|
||||||
|
|
||||||
Title: INCOMPATIBILITES WITH execv() AND execl()
|
Title: INCOMPATIBILITIES WITH execv() AND execl()
|
||||||
Description: Simplified 'execl()' and 'execv()' functions are provided by
|
Description: Simplified 'execl()' and 'execv()' functions are provided by
|
||||||
NuttX. NuttX does not support processes and hence the concept
|
NuttX. NuttX does not support processes and hence the concept
|
||||||
of overlaying a tasks process image with a new process image
|
of overlaying a tasks process image with a new process image
|
||||||
@@ -175,7 +175,7 @@ o Task/Scheduler (sched/)
|
|||||||
Yahoo! Groups message 7726: "I think that the system
|
Yahoo! Groups message 7726: "I think that the system
|
||||||
should be required to handle pthread_cancel safely in
|
should be required to handle pthread_cancel safely in
|
||||||
all cases. In the NuttX model, a task is like a Unix
|
all cases. In the NuttX model, a task is like a Unix
|
||||||
process and a pthread is like a Unix thread. Cancelling
|
process and a pthread is like a Unix thread. Canceling
|
||||||
threads should always be safe (or at least as unsafe) as
|
threads should always be safe (or at least as unsafe) as
|
||||||
under Unix because the model is complete for pthreads...
|
under Unix because the model is complete for pthreads...
|
||||||
|
|
||||||
@@ -188,7 +188,7 @@ o Task/Scheduler (sched/)
|
|||||||
|
|
||||||
"The patch I just incorporated is also insufficient. It
|
"The patch I just incorporated is also insufficient. It
|
||||||
works only if the serial driver is shut down when the
|
works only if the serial driver is shut down when the
|
||||||
thread is cancelled. But what if there are other open
|
thread is canceled. But what if there are other open
|
||||||
references to the driver? Then the driver will not be
|
references to the driver? Then the driver will not be
|
||||||
shut down, the semaphores will not be re-initialized, and
|
shut down, the semaphores will not be re-initialized, and
|
||||||
the semaphore counts will still be off by one.
|
the semaphore counts will still be off by one.
|
||||||
@@ -202,7 +202,7 @@ o Task/Scheduler (sched/)
|
|||||||
hooks so that given a semaphore it can traverse all
|
hooks so that given a semaphore it can traverse all
|
||||||
holders. What is needed would be logic so that given
|
holders. What is needed would be logic so that given
|
||||||
a task, you can traverse all semaphores held by the task,
|
a task, you can traverse all semaphores held by the task,
|
||||||
releasing each semaphore cound held by the exiting task.
|
releasing each semaphore count held by the exiting task.
|
||||||
Nothing like this exists now so that solution is not
|
Nothing like this exists now so that solution is not
|
||||||
imminent.
|
imminent.
|
||||||
|
|
||||||
@@ -228,16 +228,15 @@ o Task/Scheduler (sched/)
|
|||||||
hidden behind simple accessor functions and so the internal
|
hidden behind simple accessor functions and so the internal
|
||||||
data structures can be changed if need with very little impact.
|
data structures can be changed if need with very little impact.
|
||||||
|
|
||||||
|
Explicitly reference to the list structure are hidden behind
|
||||||
Explicity refereence to the list strucutre are hidden behnid
|
|
||||||
the macro this_task().
|
the macro this_task().
|
||||||
|
|
||||||
Status: Open
|
Status: Open
|
||||||
Priority: Low. Things are just the way that we want them for the way
|
Priority: Low. Things are just the way that we want them for the way
|
||||||
that NuttX is used today.
|
that NuttX is used today.
|
||||||
|
|
||||||
o Memory Managment (mm/)
|
o Memory Management (mm/)
|
||||||
^^^^^^^^^^^^^^^^^^^^^^
|
^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
Title: FREE MEMORY ON TASK EXIT
|
Title: FREE MEMORY ON TASK EXIT
|
||||||
Description: Add an option to free all memory allocated by a task when the
|
Description: Add an option to free all memory allocated by a task when the
|
||||||
@@ -390,7 +389,7 @@ o pthreads (sched/pthreads)
|
|||||||
Priority: Low -- about zero, probably not that useful. Priority inheritance is
|
Priority: Low -- about zero, probably not that useful. Priority inheritance is
|
||||||
already supported and is a much better solution. And it turns out
|
already supported and is a much better solution. And it turns out
|
||||||
that priority protection is just about as complex as priority inheritance.
|
that priority protection is just about as complex as priority inheritance.
|
||||||
Exerpted from my post in a Linked-In discussion:
|
Excerpted from my post in a Linked-In discussion:
|
||||||
|
|
||||||
"I started to implement this HLS/"PCP" semaphore in an RTOS that I
|
"I started to implement this HLS/"PCP" semaphore in an RTOS that I
|
||||||
work with (http://www.nuttx.org) and I discovered after doing the
|
work with (http://www.nuttx.org) and I discovered after doing the
|
||||||
@@ -589,7 +588,26 @@ o Kernel/Protected Build
|
|||||||
interrupt level callbacks into applications. This, of course,
|
interrupt level callbacks into applications. This, of course,
|
||||||
will never work in anything but a non-secure, flat build.
|
will never work in anything but a non-secure, flat build.
|
||||||
Status: Open
|
Status: Open
|
||||||
Priority: Medium. The driver is only usable with all of its features in a FLAT build.
|
Priority: Medium. The driver is only usable with all of its features
|
||||||
|
in a FLAT build.
|
||||||
|
|
||||||
|
Title: USER MODE TASKS CAN MODIFY PRIVILEGED TASKS
|
||||||
|
Description: Certain interfaces, such as sched_setparam(),
|
||||||
|
sched_setscheduler(), etc. can be used by user mode tasks to
|
||||||
|
modify the behavior of priviledged kernel threads.
|
||||||
|
task_delete() could even be used to kill a kernel thread.
|
||||||
|
For a truly secure system. Privileges need to be checked in
|
||||||
|
every interface that permits one thread to modify the
|
||||||
|
properties of another thread.
|
||||||
|
|
||||||
|
NOTE: It would be a simple matter to simply disable user
|
||||||
|
threads from modifying privileged threads. However, you
|
||||||
|
might also want to be able to modify privileged threads from
|
||||||
|
user tasks with certain permissions. Permissions is a much
|
||||||
|
more complex issue.
|
||||||
|
Status: Open
|
||||||
|
Priority: Low for most embedded systems but would be a critical need if
|
||||||
|
NuttX were used in a secure system.
|
||||||
|
|
||||||
o C++ Support
|
o C++ Support
|
||||||
^^^^^^^^^^^
|
^^^^^^^^^^^
|
||||||
@@ -784,7 +802,7 @@ o Binary loaders (binfmt/)
|
|||||||
to get fixed as needed for Windows native tool builds.
|
to get fixed as needed for Windows native tool builds.
|
||||||
|
|
||||||
Title: TOOLCHAIN COMPATIBILITY PROBLEM
|
Title: TOOLCHAIN COMPATIBILITY PROBLEM
|
||||||
Descripton: The older 4.3.3 compiler generates GOTOFF relocations to the constant
|
Description: The older 4.3.3 compiler generates GOTOFF relocations to the constant
|
||||||
strings, like:
|
strings, like:
|
||||||
|
|
||||||
.L3:
|
.L3:
|
||||||
@@ -794,7 +812,7 @@ o Binary loaders (binfmt/)
|
|||||||
.word .LC3(GOTOFF)
|
.word .LC3(GOTOFF)
|
||||||
.word .LC4(GOTOFF)
|
.word .LC4(GOTOFF)
|
||||||
|
|
||||||
Where .LC0, LC1, LC2, LC3, and .LC4 are the labels correponding to strings in
|
Where .LC0, LC1, LC2, LC3, and .LC4 are the labels corresponding to strings in
|
||||||
the .rodata.str1.1 section. One consequence of this is that .rodata must reside
|
the .rodata.str1.1 section. One consequence of this is that .rodata must reside
|
||||||
in D-Space since it will addressed relative to the GOT (see the section entitled
|
in D-Space since it will addressed relative to the GOT (see the section entitled
|
||||||
"Read-Only Data in RAM" at
|
"Read-Only Data in RAM" at
|
||||||
@@ -880,7 +898,7 @@ o Network (net/, drivers/net)
|
|||||||
RFC3678 (IGMPv3) suggests ioctl() commands to do this (SIOCSIPMSFILTER) but
|
RFC3678 (IGMPv3) suggests ioctl() commands to do this (SIOCSIPMSFILTER) but
|
||||||
also status that those APIs are historic. NuttX implements these ioctl
|
also status that those APIs are historic. NuttX implements these ioctl
|
||||||
commands, but is non-standard because: (1) It does not support IGMPv3, and
|
commands, but is non-standard because: (1) It does not support IGMPv3, and
|
||||||
(2) it looks up drivers by their device name (eg., "eth0") vs IP address.
|
(2) it looks up drivers by their device name (e.g., "eth0") vs IP address.
|
||||||
|
|
||||||
Linux uses setsockopt() to control multicast group membership using the
|
Linux uses setsockopt() to control multicast group membership using the
|
||||||
IP_ADD_MEMBERSHIP and IP_DROP_MEMBERSHIP options. It also looks up drivers
|
IP_ADD_MEMBERSHIP and IP_DROP_MEMBERSHIP options. It also looks up drivers
|
||||||
@@ -896,7 +914,7 @@ o Network (net/, drivers/net)
|
|||||||
that connection may time out. How should this be handled? Should the
|
that connection may time out. How should this be handled? Should the
|
||||||
connection be removed from the backlog if it is times out or is closed?
|
connection be removed from the backlog if it is times out or is closed?
|
||||||
Or should it remain in the backlog with a status indication so that accept()
|
Or should it remain in the backlog with a status indication so that accept()
|
||||||
can fail when it encounteres the invalid connection?
|
can fail when it encounters the invalid connection?
|
||||||
Status: Open
|
Status: Open
|
||||||
Priority: Medium. Important on slow applications that will not accept
|
Priority: Medium. Important on slow applications that will not accept
|
||||||
connections promptly.
|
connections promptly.
|
||||||
@@ -975,7 +993,7 @@ o Network (net/, drivers/net)
|
|||||||
it is no longer needed. Perhaps there should be a delayed
|
it is no longer needed. Perhaps there should be a delayed
|
||||||
call to unlink() (using a watchdog or the work queue). If
|
call to unlink() (using a watchdog or the work queue). If
|
||||||
the driver is re-opened, the delayed unlink could be
|
the driver is re-opened, the delayed unlink could be
|
||||||
cancelled? Needs more thought.
|
canceled? Needs more thought.
|
||||||
NOTE: This is not an issue for Unix domain streams sockets:
|
NOTE: This is not an issue for Unix domain streams sockets:
|
||||||
The end-of-life of the FIFO is well determined when sockets
|
The end-of-life of the FIFO is well determined when sockets
|
||||||
are disconnected and support for that case is fully implemented.
|
are disconnected and support for that case is fully implemented.
|
||||||
@@ -1020,7 +1038,7 @@ o USB (drivers/usbdev, drivers/usbhost)
|
|||||||
that involves delays. This needs to be redesigned to eliminate these
|
that involves delays. This needs to be redesigned to eliminate these
|
||||||
delays. See logic conditioned on CONFIG_USBMSC_RACEWAR.
|
delays. See logic conditioned on CONFIG_USBMSC_RACEWAR.
|
||||||
|
|
||||||
If queuing of stall requests is supported by DCD then this workaround
|
If queuing of stall requests is supported by the DCD then this workaround
|
||||||
is not required. In this case, (1) the stall is not sent until all
|
is not required. In this case, (1) the stall is not sent until all
|
||||||
write requests preceding the stall request are sent, (2) the stall is
|
write requests preceding the stall request are sent, (2) the stall is
|
||||||
sent, and then after the stall is cleared, (3) all write requests
|
sent, and then after the stall is cleared, (3) all write requests
|
||||||
@@ -1135,7 +1153,7 @@ o USB (drivers/usbdev, drivers/usbhost)
|
|||||||
Priority: Medium-Low
|
Priority: Medium-Low
|
||||||
|
|
||||||
Title: USB CDC/ACM HOST CLASS DRIVER
|
Title: USB CDC/ACM HOST CLASS DRIVER
|
||||||
Desciption: A CDC/ACM host class driver has been added. This has been
|
Description: A CDC/ACM host class driver has been added. This has been
|
||||||
testing by running the USB CDC/ACM host on an Olimex
|
testing by running the USB CDC/ACM host on an Olimex
|
||||||
LPC1766STK and using the configs/stm3210e-eval/usbserial
|
LPC1766STK and using the configs/stm3210e-eval/usbserial
|
||||||
configuration (using the CDC/ACM device side driver). There
|
configuration (using the CDC/ACM device side driver). There
|
||||||
@@ -1374,7 +1392,7 @@ o File system / Generic drivers (fs/, drivers/)
|
|||||||
Priority: Medium
|
Priority: Medium
|
||||||
|
|
||||||
Title: UNIFIED DESCRIPTOR REPRESENTATION
|
Title: UNIFIED DESCRIPTOR REPRESENTATION
|
||||||
Descripton: There are two separate ranges of descriptors for file and
|
Description: There are two separate ranges of descriptors for file and
|
||||||
socket descriptors: if a descriptor is in one range then it is
|
socket descriptors: if a descriptor is in one range then it is
|
||||||
recognized as a file descriptor; if it is in another range
|
recognized as a file descriptor; if it is in another range
|
||||||
then it is recognized as a socket descriptor. These separate
|
then it is recognized as a socket descriptor. These separate
|
||||||
@@ -1410,7 +1428,7 @@ o File system / Generic drivers (fs/, drivers/)
|
|||||||
Status: Open
|
Status: Open
|
||||||
Priority: Low
|
Priority: Low
|
||||||
|
|
||||||
Title: FAT LONG FILENAME COMPATIBILTY
|
Title: FAT LONG FILENAME COMPATIBILITY
|
||||||
Description: Recently there have been reports that file with long file
|
Description: Recently there have been reports that file with long file
|
||||||
names created by NuttX don't have long file names when viewed
|
names created by NuttX don't have long file names when viewed
|
||||||
on Windows. The long file name support has been around for a
|
on Windows. The long file name support has been around for a
|
||||||
@@ -1423,7 +1441,7 @@ o File system / Generic drivers (fs/, drivers/)
|
|||||||
Description: I have seen cases where (1) long file names are enabled,
|
Description: I have seen cases where (1) long file names are enabled,
|
||||||
but (2) a short file name is created like:
|
but (2) a short file name is created like:
|
||||||
|
|
||||||
nsh> echo "This is another thest" >/mnt/sdcard/another.txt
|
nsh> echo "This is another test" >/mnt/sdcard/another.txt
|
||||||
|
|
||||||
But then on subsequent 'ls' operations, the file does not appear:
|
But then on subsequent 'ls' operations, the file does not appear:
|
||||||
|
|
||||||
@@ -1472,7 +1490,7 @@ o File system / Generic drivers (fs/, drivers/)
|
|||||||
|
|
||||||
4) When comparing the checksum in the long file name
|
4) When comparing the checksum in the long file name
|
||||||
entry with the checksum of the short file name, the
|
entry with the checksum of the short file name, the
|
||||||
checksum fails and the entire directlry sequence is
|
checksum fails and the entire directory sequence is
|
||||||
ignored by readder() logic. This the file does not
|
ignored by readder() logic. This the file does not
|
||||||
appear in the 'ls'.
|
appear in the 'ls'.
|
||||||
|
|
||||||
@@ -1539,7 +1557,7 @@ o Graphics subsystem (graphics/)
|
|||||||
Priority: Low, the need has not yet arisen.
|
Priority: Low, the need has not yet arisen.
|
||||||
|
|
||||||
Title: PER-WINDOW FRAMEBUFFERS
|
Title: PER-WINDOW FRAMEBUFFERS
|
||||||
Description: One of the most awkard things to handle in the NX windowing
|
Description: One of the most awkward things to handle in the NX windowing
|
||||||
system is the re-draw callback. This is difficult because it
|
system is the re-draw callback. This is difficult because it
|
||||||
requires ad hoc, custom logic to be able to do the redrawing
|
requires ad hoc, custom logic to be able to do the redrawing
|
||||||
in most cases.
|
in most cases.
|
||||||
@@ -1567,26 +1585,6 @@ o Graphics subsystem (graphics/)
|
|||||||
Priority: Low, not a serious issue but worth noting. There is no plan
|
Priority: Low, not a serious issue but worth noting. There is no plan
|
||||||
to change this behavior.
|
to change this behavior.
|
||||||
|
|
||||||
o Pascal Add-On (pcode/)
|
|
||||||
^^^^^^^^^^^^^^^^^^^^^^
|
|
||||||
|
|
||||||
Title: P-CODES IN MEMORY UNTESTED
|
|
||||||
Description: Need APIs to verify execution of P-Code from memory buffer.
|
|
||||||
Status: Open
|
|
||||||
Priority: Low
|
|
||||||
|
|
||||||
Title: SMALLER LOADER AND OBJECT FORMAT
|
|
||||||
Description: Loader and object format may be too large for some small
|
|
||||||
memory systems. Consider ways to reduce memory footprint.
|
|
||||||
Status: Open
|
|
||||||
Priority: Medium
|
|
||||||
|
|
||||||
Title: PDBG
|
|
||||||
Description: Move the the pascal p-code debugger into the NuttX apps/ tree
|
|
||||||
where it can be used from the NSH command line.
|
|
||||||
Status: Open
|
|
||||||
Priority: Low
|
|
||||||
|
|
||||||
o Build system
|
o Build system
|
||||||
^^^^^^^^^^^^
|
^^^^^^^^^^^^
|
||||||
|
|
||||||
@@ -1603,21 +1601,25 @@ o Build system
|
|||||||
Status: Open
|
Status: Open
|
||||||
Priority: Low.
|
Priority: Low.
|
||||||
|
|
||||||
|
Title: NATIVE WINDOWS BUILD BROKEN
|
||||||
|
Description: The way that apps/ no generates Kmenu files depends on changes added
|
||||||
|
to apps/tools/mkkconfig.sh. Similar changes need to be made to
|
||||||
|
apps/tools/mkkconfig.bat to restore the Windows Native build.
|
||||||
|
UPDATE: The mkkconfig.bat script has been updated and appears to work.
|
||||||
|
A native build has still not been attempted and there could likely be
|
||||||
|
issues the carriage returns in Kconfig files. There are also some
|
||||||
|
issues the interpreters/ficl and bas directories during 'make menuconfig'
|
||||||
|
that still need to be investigated.
|
||||||
|
Status: Open
|
||||||
|
Priority: Low, since I am not aware of anyone using the Windows Native build.
|
||||||
|
But, of course, very high if you want to use it.
|
||||||
|
|
||||||
o Other drivers (drivers/)
|
o Other drivers (drivers/)
|
||||||
^^^^^^^^^^^^^^^^^^^^^^^^
|
^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
o Linux/Cywgin simulation (arch/sim)
|
o Linux/Cywgin simulation (arch/sim)
|
||||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
Title: SIMULATOR NETWORKING SUPPORT
|
|
||||||
Description: I never did get networking to work on the sim Linux target. On Linux,
|
|
||||||
it tries to use the tap device (/dev/net/tun) to emulate an Ethernet
|
|
||||||
NIC, but I never got it correctly integrated with the NuttX networking.
|
|
||||||
NOTE: On Cygwin, the build uses the Cygwin WPCAP library and is, at
|
|
||||||
least, partially functional (it has never been rigorously tested).
|
|
||||||
Status: Open
|
|
||||||
Priority: Low (unless you want to test networking features on the simulation).
|
|
||||||
|
|
||||||
Title: SIMULATOR HAS NO INTERRUPTS (NON-PREMPTIBLE)
|
Title: SIMULATOR HAS NO INTERRUPTS (NON-PREMPTIBLE)
|
||||||
Description: The current simulator implementation is has no interrupts and, hence,
|
Description: The current simulator implementation is has no interrupts and, hence,
|
||||||
is non-preemptible. Also, without simulated interrupt, there can
|
is non-preemptible. Also, without simulated interrupt, there can
|
||||||
@@ -1765,7 +1767,7 @@ o ARM (arch/arm/)
|
|||||||
|
|
||||||
But this has not been proven to be a solution.
|
But this has not been proven to be a solution.
|
||||||
|
|
||||||
UPDATE: Other ARM architectures have a similer issue.
|
UPDATE: Other ARM architectures have a similar issue.
|
||||||
|
|
||||||
Status: Open
|
Status: Open
|
||||||
Priority: Low. The conditions of continuous interrupts is really the problem.
|
Priority: Low. The conditions of continuous interrupts is really the problem.
|
||||||
@@ -1823,7 +1825,7 @@ o NuttShell (NSH) (apps/nshlib)
|
|||||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
Title: IFCONFIG AND MULTIPLE NETWORK INTERFACES
|
Title: IFCONFIG AND MULTIPLE NETWORK INTERFACES
|
||||||
Descripton: The ifconfig command will not behave correctly if an interface
|
Description: The ifconfig command will not behave correctly if an interface
|
||||||
is provided and there are multiple interfaces. It should only
|
is provided and there are multiple interfaces. It should only
|
||||||
show status for the single interface on the command line; it will
|
show status for the single interface on the command line; it will
|
||||||
still show status for all interfaces.
|
still show status for all interfaces.
|
||||||
@@ -1848,6 +1850,26 @@ o System libraries apps/system (apps/system)
|
|||||||
Priority: Low (unless you are using mixed C-buffered I/O with readline and
|
Priority: Low (unless you are using mixed C-buffered I/O with readline and
|
||||||
fgetc, for example).
|
fgetc, for example).
|
||||||
|
|
||||||
|
o Pascal Add-On (pcode/)
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
Title: P-CODES IN MEMORY UNTESTED
|
||||||
|
Description: Need APIs to verify execution of P-Code from memory buffer.
|
||||||
|
Status: Open
|
||||||
|
Priority: Low
|
||||||
|
|
||||||
|
Title: SMALLER LOADER AND OBJECT FORMAT
|
||||||
|
Description: Loader and object format may be too large for some small
|
||||||
|
memory systems. Consider ways to reduce memory footprint.
|
||||||
|
Status: Open
|
||||||
|
Priority: Medium
|
||||||
|
|
||||||
|
Title: PDBG
|
||||||
|
Description: Move the the pascal p-code debugger into the NuttX apps/ tree
|
||||||
|
where it can be used from the NSH command line.
|
||||||
|
Status: Open
|
||||||
|
Priority: Low
|
||||||
|
|
||||||
o Other Applications & Tests (apps/examples/)
|
o Other Applications & Tests (apps/examples/)
|
||||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
|||||||
+67
-142
@@ -134,6 +134,8 @@ src/Makefile
|
|||||||
|
|
||||||
Supported Architectures
|
Supported Architectures
|
||||||
^^^^^^^^^^^^^^^^^^^^^^^
|
^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
NOTE: nuttx/Documentation/NuttX.html for current information about the
|
||||||
|
state of these MCU ports.
|
||||||
|
|
||||||
arch/sim - Linux/Cygwin simulation
|
arch/sim - Linux/Cygwin simulation
|
||||||
A user-mode port of NuttX to the x86 Linux platform is available.
|
A user-mode port of NuttX to the x86 Linux platform is available.
|
||||||
@@ -145,135 +147,68 @@ arch/arm - ARM-based micro-controllers
|
|||||||
This directory holds common ARM architectures. At present, this includes
|
This directory holds common ARM architectures. At present, this includes
|
||||||
the following subdirectories:
|
the following subdirectories:
|
||||||
|
|
||||||
arch/arm/include and arch/arm/src/common
|
Architecture Support
|
||||||
Common ARM/Cortex-M3 logic.
|
arch/arm/include and arch/arm/src/common
|
||||||
|
arch/arm/src/arm and arch/arm/include/arm
|
||||||
|
arch/arm/src/armv7-a and arch/arm/include/armv7-a
|
||||||
|
arch/arm/src/armv7-m and arch/arm/include/armv7-m
|
||||||
|
arch/arm/src/armv7-r and arch/arm/include/armv7-4
|
||||||
|
|
||||||
arch/arm/src/arm and arch/arm/include/arm
|
MCU support
|
||||||
Common ARM-specific logic
|
arch/arm/include/c5471 and arch/arm/src/c5471
|
||||||
|
arch/arm/include/calypso and arch/arm/src/calypso
|
||||||
arch/arm/src/armv7-m and arch/arm/include/armv7-m
|
arch/arm/include/dm320 and arch/arm/src/dm320
|
||||||
Common ARMv7-M logic (Cortex-M3 and Cortex-M4)
|
arch/arm/include/efm32 and arch/arm/src/efm32
|
||||||
|
arch/arm/include/imx1 and arch/arm/src/imx1
|
||||||
arch/arm/include/c5471 and arch/arm/src/c5471
|
arch/arm/include/imx6 and arch/arm/src/imx6
|
||||||
TI TMS320C5471 (also called TMS320DM180 or just C5471).
|
arch/arm/include/kinetis and arch/arm/src/kinetis
|
||||||
NuttX operates on the ARM7 of this dual core processor. This port
|
arch/arm/include/kl and arch/arm/src/kl
|
||||||
complete, verified, and included in the NuttX release 0.1.1.
|
arch/arm/include/lpc11xx and arch/arm/src/lpc11xx
|
||||||
|
arch/arm/include/lpc17xx and arch/arm/src/lpc17xx
|
||||||
arch/arm/include/calypso and arch/arm/src/calypso
|
arch/arm/include/lpc214x and arch/arm/src/lpc214x
|
||||||
TI "Calypso" MCU used in various cell phones (and, in particular,
|
arch/arm/include/lpc2378 and arch/arm/src/lpc2378.
|
||||||
by the Osmocom-bb project). Like the c5471, NuttX operates on the
|
arch/arm/include/lpc31xx and arch/arm/src/lpc31xx
|
||||||
ARM7 of this dual core processor. This port was contributed by
|
arch/arm/include/lpc43xx and arch/arm/src/lpc43xx
|
||||||
Denis Carilki and includes the work of Denis, Alan Carvalho de Assis,
|
arch/arm/include/moxart and arch/arm/src/moxart
|
||||||
and Stefan Richter. Calypso support first appeared in NuttX-6.17.
|
arch/arm/include/nuc1xx and arch/arm/src/nuc1xx
|
||||||
|
arch/arm/include/sam34 and arch/arm/src/sam34
|
||||||
arch/arm/include/dm320 and arch/arm/src/dm320
|
arch/arm/include/sama45 and arch/arm/src/sama5
|
||||||
TI TMS320DM320 (also called just DM320).
|
arch/arm/include/samdl and arch/arm/src/samdl
|
||||||
NuttX operates on the ARM9EJS of this dual core processor. This port
|
arch/arm/include/samv7 and arch/arm/src/samv7
|
||||||
complete, verified, and included in the NuttX release 0.2.1.
|
arch/arm/include/stm32 and arch/arm/src/stm32
|
||||||
|
arch/arm/include/stm32f7 and arch/arm/src/stm32f7
|
||||||
arch/arm/include/imx and arch/arm/src/imx
|
arch/arm/include/stm32l4 and arch/arm/src/stm32l4
|
||||||
Freescale MC9328MX1 or i.MX1. This port uses the Freescale MX1ADS
|
arch/arm/include/str71x and arch/arm/src/str71x
|
||||||
development board with a GNU arm-elf toolchain* under either Linux or Cygwin.
|
arch/arm/include/tiva and arch/arm/src/tiva
|
||||||
STATUS: This port has stalled because of development tool issues. Coding
|
arch/arm/include/tms570 and arch/arm/src/tms570
|
||||||
is complete on the basic port (timer, serial console, SPI).
|
|
||||||
|
|
||||||
arch/arm/include/lm and arch/arm/src/lm
|
|
||||||
These directories contain support for the Luminary LM3S/4F family. The
|
|
||||||
initial, release of this port was included in NuttX version 0.4.6. The
|
|
||||||
current port includes timer, serial console, Ethernet, SSI, and microSD
|
|
||||||
support. There are working configurations the NuttX OS test, to run the
|
|
||||||
NuttShell (NSH), the NuttX networking test, and the uIP web server.
|
|
||||||
|
|
||||||
arch/arm/include/lpc214x and arch/arm/src/lpc214x
|
|
||||||
These directories provide support for NXP LPC214x family of
|
|
||||||
ARM7TDMI processors. This port boots and passes the OS test (examples/ostest).
|
|
||||||
The port is complete and verifed. As of NuttX 0.3.17, the port includes:
|
|
||||||
timer interrupts, serial console, USB driver, and SPI-based MMC/SD card
|
|
||||||
support. A verifed NuttShell (NSH) configuration is also available.
|
|
||||||
|
|
||||||
arch/arm/include/lpc2378 and arch/arm/src/lpc2378.
|
|
||||||
NXP LPC2378. Support is provided for the NXP LPC2378 MCU. This port was
|
|
||||||
contributed by Rommel Marcelo is was first released in NuttX-5.3.
|
|
||||||
STATUS: This port boots and passes the OS test (examples/ostest) and
|
|
||||||
includes a working implementation of the NuttShell (NSH). The port is
|
|
||||||
complete and verified. As of NuttX 5.3, the port includes only basic
|
|
||||||
timer interrupts and serial console support.
|
|
||||||
|
|
||||||
arch/arm/include/lpc31xx and arch/arm/src/lpc31xx
|
|
||||||
These directories provide support for NXP LPC31xx family of
|
|
||||||
ARM926EJ-S processors. The port for the NXP LPC3131 was first
|
|
||||||
released in NuttX-5.1 (but was not functional until NuttX-5.2).
|
|
||||||
STATUS: The basic EA3131 port is complete and verified in NuttX-5.2
|
|
||||||
This basic port includes basic boot-up, serial console, and timer
|
|
||||||
interrupts. This port was extended in NuttX 5.3 with a USB high
|
|
||||||
speed driver contributed by David Hewson. This port has been
|
|
||||||
verified using the NuttX OS test, USB serial and mass storage tests
|
|
||||||
and includes a working implementation of the NuttShell ((NSH)).
|
|
||||||
|
|
||||||
This port was later extended to support additional members of the
|
|
||||||
LPC31xx family including, specifically, the LPC3152.
|
|
||||||
|
|
||||||
arch/arm/include/sam3u and arch/arm/src/sam3u
|
|
||||||
Atmel AT91SAM3U. This port is for Atmel AT91SAM3U4E MCU.
|
|
||||||
STATUS: The basic AT91SAM3U port was released in NuttX version 5.1.
|
|
||||||
The basic port includes boot-up logic, interrupt driven serial
|
|
||||||
console, and system timer interrupts. That release passes the
|
|
||||||
NuttX OS test and is proven to have a valid OS implementation. A
|
|
||||||
onfiguration to support the NuttShell is also included.
|
|
||||||
|
|
||||||
arch/arm/include/stm32 and arch/arm/src/stm32
|
|
||||||
These directories contain support for the STMicro STM32 F1, F2, and
|
|
||||||
F4 families.
|
|
||||||
|
|
||||||
STATUS: The basic STM32 F1 port was released in NuttX version 0.4.12.
|
|
||||||
and has continued to develop consistently over time. It now includes
|
|
||||||
support for the F2 and F4 families and a rich offering of peripheral
|
|
||||||
drivers.
|
|
||||||
|
|
||||||
arch/arm/include/str71x and arch/arm/src/str71x
|
|
||||||
These directories provide support for the STMicro STR71x processors.
|
|
||||||
Coding is complete on the basic port (boot logic, system time, serial console),
|
|
||||||
but no testing has been performed due to some problems I am having with my
|
|
||||||
JTAG wiggler and OpenOCD on Linux.
|
|
||||||
|
|
||||||
arch/avr
|
arch/avr
|
||||||
This directory is dedicated to ports to the Atmel AVR (8-bit) and AVR32 (32-bit)
|
This directory is dedicated to ports to the Atmel AVR (8-bit) and AVR32 (32-bit)
|
||||||
MCU families. STATUS: Under development.
|
MCU families. STATUS: Under development.
|
||||||
|
|
||||||
arch/avr/include/avr and arch/avr/src/avr
|
Architecture Support
|
||||||
Common support for all 8-bit AVR MCUs
|
arch/avr/include/avr and arch/avr/src/avr
|
||||||
|
arch/avr/include/avr32 and arch/avr/src/avr32
|
||||||
|
|
||||||
arch/avr/include/atmega and arch/avr/src/atmega
|
MCU support
|
||||||
Support specifically for the AVR ATMega family (specifically only for
|
arch/avr/include/atmega and arch/avr/src/atmega
|
||||||
the ATMega128 at the moment).
|
arch/avr/include/at90usb and arch/avr/src/at90usb
|
||||||
|
arch/avr/include/at32uc3 and arch/avr/src/at32uc3
|
||||||
arch/avr/include/at90usb and arch/avr/src/at90usb
|
|
||||||
Support specifically for the AVR AT90USB646, 647, 1286, and 1287 family.
|
|
||||||
|
|
||||||
arch/avr/include/avr32 and arch/avr/src/avr32
|
|
||||||
Common support for all AVR32 MCUs
|
|
||||||
|
|
||||||
arch/avr/include/at32uc3 and arch/avr/src/at32uc3
|
|
||||||
Support specifically for the AT32UC3Bxxx family (specifically only for
|
|
||||||
the AT32UC3B0256 at the moment).
|
|
||||||
|
|
||||||
arch/hc
|
arch/hc
|
||||||
This directory is dedicated to ports to the Freescale HC family.
|
This directory is dedicated to ports to the Freescale HC family.
|
||||||
|
|
||||||
arch/arm/include/m9s12 and arch/arm/src/m9s12
|
arch/arm/include/m9s12 and arch/arm/src/m9s12
|
||||||
These directories provide support for the Freescale mc9s12x family.
|
|
||||||
STATUS: Fragments of this port were first released in nuttx-5.0 and
|
|
||||||
the port was "code-complete" as nuttx-5.18. However, the final
|
|
||||||
verification effort has been stalled because of higher priority tasks.
|
|
||||||
|
|
||||||
arch/mips
|
arch/mips
|
||||||
This directory is dedicated to ports to the MIPS family.
|
This directory is dedicated to ports to the MIPS family.
|
||||||
|
|
||||||
arch/mips/include/mips32 and arch/mips/src/mips32
|
Architecture Support
|
||||||
Common support for all MIPS32 architectures
|
arch/mips/include/mips32 and arch/mips/src/mips32
|
||||||
|
|
||||||
arch/mips/include/pic32mx and arch/mips/src/pic32mx
|
MCU support
|
||||||
Support for all MicroChip PIC32MX architectures
|
arch/mips/include/pic32mx and arch/mips/src/pic32mx
|
||||||
|
arch/mips/include/pic32mz and arch/mips/src/pic32mz
|
||||||
|
|
||||||
arch/rgmp
|
arch/rgmp
|
||||||
|
|
||||||
@@ -288,52 +223,42 @@ arch/rgmp
|
|||||||
|
|
||||||
arch/sh - SuperH and related Hitachi/Renesas microcontrollers
|
arch/sh - SuperH and related Hitachi/Renesas microcontrollers
|
||||||
|
|
||||||
arch/sh/include and arch/sh/src/common
|
Architecture Support
|
||||||
Common SuperH logic.
|
arch/sh/include and arch/sh/src/common
|
||||||
|
|
||||||
arch/sh/include/shs and arch/sh/src/sh1
|
MCU support
|
||||||
Support for the SH-1 processor.
|
arch/sh/include/m16c and arch/sh/src/m16c
|
||||||
|
arch/sh/include/sh1 and arch/sh/src/sh1
|
||||||
|
|
||||||
arch/x86 - Intel x86 architectures
|
arch/x86 - Intel x86 architectures
|
||||||
This directory holds related, 32- and 64-bit architectures from Intel.
|
This directory holds related, 32- and 64-bit architectures from Intel.
|
||||||
At present, this includes the following subdirectories:
|
At present, this includes the following subdirectories:
|
||||||
|
|
||||||
arch/x86/include and arch/x86/src/common
|
Architecture Support
|
||||||
Common x86 logic.
|
arch/x86/include and arch/x86/src/common
|
||||||
|
|
||||||
arch/x86/include/i486 and arch/x86/src/i486
|
MCU support
|
||||||
These directories hold definitions and logic appropriate for any
|
arch/x86/include/i486 and arch/x86/src/i486
|
||||||
instantiation of the 32-bit i486 architecture.
|
arch/x86/include/qemu and arch/x86/src/qemu
|
||||||
|
|
||||||
arch/x86/include/qemu and arch/x86/src/qemu
|
|
||||||
This is the implementation of NuttX on the QEMU x86 simulation.
|
|
||||||
|
|
||||||
arch/z16 - ZiLOG 16-bit processors
|
arch/z16 - ZiLOG 16-bit processors
|
||||||
This directory holds related, 16-bit architectures from ZiLOG. At
|
This directory holds related, 16-bit architectures from ZiLOG. At
|
||||||
present, this includes the following subdirectories:
|
present, this includes the following subdirectories:
|
||||||
|
|
||||||
arch/z16/include and arch/z16/src/common
|
Architecture Support
|
||||||
Common microcontroller logic.
|
arch/z16/include and arch/z16/src/common
|
||||||
|
|
||||||
arch/z16/include/z16f and arch/z16/src/z16f
|
MCU support
|
||||||
ZiLOG z16f Microcontroller.
|
arch/z16/include/z16f and arch/z16/src/z16f
|
||||||
STATUS: Released in nuttx-0.3.7. Fully functional other than issues
|
|
||||||
addressed in ${TOPDIR}/TODO.
|
|
||||||
|
|
||||||
arch/z80 - ZiLOG 8-bit microcontrollers
|
arch/z80 - ZiLOG 8-bit microcontrollers
|
||||||
This directory holds related, 8-bit architectures from ZiLOG. At
|
This directory holds related, 8-bit architectures from ZiLOG. At
|
||||||
present, this includes the following subdirectories:
|
present, this includes the following subdirectories:
|
||||||
|
|
||||||
arch/z80/include and arch/z80/src/common
|
Architecture Support
|
||||||
Common microcontroller logic.
|
arch/z80/include and arch/z80/src/common
|
||||||
|
|
||||||
arch/z80/include/z80 and arch/z80/src/z80
|
MCU support
|
||||||
Classic ZiLOG z80 Microcontroller.
|
arch/z80/include/z80 and arch/z80/src/z80
|
||||||
STATUS: Functional with no known defects. There are still several
|
arch/z80/include/z8 and arch/z80/src/z8
|
||||||
OS features that have not yet been tested (e.g., networking).
|
arch/z80/include/ez80 and arch/z80/src/ez80
|
||||||
|
|
||||||
arch/z80/include/z8 and arch/z80/src/z8
|
|
||||||
ZiLOG Z8Encore! Microcontroller
|
|
||||||
|
|
||||||
arch/z80/include/ez80 and arch/z80/src/ez80
|
|
||||||
ZiLOG ez80 Acclaim! Microcontroller
|
|
||||||
|
|||||||
+2
-2
@@ -27,7 +27,7 @@ config ARCH_CHIP_C5471
|
|||||||
bool "TMS320 C5471"
|
bool "TMS320 C5471"
|
||||||
select ARCH_ARM7TDMI
|
select ARCH_ARM7TDMI
|
||||||
select ARCH_HAVE_LOWVECTORS
|
select ARCH_HAVE_LOWVECTORS
|
||||||
select ARCH_HAVE_OTHER_UART
|
select OTHER_UART_SERIALDRIVER
|
||||||
---help---
|
---help---
|
||||||
TI TMS320 C5471, A180, or DA180 (ARM7TDMI)
|
TI TMS320 C5471, A180, or DA180 (ARM7TDMI)
|
||||||
|
|
||||||
@@ -36,7 +36,7 @@ config ARCH_CHIP_CALYPSO
|
|||||||
select ARCH_ARM7TDMI
|
select ARCH_ARM7TDMI
|
||||||
select ARCH_HAVE_HEAP2
|
select ARCH_HAVE_HEAP2
|
||||||
select ARCH_HAVE_LOWVECTORS
|
select ARCH_HAVE_LOWVECTORS
|
||||||
select ARCH_HAVE_OTHER_UART
|
select OTHER_UART_SERIALDRIVER
|
||||||
select ARCH_HAVE_POWEROFF
|
select ARCH_HAVE_POWEROFF
|
||||||
---help---
|
---help---
|
||||||
TI Calypso-based cell phones (ARM7TDMI)
|
TI Calypso-based cell phones (ARM7TDMI)
|
||||||
|
|||||||
@@ -1,7 +1,7 @@
|
|||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* arch/arm/include/lpc43xx/chip.h
|
* arch/arm/include/lpc43xx/chip.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2012-2013 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2012-2013, 2016 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
@@ -167,7 +167,7 @@
|
|||||||
# warning "Data sheet and user manual are consistement for the LPC4320"
|
# warning "Data sheet and user manual are consistement for the LPC4320"
|
||||||
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
||||||
# define LPC43_FLASH_BANKB_SIZE (0)
|
# define LPC43_FLASH_BANKB_SIZE (0)
|
||||||
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 168Kb Local SRAM*/
|
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 168Kb Local SRAM */
|
||||||
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
||||||
# define LPC43_AHBSRAM_BANK0_SIZE (16*1024) /* 32Kb AHB SRAM */
|
# define LPC43_AHBSRAM_BANK0_SIZE (16*1024) /* 32Kb AHB SRAM */
|
||||||
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
||||||
@@ -194,7 +194,7 @@
|
|||||||
# warning "Data sheet and user manual are consistement for the LPC4320"
|
# warning "Data sheet and user manual are consistement for the LPC4320"
|
||||||
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
||||||
# define LPC43_FLASH_BANKB_SIZE (0)
|
# define LPC43_FLASH_BANKB_SIZE (0)
|
||||||
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 168Kb Local SRAM*/
|
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 168Kb Local SRAM */
|
||||||
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
||||||
# define LPC43_AHBSRAM_BANK0_SIZE (16*1024) /* 32Kb AHB SRAM */
|
# define LPC43_AHBSRAM_BANK0_SIZE (16*1024) /* 32Kb AHB SRAM */
|
||||||
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
||||||
@@ -220,7 +220,7 @@
|
|||||||
#elif defined(CONFIG_ARCH_CHIP_LPC4330FBD144)
|
#elif defined(CONFIG_ARCH_CHIP_LPC4330FBD144)
|
||||||
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
||||||
# define LPC43_FLASH_BANKB_SIZE (0)
|
# define LPC43_FLASH_BANKB_SIZE (0)
|
||||||
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
|
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM */
|
||||||
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
|
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
|
||||||
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
||||||
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
||||||
@@ -246,7 +246,7 @@
|
|||||||
#elif defined(CONFIG_ARCH_CHIP_LPC4330FET100)
|
#elif defined(CONFIG_ARCH_CHIP_LPC4330FET100)
|
||||||
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
||||||
# define LPC43_FLASH_BANKB_SIZE (0)
|
# define LPC43_FLASH_BANKB_SIZE (0)
|
||||||
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
|
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM */
|
||||||
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
|
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
|
||||||
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
||||||
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
||||||
@@ -272,7 +272,7 @@
|
|||||||
#elif defined(CONFIG_ARCH_CHIP_LPC4330FET180)
|
#elif defined(CONFIG_ARCH_CHIP_LPC4330FET180)
|
||||||
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
||||||
# define LPC43_FLASH_BANKB_SIZE (0)
|
# define LPC43_FLASH_BANKB_SIZE (0)
|
||||||
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
|
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM */
|
||||||
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
|
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
|
||||||
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
||||||
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
||||||
@@ -298,7 +298,7 @@
|
|||||||
#elif defined(CONFIG_ARCH_CHIP_LPC4330FET256)
|
#elif defined(CONFIG_ARCH_CHIP_LPC4330FET256)
|
||||||
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
||||||
# define LPC43_FLASH_BANKB_SIZE (0)
|
# define LPC43_FLASH_BANKB_SIZE (0)
|
||||||
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
|
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM */
|
||||||
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
|
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
|
||||||
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
||||||
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
||||||
@@ -322,9 +322,9 @@
|
|||||||
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
||||||
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
||||||
#elif defined(CONFIG_ARCH_CHIP_LPC4337JBD144)
|
#elif defined(CONFIG_ARCH_CHIP_LPC4337JBD144)
|
||||||
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
|
# define LPC43_FLASH_BANKA_SIZE (512*1024) /* 1024Kb FLASH */
|
||||||
# define LPC43_FLASH_BANKB_SIZE (512*1025)
|
# define LPC43_FLASH_BANKB_SIZE (512*1024)
|
||||||
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
|
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
|
||||||
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
||||||
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
||||||
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
||||||
@@ -350,7 +350,7 @@
|
|||||||
#elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208)
|
#elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208)
|
||||||
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
||||||
# define LPC43_FLASH_BANKB_SIZE (0)
|
# define LPC43_FLASH_BANKB_SIZE (0)
|
||||||
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
|
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM */
|
||||||
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
|
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
|
||||||
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
||||||
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
||||||
@@ -376,7 +376,7 @@
|
|||||||
#elif defined(CONFIG_ARCH_CHIP_LPC4350FET180)
|
#elif defined(CONFIG_ARCH_CHIP_LPC4350FET180)
|
||||||
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
||||||
# define LPC43_FLASH_BANKB_SIZE (0)
|
# define LPC43_FLASH_BANKB_SIZE (0)
|
||||||
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
|
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM */
|
||||||
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
|
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
|
||||||
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
||||||
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
||||||
@@ -402,7 +402,7 @@
|
|||||||
#elif defined(CONFIG_ARCH_CHIP_LPC4350FET256)
|
#elif defined(CONFIG_ARCH_CHIP_LPC4350FET256)
|
||||||
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
||||||
# define LPC43_FLASH_BANKB_SIZE (0)
|
# define LPC43_FLASH_BANKB_SIZE (0)
|
||||||
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
|
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM */
|
||||||
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
|
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
|
||||||
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
||||||
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
||||||
@@ -426,9 +426,9 @@
|
|||||||
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
||||||
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
||||||
#elif defined(CONFIG_ARCH_CHIP_LPC4353FBD208)
|
#elif defined(CONFIG_ARCH_CHIP_LPC4353FBD208)
|
||||||
# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
|
# define LPC43_FLASH_BANKA_SIZE (256*1024) /* 512Kb FLASH */
|
||||||
# define LPC43_FLASH_BANKB_SIZE (256*1025)
|
# define LPC43_FLASH_BANKB_SIZE (256*1024)
|
||||||
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
|
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
|
||||||
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
||||||
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
||||||
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
||||||
@@ -452,9 +452,9 @@
|
|||||||
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
||||||
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
||||||
#elif defined(CONFIG_ARCH_CHIP_LPC4353FET180)
|
#elif defined(CONFIG_ARCH_CHIP_LPC4353FET180)
|
||||||
# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
|
# define LPC43_FLASH_BANKA_SIZE (256*1024) /* 512Kb FLASH */
|
||||||
# define LPC43_FLASH_BANKB_SIZE (256*1025)
|
# define LPC43_FLASH_BANKB_SIZE (256*1024)
|
||||||
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
|
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
|
||||||
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
||||||
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
||||||
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
||||||
@@ -478,9 +478,9 @@
|
|||||||
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
||||||
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
||||||
#elif defined(CONFIG_ARCH_CHIP_LPC4353FET256)
|
#elif defined(CONFIG_ARCH_CHIP_LPC4353FET256)
|
||||||
# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
|
# define LPC43_FLASH_BANKA_SIZE (256*1024) /* 512Kb FLASH */
|
||||||
# define LPC43_FLASH_BANKB_SIZE (256*1025)
|
# define LPC43_FLASH_BANKB_SIZE (256*1024)
|
||||||
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
|
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
|
||||||
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
||||||
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
||||||
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
||||||
@@ -504,9 +504,9 @@
|
|||||||
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
||||||
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
||||||
#elif defined(CONFIG_ARCH_CHIP_LPC4357FET180)
|
#elif defined(CONFIG_ARCH_CHIP_LPC4357FET180)
|
||||||
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
|
# define LPC43_FLASH_BANKA_SIZE (512*1024) /* 1024Kb FLASH */
|
||||||
# define LPC43_FLASH_BANKB_SIZE (512*1025)
|
# define LPC43_FLASH_BANKB_SIZE (512*1024)
|
||||||
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
|
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
|
||||||
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
||||||
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
||||||
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
||||||
@@ -530,9 +530,9 @@
|
|||||||
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
||||||
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
||||||
#elif defined(CONFIG_ARCH_CHIP_LPC4357FBD208)
|
#elif defined(CONFIG_ARCH_CHIP_LPC4357FBD208)
|
||||||
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
|
# define LPC43_FLASH_BANKA_SIZE (512*1024) /* 1024Kb FLASH */
|
||||||
# define LPC43_FLASH_BANKB_SIZE (512*1025)
|
# define LPC43_FLASH_BANKB_SIZE (512*1024)
|
||||||
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
|
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
|
||||||
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
||||||
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
||||||
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
||||||
@@ -556,9 +556,9 @@
|
|||||||
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
||||||
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
||||||
#elif defined(CONFIG_ARCH_CHIP_LPC4357FET256)
|
#elif defined(CONFIG_ARCH_CHIP_LPC4357FET256)
|
||||||
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
|
# define LPC43_FLASH_BANKA_SIZE (512*1024) /* 1024Kb FLASH */
|
||||||
# define LPC43_FLASH_BANKB_SIZE (512*1025)
|
# define LPC43_FLASH_BANKB_SIZE (512*1024)
|
||||||
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
|
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
|
||||||
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
||||||
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
||||||
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
||||||
@@ -632,6 +632,31 @@
|
|||||||
# define LPC43_NDAC (1) /* One 10-bit DAC */
|
# define LPC43_NDAC (1) /* One 10-bit DAC */
|
||||||
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels (per ADC)*/
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels (per ADC)*/
|
||||||
# define LPC43_NADC12 (1) /* ONne 12-bit ADC controllers (ADCHS)*/
|
# define LPC43_NADC12 (1) /* ONne 12-bit ADC controllers (ADCHS)*/
|
||||||
|
#elif defined(CONFIG_ARCH_CHIP_LPC4337JET100)
|
||||||
|
# define LPC43_FLASH_BANKA_SIZE (512*1024) /* 1024Kb FLASH */
|
||||||
|
# define LPC43_FLASH_BANKB_SIZE (512*1024)
|
||||||
|
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
|
||||||
|
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
||||||
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
||||||
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
||||||
|
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
|
||||||
|
# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
|
||||||
|
# define LPC43_NLCD (0) /* Has LCD controller */
|
||||||
|
# define LPC43_ETHERNET (1) /* One Ethernet controller */
|
||||||
|
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
|
||||||
|
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
|
||||||
|
# define LPC43_USB1_ULPI (0) /* Have USB1 (Host, Device) with ULPI I/F */
|
||||||
|
# define LPC43_MCPWM (0) /* One PWM interface */
|
||||||
|
# define LPC43_QEI (0) /* One Quadrature Encoder interface */
|
||||||
|
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
|
||||||
|
# define LPC43_NSSP (2) /* Two SSP controllers */
|
||||||
|
# define LPC43_NTIMERS (4) /* Four Timers */
|
||||||
|
# define LPC43_NI2C (2) /* Two I2C controllers */
|
||||||
|
# define LPC43_NI2S (2) /* Two I2S controllers */
|
||||||
|
# define LPC43_NCAN (2) /* Two CAN controllers */
|
||||||
|
# define LPC43_NDAC (1) /* One 10-bit DAC */
|
||||||
|
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
|
||||||
|
# define LPC43_NADC_CHANNELS (4) /* Four ADC channels */
|
||||||
#else
|
#else
|
||||||
# error "Unsupported LPC43xx chip"
|
# error "Unsupported LPC43xx chip"
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
@@ -903,6 +903,43 @@
|
|||||||
# define STM32_NRNG 0 /* No random number generator (RNG) */
|
# define STM32_NRNG 0 /* No random number generator (RNG) */
|
||||||
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
||||||
|
|
||||||
|
#elif defined(CONFIG_ARCH_CHIP_STM32F105RB)
|
||||||
|
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
|
||||||
|
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
|
||||||
|
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
|
||||||
|
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||||
|
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||||
|
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
|
||||||
|
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||||
|
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||||
|
# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
|
||||||
|
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||||
|
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
|
||||||
|
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
|
||||||
|
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
|
||||||
|
# define STM32_NFSMC 1 /* FSMC */
|
||||||
|
# define STM32_NATIM 1 /* One advanced timers TIM1 */
|
||||||
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
|
||||||
|
# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
|
||||||
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
||||||
|
# define STM32_NDMA 2 /* DMA1-2 */
|
||||||
|
# define STM32_NSPI 3 /* SPI1-3 */
|
||||||
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
||||||
|
# define STM32_NUSART 5 /* USART1-3, UART 4-5 */
|
||||||
|
# define STM32_NI2C 2 /* I2C1-2 */
|
||||||
|
# define STM32_NCAN 2 /* CAN1-2 */
|
||||||
|
# define STM32_NSDIO 0 /* No SDIO */
|
||||||
|
# define STM32_NLCD 0 /* No LCD */
|
||||||
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
||||||
|
# define STM32_NGPIO 51 /* GPIOA-E */
|
||||||
|
# define STM32_NADC 2 /* ADC1-2 */
|
||||||
|
# define STM32_NDAC 2 /* DAC1-2 */
|
||||||
|
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
||||||
|
# define STM32_NCRC 1 /* CRC */
|
||||||
|
# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */
|
||||||
|
# define STM32_NRNG 0 /* No random number generator (RNG) */
|
||||||
|
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
||||||
|
|
||||||
#elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
|
#elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
|
||||||
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
|
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
|
||||||
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
|
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
|
||||||
@@ -1568,7 +1605,7 @@
|
|||||||
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
|
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
|
||||||
# define STM32_NBTIM 0 /* No basic timers */
|
# define STM32_NBTIM 0 /* No basic timers */
|
||||||
# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/
|
# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/
|
||||||
# define STM32_NSPI 4 /* SPI1-4 */
|
# define STM32_NSPI 5 /* SPI1-5 */
|
||||||
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
||||||
# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */
|
# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */
|
||||||
# define STM32_NI2C 3 /* I2C1-3 */
|
# define STM32_NI2C 3 /* I2C1-3 */
|
||||||
@@ -1606,7 +1643,7 @@
|
|||||||
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
|
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
|
||||||
# define STM32_NBTIM 0 /* No basic timers */
|
# define STM32_NBTIM 0 /* No basic timers */
|
||||||
# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/
|
# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/
|
||||||
# define STM32_NSPI 4 /* SPI1-4 */
|
# define STM32_NSPI 5 /* SPI1-5 */
|
||||||
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
||||||
# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */
|
# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */
|
||||||
# define STM32_NI2C 3 /* I2C1-3 */
|
# define STM32_NI2C 3 /* I2C1-3 */
|
||||||
@@ -2430,7 +2467,7 @@
|
|||||||
# if defined(CONFIG_ARCH_CHIP_STM32F469A)
|
# if defined(CONFIG_ARCH_CHIP_STM32F469A)
|
||||||
# define STM32_NETHERNET 0 /* No Ethernet MAC */
|
# define STM32_NETHERNET 0 /* No Ethernet MAC */
|
||||||
# elif defined(CONFIG_ARCH_CHIP_STM32F469I) || \
|
# elif defined(CONFIG_ARCH_CHIP_STM32F469I) || \
|
||||||
# defined(CONFIG_ARCH_CHIP_STM32F469B) || \
|
defined(CONFIG_ARCH_CHIP_STM32F469B) || \
|
||||||
defined(CONFIG_ARCH_CHIP_STM32F469N)
|
defined(CONFIG_ARCH_CHIP_STM32F469N)
|
||||||
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
||||||
# endif
|
# endif
|
||||||
|
|||||||
@@ -120,7 +120,7 @@
|
|||||||
# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */
|
# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */
|
||||||
# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */
|
# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */
|
||||||
# define STM32_IRQ_UART4 (68) /* 52: USART2 global interrupt */
|
# define STM32_IRQ_UART4 (68) /* 52: USART2 global interrupt */
|
||||||
# define STM32_IRQ_UART5 (69) /* 53: USART5 global interrupt */
|
# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */
|
||||||
# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */
|
# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */
|
||||||
# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */
|
# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */
|
||||||
# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */
|
# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */
|
||||||
|
|||||||
+235
-62
@@ -1,7 +1,7 @@
|
|||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* arch/arm/include/stm32f7/chip.h
|
* arch/arm/include/stm32f7/chip.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
@@ -45,99 +45,272 @@
|
|||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
************************************************************************************/
|
************************************************************************************/
|
||||||
/* STM32F745xx, STM32F746xx, and STM32F56xx. Differences between family members:
|
/* STM32F745xx, STM32F746xx, STM32F756xx, STM32F765xx, STM32F767xx, STM32F768xx,
|
||||||
|
* STM32F769xx, STM32F777xx and STM32F779xx Differences between family members:
|
||||||
*
|
*
|
||||||
* ----------- ---------------- ----- -------- ------------ --------
|
* ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
|
||||||
* PART PACKAGE GPIOs SPI/I2S ADC CHANNELS LCD-TFT?
|
* SPI ADC LCD
|
||||||
* ----------- ---------------- ----- -------- ------------ --------
|
* PART PACKAGE GPIOs I2S CHAN TFT MIPI JPEG CAN ETH DFSDM CRYPTO FPU RAM L1
|
||||||
* STM32F745Vx LQFP100 82 4/3 16 No
|
* ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
|
||||||
* STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No
|
* STM32F745Vx LQFP100 82 4/3 16 No No No 2 Yes No No SFPU (240+16+64) 4+4
|
||||||
* STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No
|
* STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
|
||||||
* STM32F745Bx LQFP208 168 6/3 24 No
|
* STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
|
||||||
* STM32F745Nx TFBGA216 68 6/3 24 No
|
* STM32F745Bx LQFP208 168 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
|
||||||
|
* STM32F745Nx TFBGA216 68 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
|
||||||
*
|
*
|
||||||
* STM32F746Vx LQFP100 82 4/3 16 Yes
|
* STM32F746Vx LQFP100 82 4/3 16 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
|
||||||
* STM32F746Zx WLCSP143/LQFP144 114 6/3 24 Yes
|
* STM32F746Zx WLCSP143/LQFP144 114 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
|
||||||
* STM32F746Ix UFBGA176/LQFP176 140 6/3 24 Yes
|
* STM32F746Ix UFBGA176/LQFP176 140 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
|
||||||
* STM32F746Bx LQFP208 168 6/3 24 Yes
|
* STM32F746Bx LQFP208 168 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
|
||||||
* STM32F746Nx TFBGA216 168 6/3 24 Yes
|
* STM32F746Nx TFBGA216 168 6/3 24 Yes No No 2 Yes No No SFPU
|
||||||
*
|
*
|
||||||
* STM32F756Vx LQFP100 82 4/3 16 Yes
|
* STM32F756Vx LQFP100 82 4/3 16 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
|
||||||
* STM32F756Zx WLCSP143/LQFP144 114 6/3 24 Yes
|
* STM32F756Zx WLCSP143/LQFP144 114 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
|
||||||
* STM32F756Ix UFBGA176/LQFP176 140 6/3 24 Yes
|
* STM32F756Ix UFBGA176/LQFP176 140 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
|
||||||
* STM32F756Bx LQFP208 168 6/3 24 Yes
|
* STM32F756Bx LQFP208 168 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
|
||||||
* STM32F756Nx TFBGA216 168 6/3 24 Yes
|
* STM32F756Nx TFBGA216 168 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
|
||||||
* ----------- ---------------- ----- -------- ------------ --------
|
*
|
||||||
|
* STM32F765Vx LQFP100 82 4/3 16 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||||
|
* STM32F765Zx WLCSP143/LQFP144 114 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||||
|
* STM32F765Ix UFBGA176/LQFP176 140 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||||
|
* STM32F765Bx LQFP208 168 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||||
|
* STM32F765Nx TFBGA216 168 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||||
|
*
|
||||||
|
* STM32F767Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||||
|
* STM32F767Zx WLCSP143/LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||||
|
* STM32F767Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||||
|
* STM32F767Bx LQFP208 168 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||||
|
* STM32F767Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||||
|
*
|
||||||
|
* STM32F768Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes No DFPU (368+16+128) 16+16
|
||||||
|
*
|
||||||
|
* STM32F769Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||||
|
* STM32F769Zx LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||||
|
* STM32F769Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||||
|
* STM32F769Bx LQFP208 168 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||||
|
* STM32F769Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||||
|
*
|
||||||
|
* STM32F769Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes No DFPU (368+16+128) 16+16
|
||||||
|
*
|
||||||
|
* STM32F777Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
|
||||||
|
* STM32F777Zx LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
|
||||||
|
* STM32F777Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
|
||||||
|
* STM32F777Bx LQFP208 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
|
||||||
|
* STM32F777Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
|
||||||
|
*
|
||||||
|
* STM32F778Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes Yes DFPU (368+16+128) 16+16
|
||||||
|
*
|
||||||
|
* STM32F779Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
|
||||||
|
* STM32F779Bx LQFP208 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
|
||||||
|
* STM32F779Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
|
||||||
|
|
||||||
|
* STM32F779Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes Yes DFPU (368+16+128) 16+16
|
||||||
|
* ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
|
||||||
*
|
*
|
||||||
* Parts STM32F74xxE have 512Kb of FLASH
|
* Parts STM32F74xxE have 512Kb of FLASH
|
||||||
* Parts STM32F74xxG have 1024Kb of FLASH
|
* Parts STM32F74xxG have 1024Kb of FLASH
|
||||||
|
* Parts STM32F74xxI have 2048Kb of FLASH
|
||||||
|
*
|
||||||
|
* The correct FLASH size will be set CONFIG_STM32F7_FLASH_CONFIG_x or overridden
|
||||||
|
* with CONFIG_STM32F7_FLASH_OVERRIDE_x
|
||||||
*
|
*
|
||||||
* The correct FLASH size must be set with a CONFIG_STM32F7_FLASH_*KB
|
|
||||||
* selection.
|
|
||||||
*/
|
*/
|
||||||
|
#if defined(CONFIG_ARCH_CHIP_STM32F745VG) || \
|
||||||
#if defined(CONFIG_ARCH_CHIP_STM32F745) || defined(CONFIG_ARCH_CHIP_STM32F746) || \
|
defined(CONFIG_ARCH_CHIP_STM32F745VE) || \
|
||||||
defined(CONFIG_ARCH_CHIP_STM32F756)
|
defined(CONFIG_ARCH_CHIP_STM32F745IG) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F745IE) || \
|
||||||
#if defined(CONFIG_ARCH_CHIP_STM32F745)
|
defined(CONFIG_ARCH_CHIP_STM32F745ZE) || \
|
||||||
# define STM32F7_STM32F745XX 1 /* STM32F745xx family */
|
defined(CONFIG_ARCH_CHIP_STM32F745ZG) || \
|
||||||
# undef STM32F7_STM32F746XX /* Not STM32F746xx family */
|
defined(CONFIG_ARCH_CHIP_STM32F746BG) || \
|
||||||
# undef STM32F7_STM32F756XX /* Not STM32F756xx family */
|
defined(CONFIG_ARCH_CHIP_STM32F746VG) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F746VE) || \
|
||||||
# define STM32F7_NLCDTFT 0 /* No LCD-TFT */
|
defined(CONFIG_ARCH_CHIP_STM32F746BE) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F746ZG) || \
|
||||||
#elif defined(CONFIG_ARCH_CHIP_STM32F746)
|
defined(CONFIG_ARCH_CHIP_STM32F746IE) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F746NG) || \
|
||||||
# undef STM32F7_STM32F745XX /* Not STM32F745xx family */
|
defined(CONFIG_ARCH_CHIP_STM32F746NE) || \
|
||||||
# define STM32F7_STM32F746XX 1 /* STM32F746xx family */
|
defined(CONFIG_ARCH_CHIP_STM32F746ZE) || \
|
||||||
# undef STM32F7_STM32F756XX /* Not STM32F756xx family */
|
defined(CONFIG_ARCH_CHIP_STM32F746IG) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F756NG) || \
|
||||||
# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
|
defined(CONFIG_ARCH_CHIP_STM32F756BG) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F756IG) || \
|
||||||
#else /* if defined(CONFIG_ARCH_CHIP_STM32F746) */
|
defined(CONFIG_ARCH_CHIP_STM32F756VG) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F756ZG) || \
|
||||||
# undef STM32F7_STM32F745XX /* Not STM32F745xx family */
|
defined(CONFIG_ARCH_CHIP_STM32F765NI) || \
|
||||||
# undef STM32F7_STM32F746XX /* Not STM32F746xx family */
|
defined(CONFIG_ARCH_CHIP_STM32F765VI) || \
|
||||||
# define STM32F7_STM32F756XX 1 /* STM32F756xx family */
|
defined(CONFIG_ARCH_CHIP_STM32F765VG) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F765BI) || \
|
||||||
# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
|
defined(CONFIG_ARCH_CHIP_STM32F765NG) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F765ZG) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F765ZI) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F765IG) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F765BG) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F765II) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F767NG) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F767IG) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F767VG) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F767ZG) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F767NI) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F767VI) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F767BG) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F767ZI) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F767II) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F769BI) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F769II) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F769BG) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F769NI) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F769AI) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F769NG) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F769IG) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F777ZI) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F777VI) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F777NI) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F777BI) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F777II) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F778AI) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F779II) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F779NI) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F779BI) || \
|
||||||
|
defined(CONFIG_ARCH_CHIP_STM32F779AI)
|
||||||
|
#else
|
||||||
|
# error STM32 F7 chip not identified
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */
|
/* Size SRAM */
|
||||||
# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
|
|
||||||
# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM inerface */
|
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||||
# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM inerface */
|
# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */
|
||||||
|
# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
|
||||||
|
# if defined(CONFIG_ARMV7M_HAVE_DTCM)
|
||||||
|
# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */
|
||||||
|
# else
|
||||||
|
# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
|
||||||
|
# endif
|
||||||
|
# if defined(CONFIG_ARMV7M_HAVE_ITCM)
|
||||||
|
# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
|
||||||
|
# else
|
||||||
|
# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
|
||||||
|
# endif
|
||||||
|
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77X)
|
||||||
|
# define STM32F7_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */
|
||||||
|
# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
|
||||||
|
# if defined(CONFIG_ARMV7M_HAVE_DTCM)
|
||||||
|
# define STM32F7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */
|
||||||
|
# else
|
||||||
|
# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
|
||||||
|
# endif
|
||||||
|
# if defined(CONFIG_ARMV7M_HAVE_ITCM)
|
||||||
|
# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
|
||||||
|
# else
|
||||||
|
# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
|
||||||
|
# endif
|
||||||
|
#else
|
||||||
|
# error STM32 F7 chip Family not identified
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Common to all Family members */
|
||||||
|
|
||||||
# define STM32F7_NFSMC 1 /* Have FSMC memory controller */
|
|
||||||
# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
||||||
# define STM32F7_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
# define STM32F7_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
||||||
# define STM32F7_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
|
# define STM32F7_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
|
||||||
# define STM32F7_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
|
# define STM32F7_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
|
||||||
# define STM32F7_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
# define STM32F7_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
||||||
# define STM32F7_NBTIM 2 /* Two basic timers, TIM6-7 */
|
# define STM32F7_NBTIM 2 /* Two basic timers, TIM6-7 */
|
||||||
# define STM32F7_NRNG 1 /* Random number generator (RNG) */
|
|
||||||
# define STM32F7_NUART 4 /* UART 4-5 and 7-8 */
|
# define STM32F7_NUART 4 /* UART 4-5 and 7-8 */
|
||||||
# define STM32F7_NUSART 4 /* USART1-3 and 6 */
|
# define STM32F7_NUSART 4 /* USART1-3 and 6 */
|
||||||
# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */
|
|
||||||
# define STM32F7_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */
|
# define STM32F7_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */
|
||||||
# define STM32F7_NI2C 4 /* I2C1-4 */
|
# define STM32F7_NI2C 4 /* I2C1-4 */
|
||||||
# define STM32F7_NUSBOTGFS 1 /* USB OTG FS */
|
# define STM32F7_NUSBOTGFS 1 /* USB OTG FS */
|
||||||
# define STM32F7_NUSBOTGHS 1 /* USB OTG HS */
|
# define STM32F7_NUSBOTGHS 1 /* USB OTG HS */
|
||||||
# define STM32F7_NCAN 2 /* CAN1-2 */
|
|
||||||
# define STM32F7_NSAI 2 /* SAI1-2 */
|
# define STM32F7_NSAI 2 /* SAI1-2 */
|
||||||
# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */
|
# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */
|
||||||
# define STM32F7_NSDMMC 1 /* SDMMC interface */
|
|
||||||
# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
||||||
# define STM32F7_NDMA 2 /* DMA1-2 */
|
# define STM32F7_NDMA 2 /* DMA1-2 */
|
||||||
# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */
|
|
||||||
# define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */
|
# define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */
|
||||||
# define STM32F7_NADC 3 /* 12-bit ADC1-3, 24 channels *except V series) */
|
# define STM32F7_NADC 3 /* 12-bit ADC1-3, 24 channels *except V series) */
|
||||||
# define STM32F7_NDAC 2 /* 12-bit DAC1-2 */
|
# define STM32F7_NDAC 2 /* 12-bit DAC1-2 */
|
||||||
# define STM32F7_NCAPSENSE 0 /* No capacitive sensing channels */
|
# define STM32F7_NCAPSENSE 0 /* No capacitive sensing channels */
|
||||||
# define STM32F7_NCRC 1 /* CRC */
|
# define STM32F7_NCRC 1 /* CRC */
|
||||||
|
|
||||||
|
/* TBD FPU Configuration */
|
||||||
|
|
||||||
|
#if defined(CONFIG_ARCH_HAVE_FPU)
|
||||||
#else
|
#else
|
||||||
# error STM32 F7 chip not identified
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_ARCH_HAVE_DPFPU)
|
||||||
|
#else
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Diversification based on Family and package */
|
||||||
|
|
||||||
|
#if defined(CONFIG_STM32F7_HAVE_FSMC)
|
||||||
|
# define STM32F7_NFSMC 1 /* Have FSMC memory controller */
|
||||||
|
#else
|
||||||
|
# define STM32F7_NFSMC 0 /* No FSMC memory controller */
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_STM32F7_HAVE_ETHRNET)
|
||||||
|
# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */
|
||||||
|
#else
|
||||||
|
# define STM32F7_NETHERNET 0 /* No 100/100 Ethernet MAC */
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_STM32F7_HAVE_RNG)
|
||||||
|
# define STM32F7_NRNG 1 /* Random number generator (RNG) */
|
||||||
|
#else
|
||||||
|
# define STM32F7_NRNG 0 /* No Random number generator (RNG) */
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6)
|
||||||
|
# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */
|
||||||
|
#else
|
||||||
|
# define STM32F7_NSPI 4 /* SPI1-4 V series */
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_STM32F7_HAVE_SDMMC2)
|
||||||
|
# define STM32F7_NSDMMC 2 /* 2 SDMMC interfaces */
|
||||||
|
#else
|
||||||
|
# define STM32F7_NSDMMC 1 /* 1 SDMMC interface */
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_STM32F7_HAVE_CAN3)
|
||||||
|
# define STM32F7_NCAN 3 /* CAN1-3 */
|
||||||
|
#else
|
||||||
|
# define STM32F7_NCAN 2 /* CAN1-2 */
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_STM32F7_HAVE_DCMI)
|
||||||
|
# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */
|
||||||
|
#else
|
||||||
|
# define STM32F7_NDCMI 0 /* No Digital camera interface (DCMI) */
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_STM32F7_HAVE_DSIHOST)
|
||||||
|
# define STM32F7_NDSIHOST 1 /* Have MIPI DSI Host */
|
||||||
|
#else
|
||||||
|
# define STM32F7_NDSIHOST 0 /* No MIPI DSI Host */
|
||||||
|
#endif
|
||||||
|
#if defined (CONFIG_STM32F7_HAVE_LTDC)
|
||||||
|
# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
|
||||||
|
#else
|
||||||
|
# define STM32F7_NLCDTFT 0 /* No LCD-TFT */
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_STM32F7_HAVE_DMA2D)
|
||||||
|
# define STM32F7_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */
|
||||||
|
#else
|
||||||
|
# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_STM32F7_HAVE_JPEG)
|
||||||
|
#define STM32F7_NJPEG 1 /* One JPEG Converter */
|
||||||
|
#else
|
||||||
|
#define STM32F7_NJPEG 0 /* No JPEG Converter */
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_STM32F7_HAVE_CRYP)
|
||||||
|
#define STM32F7_NCRYP 1 /* One CRYP engine */
|
||||||
|
#else
|
||||||
|
#define STM32F7_NCRYP 0 /* No CRYP engine */
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_STM32F7_HAVE_HASH)
|
||||||
|
#define STM32F7_NHASH 1 /* One HASH engine */
|
||||||
|
#else
|
||||||
|
#define STM32F7_NHASH 0 /* No HASH engine */
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_STM32F7_HAVE_DFSDM)
|
||||||
|
#define STM32F7_NDFSDM 4 /* One set of 4 Digital filters */
|
||||||
|
#else
|
||||||
|
#define STM32F7_NDFSDM 0 /* No Digital filters */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* NVIC priority levels *************************************************************/
|
/* NVIC priority levels *************************************************************/
|
||||||
|
|||||||
@@ -78,6 +78,8 @@
|
|||||||
|
|
||||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||||
# include <arch/stm32f7/stm32f74xx75xx_irq.h>
|
# include <arch/stm32f7/stm32f74xx75xx_irq.h>
|
||||||
|
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||||
|
# include <arch/stm32f7/stm32f76xx77xx_irq.h>
|
||||||
#else
|
#else
|
||||||
# error "Unsupported STM32 F7 chip"
|
# error "Unsupported STM32 F7 chip"
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
@@ -0,0 +1,215 @@
|
|||||||
|
/****************************************************************************************************
|
||||||
|
* arch/arm/include/stm32f7/stm32f76xx77xx_irq.h.h
|
||||||
|
*
|
||||||
|
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||||
|
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||||
|
* David Sidrane <david_s5@nscdg.com>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||||
|
* used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||||
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||||
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
****************************************************************************************************/
|
||||||
|
|
||||||
|
/* This file should never be included directed but, rather, only indirectly through arch/irq.h */
|
||||||
|
|
||||||
|
#ifndef __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H
|
||||||
|
#define __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H
|
||||||
|
|
||||||
|
/****************************************************************************************************
|
||||||
|
* Included Files
|
||||||
|
****************************************************************************************************/
|
||||||
|
|
||||||
|
#include <nuttx/config.h>
|
||||||
|
|
||||||
|
/****************************************************************************************************
|
||||||
|
* Pre-processor Definitions
|
||||||
|
****************************************************************************************************/
|
||||||
|
|
||||||
|
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in the
|
||||||
|
* NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables.
|
||||||
|
*
|
||||||
|
* Processor Exceptions (vectors 0-15). These common definitions can be found in the file
|
||||||
|
* nuttx/arch/arm/include/stm32f7/irq.h which includes this file
|
||||||
|
*
|
||||||
|
* External interrupts (vectors >= 16)
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
|
||||||
|
#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
|
||||||
|
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
|
||||||
|
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
|
||||||
|
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
|
||||||
|
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
|
||||||
|
#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
|
||||||
|
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
|
||||||
|
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
|
||||||
|
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
|
||||||
|
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
|
||||||
|
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
|
||||||
|
#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
|
||||||
|
#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
|
||||||
|
#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
|
||||||
|
#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
|
||||||
|
#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
|
||||||
|
#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
|
||||||
|
#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
|
||||||
|
#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
|
||||||
|
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
|
||||||
|
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
|
||||||
|
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
|
||||||
|
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
|
||||||
|
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
|
||||||
|
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
|
||||||
|
#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
|
||||||
|
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
|
||||||
|
#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
|
||||||
|
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||||
|
#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
|
||||||
|
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
|
||||||
|
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
|
||||||
|
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
|
||||||
|
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
|
||||||
|
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
|
||||||
|
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
|
||||||
|
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
|
||||||
|
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
|
||||||
|
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
|
||||||
|
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
|
||||||
|
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
|
||||||
|
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
|
||||||
|
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
|
||||||
|
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
|
||||||
|
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
|
||||||
|
#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
|
||||||
|
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
|
||||||
|
#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
|
||||||
|
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
|
||||||
|
#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
|
||||||
|
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||||
|
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
|
||||||
|
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
|
||||||
|
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
|
||||||
|
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */
|
||||||
|
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */
|
||||||
|
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
|
||||||
|
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
|
||||||
|
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
|
||||||
|
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
|
||||||
|
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
|
||||||
|
#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||||
|
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
|
||||||
|
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
|
||||||
|
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
|
||||||
|
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
|
||||||
|
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
|
||||||
|
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
|
||||||
|
#define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
|
||||||
|
#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
|
||||||
|
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
|
||||||
|
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
|
||||||
|
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
|
||||||
|
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
|
||||||
|
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
|
||||||
|
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
|
||||||
|
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
|
||||||
|
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
|
||||||
|
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
|
||||||
|
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
|
||||||
|
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
|
||||||
|
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
|
||||||
|
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
|
||||||
|
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
|
||||||
|
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
|
||||||
|
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
|
||||||
|
#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */
|
||||||
|
#define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
|
||||||
|
#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
|
||||||
|
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
|
||||||
|
#define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 global interrupt */
|
||||||
|
#define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 global interrupt */
|
||||||
|
#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */
|
||||||
|
#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 global interrupt */
|
||||||
|
#define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 global interrupt */
|
||||||
|
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 global interrupt */
|
||||||
|
#define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LCD-TFT global interrupt */
|
||||||
|
#define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LCD-TFT global Error interrupt */
|
||||||
|
#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D global interrupt */
|
||||||
|
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 global interrupt */
|
||||||
|
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI global interrupt */
|
||||||
|
#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST+93) /* 93: LP Timer1 global interrupt */
|
||||||
|
#define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+94) /* 94: HDMI-CEC global interrupt */
|
||||||
|
#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST+95) /* 95: I2C4 event interrupt */
|
||||||
|
#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST+96) /* 96: I2C4 Error interrupt */
|
||||||
|
#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+97) /* 97: SPDIFRX global interrupt */
|
||||||
|
#define STM32_IRQ_DSIHOST (STM32_IRQ_FIRST+98) /* 98: DSI host global interrupt */
|
||||||
|
#define STM32_IRQ_DFSDM1FLT0 (STM32_IRQ_FIRST+99) /* 99: DFSDM1 Filter 0 global interrupt */
|
||||||
|
#define STM32_IRQ_DFSDM1FLT1 (STM32_IRQ_FIRST+100) /* 100: DFSDM1 Filter 1 global interrupt */
|
||||||
|
#define STM32_IRQ_DFSDM1FLT2 (STM32_IRQ_FIRST+101) /* 101: DFSDM1 Filter 2 global interrupt */
|
||||||
|
#define STM32_IRQ_DFSDM1FLT3 (STM32_IRQ_FIRST+102) /* 102: DFSDM1 Filter 3 global interrupt */
|
||||||
|
#define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST+103) /* 103: SDMMC2 global interrupt */
|
||||||
|
#define STM32_IRQ_CAN3TX (STM32_IRQ_FIRST+104) /* 104: CAN3 TX interrupt */
|
||||||
|
#define STM32_IRQ_CAN3RX0 (STM32_IRQ_FIRST+105) /* 105: CAN3 RX0 interrupt */
|
||||||
|
#define STM32_IRQ_CAN3RX1 (STM32_IRQ_FIRST+106) /* 106: CAN3 RX1 interrupt */
|
||||||
|
#define STM32_IRQ_CAN3SCE (STM32_IRQ_FIRST+107) /* 107: CAN3 SCE interrupt */
|
||||||
|
#define STM32_IRQ_JPEG (STM32_IRQ_FIRST+108) /* 108: JPEG global interrupt */
|
||||||
|
#define STM32_IRQ_MDIOS (STM32_IRQ_FIRST+109) /* 109: MDIO slave global interrupt */
|
||||||
|
|
||||||
|
#define NR_INTERRUPTS 110
|
||||||
|
#define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS)
|
||||||
|
|
||||||
|
/* EXTI interrupts (Do not use IRQ numbers) */
|
||||||
|
|
||||||
|
#define NR_IRQS NR_VECTORS
|
||||||
|
|
||||||
|
/****************************************************************************************************
|
||||||
|
* Public Types
|
||||||
|
****************************************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************************************
|
||||||
|
* Public Data
|
||||||
|
****************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ASSEMBLY__
|
||||||
|
#ifdef __cplusplus
|
||||||
|
#define EXTERN extern "C"
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#else
|
||||||
|
#define EXTERN extern
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/****************************************************************************************************
|
||||||
|
* Public Functions
|
||||||
|
****************************************************************************************************/
|
||||||
|
|
||||||
|
#undef EXTERN
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H */
|
||||||
@@ -21,49 +21,49 @@ menu "Allwinner A1X Peripheral Support"
|
|||||||
config A1X_UART0
|
config A1X_UART0
|
||||||
bool "UART 0"
|
bool "UART 0"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART0
|
select UART0_SERIALDRIVER
|
||||||
select ARCH_HAVE_SERIAL_TERMIOS
|
select ARCH_HAVE_SERIAL_TERMIOS
|
||||||
|
|
||||||
config A1X_UART1
|
config A1X_UART1
|
||||||
bool "UART 1"
|
bool "UART 1"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART1
|
select UART1_SERIALDRIVER
|
||||||
select ARCH_HAVE_SERIAL_TERMIOS
|
select ARCH_HAVE_SERIAL_TERMIOS
|
||||||
|
|
||||||
config A1X_UART2
|
config A1X_UART2
|
||||||
bool "UART 2"
|
bool "UART 2"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART2
|
select UART2_SERIALDRIVER
|
||||||
select ARCH_HAVE_SERIAL_TERMIOS
|
select ARCH_HAVE_SERIAL_TERMIOS
|
||||||
|
|
||||||
config A1X_UART3
|
config A1X_UART3
|
||||||
bool "UART 3"
|
bool "UART 3"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART3
|
select UART3_SERIALDRIVER
|
||||||
select ARCH_HAVE_SERIAL_TERMIOS
|
select ARCH_HAVE_SERIAL_TERMIOS
|
||||||
|
|
||||||
config A1X_UART4
|
config A1X_UART4
|
||||||
bool "UART 4"
|
bool "UART 4"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART4
|
select UART4_SERIALDRIVER
|
||||||
select ARCH_HAVE_SERIAL_TERMIOS
|
select ARCH_HAVE_SERIAL_TERMIOS
|
||||||
|
|
||||||
config A1X_UART5
|
config A1X_UART5
|
||||||
bool "UART 5"
|
bool "UART 5"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART5
|
select UART5_SERIALDRIVER
|
||||||
select ARCH_HAVE_SERIAL_TERMIOS
|
select ARCH_HAVE_SERIAL_TERMIOS
|
||||||
|
|
||||||
config A1X_UART6
|
config A1X_UART6
|
||||||
bool "UART 6"
|
bool "UART 6"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART6
|
select UART6_SERIALDRIVER
|
||||||
select ARCH_HAVE_SERIAL_TERMIOS
|
select ARCH_HAVE_SERIAL_TERMIOS
|
||||||
|
|
||||||
config A1X_UART7
|
config A1X_UART7
|
||||||
bool "UART 7"
|
bool "UART 7"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART7
|
select UART7_SERIALDRIVER
|
||||||
select ARCH_HAVE_SERIAL_TERMIOS
|
select ARCH_HAVE_SERIAL_TERMIOS
|
||||||
|
|
||||||
config A1X_IR0
|
config A1X_IR0
|
||||||
|
|||||||
@@ -334,7 +334,13 @@ static void up_dumpstate(void)
|
|||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Then dump the registers (if available) */
|
#ifdef CONFIG_SMP
|
||||||
|
/* Show the CPU number */
|
||||||
|
|
||||||
|
lldbg("CPU%d:\n", up_cpu_index());
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Then dump the CPU registers (if available) */
|
||||||
|
|
||||||
up_registerdump();
|
up_registerdump();
|
||||||
|
|
||||||
|
|||||||
@@ -51,6 +51,37 @@
|
|||||||
|
|
||||||
#ifdef CONFIG_SMP
|
#ifdef CONFIG_SMP
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Private Functions
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Name: arm_registerdump
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
#if 0 /* Was useful in solving some startup problems */
|
||||||
|
static inline void arm_registerdump(FAR struct tcb_s *tcb)
|
||||||
|
{
|
||||||
|
int regndx;
|
||||||
|
|
||||||
|
lldbg("CPU%d:\n", up_cpu_index());
|
||||||
|
|
||||||
|
/* Dump the startup registers */
|
||||||
|
|
||||||
|
for (regndx = REG_R0; regndx <= REG_R15; regndx += 8)
|
||||||
|
{
|
||||||
|
uint32_t *ptr = (uint32_t *)&tcb->xcp.regs[regndx];
|
||||||
|
lldbg("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
|
||||||
|
regndx, ptr[0], ptr[1], ptr[2], ptr[3],
|
||||||
|
ptr[4], ptr[5], ptr[6], ptr[7]);
|
||||||
|
}
|
||||||
|
|
||||||
|
lldbg("CPSR: %08x\n", tcb->xcp.regs[REG_CPSR]);
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
# define arm_registerdump(tcb)
|
||||||
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -75,15 +106,17 @@ int arm_start_handler(int irq, FAR void *context)
|
|||||||
{
|
{
|
||||||
FAR struct tcb_s *tcb;
|
FAR struct tcb_s *tcb;
|
||||||
|
|
||||||
/* Invalidate CPUn L1 so that is will be reloaded from coherent L2. */
|
sllvdbg("CPU%d Started\n", up_cpu_index());
|
||||||
|
|
||||||
cp15_invalidate_dcache_all();
|
|
||||||
|
|
||||||
/* Reset scheduler parameters */
|
/* Reset scheduler parameters */
|
||||||
|
|
||||||
tcb = this_task();
|
tcb = this_task();
|
||||||
sched_resume_scheduler(tcb);
|
sched_resume_scheduler(tcb);
|
||||||
|
|
||||||
|
/* Dump registers so that we can see what is going to happen on return */
|
||||||
|
|
||||||
|
arm_registerdump(tcb);
|
||||||
|
|
||||||
/* Then switch contexts. This instantiates the exception context of the
|
/* Then switch contexts. This instantiates the exception context of the
|
||||||
* tcb at the head of the assigned task list. In this case, this should
|
* tcb at the head of the assigned task list. In this case, this should
|
||||||
* be the CPUs NULL task.
|
* be the CPUs NULL task.
|
||||||
@@ -122,6 +155,8 @@ int arm_start_handler(int irq, FAR void *context)
|
|||||||
|
|
||||||
int up_cpu_start(int cpu)
|
int up_cpu_start(int cpu)
|
||||||
{
|
{
|
||||||
|
sllvdbg("Starting CPU%d\n", cpu);
|
||||||
|
|
||||||
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
|
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
|
||||||
|
|
||||||
/* Make the content of CPU0 L1 cache has been written to coherent L2 */
|
/* Make the content of CPU0 L1 cache has been written to coherent L2 */
|
||||||
|
|||||||
@@ -331,9 +331,9 @@ struct c5471_driver_s
|
|||||||
uint32_t c_rxdropped; /* Packets dropped because of size */
|
uint32_t c_rxdropped; /* Packets dropped because of size */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* This holds the information visible to uIP/NuttX */
|
/* This holds the information visible to the NuttX network */
|
||||||
|
|
||||||
struct net_driver_s c_dev; /* Interface understood by uIP */
|
struct net_driver_s c_dev; /* Interface understood by the network */
|
||||||
};
|
};
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
@@ -960,7 +960,7 @@ static int c5471_transmit(struct c5471_driver_s *c5471)
|
|||||||
* Function: c5471_txpoll
|
* Function: c5471_txpoll
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* The transmitter is available, check if uIP has any outgoing packets ready
|
* The transmitter is available, check if the network has any outgoing packets ready
|
||||||
* to send. This is a callback from devif_poll(). devif_poll() may be called:
|
* to send. This is a callback from devif_poll(). devif_poll() may be called:
|
||||||
*
|
*
|
||||||
* 1. When the preceding TX packet send is complete,
|
* 1. When the preceding TX packet send is complete,
|
||||||
@@ -1162,7 +1162,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
|
|||||||
int j = 0;
|
int j = 0;
|
||||||
|
|
||||||
/* Walk the newly received packet contained within the EIM and transfer
|
/* Walk the newly received packet contained within the EIM and transfer
|
||||||
* its contents to the uIP buffer. This frees up the memory contained within
|
* its contents to the network buffer. This frees up the memory contained within
|
||||||
* the EIM for additional packets that might be received later from the network.
|
* the EIM for additional packets that might be received later from the network.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
@@ -1185,7 +1185,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
|
|||||||
framelen = (getreg32(c5471->c_txcpudesc) & EIM_TXDESC_BYTEMASK);
|
framelen = (getreg32(c5471->c_txcpudesc) & EIM_TXDESC_BYTEMASK);
|
||||||
packetlen += framelen;
|
packetlen += framelen;
|
||||||
|
|
||||||
/* Check if the received packet will fit within the uIP packet buffer */
|
/* Check if the received packet will fit within the network packet buffer */
|
||||||
|
|
||||||
if (packetlen < (CONFIG_NET_ETH_MTU + 4))
|
if (packetlen < (CONFIG_NET_ETH_MTU + 4))
|
||||||
{
|
{
|
||||||
@@ -1234,7 +1234,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
|
|||||||
c5471_inctxcpu(c5471);
|
c5471_inctxcpu(c5471);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Adjust the packet length to remove the CRC bytes that uIP doesn't care about. */
|
/* Adjust the packet length to remove the CRC bytes that the network doesn't care about. */
|
||||||
|
|
||||||
packetlen -= 4;
|
packetlen -= 4;
|
||||||
|
|
||||||
@@ -1244,8 +1244,8 @@ static void c5471_receive(struct c5471_driver_s *c5471)
|
|||||||
c5471->c_rxpackets++;
|
c5471->c_rxpackets++;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* If we successfully transferred the data into the uIP buffer, then pass it on
|
/* If we successfully transferred the data into the network buffer, then pass it on
|
||||||
* to uIP for processing.
|
* to the network for processing.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
if (packetlen > 0 && packetlen < CONFIG_NET_ETH_MTU)
|
if (packetlen > 0 && packetlen < CONFIG_NET_ETH_MTU)
|
||||||
@@ -1496,7 +1496,7 @@ static void c5471_txdone(struct c5471_driver_s *c5471)
|
|||||||
|
|
||||||
wd_cancel(c5471->c_txtimeout);
|
wd_cancel(c5471->c_txtimeout);
|
||||||
|
|
||||||
/* Then poll uIP for new XMIT data */
|
/* Then poll the network for new XMIT data */
|
||||||
|
|
||||||
(void)devif_poll(&c5471->c_dev, c5471_txpoll);
|
(void)devif_poll(&c5471->c_dev, c5471_txpoll);
|
||||||
}
|
}
|
||||||
@@ -1615,7 +1615,7 @@ static void c5471_txtimeout(int argc, uint32_t arg, ...)
|
|||||||
c5471_ifdown(&c5471->c_dev);
|
c5471_ifdown(&c5471->c_dev);
|
||||||
c5471_ifup(&c5471->c_dev);
|
c5471_ifup(&c5471->c_dev);
|
||||||
|
|
||||||
/* Then poll uIP for new XMIT data */
|
/* Then poll the network for new XMIT data */
|
||||||
|
|
||||||
(void)devif_poll(&c5471->c_dev, c5471_txpoll);
|
(void)devif_poll(&c5471->c_dev, c5471_txpoll);
|
||||||
}
|
}
|
||||||
@@ -1647,7 +1647,7 @@ static void c5471_polltimer(int argc, uint32_t arg, ...)
|
|||||||
|
|
||||||
if ((EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) == 0)
|
if ((EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) == 0)
|
||||||
{
|
{
|
||||||
/* If so, update TCP timing states and poll uIP for new XMIT data */
|
/* If so, update TCP timing states and poll the network for new XMIT data */
|
||||||
|
|
||||||
(void)devif_timer(&c5471->c_dev, c5471_txpoll);
|
(void)devif_timer(&c5471->c_dev, c5471_txpoll);
|
||||||
}
|
}
|
||||||
@@ -1811,7 +1811,7 @@ static int c5471_txavail(struct net_driver_s *dev)
|
|||||||
|
|
||||||
if ((EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) == 0)
|
if ((EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) == 0)
|
||||||
{
|
{
|
||||||
/* If so, then poll uIP for new XMIT data */
|
/* If so, then poll the network for new XMIT data */
|
||||||
|
|
||||||
(void)devif_poll(&c5471->c_dev, c5471_txpoll);
|
(void)devif_poll(&c5471->c_dev, c5471_txpoll);
|
||||||
}
|
}
|
||||||
|
|||||||
@@ -220,7 +220,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
|
|||||||
if (tcb->stack_alloc_ptr)
|
if (tcb->stack_alloc_ptr)
|
||||||
{
|
{
|
||||||
#if defined(CONFIG_TLS) && defined(CONFIG_STACK_COLORATION)
|
#if defined(CONFIG_TLS) && defined(CONFIG_STACK_COLORATION)
|
||||||
uinptr_t stack_base;
|
uintptr_t stack_base;
|
||||||
#endif
|
#endif
|
||||||
size_t top_of_stack;
|
size_t top_of_stack;
|
||||||
size_t size_of_stack;
|
size_t size_of_stack;
|
||||||
@@ -264,7 +264,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
|
|||||||
* water marks.
|
* water marks.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
stackbase = (uintptr_t)tcb->stack_alloc_ptr + sizeof(struct tls_info_s);
|
stack_base = (uintptr_t)tcb->stack_alloc_ptr + sizeof(struct tls_info_s);
|
||||||
stack_size = tcb->adj_stack_size - sizeof(struct tls_info_s);
|
stack_size = tcb->adj_stack_size - sizeof(struct tls_info_s);
|
||||||
up_stack_color((FAR void *)stack_base, stack_size);
|
up_stack_color((FAR void *)stack_base, stack_size);
|
||||||
|
|
||||||
|
|||||||
@@ -174,7 +174,13 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
|
|||||||
* value that we can use later to test for high water marks.
|
* value that we can use later to test for high water marks.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
# warning Missing logic
|
#ifdef CONFIG_TLS
|
||||||
|
up_stack_color(
|
||||||
|
(FAR void *)((uintptr_t)tcb->stack_alloc_ptr + sizeof(struct tls_info_s)),
|
||||||
|
tcb->adj_stack_size - sizeof(struct tls_info_s));
|
||||||
|
#else
|
||||||
|
up_stack_color(tcb->stack_alloc_ptr, tcb->adj_stack_size);
|
||||||
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
return OK;
|
return OK;
|
||||||
|
|||||||
@@ -11,12 +11,12 @@ menu "DM320 Peripheral Selections"
|
|||||||
config DM320_UART0
|
config DM320_UART0
|
||||||
bool
|
bool
|
||||||
default y
|
default y
|
||||||
select ARCH_HAVE_UART0
|
select UART0_SERIALDRIVER
|
||||||
|
|
||||||
config DM320_UART1
|
config DM320_UART1
|
||||||
bool
|
bool
|
||||||
default y
|
default y
|
||||||
select ARCH_HAVE_UART1
|
select UART1_SERIALDRIVER
|
||||||
|
|
||||||
endmenu # DM320 Peripheral Selections
|
endmenu # DM320 Peripheral Selections
|
||||||
endif # ARCH_CHIP_DM320
|
endif # ARCH_CHIP_DM320
|
||||||
|
|||||||
@@ -157,45 +157,42 @@ config EFM32_BITBAND
|
|||||||
config EFM32_USART0
|
config EFM32_USART0
|
||||||
bool "USART0"
|
bool "USART0"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_USART0
|
|
||||||
select ARCH_HAVE_SERIAL_TERMIOS
|
select ARCH_HAVE_SERIAL_TERMIOS
|
||||||
|
|
||||||
config EFM32_USART1
|
config EFM32_USART1
|
||||||
bool "USART1"
|
bool "USART1"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_USART1
|
|
||||||
select ARCH_HAVE_SERIAL_TERMIOS
|
select ARCH_HAVE_SERIAL_TERMIOS
|
||||||
|
|
||||||
config EFM32_USART2
|
config EFM32_USART2
|
||||||
bool "USART2"
|
bool "USART2"
|
||||||
default n
|
default n
|
||||||
depends on EFM32_HAVE_USART2
|
depends on EFM32_HAVE_USART2
|
||||||
select ARCH_HAVE_USART2
|
|
||||||
select ARCH_HAVE_SERIAL_TERMIOS
|
select ARCH_HAVE_SERIAL_TERMIOS
|
||||||
|
|
||||||
config EFM32_UART0
|
config EFM32_UART0
|
||||||
bool "UART0"
|
bool "UART0"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART0
|
select UART0_SERIALDRIVER
|
||||||
select EFM32_UART
|
select EFM32_UART
|
||||||
|
|
||||||
config EFM32_UART1
|
config EFM32_UART1
|
||||||
bool "UART1"
|
bool "UART1"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART1
|
select UART1_SERIALDRIVER
|
||||||
select EFM32_UART
|
select EFM32_UART
|
||||||
|
|
||||||
config EFM32_LEUART0
|
config EFM32_LEUART0
|
||||||
bool "Low energy UART0"
|
bool "Low energy UART0"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_OTHER_UART
|
select OTHER_UART_SERIALDRIVER
|
||||||
select EFM32_LEUART
|
select EFM32_LEUART
|
||||||
|
|
||||||
config EFM32_LEUART1
|
config EFM32_LEUART1
|
||||||
bool "Low energy UART1"
|
bool "Low energy UART1"
|
||||||
default n
|
default n
|
||||||
depends on EFM32_HAVE_LEUART1
|
depends on EFM32_HAVE_LEUART1
|
||||||
select ARCH_HAVE_OTHER_UART
|
select OTHER_UART_SERIALDRIVER
|
||||||
select EFM32_LEUART
|
select EFM32_LEUART
|
||||||
|
|
||||||
config EFM32_OTGFS
|
config EFM32_OTGFS
|
||||||
@@ -261,7 +258,7 @@ choice
|
|||||||
|
|
||||||
config EFM32_USART0_ISUART
|
config EFM32_USART0_ISUART
|
||||||
bool "USART0 is a UART"
|
bool "USART0 is a UART"
|
||||||
select USART0_ISUART
|
select USART0_SERIALDRIVER
|
||||||
select EFM32_USART_ISUART
|
select EFM32_USART_ISUART
|
||||||
|
|
||||||
config EFM32_USART0_ISSPI
|
config EFM32_USART0_ISSPI
|
||||||
@@ -277,7 +274,7 @@ choice
|
|||||||
|
|
||||||
config EFM32_USART1_ISUART
|
config EFM32_USART1_ISUART
|
||||||
bool "USART1 is a UART"
|
bool "USART1 is a UART"
|
||||||
select USART1_ISUART
|
select USART1_SERIALDRIVER
|
||||||
select EFM32_USART_ISUART
|
select EFM32_USART_ISUART
|
||||||
|
|
||||||
config EFM32_USART1_ISSPI
|
config EFM32_USART1_ISSPI
|
||||||
@@ -293,7 +290,7 @@ choice
|
|||||||
|
|
||||||
config EFM32_USART2_ISUART
|
config EFM32_USART2_ISUART
|
||||||
bool "USART2 is a UART"
|
bool "USART2 is a UART"
|
||||||
select USART2_ISUART
|
select USART2_SERIALDRIVER
|
||||||
select EFM32_USART_ISUART
|
select EFM32_USART_ISUART
|
||||||
|
|
||||||
config EFM32_USART2_ISSPI
|
config EFM32_USART2_ISSPI
|
||||||
|
|||||||
@@ -2,7 +2,9 @@
|
|||||||
* arch/arm/src/efm32/efm32_adc.c
|
* arch/arm/src/efm32/efm32_adc.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2014 Bouteville Pierre-Noel. All rights reserved.
|
* Copyright (C) 2014 Bouteville Pierre-Noel. All rights reserved.
|
||||||
|
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||||
* Authors: Bouteville Pierre-Noel <pnb990@gmail.com>
|
* Authors: Bouteville Pierre-Noel <pnb990@gmail.com>
|
||||||
|
* Gregory Nutt <gnutt@nuttx.org>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* modification, are permitted provided that the following conditions
|
* modification, are permitted provided that the following conditions
|
||||||
@@ -63,9 +65,9 @@
|
|||||||
#include "efm32.h"
|
#include "efm32.h"
|
||||||
#include "efm32_adc.h"
|
#include "efm32_adc.h"
|
||||||
|
|
||||||
/* ADC "upper half" support must be enabled */
|
/* ADC "lower half" support must be enabled */
|
||||||
|
|
||||||
#ifdef CONFIG_ADC
|
#ifdef CONFIG_EFM32_ADC
|
||||||
|
|
||||||
/* Some ADC peripheral must be enabled */
|
/* Some ADC peripheral must be enabled */
|
||||||
|
|
||||||
@@ -100,6 +102,7 @@
|
|||||||
|
|
||||||
struct efm32_dev_s
|
struct efm32_dev_s
|
||||||
{
|
{
|
||||||
|
FAR const struct adc_callback_s *cb;
|
||||||
uint8_t irq; /* Interrupt generated by this ADC block */
|
uint8_t irq; /* Interrupt generated by this ADC block */
|
||||||
uint8_t nchannels; /* Number of channels */
|
uint8_t nchannels; /* Number of channels */
|
||||||
uint8_t current; /* Current ADC channel being converted */
|
uint8_t current; /* Current ADC channel being converted */
|
||||||
@@ -124,6 +127,8 @@ static int adc_interrupt(FAR struct adc_dev_s *dev);
|
|||||||
|
|
||||||
/* ADC Driver Methods */
|
/* ADC Driver Methods */
|
||||||
|
|
||||||
|
static int adc_bind(FAR struct adc_dev_s *dev,
|
||||||
|
FAR const struct adc_callback_s *callback);
|
||||||
static void adc_reset(FAR struct adc_dev_s *dev);
|
static void adc_reset(FAR struct adc_dev_s *dev);
|
||||||
static int adc_setup(FAR struct adc_dev_s *dev);
|
static int adc_setup(FAR struct adc_dev_s *dev);
|
||||||
static void adc_shutdown(FAR struct adc_dev_s *dev);
|
static void adc_shutdown(FAR struct adc_dev_s *dev);
|
||||||
@@ -148,6 +153,7 @@ static void adc_startconv(FAR struct efm32_dev_s *priv, bool enable);
|
|||||||
|
|
||||||
static const struct adc_ops_s g_adcops =
|
static const struct adc_ops_s g_adcops =
|
||||||
{
|
{
|
||||||
|
.ao_bind = adc_bind,
|
||||||
.ao_reset = adc_reset,
|
.ao_reset = adc_reset,
|
||||||
.ao_setup = adc_setup,
|
.ao_setup = adc_setup,
|
||||||
.ao_shutdown = adc_shutdown,
|
.ao_shutdown = adc_shutdown,
|
||||||
@@ -790,7 +796,7 @@ static void adc_startconv(struct efm32_dev_s *priv, bool enable)
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: adc_reset
|
* Name: adc_hw_reset
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Deinitializes the ADCx peripheral registers to their default
|
* Deinitializes the ADCx peripheral registers to their default
|
||||||
@@ -873,6 +879,25 @@ static void adc_enable(FAR struct efm32_dev_s *priv, bool enable)
|
|||||||
adc_putreg(priv, EFM32_ADC_CR2_OFFSET, regval);
|
adc_putreg(priv, EFM32_ADC_CR2_OFFSET, regval);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Name: adc_bind
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* Bind the upper-half driver callbacks to the lower-half implementation. This
|
||||||
|
* must be called early in order to receive ADC event notifications.
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
static int adc_bind(FAR struct adc_dev_s *dev,
|
||||||
|
FAR const struct adc_callback_s *callback)
|
||||||
|
{
|
||||||
|
FAR struct efm32_dev_s *priv = (FAR struct efm32_dev_s *)dev->ad_priv;
|
||||||
|
|
||||||
|
DEBUGASSERT(priv != NULL);
|
||||||
|
priv->cb = callback;
|
||||||
|
return OK;
|
||||||
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: adc_reset
|
* Name: adc_reset
|
||||||
*
|
*
|
||||||
@@ -1180,14 +1205,21 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
|
|||||||
value = adc_getreg(priv, EFM32_ADC_DR_OFFSET);
|
value = adc_getreg(priv, EFM32_ADC_DR_OFFSET);
|
||||||
value &= ADC_DR_DATA_MASK;
|
value &= ADC_DR_DATA_MASK;
|
||||||
|
|
||||||
/* Give the ADC data to the ADC driver. adc_receive accepts 3 parameters:
|
/* Verify that the upper-half driver has bound its callback functions */
|
||||||
*
|
|
||||||
* 1) The first is the ADC device instance for this ADC block.
|
|
||||||
* 2) The second is the channel number for the data, and
|
|
||||||
* 3) The third is the converted data for the channel.
|
|
||||||
*/
|
|
||||||
|
|
||||||
adc_receive(dev, priv->chanlist[priv->current], value);
|
if (priv->cb != NULL)
|
||||||
|
{
|
||||||
|
/* Give the ADC data to the ADC driver. The ADC receive method
|
||||||
|
* accepts 3 parameters:
|
||||||
|
*
|
||||||
|
* 1) The first is the ADC device instance for this ADC block.
|
||||||
|
* 2) The second is the channel number for the data, and
|
||||||
|
* 3) The third is the converted data for the channel.
|
||||||
|
*/
|
||||||
|
|
||||||
|
DEBUGASSERT(priv->cb->au_receive != NULL);
|
||||||
|
priv->cb->au_receive(dev, priv->chanlist[priv->current], value);
|
||||||
|
}
|
||||||
|
|
||||||
/* Set the channel number of the next channel that will complete conversion */
|
/* Set the channel number of the next channel that will complete conversion */
|
||||||
|
|
||||||
@@ -1272,7 +1304,8 @@ struct adc_dev_s *efm32_adcinitialize(int intf, const uint8_t *chanlist, int nch
|
|||||||
|
|
||||||
/* Configure the selected ADC */
|
/* Configure the selected ADC */
|
||||||
|
|
||||||
priv = dev->ad_priv;
|
priv = dev->ad_priv;
|
||||||
|
priv->cb = NULL;
|
||||||
|
|
||||||
DEBUGASSERT(nchannels <= ADC_MAX_SAMPLES);
|
DEBUGASSERT(nchannels <= ADC_MAX_SAMPLES);
|
||||||
priv->nchannels = nchannels;
|
priv->nchannels = nchannels;
|
||||||
@@ -1283,4 +1316,4 @@ struct adc_dev_s *efm32_adcinitialize(int intf, const uint8_t *chanlist, int nch
|
|||||||
|
|
||||||
#endif /* CONFIG_EFM32_EFM32GG */
|
#endif /* CONFIG_EFM32_EFM32GG */
|
||||||
#endif /* CONFIG_EFM32_ADC1 */
|
#endif /* CONFIG_EFM32_ADC1 */
|
||||||
#endif /* CONFIG_ADC */
|
#endif /* CONFIG_EFM32_ADC */
|
||||||
|
|||||||
@@ -845,7 +845,7 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size)
|
|||||||
|
|
||||||
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 0);
|
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 0);
|
||||||
|
|
||||||
#if (defined(CONFIG_EFM32_EFM32GG) || defined(CONFIG_EFM32_EFM32WG)) && (2==WORDS_PER_DATA_PHASE)
|
#if (defined(CONFIG_EFM32_EFM32GG) || defined(CONFIG_EFM32_EFM32WG))
|
||||||
|
|
||||||
/* Turn off double word write cycle support. */
|
/* Turn off double word write cycle support. */
|
||||||
|
|
||||||
|
|||||||
@@ -12,17 +12,17 @@ menu "iMX.1 Peripheral Selection"
|
|||||||
config IMX1_UART1
|
config IMX1_UART1
|
||||||
bool "UART1"
|
bool "UART1"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART1
|
select UART1_SERIALDRIVER
|
||||||
|
|
||||||
config IMX1_UART2
|
config IMX1_UART2
|
||||||
bool "UART2"
|
bool "UART2"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART2
|
select UART2_SERIALDRIVER
|
||||||
|
|
||||||
config IMX1_UART3
|
config IMX1_UART3
|
||||||
bool "UART3"
|
bool "UART3"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART3
|
select UART3_SERIALDRIVER
|
||||||
|
|
||||||
config IMX1_SPI1
|
config IMX1_SPI1
|
||||||
bool "SPI1"
|
bool "SPI1"
|
||||||
|
|||||||
@@ -74,7 +74,7 @@
|
|||||||
#define IMX_CSPI1_SPIDMA (IMX_CSPI1_VBASE + CSPI_DMA_OFFSET)
|
#define IMX_CSPI1_SPIDMA (IMX_CSPI1_VBASE + CSPI_DMA_OFFSET)
|
||||||
#define IMX_CSPI1_SPIRESET (IMX_CSPI1_VBASE + CSPI_RESET_OFFSET)
|
#define IMX_CSPI1_SPIRESET (IMX_CSPI1_VBASE + CSPI_RESET_OFFSET)
|
||||||
|
|
||||||
/* CSPI1 */
|
/* CSPI2 */
|
||||||
|
|
||||||
#define IMX_CSPI2_RXD (IMX_CSPI2_VBASE + CSPI_RXD_OFFSET)
|
#define IMX_CSPI2_RXD (IMX_CSPI2_VBASE + CSPI_RXD_OFFSET)
|
||||||
#define IMX_CSPI2_TXD (IMX_CSPI2_VBASE + CSPI_TXD_OFFSET)
|
#define IMX_CSPI2_TXD (IMX_CSPI2_VBASE + CSPI_TXD_OFFSET)
|
||||||
@@ -138,7 +138,7 @@
|
|||||||
/* CSPI Sample Period Control Register */
|
/* CSPI Sample Period Control Register */
|
||||||
|
|
||||||
#define CSPI_SPCR_WAIT_SHIFT 0
|
#define CSPI_SPCR_WAIT_SHIFT 0
|
||||||
#define CSPI_SPCR_WAIT_MASK (0x7ff << CSPI_CTRL_DATARATE_SHIFT)
|
#define CSPI_SPCR_WAIT_MASK (0x7ff << CSPI_SPCR_WAIT_SHIFT)
|
||||||
#define CSPI_SPCR_CSRC (1 << 15) /* Bit 15: 1:32768 or 32 kHz clock source */
|
#define CSPI_SPCR_CSRC (1 << 15) /* Bit 15: 1:32768 or 32 kHz clock source */
|
||||||
|
|
||||||
/* CSPI DMA Control Register */
|
/* CSPI DMA Control Register */
|
||||||
|
|||||||
@@ -54,32 +54,61 @@ config IMX6_HAVE_HDCP
|
|||||||
|
|
||||||
endmenu # "iMX.6 Chip Selection"
|
endmenu # "iMX.6 Chip Selection"
|
||||||
|
|
||||||
|
config IMX6_ECSPI
|
||||||
|
bool
|
||||||
|
default n
|
||||||
|
|
||||||
menu "iMX.6 Peripheral Selection"
|
menu "iMX.6 Peripheral Selection"
|
||||||
|
|
||||||
|
config IMX6_ECSPI1
|
||||||
|
bool "ECSPI1"
|
||||||
|
default n
|
||||||
|
select IMX6_ECSPI
|
||||||
|
|
||||||
|
config IMX6_ECSPI2
|
||||||
|
bool "ECSPI2"
|
||||||
|
default n
|
||||||
|
select IMX6_ECSPI
|
||||||
|
|
||||||
|
config IMX6_ECSPI3
|
||||||
|
bool "ECSPI3"
|
||||||
|
default n
|
||||||
|
select IMX6_ECSPI
|
||||||
|
|
||||||
|
config IMX6_ECSPI4
|
||||||
|
bool "ECSPI4"
|
||||||
|
default n
|
||||||
|
select IMX6_ECSPI
|
||||||
|
|
||||||
|
config IMX6_ECSPI5
|
||||||
|
bool "ECSPI5"
|
||||||
|
default n
|
||||||
|
select IMX6_ECSPI
|
||||||
|
|
||||||
config IMX6_UART1
|
config IMX6_UART1
|
||||||
bool "UART1"
|
bool "UART1"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART1
|
select UART1_SERIALDRIVER
|
||||||
|
|
||||||
config IMX6_UART2
|
config IMX6_UART2
|
||||||
bool "UART2"
|
bool "UART2"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART2
|
select UART2_SERIALDRIVER
|
||||||
|
|
||||||
config IMX6_UART3
|
config IMX6_UART3
|
||||||
bool "UART3"
|
bool "UART3"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART3
|
select UART3_SERIALDRIVER
|
||||||
|
|
||||||
config IMX6_UART4
|
config IMX6_UART4
|
||||||
bool "UART4"
|
bool "UART4"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART4
|
select UART4_SERIALDRIVER
|
||||||
|
|
||||||
config IMX6_UART5
|
config IMX6_UART5
|
||||||
bool "UART5"
|
bool "UART5"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART5
|
select UART5_SERIALDRIVER
|
||||||
|
|
||||||
config IMX6_SPI1
|
config IMX6_SPI1
|
||||||
bool "SPI1"
|
bool "SPI1"
|
||||||
|
|||||||
@@ -150,3 +150,7 @@ CHIP_CSRCS += imx_serial.c imx_lowputc.c
|
|||||||
ifeq ($(CONFIG_SMP),y)
|
ifeq ($(CONFIG_SMP),y)
|
||||||
CHIP_CSRCS += imx_cpuboot.c
|
CHIP_CSRCS += imx_cpuboot.c
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
ifeq ($(CONFIG_IMX6_ECSPI),y)
|
||||||
|
CHIP_CSRCS += imx_ecspi.c
|
||||||
|
endif
|
||||||
|
|||||||
@@ -0,0 +1,290 @@
|
|||||||
|
/************************************************************************************
|
||||||
|
* arch/arm/src/imx6/imx_ecspi.h
|
||||||
|
*
|
||||||
|
* Copyright (C) 2009-2010, 2015-2016 Gregory Nutt. All rights reserved.
|
||||||
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||||
|
* used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||||
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||||
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ARCH_ARM_IMX6_CHIP_ECSPI_H
|
||||||
|
#define __ARCH_ARM_IMX6_CHIP_ECSPI_H
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Included Files
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#include <nuttx/config.h>
|
||||||
|
#include "chip/imx_memorymap.h"
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Pre-processor Definitions
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
/* ECSPI Register Offsets ***********************************************************/
|
||||||
|
|
||||||
|
#define ECSPI_RXDATA_OFFSET 0x0000 /* Receive Data Register */
|
||||||
|
#define ECSPI_TXDATA_OFFSET 0x0004 /* Transmit Data Register */
|
||||||
|
#define ECSPI_CONREG_OFFSET 0x0008 /* Control Register */
|
||||||
|
#define ECSPI_CONFIGREG_OFFSET 0x000c /* Configuration Register */
|
||||||
|
#define ECSPI_INTREG_OFFSET 0x0010 /* Interrupt Control Register */
|
||||||
|
#define ECSPI_DMAREG_OFFSET 0x0014 /* DMA Control Register */
|
||||||
|
#define ECSPI_STATREG_OFFSET 0x0018 /* Status Register */
|
||||||
|
#define ECSPI_PERIODREG_OFFSET 0x001c /* Sample Period Control Register */
|
||||||
|
#define ECSPI_TESTREG_OFFSET 0x0020 /* Test Control Register */
|
||||||
|
#define ECSPI_MSGDATA_OFFSET 0x0040 /* Message Data Register */
|
||||||
|
|
||||||
|
/* ECSPI Register Addresses *********************************************************/
|
||||||
|
|
||||||
|
/* ECSPI1 */
|
||||||
|
|
||||||
|
#define IMX_ECSPI1_RXDATA (IMX_ECSPI1_VBASE + ECSPI_RXDATA_OFFSET)
|
||||||
|
#define IMX_ECSPI1_TXDATA (IMX_ECSPI1_VBASE + ECSPI_TXDATA_OFFSET)
|
||||||
|
#define IMX_ECSPI1_CONREG (IMX_ECSPI1_VBASE + ECSPI_CONREG_OFFSET)
|
||||||
|
#define IMX_ECSPI1_CONFIGREG (IMX_ECSPI1_VBASE + ECSPI_CONFIGREG_OFFSET)
|
||||||
|
#define IMX_ECSPI1_INTREG (IMX_ECSPI1_VBASE + ECSPI_INTREG_OFFSET)
|
||||||
|
#define IMX_ECSPI1_DMAREG (IMX_ECSPI1_VBASE + ECSPI_DMAREG_OFFSET)
|
||||||
|
#define IMX_ECSPI1_STATREG (IMX_ECSPI1_VBASE + ECSPI_STATREG_OFFSET)
|
||||||
|
#define IMX_ECSPI1_PERIODREG (IMX_ECSPI1_VBASE + ECSPI_PERIODREG_OFFSET)
|
||||||
|
#define IMX_ECSPI1_TESTREG (IMX_ECSPI1_VBASE + ECSPI_TESTREG_OFFSET)
|
||||||
|
#define IMX_ECSPI1_MSGDATA (IMX_ECSPI1_VBASE + ECSPI_MSGDATA_OFFSET)
|
||||||
|
|
||||||
|
/* ECSPI2 */
|
||||||
|
|
||||||
|
#define IMX_ECSPI2_RXDATA (IMX_ECSPI2_VBASE + ECSPI_RXDATA_OFFSET)
|
||||||
|
#define IMX_ECSPI2_TXDATA (IMX_ECSPI2_VBASE + ECSPI_TXDATA_OFFSET)
|
||||||
|
#define IMX_ECSPI2_CONREG (IMX_ECSPI2_VBASE + ECSPI_CONREG_OFFSET)
|
||||||
|
#define IMX_ECSPI2_CONFIGREG (IMX_ECSPI2_VBASE + ECSPI_CONFIGREG_OFFSET)
|
||||||
|
#define IMX_ECSPI2_INTREG (IMX_ECSPI2_VBASE + ECSPI_INTREG_OFFSET)
|
||||||
|
#define IMX_ECSPI2_DMAREG (IMX_ECSPI2_VBASE + ECSPI_DMAREG_OFFSET)
|
||||||
|
#define IMX_ECSPI2_STATREG (IMX_ECSPI2_VBASE + ECSPI_STATREG_OFFSET)
|
||||||
|
#define IMX_ECSPI2_PERIODREG (IMX_ECSPI2_VBASE + ECSPI_PERIODREG_OFFSET)
|
||||||
|
#define IMX_ECSPI2_TESTREG (IMX_ECSPI2_VBASE + ECSPI_TESTREG_OFFSET)
|
||||||
|
#define IMX_ECSPI2_MSGDATA (IMX_ECSPI2_VBASE + ECSPI_MSGDATA_OFFSET)
|
||||||
|
|
||||||
|
/* ECSPI3 */
|
||||||
|
|
||||||
|
#define IMX_ECSPI3_RXDATA (IMX_ECSPI3_VBASE + ECSPI_RXDATA_OFFSET)
|
||||||
|
#define IMX_ECSPI3_TXDATA (IMX_ECSPI3_VBASE + ECSPI_TXDATA_OFFSET)
|
||||||
|
#define IMX_ECSPI3_CONREG (IMX_ECSPI3_VBASE + ECSPI_CONREG_OFFSET)
|
||||||
|
#define IMX_ECSPI3_CONFIGREG (IMX_ECSPI3_VBASE + ECSPI_CONFIGREG_OFFSET)
|
||||||
|
#define IMX_ECSPI3_INTREG (IMX_ECSPI3_VBASE + ECSPI_INTREG_OFFSET)
|
||||||
|
#define IMX_ECSPI3_DMAREG (IMX_ECSPI3_VBASE + ECSPI_DMAREG_OFFSET)
|
||||||
|
#define IMX_ECSPI3_STATREG (IMX_ECSPI3_VBASE + ECSPI_STATREG_OFFSET)
|
||||||
|
#define IMX_ECSPI3_PERIODREG (IMX_ECSPI3_VBASE + ECSPI_PERIODREG_OFFSET)
|
||||||
|
#define IMX_ECSPI3_TESTREG (IMX_ECSPI3_VBASE + ECSPI_TESTREG_OFFSET)
|
||||||
|
#define IMX_ECSPI3_MSGDATA (IMX_ECSPI3_VBASE + ECSPI_MSGDATA_OFFSET)
|
||||||
|
|
||||||
|
/* ECSPI4 */
|
||||||
|
|
||||||
|
#define IMX_ECSPI4_RXDATA (IMX_ECSPI4_VBASE + ECSPI_RXDATA_OFFSET)
|
||||||
|
#define IMX_ECSPI4_TXDATA (IMX_ECSPI4_VBASE + ECSPI_TXDATA_OFFSET)
|
||||||
|
#define IMX_ECSPI4_CONREG (IMX_ECSPI4_VBASE + ECSPI_CONREG_OFFSET)
|
||||||
|
#define IMX_ECSPI4_CONFIGREG (IMX_ECSPI4_VBASE + ECSPI_CONFIGREG_OFFSET)
|
||||||
|
#define IMX_ECSPI4_INTREG (IMX_ECSPI4_VBASE + ECSPI_INTREG_OFFSET)
|
||||||
|
#define IMX_ECSPI4_DMAREG (IMX_ECSPI4_VBASE + ECSPI_DMAREG_OFFSET)
|
||||||
|
#define IMX_ECSPI4_STATREG (IMX_ECSPI4_VBASE + ECSPI_STATREG_OFFSET)
|
||||||
|
#define IMX_ECSPI4_PERIODREG (IMX_ECSPI4_VBASE + ECSPI_PERIODREG_OFFSET)
|
||||||
|
#define IMX_ECSPI4_TESTREG (IMX_ECSPI4_VBASE + ECSPI_TESTREG_OFFSET)
|
||||||
|
#define IMX_ECSPI4_MSGDATA (IMX_ECSPI4_VBASE + ECSPI_MSGDATA_OFFSET)
|
||||||
|
|
||||||
|
/* ECSPI5 */
|
||||||
|
|
||||||
|
#define IMX_ECSPI5_RXDATA (IMX_ECSPI5_VBASE + ECSPI_RXDATA_OFFSET)
|
||||||
|
#define IMX_ECSPI5_TXDATA (IMX_ECSPI5_VBASE + ECSPI_TXDATA_OFFSET)
|
||||||
|
#define IMX_ECSPI5_CONREG (IMX_ECSPI5_VBASE + ECSPI_CONREG_OFFSET)
|
||||||
|
#define IMX_ECSPI5_CONFIGREG (IMX_ECSPI5_VBASE + ECSPI_CONFIGREG_OFFSET)
|
||||||
|
#define IMX_ECSPI5_INTREG (IMX_ECSPI5_VBASE + ECSPI_INTREG_OFFSET)
|
||||||
|
#define IMX_ECSPI5_DMAREG (IMX_ECSPI5_VBASE + ECSPI_DMAREG_OFFSET)
|
||||||
|
#define IMX_ECSPI5_STATREG (IMX_ECSPI5_VBASE + ECSPI_STATREG_OFFSET)
|
||||||
|
#define IMX_ECSPI5_PERIODREG (IMX_ECSPI5_VBASE + ECSPI_PERIODREG_OFFSET)
|
||||||
|
#define IMX_ECSPI5_TESTREG (IMX_ECSPI5_VBASE + ECSPI_TESTREG_OFFSET)
|
||||||
|
#define IMX_ECSPI5_MSGDATA (IMX_ECSPI5_VBASE + ECSPI_MSGDATA_OFFSET)
|
||||||
|
|
||||||
|
/* ECSPI Register Bit Definitions ***************************************************/
|
||||||
|
|
||||||
|
/* Control Register */
|
||||||
|
|
||||||
|
#define ECSPI_CONREG_EN (1 << 0) /* Bit 0: SPI Block enable control */
|
||||||
|
#define ECSPI_CONREG_HT (1 << 1) /* Bit 1: Hardware trigger enable */
|
||||||
|
#define ECSPI_CONREG_XCH (1 << 2) /* Bit 2: SPI Exchange bit */
|
||||||
|
#define ECSPI_CONREG_SMC (1 << 3) /* Bit 3: Start mode control */
|
||||||
|
#define ECSPI_CONREG_CHMODE_SHIFT (4) /* Bits 4-7: SPI Channel mode */
|
||||||
|
#define ECSPI_CONREG_CHMODE_MASK (15 << ECSPI_CONREG_CHMODE_SHIFT)
|
||||||
|
# define ECSPI_CONREG_CH0MASTER (1 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 0 master mode */
|
||||||
|
# define ECSPI_CONREG_CH1MASTER (2 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 1 master mode */
|
||||||
|
# define ECSPI_CONREG_CH2MASTER (4 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 2 master mode */
|
||||||
|
# define ECSPI_CONREG_CH3MASTER (8 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 3 master mode */
|
||||||
|
#define ECSPI_CONREG_POSTDIV_SHIFT (8) /* Bits 8-11: SPI Post divider (exponent) */
|
||||||
|
#define ECSPI_CONREG_POSTDIV_MASK (15 << ECSPI_CONREG_POSTDIV_SHIFT)
|
||||||
|
# define ECSPI_CONREG_POSTDIV_EXP(n) ((uint32_t)(n) << ECSPI_CONREG_POSTDIV_SHIFT)
|
||||||
|
# define ECSPI_CONREG_POSTDIV_1 (0 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*0 */
|
||||||
|
# define ECSPI_CONREG_POSTDIV_2 (1 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*1 */
|
||||||
|
# define ECSPI_CONREG_POSTDIV_4 (2 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*2 */
|
||||||
|
# define ECSPI_CONREG_POSTDIV_8 (3 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*3 */
|
||||||
|
# define ECSPI_CONREG_POSTDIV_16 (4 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*4 */
|
||||||
|
# define ECSPI_CONREG_POSTDIV_32 (5 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*5 */
|
||||||
|
# define ECSPI_CONREG_POSTDIV_64 (6 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*6 */
|
||||||
|
# define ECSPI_CONREG_POSTDIV_128 (7 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*7 */
|
||||||
|
# define ECSPI_CONREG_POSTDIV_256 (8 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*8 */
|
||||||
|
# define ECSPI_CONREG_POSTDIV_512 (9 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*9 */
|
||||||
|
# define ECSPI_CONREG_POSTDIV_1024 (10 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*10 */
|
||||||
|
# define ECSPI_CONREG_POSTDIV_2048 (11 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*11 */
|
||||||
|
# define ECSPI_CONREG_POSTDIV_4096 (12 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*12 */
|
||||||
|
# define ECSPI_CONREG_POSTDIV_8192 (13 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*13 */
|
||||||
|
# define ECSPI_CONREG_POSTDIV_16384 (14 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*14 */
|
||||||
|
# define ECSPI_CONREG_POSTDIV_32768 (15 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*15 */
|
||||||
|
#define ECSPI_CONREG_PREDIV_SHIFT (12) /* Bits 12-15: SPI Pre divider (minus 1) */
|
||||||
|
#define ECSPI_CONREG_PREDIV_MASK (15 << ECSPI_CONREG_PREDIV_SHIFT)
|
||||||
|
# define ECSPI_CONREG_PREDIV(n) ((uint32_t)(n) << ECSPI_CONREG_PREDIV_SHIFT)
|
||||||
|
#define ECSPI_CONREG_DRCTL_SHIFT 16 /* Bits 16-17: SPI Data ready control */
|
||||||
|
#define ECSPI_CONREG_DRCTL_MASK (3 << ECSPI_CONREG_DRCTL_SHIFT)
|
||||||
|
# define ECSPI_CONREG_DRCTL_IGNRDY (0 << ECSPI_CONREG_DRCTL_SHIFT)
|
||||||
|
# define ECSPI_CONREG_DRCTL_FALLING (1 << ECSPI_CONREG_DRCTL_SHIFT)
|
||||||
|
# define ECSPI_CONREG_DRCTL_ACTVLOW (2 << ECSPI_CONREG_DRCTL_SHIFT)
|
||||||
|
#define ECSPI_CONREG_CHSEL_SHIFT (18) /* Bits 18-19: SPI Channel select bits */
|
||||||
|
#define ECSPI_CONREG_CHSEL_MASK (3 << ECSPI_CONREG_CHSEL_SHIFT)
|
||||||
|
# define ECSPI_CONREG_CHSEL_SS0 (0 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 0 select (SS0) */
|
||||||
|
# define ECSPI_CONREG_CHSEL_SS1 (1 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 1 select (SS1) */
|
||||||
|
# define ECSPI_CONREG_CHSEL_SS2 (2 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 2 select (SS2) */
|
||||||
|
# define ECSPI_CONREG_CHSEL_SS3 (3 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 3 select (SS3) */
|
||||||
|
#define ECSPI_CONREG_BURSTLEN_SHIFT (20) /* Bits 20-31: Burst length */
|
||||||
|
#define ECSPI_CONREG_BURSTLEN_MASK (0xfff << ECSPI_CONREG_BURSTLEN_SHIFT)
|
||||||
|
# define ECSPI_CONREG_BURSTLEN(n) ((uint32_t)(n) << ECSPI_CONREG_BURSTLEN_SHIFT)
|
||||||
|
|
||||||
|
/* Configuration Register */
|
||||||
|
|
||||||
|
#define ECSPI_CONFIGREG_SCLKPHA_SHIFT (0) /* Bits 0-3: SPI Clock/Data Phase Control */
|
||||||
|
#define ECSPI_CONFIGREG_SCLKPHA_MASK (15 << ECSPI_CONFIGREG_SCLKPHA_SHIFT)
|
||||||
|
# define ECSPI_CONFIGREG_CH0PHA (1 << ECSPI_CONFIGREG_SCLKPHA_SHIFT) /* Channel 0 SCLK Phase */
|
||||||
|
# define ECSPI_CONFIGREG_CH1PHA (2 << ECSPI_CONFIGREG_SCLKPHA_SHIFT) /* Channel 1 SCLK Phase */
|
||||||
|
# define ECSPI_CONFIGREG_CH2PHA (4 << ECSPI_CONFIGREG_SCLKPHA_SHIFT) /* Channel 2 SCLK Phase */
|
||||||
|
# define ECSPI_CONFIGREG_CH3PHA (8 << ECSPI_CONFIGREG_SCLKPHA_SHIFT) /* Channel 3 SCLK Phase */
|
||||||
|
#define ECSPI_CONFIGREG_SCLKPOL_SHIFT (4) /* Bits 4-7: SPI Clock polarity control */
|
||||||
|
#define ECSPI_CONFIGREG_SCLKPOL_MASK (15 << ECSPI_CONFIGREG_SCLKPOL_SHIFT)
|
||||||
|
# define ECSPI_CONFIGREG_CH0POL (1 << ECSPI_CONFIGREG_SCLKPOL_SHIFT) /* Channel 0 SCLK polarity */
|
||||||
|
# define ECSPI_CONFIGREG_CH1POL (2 << ECSPI_CONFIGREG_SCLKPOL_SHIFT) /* Channel 1 SCLK polarity */
|
||||||
|
# define ECSPI_CONFIGREG_CH2POL (4 << ECSPI_CONFIGREG_SCLKPOL_SHIFT) /* Channel 2 SCLK polarity */
|
||||||
|
# define ECSPI_CONFIGREG_CH3POL (8 << ECSPI_CONFIGREG_SCLKPOL_SHIFT) /* Channel 3 SCLK polarity */
|
||||||
|
#define ECSPI_CONFIGREG_SSCTL_SHIFT (8) /* Bits 8-11: SPI SS Wave form select */
|
||||||
|
#define ECSPI_CONFIGREG_SSCTL_MASK (15 << ECSPI_CONFIGREG_SSCTL_SHIFT)
|
||||||
|
# define ECSPI_CONFIGREG_CH0SSCTRL (1 << ECSPI_CONFIGREG_SSCTL_SHIFT) /* Channel 0 SS control */
|
||||||
|
# define ECSPI_CONFIGREG_CH1SSCTRL (2 << ECSPI_CONFIGREG_SSCTL_SHIFT) /* Channel 1 SS control */
|
||||||
|
# define ECSPI_CONFIGREG_CH2SSCTRL (4 << ECSPI_CONFIGREG_SSCTL_SHIFT) /* Channel 2 SS control */
|
||||||
|
# define ECSPI_CONFIGREG_CH3SSCTRL (8 << ECSPI_CONFIGREG_SSCTL_SHIFT) /* Channel 3 SS control */
|
||||||
|
#define ECSPI_CONFIGREG_SSPOL_SHIFT (12) /* Bits 12-15: SPI SS Polarity select */
|
||||||
|
#define ECSPI_CONFIGREG_SSPOL_MASK (15 << ECSPI_CONFIGREG_SSPOL_SHIFT)
|
||||||
|
# define ECSPI_CONFIGREG_CH0SSPOL (1 << ECSPI_CONFIGREG_CHMODE_SHIFT) /* Channel 0 SS polarity */
|
||||||
|
# define ECSPI_CONFIGREG_CH1SSPOL (2 << ECSPI_CONFIGREG_CHMODE_SHIFT) /* Channel 1 SS polarity */
|
||||||
|
# define ECSPI_CONFIGREG_CH2SSPOL (4 << ECSPI_CONFIGREG_CHMODE_SHIFT) /* Channel 2 SS polarity */
|
||||||
|
# define ECSPI_CONFIGREG_CH3SSPOL (8 << ECSPI_CONFIGREG_CHMODE_SHIFT) /* Channel 3 SS polarity */
|
||||||
|
#define ECSPI_CONFIGREG_DATCTL_SHIFT (16) /* Bits 16-19: Data control */
|
||||||
|
#define ECSPI_CONFIGREG_DATCTL_MASK (15 << ECSPI_CONFIGREG_DATCTL_SHIFT)
|
||||||
|
# define ECSPI_CONFIGREG_CH0DATLOW (1 << ECSPI_CONFIGREG_DATCTL_SHIFT) /* Channel 0 SS low when inactive */
|
||||||
|
# define ECSPI_CONFIGREG_CH1DATLOW (2 << ECSPI_CONFIGREG_DATCTL_SHIFT) /* Channel 1 SS low when inactive */
|
||||||
|
# define ECSPI_CONFIGREG_CH2DATLOW (4 << ECSPI_CONFIGREG_DATCTL_SHIFT) /* Channel 2 SS low when inactive */
|
||||||
|
# define ECSPI_CONFIGREG_CH3DATLOW (8 << ECSPI_CONFIGREG_DATCTL_SHIFT) /* Channel 3 SS low when inactive */
|
||||||
|
#define ECSPI_CONFIGREG_SCLKCTL_SHIFT (20) /* Bits 20-23: SCLK Control */
|
||||||
|
#define ECSPI_CONFIGREG_SCLKCTL_MASK (15 << ECSPI_CONFIGREG_SCLKCTL_SHIFT)
|
||||||
|
# define ECSPI_CONFIGREG_CH0SCLKLOW (1 << ECSPI_CONFIGREG_SCLKCTL_SHIFT) /* Channel 0 SCLK low when inactive */
|
||||||
|
# define ECSPI_CONFIGREG_CH1SCLKLOW (2 << ECSPI_CONFIGREG_SCLKCTL_SHIFT) /* Channel 1 SCLK low when inactive */
|
||||||
|
# define ECSPI_CONFIGREG_CH2SCLKLOW (4 << ECSPI_CONFIGREG_SCLKCTL_SHIFT) /* Channel 2 SCLK low when inactive */
|
||||||
|
# define ECSPI_CONFIGREG_CH3SCLKLOW (8 << ECSPI_CONFIGREG_SCLKCTL_SHIFT) /* Channel 3 SCLK low when inactive */
|
||||||
|
#define ECSPI_CONFIGREG_HTLEN_SHIFT (24) /* Bits 24-28: HT Length */
|
||||||
|
#define ECSPI_CONFIGREG_HTLEN_MASK (15 << ECSPI_CONFIGREG_HTLEN_SHIFT)
|
||||||
|
# define ECSPI_CONFIGREG_HTLEN(n) ((uint32_t)(n) << ECSPI_CONFIGREG_HTLEN_SHIFT)
|
||||||
|
/* Bits 29-31: Reserved */
|
||||||
|
|
||||||
|
/* Common Interrupt Control Register and Status Register */
|
||||||
|
|
||||||
|
#define ECSPI_INT_TE (1 << 0) /* Bit 0: TXFIFO Empty Interrupt */
|
||||||
|
#define ECSPI_INT_TDR (1 << 1) /* Bit 1: TXFIFO Data Request Interrupt */
|
||||||
|
#define ECSPI_INT_TF (1 << 2) /* Bit 2: TXFIFO Full Interrupt */
|
||||||
|
#define ECSPI_INT_RR (1 << 3) /* Bit 3: RXFIFO Data Ready Interrupt */
|
||||||
|
#define ECSPI_INT_RDR (1 << 4) /* Bit 4: RXFIFO Data Request Interrupt enable */
|
||||||
|
#define ECSPI_INT_RF (1 << 5) /* Bit 5: RXFIFO Full Interrupt */
|
||||||
|
#define ECSPI_INT_RO (1 << 6) /* Bit 6: RXFIFO Overflow Interrupt */
|
||||||
|
#define ECSPI_INT_TC (1 << 7) /* Bit 7: Transfer Completed Interrupt enable */
|
||||||
|
/* Bits 8-31: Reserved */
|
||||||
|
|
||||||
|
#define ECSPI_INT_ALL 0x000000ff
|
||||||
|
|
||||||
|
/* ECSPI DMA Control Register */
|
||||||
|
|
||||||
|
#define ECSPI_DMAREG_TXTHRES_SHIFT (0) /* Bits 0-5: TX Threshold */
|
||||||
|
#define ECSPI_DMAREG_TXTHRES_MASK (0x3f << ECSPI_DMAREG_TXTHRES_SHIFT)
|
||||||
|
# define ECSPI_DMAREG_TXTHRES(n) ((uint32_t)(n) << ECSPI_DMAREG_TXTHRES_SHIFT)
|
||||||
|
/* Bit 6: Reserved */
|
||||||
|
#define ECSPI_DMAREG_TEDEN (1 << 7) /* Bit 7: TXFIFO Empty DMA request enable */
|
||||||
|
/* Bits 8-15: Reserved */
|
||||||
|
#define ECSPI_DMAREG_RXTHRES_SHIFT (16) /* Bits 16-21: RX Threshold */
|
||||||
|
#define ECSPI_DMAREG_RXTHRES_MASK (0x3f << ECSPI_DMAREG_RXTHRES_SHIFT)
|
||||||
|
# define ECSPI_DMAREG_RXTHRES(n) ((uint32_t)(n) << ECSPI_DMAREG_RXTHRES_SHIFT)
|
||||||
|
/* Bit 22: Reserved */
|
||||||
|
#define ECSPI_DMAREG_RXDEN (1 << 23) /* Bit 23: RXFIFO DMA request enable */
|
||||||
|
#define ECSPI_DMAREG_RXLEN_SHIFT (24) /* Bits 24-29: RX DMA length */
|
||||||
|
#define ECSPI_DMAREG_RXLEN_MASK (0x3f << ECSPI_DMAREG_RXLEN_SHIFT)
|
||||||
|
# define ECSPI_DMAREG_RXLEN(n) ((uint32_t)(n) << ECSPI_DMAREG_RXLEN_SHIFT)
|
||||||
|
/* Bit 30: Reserved */
|
||||||
|
#define ECSPI_DMAREG_RXTDEN (1 << 31) /* Bit 31: RXFIFO Tail DMA request enable */
|
||||||
|
|
||||||
|
/* ECSPI Sample Period Control Register */
|
||||||
|
|
||||||
|
#define ECSPI_PERIODREG_PERIOD_SHIFT (0) /* Bits 0-14: Sample Period Control */
|
||||||
|
#define ECSPI_PERIODREG_PERIOD_MASK (0x7fff << ECSPI_PERIODREG_PERIOD_SHIFT)
|
||||||
|
# define ECSPI_PERIODREG_PERIOD(n) ((uint32_t)(n) << ECSPI_PERIODREG_PERIOD_SHIFT)
|
||||||
|
#define ECSPI_PERIODREG_CSRC (1 << 15) /* Bit 15: Clock source control */
|
||||||
|
#define ECSPI_PERIODREG_CSDCTL_SHIFT (16) /* Bits 16-21: Chip Select delay control */
|
||||||
|
#define ECSPI_PERIODREG_CSDCTL_MASK (0x3f << ECSPI_PERIODREG_CSDCTL_SHIFT)
|
||||||
|
# define ECSPI_PERIODREG_CSDCTL(n) ((uint32_t)(n) << ECSPI_PERIODREG_CSDCTL_SHIFT)
|
||||||
|
/* Bits 22-31: Reserved */
|
||||||
|
|
||||||
|
/* Test Control Register */
|
||||||
|
|
||||||
|
#define ECSPI_TESTREG_TXCNT_SHIFT (0) /* Bits 0-6: TXFIFO Counter */
|
||||||
|
#define ECSPI_TESTREG_TXCNT_MASK (0x7f << ECSPI_TESTREG_TXCNT_SHIFT)
|
||||||
|
# define ECSPI_TESTREG_TXCNT(n) ((uint32_t)(n) << ECSPI_TESTREG_TXCNT_SHIFT)
|
||||||
|
/* Bit 7: Reserved */
|
||||||
|
#define ECSPI_TESTREG_RXCNT_SHIFT (8) /* Bits 8-14: RXFIFO Counter */
|
||||||
|
#define ECSPI_TESTREG_RXCNT_MASK (0x7f << ECSPI_TESTREG_RXCNT_SHIFT)
|
||||||
|
# define ECSPI_TESTREG_RXCNT(n) ((uint32_t)(n) << ECSPI_TESTREG_RXCNT_SHIFT)
|
||||||
|
/* Bits 15-30: Reserved */
|
||||||
|
#define ECSPI_TESTREG_LBC (1 << 31) /* Bit 31: Loop Back Control */
|
||||||
|
|
||||||
|
/* Message Data Register (32-bit message data) */
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Public Data
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Public Function Prototypes
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#endif /* __ARCH_ARM_IMX6_CHIP_ECSPI_H */
|
||||||
@@ -53,6 +53,7 @@
|
|||||||
#include "smp.h"
|
#include "smp.h"
|
||||||
#include "fpu.h"
|
#include "fpu.h"
|
||||||
#include "gic.h"
|
#include "gic.h"
|
||||||
|
#include "cp15_cacheops.h"
|
||||||
|
|
||||||
#ifdef CONFIG_SMP
|
#ifdef CONFIG_SMP
|
||||||
|
|
||||||
@@ -69,44 +70,44 @@ typedef CODE void (*cpu_start_t)(void);
|
|||||||
#if 0 /* Not used */
|
#if 0 /* Not used */
|
||||||
static const uint32_t g_cpu_reset[CONFIG_SMP_NCPUS] =
|
static const uint32_t g_cpu_reset[CONFIG_SMP_NCPUS] =
|
||||||
{
|
{
|
||||||
0,
|
SRC_SCR_CORE0_RST
|
||||||
#if CONFIG_SMP_NCPUS > 1
|
#if CONFIG_SMP_NCPUS > 1
|
||||||
SRC_SCR_CORE1_RST,
|
, SRC_SCR_CORE1_RST
|
||||||
#endif
|
#endif
|
||||||
#if CONFIG_SMP_NCPUS > 2
|
#if CONFIG_SMP_NCPUS > 2
|
||||||
SRC_SCR_CORE2_RST,
|
, SRC_SCR_CORE2_RST
|
||||||
#endif
|
#endif
|
||||||
#if CONFIG_SMP_NCPUS > 3
|
#if CONFIG_SMP_NCPUS > 3
|
||||||
SRC_SCR_CORE3_RST
|
, SRC_SCR_CORE3_RST
|
||||||
#endif
|
#endif
|
||||||
};
|
};
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
static const uint32_t g_cpu_ctrl[CONFIG_SMP_NCPUS] =
|
static const uint32_t g_cpu_ctrl[CONFIG_SMP_NCPUS] =
|
||||||
{
|
{
|
||||||
0,
|
0
|
||||||
#if CONFIG_SMP_NCPUS > 1
|
#if CONFIG_SMP_NCPUS > 1
|
||||||
SRC_SCR_CORE1_ENABLE,
|
, SRC_SCR_CORE1_ENABLE
|
||||||
#endif
|
#endif
|
||||||
#if CONFIG_SMP_NCPUS > 2
|
#if CONFIG_SMP_NCPUS > 2
|
||||||
SRC_SCR_CORE2_ENABLE,
|
, SRC_SCR_CORE2_ENABLE
|
||||||
#endif
|
#endif
|
||||||
#if CONFIG_SMP_NCPUS > 3
|
#if CONFIG_SMP_NCPUS > 3
|
||||||
SRC_SCR_CORE3_ENABLE
|
, SRC_SCR_CORE3_ENABLE
|
||||||
#endif
|
#endif
|
||||||
};
|
};
|
||||||
|
|
||||||
static const uintptr_t g_cpu_gpr[CONFIG_SMP_NCPUS] =
|
static const uintptr_t g_cpu_gpr[CONFIG_SMP_NCPUS] =
|
||||||
{
|
{
|
||||||
0,
|
IMX_SRC_GPR1
|
||||||
#if CONFIG_SMP_NCPUS > 1
|
#if CONFIG_SMP_NCPUS > 1
|
||||||
IMX_SRC_GPR3,
|
, IMX_SRC_GPR3
|
||||||
#endif
|
#endif
|
||||||
#if CONFIG_SMP_NCPUS > 2
|
#if CONFIG_SMP_NCPUS > 2
|
||||||
IMX_SRC_GPR5,
|
, IMX_SRC_GPR5
|
||||||
#endif
|
#endif
|
||||||
#if CONFIG_SMP_NCPUS > 3
|
#if CONFIG_SMP_NCPUS > 3
|
||||||
IMX_SRC_GPR7
|
, IMX_SRC_GPR7
|
||||||
#endif
|
#endif
|
||||||
};
|
};
|
||||||
|
|
||||||
@@ -296,6 +297,10 @@ void arm_cpu_boot(int cpu)
|
|||||||
(void)up_irq_enable();
|
(void)up_irq_enable();
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/* Invalidate CPUn L1 so that is will be reloaded from coherent L2. */
|
||||||
|
|
||||||
|
cp15_invalidate_dcache_all();
|
||||||
|
|
||||||
/* The next thing that we expect to happen is for logic running on CPU0
|
/* The next thing that we expect to happen is for logic running on CPU0
|
||||||
* to call up_cpu_start() which generate an SGI and a context switch to
|
* to call up_cpu_start() which generate an SGI and a context switch to
|
||||||
* the configured NuttX IDLE task.
|
* the configured NuttX IDLE task.
|
||||||
|
|||||||
@@ -0,0 +1,166 @@
|
|||||||
|
/************************************************************************************
|
||||||
|
* arch/arm/src/imx6/imx_ecspi.h
|
||||||
|
*
|
||||||
|
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||||
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||||
|
* used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||||
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||||
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ARCH_ARM_IMX6_ECSPI_H
|
||||||
|
#define __ARCH_ARM_IMX6_ECSPI_H
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Included Files
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#include <nuttx/config.h>
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <stdbool.h>
|
||||||
|
#include <nuttx/spi/spi.h>
|
||||||
|
|
||||||
|
#include "chip/imx_ecspi.h"
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Pre-processor Definitions
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Public Data
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ASSEMBLY__
|
||||||
|
#ifdef __cplusplus
|
||||||
|
#define EXTERN extern "C"
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#else
|
||||||
|
#define EXTERN extern
|
||||||
|
#endif /* __cplusplus */
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Public Function Prototypes
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
struct spi_dev_s; /* Forward reference */
|
||||||
|
enum spi_dev_e; /* Forward reference */
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Name: imx_spibus_initialize
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* Initialize common parts the selected SPI port. Initialization of
|
||||||
|
* chip select GPIOs must have been performed by board specific logic
|
||||||
|
* prior to calling this function. Specifically: GPIOs should have
|
||||||
|
* been configured for output, and all chip selects disabled.
|
||||||
|
*
|
||||||
|
* One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. However,
|
||||||
|
* If multiple devices on on the bus, then multiple chip selects will be
|
||||||
|
* required. Theregore, all GPIO chip management is deferred to board-
|
||||||
|
* specific logic.
|
||||||
|
*
|
||||||
|
* Input Parameter:
|
||||||
|
* Port number (for hardware that has mutiple SPI interfaces)
|
||||||
|
*
|
||||||
|
* Returned Value:
|
||||||
|
* Valid SPI device structre reference on succcess; a NULL on failure
|
||||||
|
*
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
FAR struct spi_dev_s *imx_spibus_initialize(int port);
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* The external functions, imx_spiselect, imx_spistatus, and imx_cmddaa must be
|
||||||
|
* provided by board-specific logic. These are implementations of the select and
|
||||||
|
* status methods of the SPI interface defined by struct spi_ops_s (see
|
||||||
|
* include/nuttx/spi/spi.h). All other methods (including imx_spibus_initialize()) are
|
||||||
|
* provided by common logic. To use this common SPI logic on your board:
|
||||||
|
*
|
||||||
|
* 1. Provide imx_spiselect() and imx_spistatus() functions in your board-specific
|
||||||
|
* logic. This function will perform chip selection and status operations using
|
||||||
|
* GPIOs in the way your board is configured.
|
||||||
|
* 2. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide the
|
||||||
|
* imx_spicmddata() function in your board-specific logic. This function will
|
||||||
|
* perform cmd/data selection operations using GPIOs in the way your board is
|
||||||
|
* configured.
|
||||||
|
* 3. Add a call to imx_spibus_initialize() in your low level initialization logic
|
||||||
|
* 4. The handle returned by imx_spibus_initialize() may then be used to bind the
|
||||||
|
* SPI driver to higher level logic (e.g., calling mmcsd_spislotinitialize(),
|
||||||
|
* for example, will bind the SPI driver to the SPI MMC/SD driver).
|
||||||
|
*
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#ifdef CONFIG_IMX6_ECSPI1
|
||||||
|
void imx_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||||
|
uint8_t imx_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||||
|
#ifdef CONFIG_SPI_CMDDATA
|
||||||
|
int imx_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_IMX6_ECSPI2
|
||||||
|
void imx_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||||
|
uint8_t imx_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||||
|
#ifdef CONFIG_SPI_CMDDATA
|
||||||
|
int imx_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_IMX6_ECSPI3
|
||||||
|
void imx_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||||
|
uint8_t imx_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||||
|
#ifdef CONFIG_SPI_CMDDATA
|
||||||
|
int imx_spi3cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_IMX6_ECSPI4
|
||||||
|
void imx_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||||
|
uint8_t imx_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||||
|
#ifdef CONFIG_SPI_CMDDATA
|
||||||
|
int imx_spi4cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_IMX6_ECSPI5
|
||||||
|
void imx_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||||
|
uint8_t imx_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||||
|
#ifdef CONFIG_SPI_CMDDATA
|
||||||
|
int imx_spi5cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#undef EXTERN
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif /* __cplusplus */
|
||||||
|
#endif /* __ASSEMBLY__ */
|
||||||
|
|
||||||
|
#endif /* __ARCH_ARM_IMX6_ECSPI_H */
|
||||||
@@ -131,42 +131,42 @@ config KINETIS_FLEXBUS
|
|||||||
config KINETIS_UART0
|
config KINETIS_UART0
|
||||||
bool "UART0"
|
bool "UART0"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART0
|
select UART0_SERIALDRIVER
|
||||||
---help---
|
---help---
|
||||||
Support UART0
|
Support UART0
|
||||||
|
|
||||||
config KINETIS_UART1
|
config KINETIS_UART1
|
||||||
bool "UART1"
|
bool "UART1"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART1
|
select UART1_SERIALDRIVER
|
||||||
---help---
|
---help---
|
||||||
Support UART1
|
Support UART1
|
||||||
|
|
||||||
config KINETIS_UART2
|
config KINETIS_UART2
|
||||||
bool "UART2"
|
bool "UART2"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART2
|
select UART2_SERIALDRIVER
|
||||||
---help---
|
---help---
|
||||||
Support UART2
|
Support UART2
|
||||||
|
|
||||||
config KINETIS_UART3
|
config KINETIS_UART3
|
||||||
bool "UART3"
|
bool "UART3"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART3
|
select UART3_SERIALDRIVER
|
||||||
---help---
|
---help---
|
||||||
Support UART3
|
Support UART3
|
||||||
|
|
||||||
config KINETIS_UART4
|
config KINETIS_UART4
|
||||||
bool "UART4"
|
bool "UART4"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART4
|
select UART4_SERIALDRIVER
|
||||||
---help---
|
---help---
|
||||||
Support UART4
|
Support UART4
|
||||||
|
|
||||||
config KINETIS_UART5
|
config KINETIS_UART5
|
||||||
bool "UART5"
|
bool "UART5"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART5
|
select UART5_SERIALDRIVER
|
||||||
---help---
|
---help---
|
||||||
Support UART5
|
Support UART5
|
||||||
|
|
||||||
|
|||||||
@@ -1,8 +1,7 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* arch/arm/src/kinetis/kinetis_clockconfig.c
|
* arch/arm/src/kinetis/kinetis_clockconfig.c
|
||||||
* arch/arm/src/chip/kinetis_clockconfig.c
|
|
||||||
*
|
*
|
||||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
@@ -66,14 +65,6 @@
|
|||||||
void __ramfunc__
|
void __ramfunc__
|
||||||
kinesis_setdividers(uint32_t div1, uint32_t div2, uint32_t div3, uint32_t div4);
|
kinesis_setdividers(uint32_t div1, uint32_t div2, uint32_t div3, uint32_t div4);
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Data
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Public Data
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Private Functions
|
* Private Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -133,7 +124,11 @@ void kinetis_pllconfig(void)
|
|||||||
* RANGE = 2 (Oscillator of 8 MHz to 32 MHz)
|
* RANGE = 2 (Oscillator of 8 MHz to 32 MHz)
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#ifdef BOARD_EXTAL_LP
|
||||||
|
putreg8(MCG_C2_EREFS | MCG_C2_RANGE_VHIGH, KINETIS_MCG_C2);
|
||||||
|
#else
|
||||||
putreg8(MCG_C2_EREFS | MCG_C2_HGO | MCG_C2_RANGE_VHIGH, KINETIS_MCG_C2);
|
putreg8(MCG_C2_EREFS | MCG_C2_HGO | MCG_C2_RANGE_VHIGH, KINETIS_MCG_C2);
|
||||||
|
#endif /* BOARD_EXTAL_LP */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Released latched state of oscillator and GPIO */
|
/* Released latched state of oscillator and GPIO */
|
||||||
@@ -156,7 +151,11 @@ void kinetis_pllconfig(void)
|
|||||||
* CLKS = 2 (Clock Source Select, External reference clock)
|
* CLKS = 2 (Clock Source Select, External reference clock)
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#ifdef BOARD_FRDIV
|
||||||
|
putreg8(BOARD_FRDIV | MCG_C1_CLKS_EXTREF, KINETIS_MCG_C1);
|
||||||
|
#else
|
||||||
putreg8(MCG_C1_FRDIV_DIV256 | MCG_C1_CLKS_EXTREF, KINETIS_MCG_C1);
|
putreg8(MCG_C1_FRDIV_DIV256 | MCG_C1_CLKS_EXTREF, KINETIS_MCG_C1);
|
||||||
|
#endif
|
||||||
|
|
||||||
/* If we aren't using an oscillator input we don't need to wait for the
|
/* If we aren't using an oscillator input we don't need to wait for the
|
||||||
* oscillator to initialize
|
* oscillator to initialize
|
||||||
|
|||||||
@@ -165,9 +165,9 @@ struct kinetis_driver_s
|
|||||||
struct enet_desc_s *txdesc; /* A pointer to the list of TX descriptor */
|
struct enet_desc_s *txdesc; /* A pointer to the list of TX descriptor */
|
||||||
struct enet_desc_s *rxdesc; /* A pointer to the list of RX descriptors */
|
struct enet_desc_s *rxdesc; /* A pointer to the list of RX descriptors */
|
||||||
|
|
||||||
/* This holds the information visible to uIP/NuttX */
|
/* This holds the information visible to the NuttX network */
|
||||||
|
|
||||||
struct net_driver_s dev; /* Interface understood by uIP */
|
struct net_driver_s dev; /* Interface understood by the network */
|
||||||
|
|
||||||
/* The DMA descriptors. A unaligned uint8_t is used to allocate the
|
/* The DMA descriptors. A unaligned uint8_t is used to allocate the
|
||||||
* memory; 16 is added to assure that we can meet the descriptor alignment
|
* memory; 16 is added to assure that we can meet the descriptor alignment
|
||||||
@@ -435,7 +435,7 @@ static int kinetis_transmit(FAR struct kinetis_driver_s *priv)
|
|||||||
* Function: kinetis_txpoll
|
* Function: kinetis_txpoll
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* The transmitter is available, check if uIP has any outgoing packets ready
|
* The transmitter is available, check if the network has any outgoing packets ready
|
||||||
* to send. This is a callback from devif_poll(). devif_poll() may be called:
|
* to send. This is a callback from devif_poll(). devif_poll() may be called:
|
||||||
*
|
*
|
||||||
* 1. When the preceding TX packet send is complete,
|
* 1. When the preceding TX packet send is complete,
|
||||||
@@ -731,7 +731,7 @@ static void kinetis_txdone(FAR struct kinetis_driver_s *priv)
|
|||||||
putreg32(regval, KINETIS_ENET_EIMR);
|
putreg32(regval, KINETIS_ENET_EIMR);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* There should be space for a new TX in any event. Poll uIP for new XMIT
|
/* There should be space for a new TX in any event. Poll the network for new XMIT
|
||||||
* data
|
* data
|
||||||
*/
|
*/
|
||||||
|
|
||||||
@@ -848,7 +848,7 @@ static void kinetis_txtimeout(int argc, uint32_t arg, ...)
|
|||||||
(void)kinetis_ifdown(&priv->dev);
|
(void)kinetis_ifdown(&priv->dev);
|
||||||
(void)kinetis_ifup(&priv->dev);
|
(void)kinetis_ifup(&priv->dev);
|
||||||
|
|
||||||
/* Then poll uIP for new XMIT data */
|
/* Then poll the network for new XMIT data */
|
||||||
|
|
||||||
(void)devif_poll(&priv->dev, kinetis_txpoll);
|
(void)devif_poll(&priv->dev, kinetis_txpoll);
|
||||||
}
|
}
|
||||||
@@ -881,7 +881,7 @@ static void kinetis_polltimer(int argc, uint32_t arg, ...)
|
|||||||
|
|
||||||
if (!kinetics_txringfull(priv))
|
if (!kinetics_txringfull(priv))
|
||||||
{
|
{
|
||||||
/* If so, update TCP timing states and poll uIP for new XMIT data. Hmmm..
|
/* If so, update TCP timing states and poll the network for new XMIT data. Hmmm..
|
||||||
* might be bug here. Does this mean if there is a transmit in progress,
|
* might be bug here. Does this mean if there is a transmit in progress,
|
||||||
* we will missing TCP time state updates?
|
* we will missing TCP time state updates?
|
||||||
*/
|
*/
|
||||||
@@ -1112,7 +1112,7 @@ static int kinetis_txavail(struct net_driver_s *dev)
|
|||||||
|
|
||||||
if (!kinetics_txringfull(priv))
|
if (!kinetics_txringfull(priv))
|
||||||
{
|
{
|
||||||
/* No, there is space for another transfer. Poll uIP for new
|
/* No, there is space for another transfer. Poll the network for new
|
||||||
* XMIT data.
|
* XMIT data.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
@@ -1,7 +1,7 @@
|
|||||||
/********************************************************************************************
|
/********************************************************************************************
|
||||||
* arch/arm/src/kinetis/kinetis_usbotg.h
|
* arch/arm/src/kinetis/kinetis_usbotg.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
@@ -217,6 +217,8 @@
|
|||||||
#define USB_INT_ATTACH (1 << 6) /* Bit 6: Attach Interrupt */
|
#define USB_INT_ATTACH (1 << 6) /* Bit 6: Attach Interrupt */
|
||||||
#define USB_INT_STALL (1 << 7) /* Bit 7: Stall Interrupt */
|
#define USB_INT_STALL (1 << 7) /* Bit 7: Stall Interrupt */
|
||||||
|
|
||||||
|
#define USB_INT_ALL 0xFF
|
||||||
|
|
||||||
/* Error Interrupt Status Register and Error Interrupt Enable Register (8-bit) */
|
/* Error Interrupt Status Register and Error Interrupt Enable Register (8-bit) */
|
||||||
|
|
||||||
#define USB_ERRSTAT_PIDERR (1 << 0) /* Bit 0: This bit is set when the PID check field fails */
|
#define USB_ERRSTAT_PIDERR (1 << 0) /* Bit 0: This bit is set when the PID check field fails */
|
||||||
@@ -228,6 +230,8 @@
|
|||||||
/* Bit 6: Reserved */
|
/* Bit 6: Reserved */
|
||||||
#define USB_ERRSTAT_BTSERR (1 << 7) /* Bit 7: Bit stuff error is detected */
|
#define USB_ERRSTAT_BTSERR (1 << 7) /* Bit 7: Bit stuff error is detected */
|
||||||
|
|
||||||
|
#define USB_EINT_ALL 0xBF
|
||||||
|
|
||||||
/* Status Register (8-bit) */
|
/* Status Register (8-bit) */
|
||||||
|
|
||||||
/* Bits 0-1: Reserved */
|
/* Bits 0-1: Reserved */
|
||||||
@@ -259,6 +263,7 @@
|
|||||||
#define USB_BDTPAGE1_MASK (0x7f << USB_BDTPAGE1_SHIFT)
|
#define USB_BDTPAGE1_MASK (0x7f << USB_BDTPAGE1_SHIFT)
|
||||||
|
|
||||||
/* Frame Number Register Low (8-bit, bits 0-7 of the 11 bit frame number) */
|
/* Frame Number Register Low (8-bit, bits 0-7 of the 11 bit frame number) */
|
||||||
|
#define USB_FRMNUML_MASK 0xFF
|
||||||
/* Frame Number Register High (8-bit) */
|
/* Frame Number Register High (8-bit) */
|
||||||
/* Bits 3-7: Reserved */
|
/* Bits 3-7: Reserved */
|
||||||
#define USB_FRMNUMH_SHIFT (0) /* Bits 0-2: Bits 8-10 of the 11-bit frame number */
|
#define USB_FRMNUMH_SHIFT (0) /* Bits 0-2: Bits 8-10 of the 11-bit frame number */
|
||||||
@@ -313,16 +318,58 @@
|
|||||||
#define USB_USBTRC0_SYNC_DET (1 << 1) /* Bit 1: Synchronous USB Interrupt Detect */
|
#define USB_USBTRC0_SYNC_DET (1 << 1) /* Bit 1: Synchronous USB Interrupt Detect */
|
||||||
#define USB_USBTRC0_RESUME_INT (1 << 0) /* Bit 0: USB Asynchronous Interrupt */
|
#define USB_USBTRC0_RESUME_INT (1 << 0) /* Bit 0: USB Asynchronous Interrupt */
|
||||||
|
|
||||||
/********************************************************************************************
|
/* Buffer Descriptor Table (BDT) ****************************************************/
|
||||||
* Public Types
|
/* Offset 0: On write (software->hardware) */
|
||||||
********************************************************************************************/
|
|
||||||
|
|
||||||
/********************************************************************************************
|
#define USB_BDT_STATUS_MASK 0xfc /* Bits 2-7: Status bits */
|
||||||
* Public Data
|
#define USB_BDT_BSTALL (1 << 2) /* Bit 2: Buffer Stall Enable bit */
|
||||||
********************************************************************************************/
|
#define USB_BDT_DTS (1 << 3) /* Bit 3: Data Toggle Synchronization Enable bit */
|
||||||
|
#define USB_BDT_NINC (1 << 4) /* Bit 4: DMA Address Increment Disable bit */
|
||||||
|
#define USB_BDT_KEEP (1 << 5) /* Bit 5: BD Keep Enable bit */
|
||||||
|
#define USB_BDT_DATA01 (1 << 6) /* Bit 6: Data Toggle Packet bit */
|
||||||
|
#define USB_BDT_UOWN (1 << 7) /* Bit 7: USB Own bit */
|
||||||
|
#define USB_BDT_BYTECOUNT_SHIFT (16) /* Bits 16-25: Byte Count bits */
|
||||||
|
#define USB_BDT_BYTECOUNT_MASK (0x3ff << USB_BDT_BYTECOUNT_SHIFT)
|
||||||
|
|
||||||
|
#define USB_BDT_DATA0 0 /* DATA0 packet expected next */
|
||||||
|
#define USB_BDT_DATA1 USB_BDT_DATA01 /* DATA1 packet expected next */
|
||||||
|
#define USB_BDT_COWN 0 /* CPU owns the descriptor */
|
||||||
|
|
||||||
|
/* Offset 0: On read (hardware->software) */
|
||||||
|
|
||||||
|
#define USB_BDT_PID_SHIFT (2) /* Bits 2-5: Packet Identifier bits */
|
||||||
|
#define USB_BDT_PID_MASK (15 << USB_BDT_PID_SHIFT)
|
||||||
|
/* Bit 7: USB Own bit (same) */
|
||||||
|
/* Bits 16-25: Byte Count bits (same) */
|
||||||
|
|
||||||
|
/* Offset 4: BUFFER_ADDRESS, 32-bit Buffer Address bits */
|
||||||
|
|
||||||
|
#define USB_BDT_BYTES_SIZE 8 /* Eight bytes per BDT */
|
||||||
|
#define USB_BDT_WORD_SIZE 2 /* Two 32-bit words per BDT */
|
||||||
|
#define USB_NBDTS_PER_EP 4 /* Number of BDTS per endpoint: IN/OUT and EVEN/ODD */
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Public Types
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ASSEMBLY__
|
||||||
|
|
||||||
|
/* Buffer Descriptor Status Register layout. */
|
||||||
|
|
||||||
|
struct usbotg_bdtentry_s
|
||||||
|
{
|
||||||
|
uint32_t status; /* Status, byte count, and PID */
|
||||||
|
uint8_t *addr; /* Buffer address */
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
/********************************************************************************************
|
/********************************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
********************************************************************************************/
|
********************************************************************************************/
|
||||||
|
|
||||||
|
struct usbdev_s;
|
||||||
|
int kinetis_usbpullup(FAR struct usbdev_s *dev, bool enable);
|
||||||
|
void kinetis_usbsuspend(FAR struct usbdev_s *dev, bool resume);
|
||||||
|
void khci_usbattach(void);
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_USBOTG_H */
|
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_USBOTG_H */
|
||||||
|
|||||||
@@ -47,21 +47,21 @@ config KL_FLEXBUS
|
|||||||
config KL_UART0
|
config KL_UART0
|
||||||
bool "UART0"
|
bool "UART0"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART0
|
select UART0_SERIALDRIVER
|
||||||
---help---
|
---help---
|
||||||
Support UART0
|
Support UART0
|
||||||
|
|
||||||
config KL_UART1
|
config KL_UART1
|
||||||
bool "UART1"
|
bool "UART1"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART1
|
select UART1_SERIALDRIVER
|
||||||
---help---
|
---help---
|
||||||
Support UART1
|
Support UART1
|
||||||
|
|
||||||
config KL_UART2
|
config KL_UART2
|
||||||
bool "UART2"
|
bool "UART2"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART2
|
select UART2_SERIALDRIVER
|
||||||
---help---
|
---help---
|
||||||
Support UART2
|
Support UART2
|
||||||
|
|
||||||
|
|||||||
@@ -70,7 +70,7 @@ CMN_CSRCS += up_dumpnvic.c
|
|||||||
endif
|
endif
|
||||||
|
|
||||||
CHIP_ASRCS =
|
CHIP_ASRCS =
|
||||||
CHIP_CSRCS = kl_clockconfig.c kl_gpio.c kl_idle.c kl_irq.c kl_lowgetc.c
|
CHIP_CSRCS = kl_clockconfig.c kl_gpio.c kl_idle.c kl_irq.c kl_getc.c
|
||||||
CHIP_CSRCS += kl_lowputc.c kl_serial.c kl_start.c kl_cfmconfig.c
|
CHIP_CSRCS += kl_lowputc.c kl_serial.c kl_start.c kl_cfmconfig.c
|
||||||
|
|
||||||
ifneq ($(CONFIG_SCHED_TICKLESS),y)
|
ifneq ($(CONFIG_SCHED_TICKLESS),y)
|
||||||
|
|||||||
@@ -1,7 +1,7 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* arch/arm/src/kl/kl_lowgetc.c
|
* arch/arm/src/kl/kl_getc.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
@@ -41,75 +41,42 @@
|
|||||||
|
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
|
||||||
#include <arch/irq.h>
|
|
||||||
#include <arch/board/board.h>
|
|
||||||
|
|
||||||
#include "up_internal.h"
|
|
||||||
#include "up_arch.h"
|
#include "up_arch.h"
|
||||||
|
|
||||||
#include "kl_config.h"
|
#include "kl_config.h"
|
||||||
#include "kl_lowgetc.h"
|
#include "kl_getc.h"
|
||||||
|
|
||||||
#include "chip/kl_uart.h"
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
/* Select UART parameters for the selected console */
|
/* Select UART parameters for the selected console */
|
||||||
|
|
||||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
|
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
|
||||||
# define CONSOLE_BASE KL_UART0_BASE
|
# define CONSOLE_BASE KL_UART0_BASE
|
||||||
# define CONSOLE_FREQ BOARD_CORECLK_FREQ
|
|
||||||
# define CONSOLE_BAUD CONFIG_UART0_BAUD
|
|
||||||
# define CONSOLE_BITS CONFIG_UART0_BITS
|
|
||||||
# define CONSOLE_PARITY CONFIG_UART0_PARITY
|
|
||||||
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
|
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
|
||||||
# define CONSOLE_BASE KL_UART1_BASE
|
# define CONSOLE_BASE KL_UART1_BASE
|
||||||
# define CONSOLE_FREQ BOARD_BUSCLK_FREQ
|
|
||||||
# define CONSOLE_BAUD CONFIG_UART1_BAUD
|
|
||||||
# define CONSOLE_BITS CONFIG_UART1_BITS
|
|
||||||
# define CONSOLE_PARITY CONFIG_UART1_PARITY
|
|
||||||
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
|
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
|
||||||
# define CONSOLE_BASE KL_UART2_BASE
|
# define CONSOLE_BASE KL_UART2_BASE
|
||||||
# define CONSOLE_FREQ BOARD_BUSCLK_FREQ
|
|
||||||
# define CONSOLE_BAUD CONFIG_UART2_BAUD
|
|
||||||
# define CONSOLE_BITS CONFIG_UART2_BITS
|
|
||||||
# define CONSOLE_PARITY CONFIG_UART2_PARITY
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Types
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Function Prototypes
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Public Data
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Data
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Functions
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: up_lowgetc
|
* Name: up_getc
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Input one byte from the serial console
|
* Input one byte from the serial console
|
||||||
*
|
*
|
||||||
|
* REVIST: If used with the serial driver enabled, then this could
|
||||||
|
* interfere with the serial driver operations. Serial interrupts should
|
||||||
|
* be disabled when this function executes in that case.
|
||||||
|
*
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
int kl_lowgetc(void)
|
int up_getc(void)
|
||||||
{
|
{
|
||||||
uint8_t ch = 0;
|
uint8_t ch = 0;
|
||||||
|
|
||||||
@@ -118,11 +85,11 @@ int kl_lowgetc(void)
|
|||||||
* we have data in the buffer to read.
|
* we have data in the buffer to read.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
while ((getreg8(CONSOLE_BASE+KL_UART_S1_OFFSET) & UART_S1_RDRF) == 0);
|
while ((getreg8(CONSOLE_BASE + KL_UART_S1_OFFSET) & UART_S1_RDRF) == 0);
|
||||||
|
|
||||||
/* Then read a character from the UART data register */
|
/* Then read a character from the UART data register */
|
||||||
|
|
||||||
ch = getreg8(CONSOLE_BASE+KL_UART_D_OFFSET);
|
ch = getreg8(CONSOLE_BASE + KL_UART_D_OFFSET);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
return (int)ch;
|
return (int)ch;
|
||||||
@@ -0,0 +1,48 @@
|
|||||||
|
/************************************************************************************
|
||||||
|
* arch/arm/src/kl/kl_getc.h
|
||||||
|
*
|
||||||
|
* Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
|
||||||
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||||
|
* used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||||
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||||
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ARCH_ARM_SRC_KL_KINETIS_GETC_H
|
||||||
|
#define __ARCH_ARM_SRC_KL_KINETIS_GETC_H
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Included Files
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#include <nuttx/config.h>
|
||||||
|
|
||||||
|
#include "kl_config.h"
|
||||||
|
#include "chip/kl_uart.h"
|
||||||
|
|
||||||
|
#endif /* __ARCH_ARM_SRC_KL_KINETIS_GETC_H */
|
||||||
@@ -1,7 +1,7 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* arch/arm/src/kl/kl_serial.c
|
* arch/arm/src/kl/kl_serial.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2013-2012 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2013-2012, 2016 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
@@ -59,15 +59,14 @@
|
|||||||
|
|
||||||
#include "kl_config.h"
|
#include "kl_config.h"
|
||||||
#include "kl_lowputc.h"
|
#include "kl_lowputc.h"
|
||||||
#include "kl_lowgetc.h"
|
|
||||||
#include "chip.h"
|
#include "chip.h"
|
||||||
#include "kl_gpio.h"
|
#include "kl_gpio.h"
|
||||||
#include "chip/kl_uart.h"
|
#include "chip/kl_uart.h"
|
||||||
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
/* Some sanity checks *******************************************************/
|
/* Some sanity checks *******************************************************/
|
||||||
/* Is there at least one UART enabled and configured as a RS-232 device? */
|
/* Is there at least one UART enabled and configured as a RS-232 device? */
|
||||||
|
|
||||||
@@ -958,18 +957,4 @@ int up_putc(int ch)
|
|||||||
return ch;
|
return ch;
|
||||||
}
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: up_getc
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Provide priority, low-level access to support OS debug writes
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
int up_getc(void)
|
|
||||||
{
|
|
||||||
/* Check for LF */
|
|
||||||
|
|
||||||
return kl_lowgetc();
|
|
||||||
}
|
|
||||||
#endif /* USE_SERIALDRIVER */
|
#endif /* USE_SERIALDRIVER */
|
||||||
|
|||||||
@@ -55,7 +55,7 @@ config LPC11_PLL
|
|||||||
|
|
||||||
config LPC11_UART0
|
config LPC11_UART0
|
||||||
bool "UART0"
|
bool "UART0"
|
||||||
select ARCH_HAVE_UART0
|
select UART0_SERIALDRIVER
|
||||||
default y
|
default y
|
||||||
|
|
||||||
config LPC11_CAN0
|
config LPC11_CAN0
|
||||||
|
|||||||
@@ -71,7 +71,7 @@ endif
|
|||||||
|
|
||||||
CHIP_ASRCS =
|
CHIP_ASRCS =
|
||||||
CHIP_CSRCS = lpc11_clockconfig.c lpc11_gpio.c lpc11_i2c.c lpc11_idle.c
|
CHIP_CSRCS = lpc11_clockconfig.c lpc11_gpio.c lpc11_i2c.c lpc11_idle.c
|
||||||
CHIP_CSRCS += lpc11_irq.c lpc11_lowputc.c lpc11_lowgetc.c lpc11_serial.c
|
CHIP_CSRCS += lpc11_irq.c lpc11_lowputc.c lpc11_getc.c lpc11_serial.c
|
||||||
CHIP_CSRCS += lpc11_spi.c lpc11_ssp.c lpc11_start.c
|
CHIP_CSRCS += lpc11_spi.c lpc11_ssp.c lpc11_start.c
|
||||||
|
|
||||||
# Configuration-dependent LPC11xx files
|
# Configuration-dependent LPC11xx files
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* arch/arm/src/lpc11/lpc11_lowgetc.c
|
* arch/arm/src/lpc11/lpc11_getc.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||||
@@ -41,77 +41,41 @@
|
|||||||
|
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
|
||||||
#include <arch/irq.h>
|
|
||||||
#include <arch/board/board.h>
|
|
||||||
|
|
||||||
#include "up_internal.h"
|
|
||||||
#include "up_arch.h"
|
#include "up_arch.h"
|
||||||
|
|
||||||
#include "chip/lpc11_syscon.h"
|
#include "lpc11_getc.h"
|
||||||
#include "chip/lpc11_uart.h"
|
|
||||||
|
|
||||||
#include "lpc11_gpio.h"
|
|
||||||
#include "lpc11_lowgetc.h"
|
|
||||||
#include "lpc11_serial.h"
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
/* Select UART parameters for the selected console */
|
/* Select UART parameters for the selected console */
|
||||||
|
|
||||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
|
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
|
||||||
# define CONSOLE_BASE LPC11_UART0_BASE
|
# define CONSOLE_BASE LPC11_UART0_BASE
|
||||||
# define CONSOLE_FREQ BOARD_CORECLK_FREQ
|
|
||||||
# define CONSOLE_BAUD CONFIG_UART0_BAUD
|
|
||||||
# define CONSOLE_BITS CONFIG_UART0_BITS
|
|
||||||
# define CONSOLE_PARITY CONFIG_UART0_PARITY
|
|
||||||
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
|
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
|
||||||
# define CONSOLE_BASE LPC11_UART1_BASE
|
# define CONSOLE_BASE LPC11_UART1_BASE
|
||||||
# define CONSOLE_FREQ BOARD_BUSCLK_FREQ
|
|
||||||
# define CONSOLE_BAUD CONFIG_UART1_BAUD
|
|
||||||
# define CONSOLE_BITS CONFIG_UART1_BITS
|
|
||||||
# define CONSOLE_PARITY CONFIG_UART1_PARITY
|
|
||||||
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
|
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
|
||||||
# define CONSOLE_BASE LPC11_UART2_BASE
|
# define CONSOLE_BASE LPC11_UART2_BASE
|
||||||
# define CONSOLE_FREQ BOARD_BUSCLK_FREQ
|
|
||||||
# define CONSOLE_BAUD CONFIG_UART2_BAUD
|
|
||||||
# define CONSOLE_BITS CONFIG_UART2_BITS
|
|
||||||
# define CONSOLE_PARITY CONFIG_UART2_PARITY
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Types
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Function Prototypes
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Public Data
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Data
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Private Functions
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: up_lowgetc
|
* Name: up_getc
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Input one byte from the serial console
|
* Input one byte from the serial console.
|
||||||
|
*
|
||||||
|
* REVIST: If used with the serial driver enabled, then this could
|
||||||
|
* interfere with the serial driver operations. Serial interrupts should
|
||||||
|
* be disabled when this function executes in that case.
|
||||||
*
|
*
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
int lpc11_lowgetc(void)
|
int up_getc(void)
|
||||||
{
|
{
|
||||||
uint8_t ch = 0;
|
uint8_t ch = 0;
|
||||||
|
|
||||||
@@ -0,0 +1,47 @@
|
|||||||
|
/************************************************************************************
|
||||||
|
* arch/arm/src/lpc11/lpc11_getc.h
|
||||||
|
*
|
||||||
|
* Copyright (C) 2015, 2016 Gregory Nutt. All rights reserved.
|
||||||
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||||
|
* used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||||
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||||
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_GETC_H
|
||||||
|
#define __ARCH_ARM_SRC_LPC11XX_LPC11_GETC_H
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Included Files
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#include <nuttx/config.h>
|
||||||
|
#include "lpc11_serial.h"
|
||||||
|
#include "chip/lpc11_uart.h"
|
||||||
|
|
||||||
|
#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_GETC_H */
|
||||||
@@ -64,7 +64,6 @@
|
|||||||
#include "chip.h"
|
#include "chip.h"
|
||||||
#include "chip/lpc11_uart.h"
|
#include "chip/lpc11_uart.h"
|
||||||
#include "lpc11_gpio.h"
|
#include "lpc11_gpio.h"
|
||||||
#include "lpc11_lowgetc.h"
|
|
||||||
#include "lpc11_serial.h"
|
#include "lpc11_serial.h"
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
@@ -1041,19 +1040,4 @@ int up_putc(int ch)
|
|||||||
return ch;
|
return ch;
|
||||||
}
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: up_getc
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Provide priority, low-level access to support OS debug writes
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
int up_getc(void)
|
|
||||||
{
|
|
||||||
/* Check for LF */
|
|
||||||
|
|
||||||
return lpc11_lowgetc();
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* USE_SERIALDRIVER */
|
#endif /* USE_SERIALDRIVER */
|
||||||
|
|||||||
@@ -172,36 +172,36 @@ config LPC17_SDCARD
|
|||||||
config LPC17_UART0
|
config LPC17_UART0
|
||||||
bool "UART0"
|
bool "UART0"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART0
|
select UART0_SERIALDRIVER
|
||||||
select ARCH_HAVE_SERIAL_TERMIOS
|
select ARCH_HAVE_SERIAL_TERMIOS
|
||||||
|
|
||||||
config LPC17_UART1
|
config LPC17_UART1
|
||||||
bool "UART1"
|
bool "UART1"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART1
|
select UART1_SERIALDRIVER
|
||||||
select ARCH_HAVE_SERIAL_TERMIOS
|
select ARCH_HAVE_SERIAL_TERMIOS
|
||||||
|
|
||||||
config LPC17_UART2
|
config LPC17_UART2
|
||||||
bool "UART2"
|
bool "UART2"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART2
|
select UART2_SERIALDRIVER
|
||||||
select ARCH_HAVE_SERIAL_TERMIOS
|
select ARCH_HAVE_SERIAL_TERMIOS
|
||||||
|
|
||||||
config LPC17_UART3
|
config LPC17_UART3
|
||||||
bool "UART3"
|
bool "UART3"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART3
|
select UART3_SERIALDRIVER
|
||||||
select ARCH_HAVE_SERIAL_TERMIOS
|
select ARCH_HAVE_SERIAL_TERMIOS
|
||||||
|
|
||||||
config LPC17_UART4
|
config LPC17_UART4
|
||||||
bool "UART4"
|
bool "UART4"
|
||||||
default n
|
default n
|
||||||
select ARCH_HAVE_UART4
|
select UART4_SERIALDRIVER
|
||||||
select ARCH_HAVE_SERIAL_TERMIOS
|
select ARCH_HAVE_SERIAL_TERMIOS
|
||||||
|
|
||||||
config LPC17_CAN1
|
config LPC17_CAN1
|
||||||
bool "CAN1"
|
bool "CAN1"
|
||||||
select ARCH_HAVE_UART4
|
select UART4_SERIALDRIVER
|
||||||
default n
|
default n
|
||||||
|
|
||||||
config LPC17_CAN2
|
config LPC17_CAN2
|
||||||
|
|||||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user