Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-06-06 08:36:24 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

Squashed commit of the following:

Browse Source 
arch/arm/src/samd5e5:  Completes GCLK configuration logic.  Still FDPLL and FDLL support.
    arch/arm/src/samd5e5:  A little more GCLK configuratino logic.  Still incomplete.
    arch/arm/src/smad5e5:  Beginning of GCLK configuration logic.
    arch/arm/src/samd5e5:  Add MCLK configuration logic.
    arch/arm/src/samd5e5:  Add XOSC0/1 configuration logic.
    arch/arm/src/samd5e5:  Add XOSC32 configuration logic.
    arch/arm/src/samd5e5:  Rip out all of the leveraged clock configuration logic and start from scratch.
This commit is contained in:
Gregory Nutt
2018-07-27 15:52:02 -06:00
parent 01eec62598
commit 6e1c292400
18 changed files with 1048 additions and 1711 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/samd5e5/Kconfig
-14
View File
@@ -474,20 +474,6 @@ config SAMD5E5_DMAC_NDESC
Each additional DMA descriptor will require 16-bytes for LPRAM
memory.
config SAMD5E5_EIC_CLKGEN
int "EIC Clock Generator"
default 2
range 0 11
---help---
Some optional functions need a peripheral clock, which can either be
a generic clock (GCLK_EIC, for wider frequency selection) or a Ultra
Low Power 32KHz clock (CLK_ULP32K, for highest power efficiency). One
of the clock sources must be configured and enabled before using the
peripheral.
This option assumes that GCLK will be used and provides the GCL
number to be used
choice
prompt "SERCOM0 mode"
default SAMD5E5_SERCOM0_ISUSART
arch/arm/src/samd5e5/Make.defs
+2 -5
View File
@@ -87,11 +87,8 @@ endif
# Required SAMD5x/E5x files
CHIP_ASRCS =
# REVISIT: sam_clockconfig.c and sam_eic.c
#CHIP_CSRCS = sam_clockconfig.c sam_cmcc.c sam_gclk.c sam_irq.c
CHIP_CSRCS = sam_cmcc.c sam_gclk.c sam_irq.c
CHIP_CSRCS += sam_lowputc.c sam_port.c sam_serial.c sam_start.c
CHIP_CSRCS += sam_supc.c sam_usart.c
CHIP_CSRCS = sam_clockconfig.c sam_cmcc.c sam_eic.c sam_gclk.c sam_irq.c
CHIP_CSRCS += sam_lowputc.c sam_port.c sam_serial.c sam_start.c sam_usart.c
# Configuration-dependent SAMD5x/E5x files
arch/arm/src/samd5e5/chip/sam_eic.h
+6 -6
View File
@@ -145,12 +145,12 @@
#define EIC_CONFIG0_FILTEN(n) (3 + ((n) << 2)) /* Filter n enable, n=0-7 */
#define EIC_CONFIG0_SENSE_SHIFT(n) ((n) << 2) /* Filter n input sense, n=0-7 */
#define EIC_CONFIG0_SENSE_MASK(n) (7 << EIC_CONFIG0_SENSE_SHIFT(n))
# define EIC_CONFIG0_SENSE_NONE (0 << EIC_CONFIG0_SENSE_SHIFT(n)) /* No detection */
# define EIC_CONFIG0_SENSE_RISE (1 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Rising edge detection */
# define EIC_CONFIG0_SENSE_FALL (2 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Falling edge detection */
# define EIC_CONFIG0_SENSE_BOTH (3 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Both edge detection */
# define EIC_CONFIG0_SENSE_HIGH (4 << EIC_CONFIG0_SENSE_SHIFT(n)) /* High level detection */
# define EIC_CONFIG0_SENSE_LOW (5 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Low level detection */
# define EIC_CONFIG0_SENSE_NONE(n) (0 << EIC_CONFIG0_SENSE_SHIFT(n)) /* No detection */
# define EIC_CONFIG0_SENSE_RISE(n) (1 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Rising edge detection */
# define EIC_CONFIG0_SENSE_FALL(n) (2 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Falling edge detection */
# define EIC_CONFIG0_SENSE_BOTH(n) (3 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Both edge detection */
# define EIC_CONFIG0_SENSE_HIGH(n) (4 << EIC_CONFIG0_SENSE_SHIFT(n)) /* High level detection */
# define EIC_CONFIG0_SENSE_LOW(n) (5 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Low level detection */
/* Configuration 1 register */
arch/arm/src/samd5e5/chip/sam_gclk.h
+7 -1
View File
@@ -47,6 +47,10 @@
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
#define SAM_NGLCK 12 /* 12 Clock generators, 0-11 */
#define SAM_NCHANNELS 48 /* 48 Clock generators, 0..47 */
/* GCLK register offsets ********************************************************************/
#define SAM_GCLK_CTRLA_OFFSET 0x0000 /* Control register */
@@ -61,7 +65,7 @@
#define SAM_GCLK_SYNCHBUSY (SAM_GCLK_BASE + SAM_GCLK_SYNCHBUSY_OFFSET)
#define SAM_GCLK_GENCTRL(n) (SAM_GCLK_BASE + SAM_GCLK_GENCTRL_OFFSET(n))
#define SAM_GCLK_PCHCTRL(m) (SAM_GCLK_BASE + SAM_GCLK_PCHCTRL_OFFSET(m))
#define SAM_GCLK_PCHCTRL(n) (SAM_GCLK_BASE + SAM_GCLK_PCHCTRL_OFFSET(n))
/* GCLK register bit definitions ************************************************************/
@@ -84,11 +88,13 @@
# define GCLK_SYNCHBUSY_GENCTRL8 (1 << 10) /* Bit 10: Generator control 8 busy */
# define GCLK_SYNCHBUSY_GENCTRL9 (1 << 11) /* Bit 11: Generator control 9 busy */
# define GCLK_SYNCHBUSY_GENCTRL10 (1 << 12) /* Bit 12: Generator control 10 busy */
# define GCLK_SYNCHBUSY_GENCTRL11 (1 << 13) /* Bit 13: Generator control 11 busy */
/* General clock generator n */
#define GCLK_GENCTRL_SRC_SHIFT (0) /* Bits 0-4: Generator source selection */
#define GCLK_GENCTRL_SRC_MASK (31 << GCLK_GENCTRL_SRC_SHIFT)
# define GCLK_GENCTRL_SRC(n) ((uint32_t)(n) << GCLK_GENCTRL_SRC_SHIFT)
# define GCLK_GENCTRL_SRC_XOSC0 (0 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC 0 oscillator input */
# define GCLK_GENCTRL_SRC_XOSC1 (1 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC 1 oscillator input */
# define GCLK_GENCTRL_SRC_GCLK_IN (2 << GCLK_GENCTRL_SRC_SHIFT) /* Generator input pad */
arch/arm/src/samd5e5/chip/sam_osc32kctrl.h
+1
View File
@@ -88,6 +88,7 @@
#define OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT (0) /* Bits 0-2: RTC clock source selection */
#define OSC32KCTRL_RTCCTRL_RTCSEL_MASK (7 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT)
# define OSC32KCTRL_RTCCTRL_RTCSEL(n) ((uint8_t)(n) << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT)
# define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (0 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT) /* 1.024KHz from 32HKz internal ULP oscillator */
# define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (1 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT) /* 32.768KHz from 32KHz internal ULP oscillator */
# define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (4 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT) /* 1.024kHz from 32KHz external oscillator */
arch/arm/src/samd5e5/chip/sam_oscctrl.h
+3
View File
@@ -168,6 +168,9 @@
# define OSCCTRL_XOSCCTRL_STARTUP_250MS (13 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 250000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_500MS (14 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 500000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_1S (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1000000µs */
#define OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT (24) /* Bits 24-27: Clock Failure Detector Prescaler */
#define OSCCTRL_XOSCCTRL_CFDPRESC_MASK (15 << OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT)
# define OSCCTRL_XOSCCTRL_CFDPRESC(n) ((uint32_t)(n) << OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT)
/* DFLL48M control register A */
arch/arm/src/samd5e5/chip/sam_pinmap.h
+4 -5
View File
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MEMORYMAP_H
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PINMAP_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PINMAP_H
/************************************************************************************
* Included Files
@@ -43,10 +43,9 @@
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(ARCH_CHIP_SAME5X)
# include "chip/samd5e5_memorymap.h"
# include "chip/samd5e5_pinmap.h"
#else
# error "Unsupported SAMD5/E5 family"
#endif
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MEMORYMAP_H */
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PINMAP_H */
arch/arm/src/samd5e5/chip/samd5e5_pinmap.h
+3 -3
View File
@@ -33,8 +33,8 @@
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PINMAP_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PINMAP_H
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAMD5E5_PINMAP_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAMD5E5_PINMAP_H
/********************************************************************************************
* Included Files
@@ -787,4 +787,4 @@
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PINMAP_H */
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAMD5E5_PINMAP_H */
arch/arm/src/samd5e5/sam_clockconfig.c
+589 -1209
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/samd5e5/sam_clockconfig.h
+130 -5
View File
@@ -50,6 +50,118 @@
* Public Types
************************************************************************************/
#ifdef BOARD_HAVE_CLKDEFS
/* This structure defines the configuration of the 32.768KHz XOSC32 */
struct sam_xosc32_config_s
{
uint8_t enable : 1; /* True: Enable XOSC32 */
uint8_t highspeed : 1; /* Controls gain of the external oscillator */
uint8_t extalen : 1; /* Crystal oscillator enable
* false: External clock connected on XIN32
* true: Crystal connected to XIN32/XOUT32 */
uint8_t en32k : 1; /* Enable 32KHz output */
uint8_t en1k : 1; /* Enable 1KHz output */
uint8_t runstdby : 1; /* Run in standby */
uint8_t ondemand : 1; /* On-demand control */
uint8_t cfden : 1; /* Clock failure detection */
uint8_t cfdeo : 1; /* Clock failure event enable */
uint8_t caliben : 1; /* OSCULP32K calibration enable */
uint8_t startup; /* Start-up time:
* 0: 62592us 4: 2000092us
* 1: 125092us 5: 4000092us
* 2: 500092us 6: 8000092us
* 3: 1000092us */
uint8_t calib; /* OSCULP32K calibration value (0-31) */
uint8_t rtcsel; /* RTC clock selection
* 0 ULP1K 1.024kHz from 32KHz internal ULP
* oscillator
* 1 ULP32K 32.768kHz from 32KHz internal ULP
* oscillator
* 4 XOSC1K 1.024kHz from 32KHz external
* oscillator
* 5 XOSC32K 32.768kHz from 32KHz external crystal
* oscillator */
};
/* This structure defines the configuration of XOSC0/1 */
struct sam_xosc_config_s
{
uint8_t enable : 1; /* True: Enable XOSC32 */
uint8_t extalen : 1; /* Crystal oscillator enable
* false: External clock connected
* true: Crystal connected */
uint8_t runstdby : 1; /* Run in standby */
uint8_t ondemand : 1; /* On-demand control */
uint8_t lowgain : 1; /* Low buffer gain enable */
uint8_t enalc : 1; /* Automatic loop control enable */
uint8_t cfden : 1; /* Clock failure detection */
uint8_t swben : 1; /* XOSC clock switch enable */
uint8_t startup; /* Start-up time:
* 0 31us 8 7813us
* 1 61us 9 15625us
* 2 122us 10 31250us
* 3 244us 11 62500us
* 4 488us 12 125000us
* 5 977us 13 250000us
* 6 1953us 14 500000us
* 7 3906us 15 1000000us */
uint32_t xosc_frequency; /* XOSC frequency */
};
/* This structure defines the configuration of the FDPLL0/1 */
struct sam_fdpll_config_s
{
};
/* This structure defines the configuration of a GCLK */
struct sam_gclk_config_s
{
uint8_t enable : 1; /* True: Enable GCLK */
uint8_t idc : 1; /* True: Improve duty cycle */
uint8_t oov : 1; /* True: Clock output selection */
uint8_t oe : 1; /* True: Output enable */
uint8_t divsel : 1; /* True: Clock source divider */
uint8_t runstdby : 1; /* Run in standby */
uint8_t source; /* GLCK clock source:
* 0 XOSC 0 oscillator input
* 1 XOSC 1 oscillator input
* 2 Generator input pad
* 3 Generic clock generator 1 output
* 4 OSCULP32K oscillator output
* 5 XOSC32K oscillator output
* 6 DFLL oscillator output
* 7 DPLL0 output
* 8 DPLL1 output */
uint16_t div; /* Division factor: 8-bits for all but GCLK1 */
};
/* This structure defines the configuration of the clock sus-system */
struct sam_clockconfig_s
{
uint8_t waitstates; /* NVM read wait states 9-15 */
uint8_t cpudiv; /* MCLK divider to get CPU frequency */
uint16_t glckset1; /* GLCKs to initialize prior to FDPLL init */
uint16_t glckset2; /* GLCKs to initialize after to FDPLL init */
uint32_t cpu_frequency; /* Resulting CPU frequency */
#if BOARD_HAVE_XOSC32K != 0
struct sam_xosc32_config_s xosc32k; /* XOSC32 configuration */
#endif
#if BOARD_HAVE_XOSC0 != 0
struct sam_xosc_config_s xosc0; /* XOSC0 configuration */
#endif
#if BOARD_HAVE_XOSC1 != 0
struct sam_xosc_config_s xosc1; /* XOSC1 configuration */
#endif
struct sam_fdpll_config_s fdpll[2]; /* FDPLL0/1 configurations */
struct sam_gclk_config_s gclk[12]; /* GLCK configurations */
};
#endif /* BOARD_HAVE_CLKDEFS */
/************************************************************************************
* Inline Functions
************************************************************************************/
@@ -74,16 +186,29 @@ extern "C"
************************************************************************************/
/************************************************************************************
* Name: sam_clockconfig
* Name: sam_clock_configure
*
* Description:
* Called to initialize the SAM3/4. This does whatever setup is needed to put the
* SoC in a usable state. This includes the initialization of clocking using the
* settings in board.h.
* Configure the clock sub-system per the provided configuration data.
*
* This should be called only (1) early in the initialization sequence, or (2)
* later but within a critical section.
*
************************************************************************************/
void sam_clockconfig(void);
struct sam_clockconfig_s;
void sam_clock_configure(const struct sam_clockconfig_s *config);
/************************************************************************************
* Name: sam_clock_initialize
*
* Description:
* Configure the initial power-up clocking. This function may be called
* only once by the power-up reset logic.
*
************************************************************************************/
void sam_clock_initialize(void);
#undef EXTERN
#if defined(__cplusplus)
arch/arm/src/samd5e5/sam_eic.c
+17 -8
View File
@@ -39,8 +39,10 @@
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include "up_arch.h"
#include "sam_gclk.h"
@@ -97,7 +99,7 @@ void sam_eic_dumpregs(void)
{
irqinfo("EIC:\n");
irqinfo(" CTRLA: %02x\n", getreg8(SAM_EIC_CTRLA));
irqinfo(" NMICTRL: %02x\n", getreg8(SAM_EIC_NVMICTRL));
irqinfo(" NMICTRL: %02x\n", getreg8(SAM_EIC_NMICTRL));
irqinfo(" NMIFLAG: %04x\n", getreg16(SAM_EIC_NMIFLAG));
irqinfo(" SYNCBUSY: %08x\n", getreg32(SAM_EIC_SYNCBUSY));
irqinfo(" EVCTRL: %08x\n", getreg32(SAM_EIC_EVCTRL));
@@ -128,21 +130,27 @@ void sam_eic_dumpregs(void)
int sam_eic_initialize(void)
{
uint16_t regval;
uintptr_t regaddr;
uint32_t regval;
/* Configure the EIC APB clock */
sam_apb_eic_enableperiph();
regval = GCLK_CLKCTRL_ID_EIC |
GCLK_CLKCTRL_GEN(CONFIG_SAMD5E5_EIC_GCLKGEN) |
GCLK_CLKCTRL_CLKEN;
/* Use the selected GCLK_EIC. Some optional functions need a peripheral
* clock, which can either be a generic clock (GCLK_EIC, for wider
* frequency selection) or a Ultra Low Power 32KHz clock (CLK_ULP32K, for
* highest power efficiency). One of the clock sources must be configured
* and enabled before using the peripheral.
*/
putreg16(regval, SAM_GCLK_CLKCTRL);
regaddr = SAM_GCLK_PCHCTRL(GCLK_CHAN_EIC);
regval = GCLK_PCHCTRL_GEN(BOARD_GLCK_EIC) | GCLK_PCHCTRL_CHEN;
putreg32(regval, regaddr);
/* Enable the EIC APB clock */
/* Enable the EIC, selecting clocking via the GLCK_EIC */
putreg8(EIC_CTRLA_ENABLE, SAM_EIC_CTRLA);
putreg8(EIC_CTRLA_ENABLE | EIC_CTRLA_ENABLE, SAM_EIC_CTRLA);
sam_eic_syncwait();
sam_eic_dumpregs();
@@ -241,6 +249,7 @@ int sam_eic_irq_ack(int irq)
int eirq = irq - SAM_IRQ_EXTINT0;
putreg32(EIC_EXTINT(eirq), SAM_EIC_INTENCLR);
return OK;
}
#endif /* CONFIG_SAMD5E5_EIC */
arch/arm/src/samd5e5/sam_lowputc.c
+3 -11
View File
@@ -293,18 +293,10 @@ int sam_usart_internal(const struct sam_usart_config_s * const config)
/* Configure the GCLKs for the SERCOM module */
sercom_coreclk_configure(config->sercom, config->gclkgen, false);
sercom_coreclk_configure(config->sercom, config->coregen, false);
if (config->sercom == 5)
{
channel = GCLK_CHAN_SERCOM5_CORE;
}
else
{
channel = config->sercom + GCLK_CHAN_SERCOM0_CORE;
}
sam_gclk_chan_enable(channel, config->gclkgen);
channel = config->sercom + GCLK_CHAN_SERCOM0_CORE;
sam_gclk_chan_enable(channel, config->coregen);
sercom_slowclk_configure(config->sercom, config->slowgen);
arch/arm/src/samd5e5/sam_sercom.h
-1
View File
@@ -47,7 +47,6 @@
#include "up_arch.h"
#include "sam_config.h"
#include "sam_periphclks.h"
#include "chip/sam_sercom.h"
/****************************************************************************
* Pre-processor Definitions
arch/arm/src/samd5e5/sam_serial.c
+15 -8
View File
@@ -782,16 +782,21 @@ static int sam_attach(struct uart_dev_s *dev)
const struct sam_usart_config_s * const config = priv->config;
int ret;
/* Attach and enable the IRQ */
/* Attach and enable the Tx and Rx IRQs */
ret = irq_attach(config->irq, sam_interrupt, dev);
ret = irq_attach(config->txirq, sam_interrupt, dev);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled
* in the USART
*/
ret = irq_attach(config->rxirq, sam_interrupt, dev);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled
* in the USART
*/
up_enable_irq(config->irq);
up_enable_irq(config->txirq);
up_enable_irq(config->rxirq);
}
}
return ret;
@@ -815,11 +820,13 @@ static void sam_detach(struct uart_dev_s *dev)
/* Disable interrupts at the SERCOM device and at the NVIC */
sam_disableallints(priv);
up_disable_irq(config->irq);
up_disable_irq(config->txirq);
up_disable_irq(config->rxirq);
/* Detach the interrupt handler */
irq_detach(config->irq);
irq_detach(config->txirq);
irq_detach(config->rxirq);
}
/****************************************************************************
arch/arm/src/samd5e5/sam_start.c
+10 -8
View File
@@ -94,7 +94,7 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void sam_fpuconfig(void);
static inline void sam_fpu_configure(void);
#endif
#ifdef CONFIG_STACK_COLORATION
static void go_os_start(void *pv, unsigned int nbytes)
@@ -126,7 +126,7 @@ void __start(void) __attribute__ ((no_instrument_function));
#endif
/****************************************************************************
* Name: sam_fpuconfig
* Name: sam_fpu_configure
*
* Description:
* Configure the FPU. Relative bit settings:
@@ -151,7 +151,7 @@ void __start(void) __attribute__ ((no_instrument_function));
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void sam_fpuconfig(void)
static inline void sam_fpu_configure(void)
{
uint32_t regval;
@@ -181,7 +181,7 @@ static inline void sam_fpuconfig(void)
#else
static inline void sam_fpuconfig(void)
static inline void sam_fpu_configure(void)
{
uint32_t regval;
@@ -212,7 +212,7 @@ static inline void sam_fpuconfig(void)
#endif
#else
# define sam_fpuconfig()
# define sam_fpu_configure()
#endif
/****************************************************************************
@@ -312,10 +312,12 @@ void __start(void)
}
#endif
/* Configure the UART so that we can get debug output as soon as possible */
/* Initialize clocking and the FPU. Configure the console UART so that
* we can get debug output as soon as possible.
*/
sam_clockconfig();
sam_fpuconfig();
sam_clock_initialize();
sam_fpu_configure();
sam_lowsetup();
showprogress('A');
arch/arm/src/samd5e5/sam_usart.c
+72 -19
View File
@@ -42,10 +42,13 @@
#include <stdint.h>
#include <assert.h>
#include <arch/irq.h>
#include <arch/samd5e5/chip.h>
#include "sam_pinmap.h"
#include "chip/sam_memorymap.h"
#include "chip/sam_pinmap.h"
#include "sam_gclk.h"
#include "sam_sercom.h"
#include "sam_usart.h"
#include <arch/board/board.h>
@@ -64,9 +67,10 @@ const struct sam_usart_config_s g_usart0config =
.sercom = 0,
.parity = CONFIG_USART0_PARITY,
.bits = CONFIG_USART0_BITS,
.irq = SAM_IRQ_SERCOM0,
.gclkgen = BOARD_SERCOM0_GCLKGEN,
.slowgen = BOARD_SERCOM0_SLOW_GCLKGEN,
.txirq = BOARD_TXIRQ_SERCOM0,
.rxirq = BOARD_RXIRQ_SERCOM0,
.coregen = BOARD_SERCOM0_COREGEN,
.slowgen = BOARD_SERCOM0_SLOWGEN,
.stopbits2 = CONFIG_USART0_2STOP,
.baud = CONFIG_USART0_BAUD,
.pad0 = BOARD_SERCOM0_PINMAP_PAD0,
@@ -85,9 +89,10 @@ const struct sam_usart_config_s g_usart1config =
.sercom = 1,
.parity = CONFIG_USART1_PARITY,
.bits = CONFIG_USART1_BITS,
.irq = SAM_IRQ_SERCOM1,
.gclkgen = BOARD_SERCOM1_GCLKGEN,
.slowgen = BOARD_SERCOM1_SLOW_GCLKGEN,
.txirq = BOARD_TXIRQ_SERCOM1,
.rxirq = BOARD_RXIRQ_SERCOM1,
.coregen = BOARD_SERCOM1_COREGEN,
.slowgen = BOARD_SERCOM1_SLOWGEN,
.stopbits2 = CONFIG_USART1_2STOP,
.baud = CONFIG_USART1_BAUD,
.pad0 = BOARD_SERCOM1_PINMAP_PAD0,
@@ -106,9 +111,10 @@ const struct sam_usart_config_s g_usart2config =
.sercom = 2,
.parity = CONFIG_USART2_PARITY,
.bits = CONFIG_USART2_BITS,
.irq = SAM_IRQ_SERCOM2,
.gclkgen = BOARD_SERCOM2_GCLKGEN,
.slowgen = BOARD_SERCOM2_SLOW_GCLKGEN,
.txirq = BOARD_TXIRQ_SERCOM2,
.rxirq = BOARD_RXIRQ_SERCOM2,
.coregen = BOARD_SERCOM2_COREGEN,
.slowgen = BOARD_SERCOM2_SLOWGEN,
.stopbits2 = CONFIG_USART2_2STOP,
.baud = CONFIG_USART2_BAUD,
.pad0 = BOARD_SERCOM2_PINMAP_PAD0,
@@ -127,9 +133,10 @@ const struct sam_usart_config_s g_usart3config =
.sercom = 3,
.parity = CONFIG_USART3_PARITY,
.bits = CONFIG_USART3_BITS,
.irq = SAM_IRQ_SERCOM3,
.gclkgen = BOARD_SERCOM3_GCLKGEN,
.slowgen = BOARD_SERCOM3_SLOW_GCLKGEN,
.txirq = BOARD_TXIRQ_SERCOM3,
.rxirq = BOARD_RXIRQ_SERCOM3,
.coregen = BOARD_SERCOM3_COREGEN,
.slowgen = BOARD_SERCOM3_SLOWGEN,
.stopbits2 = CONFIG_USART3_2STOP,
.baud = CONFIG_USART3_BAUD,
.pad0 = BOARD_SERCOM3_PINMAP_PAD0,
@@ -148,9 +155,10 @@ const struct sam_usart_config_s g_usart4config =
.sercom = 4,
.parity = CONFIG_USART4_PARITY,
.bits = CONFIG_USART4_BITS,
.irq = SAM_IRQ_SERCOM4,
.gclkgen = BOARD_SERCOM4_GCLKGEN,
.slowgen = BOARD_SERCOM4_SLOW_GCLKGEN,
.txirq = BOARD_TXIRQ_SERCOM4,
.rxirq = BOARD_RXIRQ_SERCOM4,
.coregen = BOARD_SERCOM4_COREGEN,
.slowgen = BOARD_SERCOM4_SLOWGEN,
.stopbits2 = CONFIG_USART4_2STOP,
.baud = CONFIG_USART4_BAUD,
.pad0 = BOARD_SERCOM4_PINMAP_PAD0,
@@ -169,9 +177,10 @@ const struct sam_usart_config_s g_usart5config =
.sercom = 5,
.parity = CONFIG_USART5_PARITY,
.bits = CONFIG_USART5_BITS,
.irq = SAM_IRQ_SERCOM5,
.gclkgen = BOARD_SERCOM5_GCLKGEN,
.slowgen = BOARD_SERCOM5_SLOW_GCLKGEN,
.txirq = BOARD_TXIRQ_SERCOM5,
.rxirq = BOARD_RXIRQ_SERCOM5,
.coregen = BOARD_SERCOM5_COREGEN,
.slowgen = BOARD_SERCOM5_SLOWGEN,
.stopbits2 = CONFIG_USART5_2STOP,
.baud = CONFIG_USART5_BAUD,
.pad0 = BOARD_SERCOM5_PINMAP_PAD0,
@@ -184,6 +193,50 @@ const struct sam_usart_config_s g_usart5config =
};
#endif
#ifdef SAMD5E5_HAVE_USART6
const struct sam_usart_config_s g_usart6config =
{
.sercom = 6,
.parity = CONFIG_USART6_PARITY,
.bits = CONFIG_USART6_BITS,
.txirq = BOARD_TXIRQ_SERCOM6,
.rxirq = BOARD_RXIRQ_SERCOM6,
.coregen = BOARD_SERCOM6_COREGEN,
.slowgen = BOARD_SERCOM6_SLOWGEN,
.stopbits2 = CONFIG_USART6_2STOP,
.baud = CONFIG_USART6_BAUD,
.pad0 = BOARD_SERCOM6_PINMAP_PAD0,
.pad1 = BOARD_SERCOM6_PINMAP_PAD1,
.pad2 = BOARD_SERCOM6_PINMAP_PAD2,
.pad3 = BOARD_SERCOM6_PINMAP_PAD3,
.muxconfig = BOARD_SERCOM6_MUXCONFIG,
.frequency = BOARD_SERCOM6_FREQUENCY,
.base = SAM_SERCOM6_BASE,
};
#endif
#ifdef SAMD5E5_HAVE_USART7
const struct sam_usart_config_s g_usart7config =
{
.sercom = 7,
.parity = CONFIG_USART7_PARITY,
.bits = CONFIG_USART7_BITS,
.txirq = BOARD_TXIRQ_SERCOM7,
.rxirq = BOARD_RXIRQ_SERCOM7,
.coregen = BOARD_SERCOM7_COREGEN,
.slowgen = BOARD_SERCOM7_SLOWGEN,
.stopbits2 = CONFIG_USART7_2STOP,
.baud = CONFIG_USART7_BAUD,
.pad0 = BOARD_SERCOM7_PINMAP_PAD0,
.pad1 = BOARD_SERCOM7_PINMAP_PAD1,
.pad2 = BOARD_SERCOM7_PINMAP_PAD2,
.pad3 = BOARD_SERCOM7_PINMAP_PAD3,
.muxconfig = BOARD_SERCOM7_MUXCONFIG,
.frequency = BOARD_SERCOM7_FREQUENCY,
.base = SAM_SERCOM7_BASE,
};
#endif
const struct sam_usart_config_s *g_usartconfig[SAMD5E5_NSERCOM] =
{
#if SAMD5E5_NSERCOM > 0
arch/arm/src/samd5e5/sam_usart.h
+3 -2
View File
@@ -89,8 +89,9 @@ struct sam_usart_config_s
uint8_t sercom; /* Identifies the SERCOM peripheral */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (5-9) */
uint8_t irq; /* SERCOM IRQ number */
uint8_t gclkgen; /* Source GCLK generator */
uint8_t txirq; /* Tx SERCOM IRQ number */
uint8_t rxirq; /* Rx SERCOM IRQ number */
uint8_t coregen; /* Core GCLK generator */
uint8_t slowgen; /* Slow GCLK generator */
bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */
uint32_t baud; /* Configured baud */
configs/metro-m4/include/board.h
+183 -406
View File
File diff suppressed because it is too large Load Diff