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arch/arm/src/armv7-a/arm_l2cc_pl310.c, l2cc.h, l2cc_pl310.h, Kconfig: Add initiali support for the ARM L2CC-PL310 L2 cache.
This commit is contained in:
Gregory Nutt
@@ -5,14 +5,38 @@
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comment "ARMv7-A Configuration Options"
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config ARMV7A_HAVE_L2CC
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bool
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default n
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---help---
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Selected by the configuration tool if the architecutre supports any kind of L2 cache.
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config ARMV7A_HAVE_L2CC_PL310
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bool
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default n
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select ARMV7A_HAVE_L2CC
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---help---
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Set by architecture-specific code if the hardware supports a PL310
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r3p2 L2 cache (only version r3p2 is supported).
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if ARMV7A_HAVE_L2CC
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menu "L2 Cache Configuration"
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config ARMV7A_L2CC
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bool
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default n
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---help---
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Set by the configuration tool if the architecture specific L2CC is
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enabled. This is an architecture-independent setting to inform
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firmware that an L2 cache is present and that standard L2 cache
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operations are supported.
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config ARMV7A_L2CC_PL310
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bool "ARMv7-A L2CC P310 Support"
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default n
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depends on ARMV7A_HAVE_L2CC_PL310
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select ARMV7A_L2CC
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---help---
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Enable the 2 Cache Controller (L2CC) is based on the L2CC-PL310 ARM
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multi-way cache macrocell, version r3p2. The addition of an on-chip
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@@ -25,7 +49,6 @@ if ARMV7A_L2CC_PL310
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config PL310_LOCKDOWN_BY_MASTER
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bool "PL310 Lockdown by Master"
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default n
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depends on ARMV7A_L2CC_PL310
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config PL310_LOCKDOWN_BY_LINE
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bool "PL310 Lockdown by Line"
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@@ -37,6 +60,57 @@ config PL310_ADDRESS_FILTERING
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endif # ARMV7A_L2CC_PL310
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choice
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prompt "L2 Cache Associativity"
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default ARMV7A_ASSOCIATIVITY_8WAY
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depends on ARMV7A_L2CC
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---help---
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This choice specifies the associativity of L2 cache in terms of the
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number of ways. This value could be obtained by querying cache
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configuration registers. However, by defining a configuration
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setting instead, we can avoid using RAM memory to hold information
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about properties of the memory.
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config ARMV7A_ASSOCIATIVITY_8WAY
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bool "8-Way Associativity"
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config ARMV7A_ASSOCIATIVITY_16WAY
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bool "16-Way Associativity"
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endchoice # L2 Cache Associativity
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choice
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prompt "L2 Cache Way Size"
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default ARMV7A_WAYSIZE_16KB
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depends on ARMV7A_L2CC
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---help---
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This choice specifies size of each way. This value can be obtained
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by querying cache configuration registers. However, by defining a
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configuration setting instead, we can avoid using RAM memory to hold
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information
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config ARMV7A_WAYSIZE_16KB
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bool "16 KiB"
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config ARMV7A_WAYSIZE_32KB
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bool "32 KiB"
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config ARMV7A_WAYSIZE_64KB
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bool "64 KiB"
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config ARMV7A_WAYSIZE_128KB
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bool "128 KiB"
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config ARMV7A_WAYSIZE_256KB
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bool "256 KiB"
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config ARMV7A_WAYSIZE_512KB
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bool "512 KiB"
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endchoice # L2 Cache Associativity
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endmenu # L2 Cache Configuration
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endif #
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choice
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prompt "Toolchain Selection"
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default ARMV7A_TOOLCHAIN_GNU_EABIW if HOST_WINDOWS
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@@ -80,7 +154,7 @@ config ARMV7A_TOOLCHAIN_GNU_OABI
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---help---
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This option should work for any GNU toolchain configured for arm-elf-.
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endchoice
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endchoice # ARMV7A_HAVE_L2CC
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config ARMV7A_OABI_TOOLCHAIN
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bool "OABI (vs EABI)"
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,242 @@
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/****************************************************************************
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* arch/arm/src/armv7-a/l2cc.h
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* Non-CP15 Registers
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_ARMV7_A_L2CC_H
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#define __ARCH_ARM_SRC_ARMV7_A_L2CC_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifdef CONFIG_ARMV7A_L2CC
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Variables
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/***************************************************************************
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* Name: l2cc_initialize
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*
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* Description:
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* One time configuration of the L2 cache. The L2 cache will be enabled
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* upon return.
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*
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* Input Parameters:
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* None. The L2 cache configuration is controlled by configuration
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* settings.
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*
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* Returned Value:
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* Always returns OK.
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*
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***************************************************************************/
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int l2cc_initialize(void);
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/***************************************************************************
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* Name: l2cc_enable
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*
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* Description:
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* Re-enable the L2CC-P310 L2 cache by setting the enable bit in the
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* Control Register (CR)
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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***************************************************************************/
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void l2cc_enable(void);
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/***************************************************************************
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* Name: l2cc_disable
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*
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* Description:
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* Disable the L2 cache
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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***************************************************************************/
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void l2cc_disable(void);
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/***************************************************************************
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* Name: l2cc_sync
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*
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* Description:
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* Drain the L2 cache.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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***************************************************************************/
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void l2cc_sync(void);
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/***************************************************************************
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* Name: l2cc_invalidate_all
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*
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* Description:
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* Invalidate the entire L2 cache.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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***************************************************************************/
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static void l2cc_invalidate_all(void);
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/***************************************************************************
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* Name: l2cc_invalidate
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*
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* Description:
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* Invalidate a range of addresses in the L2 cache
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*
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* Input Parameters:
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* startaddr - The first address to be invalidated
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* endaddr - The last address to be invalidated
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*
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* Returned Value:
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* None
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*
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***************************************************************************/
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void l2cc_invalidate(uintptr_t startaddr, uintptr_t endaddr);
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/***************************************************************************
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* Name: l2cc_clean_all
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*
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* Description:
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* Clean the entire L2 cache.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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***************************************************************************/
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void l2cc_clean_all(void);
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/***************************************************************************
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* Name: l2cc_clean
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*
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* Description:
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* Clean a range of address within the L2 cache.
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*
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* Input Parameters:
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* startaddr - The first address to be cleaned
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* endaddr - The last address to be cleaned
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*
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* Returned Value:
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* None
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*
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***************************************************************************/
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void l2cc_clean(uintptr_t startaddr, uintptr_t endaddr);
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/***************************************************************************
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* Name: l2cc_flush_all
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*
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* Description:
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* Flush the entire L2 cache.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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***************************************************************************/
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void l2cc_flush_all(void);
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/***************************************************************************
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* Name: l2cc_flush
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*
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* Description:
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* Flush a range of address within the L2 cache.
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*
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* Input Parameters:
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* startaddr - The first address to be flushed
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* endaddr - The last address to be flushed
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*
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* Returned Value:
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* None
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*
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***************************************************************************/
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void l2cc_flush(uint32_t startaddr, uint32_t endaddr);
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_ARMV7A_L2CC */
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#endif /* __ARCH_ARM_SRC_ARMV7_A_L2CC_H */
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@@ -7,6 +7,9 @@
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
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* Technical Reference Manual, ARM DDI 0246F (ID011711), ARM
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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@@ -56,7 +59,7 @@
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************************************************************************************/
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/* General Definitions **************************************************************/
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#define CACHE_LINE_SIZE 32
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#define PL310_CACHE_LINE_SIZE 32
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#ifdef CONFIG_PL310_LOCKDOWN_BY_MASTER
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# define PL310_NLOCKREGS 8
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@@ -191,28 +194,37 @@
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/* Auxiliary Control Register */
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#define L2CC_ACR_HPSO (1 << 10) /* Bit 10: High Priority for SO and Dev Reads Enable */
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#define L2CC_ACR_SBDLE (1 << 11) /* Bit 11: Store Buffer Device Limitation Enable */
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#define L2CC_ACR_EXCC (1 << 12) /* Bit 12: Exclusive Cache Configuration */
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#define L2CC_ACR_SAIE (1 << 13) /* Bit 13: Shared Attribute Invalidate Enable */
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#define L2CC_ACR_ASS (1 << 16) /* Bit 16: Associativity */
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#define L2CC_ACR_FLZE (1 << 0) /* Bit 0: Full line zero enable */
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#define L2CC_ACR_HPSO (1 << 10) /* Bit 10: High Priority for SO and Dev Reads Enable */
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#define L2CC_ACR_SBDLE (1 << 11) /* Bit 11: Store Buffer Device Limitation Enable */
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#define L2CC_ACR_EXCC (1 << 12) /* Bit 12: Exclusive Cache Configuration */
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#define L2CC_ACR_SAIE (1 << 13) /* Bit 13: Shared Attribute Invalidate Enable */
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#define L2CC_ACR_ASS (1 << 16) /* Bit 16: Associativity */
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#define L2CC_ACR_WAYSIZE_SHIFT (17) /* Bits 17-19: Way Size */
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#define L2CC_ACR_WAYSIZE_MASK (7 << L2CC_ACR_WAYSIZE_SHIFT)
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# define L2CC_ACR_WAYSIZE_16KB (1 << L2CC_ACR_WAYSIZE_SHIFT)
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#define L2CC_ACR_EMBEN (1 << 20) /* Bit 20: Event Monitor Bus Enable */
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#define L2CC_ACR_PEN (1 << 21) /* Bit 21: Parity Enable */
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#define L2CC_ACR_SAOEN (1 << 22) /* Bit 22: Shared Attribute Override Enable */
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# define L2CC_ACR_WAYSIZE_32KB (2 << L2CC_ACR_WAYSIZE_SHIFT)
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# define L2CC_ACR_WAYSIZE_64KB (3 << L2CC_ACR_WAYSIZE_SHIFT)
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# define L2CC_ACR_WAYSIZE_128KB (4 << L2CC_ACR_WAYSIZE_SHIFT)
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# define L2CC_ACR_WAYSIZE_256KB (5 << L2CC_ACR_WAYSIZE_SHIFT)
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# define L2CC_ACR_WAYSIZE_512KB (6 << L2CC_ACR_WAYSIZE_SHIFT)
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#define L2CC_ACR_EMBEN (1 << 20) /* Bit 20: Event Monitor Bus Enable */
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#define L2CC_ACR_PEN (1 << 21) /* Bit 21: Parity Enable */
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#define L2CC_ACR_SAOEN (1 << 22) /* Bit 22: Shared Attribute Override Enable */
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#define L2CC_ACR_FWA_SHIFT (23) /* Bits 23-24: Force Write Allocate */
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#define L2CC_ACR_FWA_MASK (3 << L2CC_ACR_FWA_SHIFT)
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# define L2CC_ACR_FWA_AWCACHE (0 << L2CC_ACR_FWA_SHIFT) /* Use AWCACHE attributes for WA */
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# define L2CC_ACR_FWA_NOALLOC (1 << L2CC_ACR_FWA_SHIFT) /* No allocate */
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# define L2CC_ACR_FWA_OVERRIDE (2 << L2CC_ACR_FWA_SHIFT) /* Override AWCACHE attributes */
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# define L2CC_ACR_FWA_MAPPED (3 << L2CC_ACR_FWA_SHIFT) /* Internally mapped to 00 */
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#define L2CC_ACR_CRPOL (1 << 25) /* Bit 25: Cache Replacement Policy */
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#define L2CC_ACR_NSLEN (1 << 26) /* Bit 26: Non-Secure Lockdown Enable */
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#define L2CC_ACR_NSIAC (1 << 27) /* Bit 27: Non-Secure Interrupt Access Control */
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#define L2CC_ACR_DPEN (1 << 28) /* Bit 28: Data Prefetch Enable */
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#define L2CC_ACR_IPEN (1 << 29) /* Bit 29: Instruction Prefetch Enable */
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#define L2CC_ACR_CRPOL (1 << 25) /* Bit 25: Cache Replacement Policy */
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#define L2CC_ACR_NSLEN (1 << 26) /* Bit 26: Non-Secure Lockdown Enable */
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#define L2CC_ACR_NSIAC (1 << 27) /* Bit 27: Non-Secure Interrupt Access Control */
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#define L2CC_ACR_DPEN (1 << 28) /* Bit 28: Data Prefetch Enable */
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#define L2CC_ACR_IPEN (1 << 29) /* Bit 29: Instruction Prefetch Enable */
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#define L2CC_ACR_EBRESP (1 << 30) /* Bit 30: Early BRESP enable */
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#define L2CC_ACR_SBZ (0x8000c1fe)
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/* Tag RAM Control Register */
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@@ -450,6 +462,7 @@
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#ifdef PL310_ADDRESS_FILTERING
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# define L2CC_FLSTRT_ENABLE (1 << 0) /* Bit 0: Address filter enable */
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# define L2CC_FLSTRT_MASK (0xfff00000) /* Bits 20-31: Bits 20-31 of address mask */
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#endif
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/* Address filter end */
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@@ -465,9 +478,9 @@
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/* Prefetch Control Register */
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#define L2CC_PCR_OFFSET_SHIFT (0) /* Bits 0-4: Prefetch Offset */
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#define L2CC_PCR_OFFSET_MASK (31 << L2CC_PCR_OFFSET_SHIFT)
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# define L2CC_PCR_OFFSET(n) ((uint32_t)(n) << L2CC_PCR_OFFSET_SHIFT)
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#define L2CC_PCR_SHIFT (0) /* Bits 0-4: Prefetch Offset */
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#define L2CC_PCR_MASK (31 << L2CC_PCR_SHIFT)
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# define L2CC_PCR_PREFETCH(n) ((uint32_t)(n) << L2CC_PCR_SHIFT)
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#define L2CC_PCR_NSIDEN (1 << 21) /* Bit 21: Not Same ID on Exclusive Sequence Enable */
|
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#define L2CC_PCR_IDLEN (1 << 23) /* Bit 23: INCR Double Linefill Enable */
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#define L2CC_PCR_PDEN (1 << 24) /* Bit 24: Prefetch Drop Enable */
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@@ -54,6 +54,8 @@ CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S arm_vfork.S
|
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CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
|
||||
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S
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# Configuration dependent assembly language files
|
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ifeq ($(CONFIG_ARCH_MEMCPY),y)
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CMN_ASRCS += arm_memcpy.S
|
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endif
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@@ -71,7 +73,11 @@ CMN_CSRCS += arm_releasepending.c arm_reprioritizertr.c
|
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CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c
|
||||
CMN_CSRCS += arm_unblocktask.c arm_undefinedinsn.c
|
||||
|
||||
# Configuration dependent C and assembly language files
|
||||
# Configuration dependent C files
|
||||
|
||||
ifeq ($(CONFIG_ARMV7A_L2CC_PL310),y)
|
||||
CMN_CSRCS += arm_l2cc_pl310.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_PAGING),y)
|
||||
CMN_CSRCS += arm_allocpage.c arm_checkmapping.c arm_pginitialize.c
|
||||
|
||||
Reference in New Issue
Block a user