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!arch/stm32l4: unify non-standard hardware definition prefixes
BREAKING CHANGE: STM32L4 non-standard hardware definition macros (IRQ, peripheral-count, SRAM and related) were renamed to the common STM32_* prefix. Out-of-tree code must update the affected references. Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl
Xiang Xiao
+208
-208
@@ -66,260 +66,260 @@
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*/
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#if defined(CONFIG_STM32L4_STM32L4XR)
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# define STM32L4_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
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# define STM32L4_SRAM3_SIZE (384*1024) /* 384Kb SRAM3 on AHB bus Matrix */
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# define STM32_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */
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# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
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# define STM32_SRAM3_SIZE (384*1024) /* 384Kb SRAM3 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L496XX)
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# define STM32L4_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
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# define STM32_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */
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# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L475XX) || defined(CONFIG_STM32L4_STM32L476XX) || \
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defined(CONFIG_STM32L4_STM32L486XX)
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# define STM32L4_SRAM1_SIZE (96*1024) /* 96Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */
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# define STM32_SRAM1_SIZE (96*1024) /* 96Kb SRAM1 on AHB bus Matrix */
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# define STM32_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \
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defined(CONFIG_STM32L4_STM32L462XX)
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# define STM32L4_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */
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# define STM32_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix */
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# define STM32_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L432XX) || defined(CONFIG_STM32L4_STM32L433XX)
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# define STM32L4_SRAM1_SIZE (48*1024) /* 48Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
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# define STM32_SRAM1_SIZE (48*1024) /* 48Kb SRAM1 on AHB bus Matrix */
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# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L412XX) || defined(CONFIG_STM32L4_STM32L422XX)
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# define STM32L4_SRAM1_SIZE (32*1024) /* 32Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (8*1024) /* 8Kb SRAM2 on AHB bus Matrix */
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# define STM32_SRAM1_SIZE (32*1024) /* 32Kb SRAM1 on AHB bus Matrix */
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# define STM32_SRAM2_SIZE (8*1024) /* 8Kb SRAM2 on AHB bus Matrix */
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#else
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# error "Unsupported STM32L4 chip"
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#endif
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#if defined(CONFIG_STM32L4_STM32L4XR)
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# define STM32L4_NFSMC 1 /* Have FSMC memory controller */
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# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
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# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
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# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32L4_NRNG 1 /* Random number generator (RNG) */
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# define STM32L4_NUART 2 /* UART 4-5 */
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# define STM32L4_NUSART 3 /* USART 1-3 */
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# define STM32L4_NLPUART 1 /* LPUART 1 */
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# define STM32L4_QSPI 0 /* No QuadSPI1 */
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# define STM32L4_OCTOSPI 2 /* OCTOSPI1-2 */
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# define STM32L4_NSPI 3 /* SPI1-3 */
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# define STM32L4_NI2C 4 /* I2C1-4 */
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# define STM32L4_NSWPMI 0 /* No SWPMI1 */
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# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32L4_NUSBFS 0 /* No USB FS */
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# define STM32L4_NCAN 1 /* CAN1 */
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# define STM32L4_NSAI 2 /* SAI1-2 */
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# define STM32L4_NSDMMC 1 /* SDMMC interface */
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# define STM32L4_NDMA 2 /* DMA1-2 */
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# define STM32L4_NPORTS 9 /* 9 GPIO ports, GPIOA-I */
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# define STM32L4_NADC 1 /* 12-bit ADC1, up to 20 channels */
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# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32L4_NCRC 1 /* CRC */
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# define STM32L4_NCOMP 2 /* Comparators */
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# define STM32L4_NOPAMP 2 /* Operational Amplifiers */
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# define STM32_NFSMC 1 /* Have FSMC memory controller */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NUART 2 /* UART 4-5 */
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# define STM32_NUSART 3 /* USART 1-3 */
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# define STM32_NLPUART 1 /* LPUART 1 */
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# define STM32_QSPI 0 /* No QuadSPI1 */
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# define STM32_OCTOSPI 2 /* OCTOSPI1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2C 4 /* I2C1-4 */
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# define STM32_NSWPMI 0 /* No SWPMI1 */
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# define STM32_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32_NUSBFS 0 /* No USB FS */
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# define STM32_NCAN 1 /* CAN1 */
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# define STM32_NSAI 2 /* SAI1-2 */
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# define STM32_NSDMMC 1 /* SDMMC interface */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NPORTS 9 /* 9 GPIO ports, GPIOA-I */
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# define STM32_NADC 1 /* 12-bit ADC1, up to 20 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NCOMP 2 /* Comparators */
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# define STM32_NOPAMP 2 /* Operational Amplifiers */
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#endif /* CONFIG_STM32L4_STM32L4XR */
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#if defined(CONFIG_STM32L4_STM32L4X5)
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# define STM32L4_NFSMC 1 /* Have FSMC memory controller */
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# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
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# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
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# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32L4_NRNG 1 /* Random number generator (RNG) */
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# define STM32L4_NUART 2 /* UART 4-5 */
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# define STM32L4_NUSART 3 /* USART 1-3 */
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# define STM32L4_NLPUART 1 /* LPUART 1 */
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# define STM32L4_QSPI 1 /* QuadSPI1 */
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# define STM32L4_NSPI 3 /* SPI1-3 */
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# define STM32L4_NI2C 3 /* I2C1-3 */
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# define STM32L4_NSWPMI 1 /* SWPMI1 */
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# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32L4_NUSBFS 0 /* No USB FS */
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# define STM32L4_NCAN 1 /* CAN1 */
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# define STM32L4_NSAI 2 /* SAI1-2 */
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# define STM32L4_NSDMMC 1 /* SDMMC interface */
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# define STM32L4_NDMA 2 /* DMA1-2 */
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# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
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# define STM32L4_NADC 3 /* 12-bit ADC1-3, 16 channels */
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# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32L4_NCRC 1 /* CRC */
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# define STM32L4_NCOMP 2 /* Comparators */
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# define STM32L4_NOPAMP 2 /* Operational Amplifiers */
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# define STM32_NFSMC 1 /* Have FSMC memory controller */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NUART 2 /* UART 4-5 */
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# define STM32_NUSART 3 /* USART 1-3 */
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# define STM32_NLPUART 1 /* LPUART 1 */
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# define STM32_QSPI 1 /* QuadSPI1 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NSWPMI 1 /* SWPMI1 */
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# define STM32_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32_NUSBFS 0 /* No USB FS */
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# define STM32_NCAN 1 /* CAN1 */
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# define STM32_NSAI 2 /* SAI1-2 */
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# define STM32_NSDMMC 1 /* SDMMC interface */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
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# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NCOMP 2 /* Comparators */
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# define STM32_NOPAMP 2 /* Operational Amplifiers */
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#endif /* CONFIG_STM32L4_STM32L4X5 */
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#if defined(CONFIG_STM32L4_STM32L4X6)
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# define STM32L4_NFSMC 1 /* Have FSMC memory controller */
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# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
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# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
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# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32L4_NRNG 1 /* Random number generator (RNG) */
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# define STM32L4_NUART 2 /* UART 4-5 */
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# define STM32L4_NUSART 3 /* USART 1-3 */
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# define STM32L4_NLPUART 1 /* LPUART 1 */
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# define STM32L4_QSPI 1 /* QuadSPI1 */
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# define STM32L4_NSPI 3 /* SPI1-3 */
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# define STM32_NFSMC 1 /* Have FSMC memory controller */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NUART 2 /* UART 4-5 */
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# define STM32_NUSART 3 /* USART 1-3 */
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# define STM32_NLPUART 1 /* LPUART 1 */
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# define STM32_QSPI 1 /* QuadSPI1 */
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# define STM32_NSPI 3 /* SPI1-3 */
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#if defined(CONFIG_STM32L4_STM32L496XX)
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# define STM32L4_NI2C 4 /* I2C1-4 */
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# define STM32_NI2C 4 /* I2C1-4 */
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#else
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# define STM32L4_NI2C 3 /* I2C1-3 */
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# define STM32_NI2C 3 /* I2C1-3 */
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#endif
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# define STM32L4_NSWPMI 1 /* SWPMI1 */
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# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32L4_NUSBFS 0 /* No USB FS */
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# define STM32_NSWPMI 1 /* SWPMI1 */
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# define STM32_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32_NUSBFS 0 /* No USB FS */
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#if defined(CONFIG_STM32L4_STM32L496XX)
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# define STM32L4_NCAN 2 /* CAN1-2 */
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# define STM32_NCAN 2 /* CAN1-2 */
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#else
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# define STM32L4_NCAN 1 /* CAN1 */
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# define STM32_NCAN 1 /* CAN1 */
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#endif
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# define STM32L4_NSAI 2 /* SAI1-2 */
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# define STM32L4_NSDMMC 1 /* SDMMC interface */
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# define STM32L4_NDMA 2 /* DMA1-2 */
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# define STM32_NSAI 2 /* SAI1-2 */
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# define STM32_NSDMMC 1 /* SDMMC interface */
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# define STM32_NDMA 2 /* DMA1-2 */
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#if defined(CONFIG_STM32L4_STM32L496XX)
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# define STM32L4_NPORTS 9 /* 9 GPIO ports, GPIOA-I */
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# define STM32_NPORTS 9 /* 9 GPIO ports, GPIOA-I */
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#else
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# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
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# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
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#endif
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# define STM32L4_NADC 3 /* 12-bit ADC1-3, up to 24 channels */
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# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32L4_NCRC 1 /* CRC */
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# define STM32L4_NCOMP 2 /* Comparators */
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# define STM32L4_NOPAMP 2 /* Operational Amplifiers */
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# define STM32_NADC 3 /* 12-bit ADC1-3, up to 24 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NCOMP 2 /* Comparators */
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# define STM32_NOPAMP 2 /* Operational Amplifiers */
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#endif /* CONFIG_STM32L4_STM32L4X6 */
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#if defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \
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defined(CONFIG_STM32L4_STM32L462XX)
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# define STM32L4_NFSMC 0 /* No FSMC memory controller */
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# define STM32L4_NATIM 1 /* One advanced timer TIM1 */
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# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
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# define STM32L4_NGTIM16 3 /* 16-bit general timers TIM3, TIM15-16 with DMA */
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# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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# define STM32L4_NBTIM 1 /* One basic timer, TIM6 */
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# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32L4_NRNG 1 /* Random number generator (RNG) */
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# define STM32L4_NUART 1 /* UART 4 */
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# define STM32L4_NUSART 3 /* USART 1-3 */
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# define STM32L4_NLPUART 1 /* LPUART 1 */
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# define STM32L4_QSPI 1 /* QuadSPI1 */
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# define STM32L4_NSPI 3 /* SPI1-3 */
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# define STM32L4_NI2C 4 /* I2C1-4 */
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# define STM32L4_NSWPMI 1 /* SWPMI1 */
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# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */
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# define STM32_NFSMC 0 /* No FSMC memory controller */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
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# define STM32_NGTIM16 3 /* 16-bit general timers TIM3, TIM15-16 with DMA */
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# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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# define STM32_NBTIM 1 /* One basic timer, TIM6 */
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# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NUART 1 /* UART 4 */
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# define STM32_NUSART 3 /* USART 1-3 */
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# define STM32_NLPUART 1 /* LPUART 1 */
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# define STM32_QSPI 1 /* QuadSPI1 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2C 4 /* I2C1-4 */
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# define STM32_NSWPMI 1 /* SWPMI1 */
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# define STM32_NUSBOTGFS 0 /* No USB OTG FS */
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#if defined(CONFIG_STM32L4_STM32L451XX)
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# define STM32L4_NUSBFS 0 /* No USB FS */
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# define STM32_NUSBFS 0 /* No USB FS */
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#else
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# define STM32L4_NUSBFS 1 /* USB FS */
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# define STM32_NUSBFS 1 /* USB FS */
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#endif
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# define STM32L4_NCAN 1 /* CAN1 */
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# define STM32L4_NSAI 1 /* SAI1 */
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# define STM32_NCAN 1 /* CAN1 */
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# define STM32_NSAI 1 /* SAI1 */
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#if defined(CONFIG_STM32L4_HAVE_SDMMC1)
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# define STM32L4_NSDMMC 1 /* SDMMC interface */
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# define STM32_NSDMMC 1 /* SDMMC interface */
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#else
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# define STM32L4_NSDMMC 0 /* No SDMMC interface */
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# define STM32_NSDMMC 0 /* No SDMMC interface */
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#endif
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# define STM32L4_NDMA 2 /* DMA1-2 */
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# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
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# define STM32L4_NADC 1 /* 12-bit ADC1, 16 channels (10 in CE,CV) */
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# define STM32L4_NDAC 1 /* 12-bit DAC1 */
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# define STM32L4_NCRC 1 /* CRC */
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# define STM32L4_NCOMP 2 /* Comparators */
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# define STM32L4_NOPAMP 1 /* Operational Amplifiers */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
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# define STM32_NADC 1 /* 12-bit ADC1, 16 channels (10 in CE,CV) */
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# define STM32_NDAC 1 /* 12-bit DAC1 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NCOMP 2 /* Comparators */
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# define STM32_NOPAMP 1 /* Operational Amplifiers */
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#endif /* CONFIG_STM32L4_STM32L451XX */
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#if defined(CONFIG_STM32L4_STM32L432XX)
|
||||
# define STM32L4_NFSMC 0 /* No FSMC memory controller */
|
||||
# define STM32L4_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
|
||||
# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */
|
||||
# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
|
||||
# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */
|
||||
# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
|
||||
# define STM32L4_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32L4_NUART 0 /* No UART */
|
||||
# define STM32L4_NUSART 2 /* USART 1-2 */
|
||||
# define STM32L4_NLPUART 1 /* LPUART 1 */
|
||||
# define STM32L4_QSPI 1 /* QuadSPI1 */
|
||||
# define STM32L4_NSPI 2 /* SPI1, SPI3 */
|
||||
# define STM32L4_NI2C 2 /* I2C1, I2C3 */
|
||||
# define STM32L4_NSWPMI 1 /* SWPMI1 */
|
||||
# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */
|
||||
# define STM32L4_NUSBFS 1 /* USB FS */
|
||||
# define STM32L4_NCAN 1 /* CAN1 */
|
||||
# define STM32L4_NSAI 1 /* SAI1 */
|
||||
# define STM32L4_NSDMMC 0 /* No SDMMC interface */
|
||||
# define STM32L4_NDMA 2 /* DMA1-2 */
|
||||
# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
|
||||
# define STM32L4_NADC 1 /* 12-bit ADC1, 10 channels */
|
||||
# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */
|
||||
# define STM32L4_NCRC 1 /* CRC */
|
||||
# define STM32L4_NCOMP 2 /* Comparators */
|
||||
# define STM32L4_NOPAMP 1 /* Operational Amplifiers */
|
||||
# define STM32_NFSMC 0 /* No FSMC memory controller */
|
||||
# define STM32_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
|
||||
# define STM32_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */
|
||||
# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
|
||||
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
||||
# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
|
||||
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32_NUART 0 /* No UART */
|
||||
# define STM32_NUSART 2 /* USART 1-2 */
|
||||
# define STM32_NLPUART 1 /* LPUART 1 */
|
||||
# define STM32_QSPI 1 /* QuadSPI1 */
|
||||
# define STM32_NSPI 2 /* SPI1, SPI3 */
|
||||
# define STM32_NI2C 2 /* I2C1, I2C3 */
|
||||
# define STM32_NSWPMI 1 /* SWPMI1 */
|
||||
# define STM32_NUSBOTGFS 0 /* No USB OTG FS */
|
||||
# define STM32_NUSBFS 1 /* USB FS */
|
||||
# define STM32_NCAN 1 /* CAN1 */
|
||||
# define STM32_NSAI 1 /* SAI1 */
|
||||
# define STM32_NSDMMC 0 /* No SDMMC interface */
|
||||
# define STM32_NDMA 2 /* DMA1-2 */
|
||||
# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
|
||||
# define STM32_NADC 1 /* 12-bit ADC1, 10 channels */
|
||||
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
|
||||
# define STM32_NCRC 1 /* CRC */
|
||||
# define STM32_NCOMP 2 /* Comparators */
|
||||
# define STM32_NOPAMP 1 /* Operational Amplifiers */
|
||||
#endif /* CONFIG_STM32L4_STM32L432XX */
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L433XX)
|
||||
# define STM32L4_NFSMC 0 /* No FSMC memory controller */
|
||||
# define STM32L4_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
|
||||
# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */
|
||||
# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
|
||||
# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */
|
||||
# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
|
||||
# define STM32L4_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32L4_NUART 0 /* No UART */
|
||||
# define STM32L4_NUSART 3 /* USART 1-3 */
|
||||
# define STM32L4_NLPUART 1 /* LPUART 1 */
|
||||
# define STM32L4_QSPI 1 /* QuadSPI1 */
|
||||
# define STM32L4_NSPI 3 /* SPI1-SPI3 */
|
||||
# define STM32L4_NI2C 3 /* I2C1-I2C3 */
|
||||
# define STM32L4_NSWPMI 1 /* SWPMI1 */
|
||||
# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */
|
||||
# define STM32L4_NUSBFS 1 /* USB FS */
|
||||
# define STM32L4_NCAN 1 /* CAN1 */
|
||||
# define STM32L4_NSAI 1 /* SAI1 */
|
||||
# define STM32L4_NSDMMC 1 /* SDMMC interface */
|
||||
# define STM32L4_NDMA 2 /* DMA1-2 */
|
||||
# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
|
||||
# define STM32L4_NADC 1 /* 12-bit ADC1, 10 channels */
|
||||
# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */
|
||||
# define STM32L4_NCRC 1 /* CRC */
|
||||
# define STM32L4_NCOMP 2 /* Comparators */
|
||||
# define STM32L4_NOPAMP 1 /* Operational Amplifiers */
|
||||
# define STM32_NFSMC 0 /* No FSMC memory controller */
|
||||
# define STM32_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
|
||||
# define STM32_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */
|
||||
# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
|
||||
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
||||
# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
|
||||
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32_NUART 0 /* No UART */
|
||||
# define STM32_NUSART 3 /* USART 1-3 */
|
||||
# define STM32_NLPUART 1 /* LPUART 1 */
|
||||
# define STM32_QSPI 1 /* QuadSPI1 */
|
||||
# define STM32_NSPI 3 /* SPI1-SPI3 */
|
||||
# define STM32_NI2C 3 /* I2C1-I2C3 */
|
||||
# define STM32_NSWPMI 1 /* SWPMI1 */
|
||||
# define STM32_NUSBOTGFS 0 /* No USB OTG FS */
|
||||
# define STM32_NUSBFS 1 /* USB FS */
|
||||
# define STM32_NCAN 1 /* CAN1 */
|
||||
# define STM32_NSAI 1 /* SAI1 */
|
||||
# define STM32_NSDMMC 1 /* SDMMC interface */
|
||||
# define STM32_NDMA 2 /* DMA1-2 */
|
||||
# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
|
||||
# define STM32_NADC 1 /* 12-bit ADC1, 10 channels */
|
||||
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
|
||||
# define STM32_NCRC 1 /* CRC */
|
||||
# define STM32_NCOMP 2 /* Comparators */
|
||||
# define STM32_NOPAMP 1 /* Operational Amplifiers */
|
||||
#endif /* CONFIG_STM32L4_STM32L433XX */
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L412XX) || defined(CONFIG_STM32L4_STM32L422XX)
|
||||
# define STM32L4_NFSMC 0 /* No FSMC memory controller */
|
||||
# define STM32L4_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
|
||||
# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */
|
||||
# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
|
||||
# define STM32L4_NBTIM 1 /* One basic timer, TIM6 */
|
||||
# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
|
||||
# define STM32L4_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32L4_NUART 0 /* No UART */
|
||||
# define STM32L4_NUSART 3 /* USART 1-3 */
|
||||
# define STM32L4_NLPUART 1 /* LPUART 1 */
|
||||
# define STM32L4_QSPI 1 /* QuadSPI1 */
|
||||
# define STM32L4_NSPI 3 /* SPI1-SPI3 */
|
||||
# define STM32L4_NI2C 3 /* I2C1-I2C3 */
|
||||
# define STM32L4_NSWPMI 0 /* No SWPMI */
|
||||
# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */
|
||||
# define STM32L4_NUSBFS 1 /* USB FS */
|
||||
# define STM32L4_NCAN 0 /* No CAN */
|
||||
# define STM32L4_NSAI 0 /* No SAI */
|
||||
# define STM32L4_NSDMMC 0 /* No SDMMC interface */
|
||||
# define STM32L4_NDMA 2 /* DMA1-2 */
|
||||
# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
|
||||
# define STM32L4_NADC 2 /* 12-bit ADC1-2, 10 channels */
|
||||
# define STM32L4_NDAC 0 /* No DAC */
|
||||
# define STM32L4_NCRC 1 /* CRC */
|
||||
# define STM32L4_NCOMP 2 /* Comparators */
|
||||
# define STM32L4_NOPAMP 1 /* Operational Amplifiers */
|
||||
# define STM32_NFSMC 0 /* No FSMC memory controller */
|
||||
# define STM32_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
|
||||
# define STM32_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */
|
||||
# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
|
||||
# define STM32_NBTIM 1 /* One basic timer, TIM6 */
|
||||
# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
|
||||
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32_NUART 0 /* No UART */
|
||||
# define STM32_NUSART 3 /* USART 1-3 */
|
||||
# define STM32_NLPUART 1 /* LPUART 1 */
|
||||
# define STM32_QSPI 1 /* QuadSPI1 */
|
||||
# define STM32_NSPI 3 /* SPI1-SPI3 */
|
||||
# define STM32_NI2C 3 /* I2C1-I2C3 */
|
||||
# define STM32_NSWPMI 0 /* No SWPMI */
|
||||
# define STM32_NUSBOTGFS 0 /* No USB OTG FS */
|
||||
# define STM32_NUSBFS 1 /* USB FS */
|
||||
# define STM32_NCAN 0 /* No CAN */
|
||||
# define STM32_NSAI 0 /* No SAI */
|
||||
# define STM32_NSDMMC 0 /* No SDMMC interface */
|
||||
# define STM32_NDMA 2 /* DMA1-2 */
|
||||
# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
|
||||
# define STM32_NADC 2 /* 12-bit ADC1-2, 10 channels */
|
||||
# define STM32_NDAC 0 /* No DAC */
|
||||
# define STM32_NCRC 1 /* CRC */
|
||||
# define STM32_NCOMP 2 /* Comparators */
|
||||
# define STM32_NOPAMP 1 /* Operational Amplifiers */
|
||||
#endif /* CONFIG_STM32L4_STM32L412XX || CONFIG_STM32L4_STM32L422XX */
|
||||
|
||||
/* NVIC priority levels *****************************************************/
|
||||
|
||||
@@ -44,26 +44,26 @@
|
||||
|
||||
/* Processor Exceptions (vectors 0-15) */
|
||||
|
||||
#define STM32L4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
|
||||
/* Vector 0: Reset stack pointer value */
|
||||
/* Vector 1: Reset (not handler as an IRQ) */
|
||||
#define STM32L4_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
|
||||
#define STM32L4_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
|
||||
#define STM32L4_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
|
||||
#define STM32L4_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
|
||||
#define STM32L4_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
|
||||
/* Vectors 7-10: Reserved */
|
||||
#define STM32L4_IRQ_SVCALL (11) /* Vector 11: SVC call */
|
||||
#define STM32L4_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
|
||||
/* Vector 13: Reserved */
|
||||
#define STM32L4_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
|
||||
#define STM32L4_IRQ_SYSTICK (15) /* Vector 15: System tick */
|
||||
#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
|
||||
/* Vector 0: Reset stack pointer value */
|
||||
/* Vector 1: Reset (not handler as an IRQ) */
|
||||
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
|
||||
#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
|
||||
#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
|
||||
#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
|
||||
#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
|
||||
/* Vectors 7-10: Reserved */
|
||||
#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */
|
||||
#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
|
||||
/* Vector 13: Reserved */
|
||||
#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
|
||||
#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */
|
||||
|
||||
/* External interrupts (vectors >= 16). These definitions are
|
||||
* chip-specific
|
||||
*/
|
||||
|
||||
#define STM32L4_IRQ_FIRST (16) /* Vector number of the first external interrupt */
|
||||
#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
|
||||
@@ -52,99 +52,99 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */
|
||||
#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */
|
||||
#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */
|
||||
#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
|
||||
#define STM32L4_IRQ_ADC1 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */
|
||||
#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
|
||||
#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
|
||||
/* Reserved 30: TIM4 global interrupt */
|
||||
#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
|
||||
#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
|
||||
#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
|
||||
#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
|
||||
#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
|
||||
#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
|
||||
#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
|
||||
#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
|
||||
#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
|
||||
#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
/* Reserved 42-48 */
|
||||
#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
|
||||
/* Reserved 50: TIM5 global interrupt */
|
||||
#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
|
||||
#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
|
||||
/* Reserved 53: UART5 global interrupt */
|
||||
#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
|
||||
#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupts */
|
||||
#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
|
||||
#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
|
||||
#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
|
||||
/* Reserved 63: DFSDM2 global interrupt */
|
||||
#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
|
||||
#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
|
||||
#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
|
||||
#define STM32L4_IRQ_USB_FS (STM32L4_IRQ_FIRST + 67) /* 67: USB event interrupt through EXTI line 17 */
|
||||
#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
|
||||
#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
|
||||
#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */
|
||||
#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
|
||||
#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
|
||||
#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
|
||||
/* Reserved 75: SAI2 global interrupt */
|
||||
#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */
|
||||
#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */
|
||||
#define STM32L4_IRQ_LCD (STM32L4_IRQ_FIRST + 78) /* 78: LCD global interrupt */
|
||||
#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */
|
||||
#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */
|
||||
#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */
|
||||
#define STM32L4_IRQ_CRS (STM32L4_IRQ_FIRST + 82) /* 82: CRS global interrupt */
|
||||
#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */
|
||||
#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */
|
||||
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */
|
||||
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */
|
||||
#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */
|
||||
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
|
||||
#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */
|
||||
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
|
||||
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
|
||||
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
|
||||
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
|
||||
/* Reserved 30: TIM4 global interrupt */
|
||||
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
|
||||
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
|
||||
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
|
||||
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
|
||||
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
|
||||
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
|
||||
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
|
||||
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
|
||||
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
|
||||
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
/* Reserved 42-48 */
|
||||
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
|
||||
/* Reserved 50: TIM5 global interrupt */
|
||||
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
|
||||
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
|
||||
/* Reserved 53: UART5 global interrupt */
|
||||
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
|
||||
#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupts */
|
||||
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
|
||||
#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
|
||||
#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
|
||||
/* Reserved 63: DFSDM2 global interrupt */
|
||||
#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
|
||||
#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
|
||||
#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
|
||||
#define STM32_IRQ_USB_FS (STM32_IRQ_FIRST + 67) /* 67: USB event interrupt through EXTI line 17 */
|
||||
#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
|
||||
#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
|
||||
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */
|
||||
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
|
||||
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
|
||||
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
|
||||
/* Reserved 75: SAI2 global interrupt */
|
||||
#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */
|
||||
#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */
|
||||
#define STM32_IRQ_LCD (STM32_IRQ_FIRST + 78) /* 78: LCD global interrupt */
|
||||
#define STM32_IRQ_AES (STM32_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */
|
||||
#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */
|
||||
#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */
|
||||
#define STM32_IRQ_CRS (STM32_IRQ_FIRST + 82) /* 82: CRS global interrupt */
|
||||
#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */
|
||||
#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3)
|
||||
# define STM32L4_IRQ_NEXTINTS 85
|
||||
# define STM32_IRQ_NEXTINTS 85
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
#endif
|
||||
|
||||
/* (EXTI interrupts do not use IRQ numbers) */
|
||||
|
||||
#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS)
|
||||
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
|
||||
@@ -48,99 +48,99 @@
|
||||
* External interrupts (vectors >= 16)
|
||||
*/
|
||||
|
||||
#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */
|
||||
#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */
|
||||
#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */
|
||||
#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
|
||||
#define STM32L4_IRQ_ADC12 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */
|
||||
#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
|
||||
#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
|
||||
#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
|
||||
#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
|
||||
#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
|
||||
#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
|
||||
#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
|
||||
#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
|
||||
#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
|
||||
#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
|
||||
#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
|
||||
#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
|
||||
#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
|
||||
#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
|
||||
#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
|
||||
#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||
#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
|
||||
#define STM32L4_IRQ_ADC3 (STM32L4_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */
|
||||
#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */
|
||||
#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
|
||||
#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
|
||||
#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
|
||||
#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
|
||||
#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
|
||||
#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
|
||||
#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||
#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
|
||||
#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
|
||||
#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
|
||||
#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */
|
||||
#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
|
||||
#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
|
||||
#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
|
||||
#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
|
||||
#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
|
||||
#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */
|
||||
#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
|
||||
#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
|
||||
#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
|
||||
#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */
|
||||
#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */
|
||||
#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */
|
||||
#define STM32L4_IRQ_RESERVED78 (STM32L4_IRQ_FIRST + 78) /* 78: Reserved */
|
||||
#define STM32L4_IRQ_RESERVED79 (STM32L4_IRQ_FIRST + 79) /* 79: Reserved */
|
||||
#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */
|
||||
#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */
|
||||
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */
|
||||
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */
|
||||
#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */
|
||||
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
|
||||
#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */
|
||||
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
|
||||
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
|
||||
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
|
||||
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
|
||||
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
|
||||
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
|
||||
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
|
||||
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
|
||||
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
|
||||
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
|
||||
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
|
||||
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
|
||||
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
|
||||
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
|
||||
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
|
||||
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
#define STM32_IRQ_DFSDM3 (STM32_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
|
||||
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
|
||||
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
|
||||
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
|
||||
#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */
|
||||
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */
|
||||
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
|
||||
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
|
||||
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
|
||||
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
|
||||
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
|
||||
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
|
||||
#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
|
||||
#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
|
||||
#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
|
||||
#define STM32_IRQ_DFSDM2 (STM32_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */
|
||||
#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
|
||||
#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
|
||||
#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
|
||||
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
|
||||
#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
|
||||
#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
|
||||
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */
|
||||
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
|
||||
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
|
||||
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
|
||||
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */
|
||||
#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */
|
||||
#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */
|
||||
#define STM32_IRQ_RESERVED78 (STM32_IRQ_FIRST + 78) /* 78: Reserved */
|
||||
#define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST + 79) /* 79: Reserved */
|
||||
#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */
|
||||
#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */
|
||||
|
||||
#define STM32L4_IRQ_NEXTINTS 82
|
||||
#define STM32_IRQ_NEXTINTS 82
|
||||
|
||||
/* EXTI interrupts (Do not use IRQ numbers) */
|
||||
|
||||
#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS)
|
||||
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
|
||||
@@ -48,117 +48,117 @@
|
||||
* External interrupts (vectors >= 16)
|
||||
*/
|
||||
|
||||
#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */
|
||||
#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */
|
||||
#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */
|
||||
#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
|
||||
#define STM32L4_IRQ_ADC12 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */
|
||||
#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
|
||||
#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
|
||||
#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
|
||||
#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
|
||||
#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
|
||||
#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
|
||||
#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
|
||||
#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
|
||||
#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
|
||||
#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
|
||||
#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
|
||||
#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
|
||||
#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
|
||||
#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
|
||||
#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
|
||||
#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||
#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
|
||||
#define STM32L4_IRQ_ADC3 (STM32L4_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */
|
||||
#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */
|
||||
#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
|
||||
#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
|
||||
#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
|
||||
#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
|
||||
#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
|
||||
#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
|
||||
#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||
#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
|
||||
#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
|
||||
#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
|
||||
#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */
|
||||
#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
|
||||
#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
|
||||
#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
|
||||
#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
|
||||
#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
|
||||
#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */
|
||||
#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
|
||||
#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
|
||||
#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
|
||||
#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */
|
||||
#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */
|
||||
#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */
|
||||
#define STM32L4_IRQ_LCD (STM32L4_IRQ_FIRST + 78) /* 78: LCD global interrupt */
|
||||
#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */
|
||||
#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */
|
||||
#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */
|
||||
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */
|
||||
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */
|
||||
#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */
|
||||
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
|
||||
#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */
|
||||
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
|
||||
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
|
||||
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
|
||||
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
|
||||
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
|
||||
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
|
||||
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
|
||||
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
|
||||
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
|
||||
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
|
||||
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
|
||||
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
|
||||
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
|
||||
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
|
||||
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
|
||||
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
#define STM32_IRQ_DFSDM3 (STM32_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
|
||||
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
|
||||
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
|
||||
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
|
||||
#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */
|
||||
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */
|
||||
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
|
||||
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
|
||||
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
|
||||
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
|
||||
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
|
||||
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
|
||||
#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
|
||||
#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
|
||||
#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
|
||||
#define STM32_IRQ_DFSDM2 (STM32_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */
|
||||
#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
|
||||
#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
|
||||
#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
|
||||
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
|
||||
#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
|
||||
#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
|
||||
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */
|
||||
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
|
||||
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
|
||||
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
|
||||
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */
|
||||
#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */
|
||||
#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */
|
||||
#define STM32_IRQ_LCD (STM32_IRQ_FIRST + 78) /* 78: LCD global interrupt */
|
||||
#define STM32_IRQ_AES (STM32_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */
|
||||
#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */
|
||||
#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */
|
||||
|
||||
/* STM32L496xx/4A6xx only: */
|
||||
|
||||
#define STM32L4_IRQ_HASH_CRS (STM32L4_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */
|
||||
#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */
|
||||
#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */
|
||||
#define STM32L4_IRQ_DCMI (STM32L4_IRQ_FIRST + 85) /* 85: DCMI global interrupt */
|
||||
#define STM32L4_IRQ_CAN2TX (STM32L4_IRQ_FIRST + 86) /* 86: CAN2 TX interrupts */
|
||||
#define STM32L4_IRQ_CAN2RX0 (STM32L4_IRQ_FIRST + 87) /* 87: CAN2 RX0 interrupts */
|
||||
#define STM32L4_IRQ_CAN2RX1 (STM32L4_IRQ_FIRST + 88) /* 88: CAN2 RX1 interrupt */
|
||||
#define STM32L4_IRQ_CAN2SCE (STM32L4_IRQ_FIRST + 89) /* 89: CAN2 SCE interrupt */
|
||||
#define STM32L4_IRQ_DMA2D (STM32L4_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */
|
||||
#define STM32_IRQ_HASH_CRS (STM32_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */
|
||||
#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */
|
||||
#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */
|
||||
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 85) /* 85: DCMI global interrupt */
|
||||
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST + 86) /* 86: CAN2 TX interrupts */
|
||||
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST + 87) /* 87: CAN2 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST + 88) /* 88: CAN2 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST + 89) /* 89: CAN2 SCE interrupt */
|
||||
#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX)
|
||||
# define STM32L4_IRQ_NEXTINTS 82
|
||||
# define STM32_IRQ_NEXTINTS 82
|
||||
#elif defined(CONFIG_STM32L4_STM32L496XX)
|
||||
# define STM32L4_IRQ_NEXTINTS 91
|
||||
# define STM32_IRQ_NEXTINTS 91
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
#endif
|
||||
|
||||
/* EXTI interrupts (Do not use IRQ numbers) */
|
||||
|
||||
#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS)
|
||||
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
|
||||
@@ -48,109 +48,109 @@
|
||||
* External interrupts (vectors >= 16)
|
||||
*/
|
||||
|
||||
#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */
|
||||
#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */
|
||||
#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */
|
||||
#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
|
||||
#define STM32L4_IRQ_ADC1 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */
|
||||
#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
|
||||
#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
|
||||
#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
|
||||
#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
|
||||
#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
|
||||
#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
|
||||
#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
|
||||
#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
|
||||
#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
|
||||
#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
|
||||
#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
|
||||
#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
|
||||
#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
|
||||
#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
|
||||
#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
|
||||
#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||
#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
|
||||
/* Reserved 47: ADC3 global interrupt */
|
||||
#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */
|
||||
#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
|
||||
#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
|
||||
#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
|
||||
#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
|
||||
#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
|
||||
#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
|
||||
#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||
#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
|
||||
#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
|
||||
#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
|
||||
#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */
|
||||
#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
|
||||
#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
|
||||
#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
|
||||
#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
|
||||
#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
|
||||
#define STM32L4_IRQ_OCTOSPI1 (STM32L4_IRQ_FIRST + 71) /* 71: OCTOSPI1 global interrupt */
|
||||
#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
|
||||
#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
|
||||
#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
|
||||
#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */
|
||||
#define STM32L4_IRQ_OCTOSPI2 (STM32L4_IRQ_FIRST + 76) /* 76: OCTOSPI2 global interrupt */
|
||||
#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */
|
||||
#define STM32L4_IRQ_DSIHSOT (STM32L4_IRQ_FIRST + 78) /* 78: DSI global interrupt */
|
||||
#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */
|
||||
#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */
|
||||
#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */
|
||||
#define STM32L4_IRQ_HASH_CRS (STM32L4_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */
|
||||
#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */
|
||||
#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */
|
||||
#define STM32L4_IRQ_DCMI (STM32L4_IRQ_FIRST + 85) /* 85: DCMI global interrupt */
|
||||
/* Reserved 86-89: CAN2 */
|
||||
#define STM32L4_IRQ_DMA2D (STM32L4_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */
|
||||
#define STM32L4_IRQ_LCD_TFT (STM32L4_IRQ_FIRST + 91) /* 91: LTDC global interrupt */
|
||||
#define STM32L4_IRQ_LCD_TFT_ER (STM32L4_IRQ_FIRST + 92) /* 92: LTDC global error interrupt */
|
||||
#define STM32L4_IRQ_GFXMMU (STM32L4_IRQ_FIRST + 93) /* 93: GFXMMU global error interrupt */
|
||||
#define STM32L4_IRQ_DMAMUX1_OVR (STM32L4_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */
|
||||
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */
|
||||
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */
|
||||
#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */
|
||||
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
|
||||
#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */
|
||||
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
|
||||
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
|
||||
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
|
||||
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
|
||||
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
|
||||
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
|
||||
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
|
||||
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
|
||||
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
|
||||
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
|
||||
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
|
||||
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
|
||||
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
|
||||
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
|
||||
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
|
||||
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
#define STM32_IRQ_DFSDM3 (STM32_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
|
||||
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
|
||||
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
|
||||
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
|
||||
/* Reserved 47: ADC3 global interrupt */
|
||||
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */
|
||||
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
|
||||
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
|
||||
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
|
||||
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
|
||||
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
|
||||
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
|
||||
#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
|
||||
#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
|
||||
#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
|
||||
#define STM32_IRQ_DFSDM2 (STM32_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */
|
||||
#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
|
||||
#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
|
||||
#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
|
||||
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
|
||||
#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
|
||||
#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
|
||||
#define STM32_IRQ_OCTOSPI1 (STM32_IRQ_FIRST + 71) /* 71: OCTOSPI1 global interrupt */
|
||||
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
|
||||
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
|
||||
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
|
||||
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */
|
||||
#define STM32_IRQ_OCTOSPI2 (STM32_IRQ_FIRST + 76) /* 76: OCTOSPI2 global interrupt */
|
||||
#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */
|
||||
#define STM32_IRQ_DSIHSOT (STM32_IRQ_FIRST + 78) /* 78: DSI global interrupt */
|
||||
#define STM32_IRQ_AES (STM32_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */
|
||||
#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */
|
||||
#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */
|
||||
#define STM32_IRQ_HASH_CRS (STM32_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */
|
||||
#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */
|
||||
#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */
|
||||
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 85) /* 85: DCMI global interrupt */
|
||||
/* Reserved 86-89: CAN2 */
|
||||
#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */
|
||||
#define STM32_IRQ_LCD_TFT (STM32_IRQ_FIRST + 91) /* 91: LTDC global interrupt */
|
||||
#define STM32_IRQ_LCD_TFT_ER (STM32_IRQ_FIRST + 92) /* 92: LTDC global error interrupt */
|
||||
#define STM32_IRQ_GFXMMU (STM32_IRQ_FIRST + 93) /* 93: GFXMMU global error interrupt */
|
||||
#define STM32_IRQ_DMAMUX1_OVR (STM32_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */
|
||||
|
||||
#define STM32L4_IRQ_NEXTINTS 95
|
||||
#define STM32_IRQ_NEXTINTS 95
|
||||
|
||||
/* EXTI interrupts (Do not use IRQ numbers) */
|
||||
|
||||
#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS)
|
||||
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
|
||||
@@ -49,7 +49,7 @@
|
||||
* arch/stm32l4/chip.h header file.
|
||||
*/
|
||||
|
||||
#define ARMV7M_PERIPHERAL_INTERRUPTS STM32L4_IRQ_NEXTINTS
|
||||
#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS
|
||||
|
||||
/* Cache line sizes (in bytes) for the STM32L4 */
|
||||
|
||||
|
||||
@@ -41,136 +41,136 @@
|
||||
* offset 0x0100 for slave.
|
||||
*/
|
||||
|
||||
#define STM32L4_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */
|
||||
#define STM32L4_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */
|
||||
#define STM32L4_ADC_CR_OFFSET 0x0008 /* ADC control register */
|
||||
#define STM32L4_ADC_CFGR_OFFSET 0x000c /* ADC configuration register */
|
||||
#define STM32L4_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */
|
||||
#define STM32L4_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */
|
||||
#define STM32L4_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */
|
||||
#define STM32L4_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */
|
||||
#define STM32L4_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */
|
||||
#define STM32L4_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */
|
||||
#define STM32L4_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */
|
||||
#define STM32L4_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */
|
||||
#define STM32L4_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */
|
||||
#define STM32L4_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 */
|
||||
#define STM32L4_ADC_DR_OFFSET 0x0040 /* ADC regular data register */
|
||||
#define STM32L4_ADC_JSQR_OFFSET 0x004c /* ADC injected sequence register */
|
||||
#define STM32L4_ADC_OFR1_OFFSET 0x0060 /* ADC offset register 1 */
|
||||
#define STM32L4_ADC_OFR2_OFFSET 0x0064 /* ADC offset register 2 */
|
||||
#define STM32L4_ADC_OFR3_OFFSET 0x0068 /* ADC offset register 3 */
|
||||
#define STM32L4_ADC_OFR4_OFFSET 0x006c /* ADC offset register 4 */
|
||||
#define STM32L4_ADC_JDR1_OFFSET 0x0080 /* ADC injected data register 1 */
|
||||
#define STM32L4_ADC_JDR2_OFFSET 0x0084 /* ADC injected data register 2 */
|
||||
#define STM32L4_ADC_JDR3_OFFSET 0x0088 /* ADC injected data register 3 */
|
||||
#define STM32L4_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */
|
||||
#define STM32L4_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */
|
||||
#define STM32L4_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */
|
||||
#define STM32L4_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register 2 */
|
||||
#define STM32L4_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */
|
||||
#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */
|
||||
#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */
|
||||
#define STM32_ADC_CR_OFFSET 0x0008 /* ADC control register */
|
||||
#define STM32_ADC_CFGR_OFFSET 0x000c /* ADC configuration register */
|
||||
#define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */
|
||||
#define STM32_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */
|
||||
#define STM32_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */
|
||||
#define STM32_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */
|
||||
#define STM32_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */
|
||||
#define STM32_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */
|
||||
#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */
|
||||
#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */
|
||||
#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */
|
||||
#define STM32_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 */
|
||||
#define STM32_ADC_DR_OFFSET 0x0040 /* ADC regular data register */
|
||||
#define STM32_ADC_JSQR_OFFSET 0x004c /* ADC injected sequence register */
|
||||
#define STM32_ADC_OFR1_OFFSET 0x0060 /* ADC offset register 1 */
|
||||
#define STM32_ADC_OFR2_OFFSET 0x0064 /* ADC offset register 2 */
|
||||
#define STM32_ADC_OFR3_OFFSET 0x0068 /* ADC offset register 3 */
|
||||
#define STM32_ADC_OFR4_OFFSET 0x006c /* ADC offset register 4 */
|
||||
#define STM32_ADC_JDR1_OFFSET 0x0080 /* ADC injected data register 1 */
|
||||
#define STM32_ADC_JDR2_OFFSET 0x0084 /* ADC injected data register 2 */
|
||||
#define STM32_ADC_JDR3_OFFSET 0x0088 /* ADC injected data register 3 */
|
||||
#define STM32_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */
|
||||
#define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */
|
||||
#define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */
|
||||
#define STM32_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register 2 */
|
||||
#define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */
|
||||
|
||||
/* Master and Slave ADC Common Registers */
|
||||
|
||||
#define STM32L4_ADC_CSR_OFFSET 0x0000 /* Common status register */
|
||||
#define STM32L4_ADC_CCR_OFFSET 0x0008 /* Common control register */
|
||||
#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */
|
||||
#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */
|
||||
#ifndef CONFIG_STM32L4_STM32L4X3
|
||||
# define STM32L4_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */
|
||||
# define STM32_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */
|
||||
#endif
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_ADC1_ISR (STM32L4_ADC1_BASE+STM32L4_ADC_ISR_OFFSET)
|
||||
#define STM32L4_ADC1_IER (STM32L4_ADC1_BASE+STM32L4_ADC_IER_OFFSET)
|
||||
#define STM32L4_ADC1_CR (STM32L4_ADC1_BASE+STM32L4_ADC_CR_OFFSET)
|
||||
#define STM32L4_ADC1_CFGR (STM32L4_ADC1_BASE+STM32L4_ADC_CFGR_OFFSET)
|
||||
#define STM32L4_ADC1_CFGR2 (STM32L4_ADC1_BASE+STM32L4_ADC_CFGR2_OFFSET)
|
||||
#define STM32L4_ADC1_SMPR1 (STM32L4_ADC1_BASE+STM32L4_ADC_SMPR1_OFFSET)
|
||||
#define STM32L4_ADC1_SMPR2 (STM32L4_ADC1_BASE+STM32L4_ADC_SMPR2_OFFSET)
|
||||
#define STM32L4_ADC1_TR1 (STM32L4_ADC1_BASE+STM32L4_ADC_TR1_OFFSET)
|
||||
#define STM32L4_ADC1_TR2 (STM32L4_ADC1_BASE+STM32L4_ADC_TR2_OFFSET)
|
||||
#define STM32L4_ADC1_TR3 (STM32L4_ADC1_BASE+STM32L4_ADC_TR3_OFFSET)
|
||||
#define STM32L4_ADC1_SQR1 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR1_OFFSET)
|
||||
#define STM32L4_ADC1_SQR2 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR2_OFFSET)
|
||||
#define STM32L4_ADC1_SQR3 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR3_OFFSET)
|
||||
#define STM32L4_ADC1_SQR4 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR4_OFFSET)
|
||||
#define STM32L4_ADC1_DR (STM32L4_ADC1_BASE+STM32L4_ADC_DR_OFFSET)
|
||||
#define STM32L4_ADC1_JSQR (STM32L4_ADC1_BASE+STM32L4_ADC_JSQR_OFFSET)
|
||||
#define STM32L4_ADC1_OFR1 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR1_OFFSET)
|
||||
#define STM32L4_ADC1_OFR2 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR2_OFFSET)
|
||||
#define STM32L4_ADC1_OFR3 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR3_OFFSET)
|
||||
#define STM32L4_ADC1_OFR4 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR4_OFFSET)
|
||||
#define STM32L4_ADC1_JDR1 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR1_OFFSET)
|
||||
#define STM32L4_ADC1_JDR2 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR2_OFFSET)
|
||||
#define STM32L4_ADC1_JDR3 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR3_OFFSET)
|
||||
#define STM32L4_ADC1_JDR4 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR4_OFFSET)
|
||||
#define STM32L4_ADC1_AWD2CR (STM32L4_ADC1_BASE+STM32L4_ADC_AWD2CR_OFFSET)
|
||||
#define STM32L4_ADC1_AWD3CR (STM32L4_ADC1_BASE+STM32L4_ADC_AWD3CR_OFFSET)
|
||||
#define STM32L4_ADC1_DIFSEL (STM32L4_ADC1_BASE+STM32L4_ADC_DIFSEL_OFFSET)
|
||||
#define STM32L4_ADC1_CALFACT (STM32L4_ADC1_BASE+STM32L4_ADC_CALFACT_OFFSET)
|
||||
#define STM32_ADC1_ISR (STM32_ADC1_BASE+STM32_ADC_ISR_OFFSET)
|
||||
#define STM32_ADC1_IER (STM32_ADC1_BASE+STM32_ADC_IER_OFFSET)
|
||||
#define STM32_ADC1_CR (STM32_ADC1_BASE+STM32_ADC_CR_OFFSET)
|
||||
#define STM32_ADC1_CFGR (STM32_ADC1_BASE+STM32_ADC_CFGR_OFFSET)
|
||||
#define STM32_ADC1_CFGR2 (STM32_ADC1_BASE+STM32_ADC_CFGR2_OFFSET)
|
||||
#define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
#define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
#define STM32_ADC1_TR1 (STM32_ADC1_BASE+STM32_ADC_TR1_OFFSET)
|
||||
#define STM32_ADC1_TR2 (STM32_ADC1_BASE+STM32_ADC_TR2_OFFSET)
|
||||
#define STM32_ADC1_TR3 (STM32_ADC1_BASE+STM32_ADC_TR3_OFFSET)
|
||||
#define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
#define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
#define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
#define STM32_ADC1_SQR4 (STM32_ADC1_BASE+STM32_ADC_SQR4_OFFSET)
|
||||
#define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET)
|
||||
#define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
#define STM32_ADC1_OFR1 (STM32_ADC1_BASE+STM32_ADC_OFR1_OFFSET)
|
||||
#define STM32_ADC1_OFR2 (STM32_ADC1_BASE+STM32_ADC_OFR2_OFFSET)
|
||||
#define STM32_ADC1_OFR3 (STM32_ADC1_BASE+STM32_ADC_OFR3_OFFSET)
|
||||
#define STM32_ADC1_OFR4 (STM32_ADC1_BASE+STM32_ADC_OFR4_OFFSET)
|
||||
#define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
#define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
#define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
#define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
#define STM32_ADC1_AWD2CR (STM32_ADC1_BASE+STM32_ADC_AWD2CR_OFFSET)
|
||||
#define STM32_ADC1_AWD3CR (STM32_ADC1_BASE+STM32_ADC_AWD3CR_OFFSET)
|
||||
#define STM32_ADC1_DIFSEL (STM32_ADC1_BASE+STM32_ADC_DIFSEL_OFFSET)
|
||||
#define STM32_ADC1_CALFACT (STM32_ADC1_BASE+STM32_ADC_CALFACT_OFFSET)
|
||||
|
||||
#define STM32L4_ADC2_ISR (STM32L4_ADC2_BASE+STM32L4_ADC_ISR_OFFSET)
|
||||
#define STM32L4_ADC2_IER (STM32L4_ADC2_BASE+STM32L4_ADC_IER_OFFSET)
|
||||
#define STM32L4_ADC2_CR (STM32L4_ADC2_BASE+STM32L4_ADC_CR_OFFSET)
|
||||
#define STM32L4_ADC2_CFGR (STM32L4_ADC2_BASE+STM32L4_ADC_CFGR_OFFSET)
|
||||
#define STM32L4_ADC2_CFGR2 (STM32L4_ADC2_BASE+STM32L4_ADC_CFGR2_OFFSET)
|
||||
#define STM32L4_ADC2_SMPR1 (STM32L4_ADC2_BASE+STM32L4_ADC_SMPR1_OFFSET)
|
||||
#define STM32L4_ADC2_SMPR2 (STM32L4_ADC2_BASE+STM32L4_ADC_SMPR2_OFFSET)
|
||||
#define STM32L4_ADC2_TR1 (STM32L4_ADC2_BASE+STM32L4_ADC_TR1_OFFSET)
|
||||
#define STM32L4_ADC2_TR2 (STM32L4_ADC2_BASE+STM32L4_ADC_TR2_OFFSET)
|
||||
#define STM32L4_ADC2_TR3 (STM32L4_ADC2_BASE+STM32L4_ADC_TR3_OFFSET)
|
||||
#define STM32L4_ADC2_SQR1 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR1_OFFSET)
|
||||
#define STM32L4_ADC2_SQR2 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR2_OFFSET)
|
||||
#define STM32L4_ADC2_SQR3 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR3_OFFSET)
|
||||
#define STM32L4_ADC2_SQR4 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR4_OFFSET)
|
||||
#define STM32L4_ADC2_DR (STM32L4_ADC2_BASE+STM32L4_ADC_DR_OFFSET)
|
||||
#define STM32L4_ADC2_JSQR (STM32L4_ADC2_BASE+STM32L4_ADC_JSQR_OFFSET)
|
||||
#define STM32L4_ADC2_OFR1 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR1_OFFSET)
|
||||
#define STM32L4_ADC2_OFR2 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR2_OFFSET)
|
||||
#define STM32L4_ADC2_OFR3 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR3_OFFSET)
|
||||
#define STM32L4_ADC2_OFR4 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR4_OFFSET)
|
||||
#define STM32L4_ADC2_JDR1 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR1_OFFSET)
|
||||
#define STM32L4_ADC2_JDR2 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR2_OFFSET)
|
||||
#define STM32L4_ADC2_JDR3 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR3_OFFSET)
|
||||
#define STM32L4_ADC2_JDR4 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR4_OFFSET)
|
||||
#define STM32L4_ADC2_AWD2CR (STM32L4_ADC2_BASE+STM32L4_ADC_AWD2CR_OFFSET)
|
||||
#define STM32L4_ADC2_AWD3CR (STM32L4_ADC2_BASE+STM32L4_ADC_AWD3CR_OFFSET)
|
||||
#define STM32L4_ADC2_DIFSEL (STM32L4_ADC2_BASE+STM32L4_ADC_DIFSEL_OFFSET)
|
||||
#define STM32L4_ADC2_CALFACT (STM32L4_ADC2_BASE+STM32L4_ADC_CALFACT_OFFSET)
|
||||
#define STM32_ADC2_ISR (STM32_ADC2_BASE+STM32_ADC_ISR_OFFSET)
|
||||
#define STM32_ADC2_IER (STM32_ADC2_BASE+STM32_ADC_IER_OFFSET)
|
||||
#define STM32_ADC2_CR (STM32_ADC2_BASE+STM32_ADC_CR_OFFSET)
|
||||
#define STM32_ADC2_CFGR (STM32_ADC2_BASE+STM32_ADC_CFGR_OFFSET)
|
||||
#define STM32_ADC2_CFGR2 (STM32_ADC2_BASE+STM32_ADC_CFGR2_OFFSET)
|
||||
#define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
#define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
#define STM32_ADC2_TR1 (STM32_ADC2_BASE+STM32_ADC_TR1_OFFSET)
|
||||
#define STM32_ADC2_TR2 (STM32_ADC2_BASE+STM32_ADC_TR2_OFFSET)
|
||||
#define STM32_ADC2_TR3 (STM32_ADC2_BASE+STM32_ADC_TR3_OFFSET)
|
||||
#define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
#define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
#define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
#define STM32_ADC2_SQR4 (STM32_ADC2_BASE+STM32_ADC_SQR4_OFFSET)
|
||||
#define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET)
|
||||
#define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
#define STM32_ADC2_OFR1 (STM32_ADC2_BASE+STM32_ADC_OFR1_OFFSET)
|
||||
#define STM32_ADC2_OFR2 (STM32_ADC2_BASE+STM32_ADC_OFR2_OFFSET)
|
||||
#define STM32_ADC2_OFR3 (STM32_ADC2_BASE+STM32_ADC_OFR3_OFFSET)
|
||||
#define STM32_ADC2_OFR4 (STM32_ADC2_BASE+STM32_ADC_OFR4_OFFSET)
|
||||
#define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
#define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
#define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
#define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
#define STM32_ADC2_AWD2CR (STM32_ADC2_BASE+STM32_ADC_AWD2CR_OFFSET)
|
||||
#define STM32_ADC2_AWD3CR (STM32_ADC2_BASE+STM32_ADC_AWD3CR_OFFSET)
|
||||
#define STM32_ADC2_DIFSEL (STM32_ADC2_BASE+STM32_ADC_DIFSEL_OFFSET)
|
||||
#define STM32_ADC2_CALFACT (STM32_ADC2_BASE+STM32_ADC_CALFACT_OFFSET)
|
||||
|
||||
#define STM32L4_ADC3_ISR (STM32L4_ADC3_BASE+STM32L4_ADC_ISR_OFFSET)
|
||||
#define STM32L4_ADC3_IER (STM32L4_ADC3_BASE+STM32L4_ADC_IER_OFFSET)
|
||||
#define STM32L4_ADC3_CR (STM32L4_ADC3_BASE+STM32L4_ADC_CR_OFFSET)
|
||||
#define STM32L4_ADC3_CFGR (STM32L4_ADC3_BASE+STM32L4_ADC_CFGR_OFFSET)
|
||||
#define STM32L4_ADC3_CFGR2 (STM32L4_ADC3_BASE+STM32L4_ADC_CFGR2_OFFSET)
|
||||
#define STM32L4_ADC3_SMPR1 (STM32L4_ADC3_BASE+STM32L4_ADC_SMPR1_OFFSET)
|
||||
#define STM32L4_ADC3_SMPR2 (STM32L4_ADC3_BASE+STM32L4_ADC_SMPR2_OFFSET)
|
||||
#define STM32L4_ADC3_TR1 (STM32L4_ADC3_BASE+STM32L4_ADC_TR1_OFFSET)
|
||||
#define STM32L4_ADC3_TR2 (STM32L4_ADC3_BASE+STM32L4_ADC_TR2_OFFSET)
|
||||
#define STM32L4_ADC3_TR3 (STM32L4_ADC3_BASE+STM32L4_ADC_TR3_OFFSET)
|
||||
#define STM32L4_ADC3_SQR1 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR1_OFFSET)
|
||||
#define STM32L4_ADC3_SQR2 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR2_OFFSET)
|
||||
#define STM32L4_ADC3_SQR3 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR3_OFFSET)
|
||||
#define STM32L4_ADC3_SQR4 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR4_OFFSET)
|
||||
#define STM32L4_ADC3_DR (STM32L4_ADC3_BASE+STM32L4_ADC_DR_OFFSET)
|
||||
#define STM32L4_ADC3_JSQR (STM32L4_ADC3_BASE+STM32L4_ADC_JSQR_OFFSET)
|
||||
#define STM32L4_ADC3_OFR1 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR1_OFFSET)
|
||||
#define STM32L4_ADC3_OFR2 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR2_OFFSET)
|
||||
#define STM32L4_ADC3_OFR3 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR3_OFFSET)
|
||||
#define STM32L4_ADC3_OFR4 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR4_OFFSET)
|
||||
#define STM32L4_ADC3_JDR1 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR1_OFFSET)
|
||||
#define STM32L4_ADC3_JDR2 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR2_OFFSET)
|
||||
#define STM32L4_ADC3_JDR3 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR3_OFFSET)
|
||||
#define STM32L4_ADC3_JDR4 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR4_OFFSET)
|
||||
#define STM32L4_ADC3_AWD2CR (STM32L4_ADC3_BASE+STM32L4_ADC_AWD2CR_OFFSET)
|
||||
#define STM32L4_ADC3_AWD3CR (STM32L4_ADC3_BASE+STM32L4_ADC_AWD3CR_OFFSET)
|
||||
#define STM32L4_ADC3_DIFSEL (STM32L4_ADC3_BASE+STM32L4_ADC_DIFSEL_OFFSET)
|
||||
#define STM32L4_ADC3_CALFACT (STM32L4_ADC3_BASE+STM32L4_ADC_CALFACT_OFFSET)
|
||||
#define STM32_ADC3_ISR (STM32_ADC3_BASE+STM32_ADC_ISR_OFFSET)
|
||||
#define STM32_ADC3_IER (STM32_ADC3_BASE+STM32_ADC_IER_OFFSET)
|
||||
#define STM32_ADC3_CR (STM32_ADC3_BASE+STM32_ADC_CR_OFFSET)
|
||||
#define STM32_ADC3_CFGR (STM32_ADC3_BASE+STM32_ADC_CFGR_OFFSET)
|
||||
#define STM32_ADC3_CFGR2 (STM32_ADC3_BASE+STM32_ADC_CFGR2_OFFSET)
|
||||
#define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
#define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
#define STM32_ADC3_TR1 (STM32_ADC3_BASE+STM32_ADC_TR1_OFFSET)
|
||||
#define STM32_ADC3_TR2 (STM32_ADC3_BASE+STM32_ADC_TR2_OFFSET)
|
||||
#define STM32_ADC3_TR3 (STM32_ADC3_BASE+STM32_ADC_TR3_OFFSET)
|
||||
#define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
#define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
#define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
#define STM32_ADC3_SQR4 (STM32_ADC3_BASE+STM32_ADC_SQR4_OFFSET)
|
||||
#define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET)
|
||||
#define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
#define STM32_ADC3_OFR1 (STM32_ADC3_BASE+STM32_ADC_OFR1_OFFSET)
|
||||
#define STM32_ADC3_OFR2 (STM32_ADC3_BASE+STM32_ADC_OFR2_OFFSET)
|
||||
#define STM32_ADC3_OFR3 (STM32_ADC3_BASE+STM32_ADC_OFR3_OFFSET)
|
||||
#define STM32_ADC3_OFR4 (STM32_ADC3_BASE+STM32_ADC_OFR4_OFFSET)
|
||||
#define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
#define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
#define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
#define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
#define STM32_ADC3_AWD2CR (STM32_ADC3_BASE+STM32_ADC_AWD2CR_OFFSET)
|
||||
#define STM32_ADC3_AWD3CR (STM32_ADC3_BASE+STM32_ADC_AWD3CR_OFFSET)
|
||||
#define STM32_ADC3_DIFSEL (STM32_ADC3_BASE+STM32_ADC_DIFSEL_OFFSET)
|
||||
#define STM32_ADC3_CALFACT (STM32_ADC3_BASE+STM32_ADC_CALFACT_OFFSET)
|
||||
|
||||
#define STM32L4_ADC_CSR (STM32L4_ADCCMN_BASE+STM32L4_ADC_CSR_OFFSET)
|
||||
#define STM32L4_ADC_CCR (STM32L4_ADCCMN_BASE+STM32L4_ADC_CCR_OFFSET)
|
||||
#define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET)
|
||||
#define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET)
|
||||
#ifndef CONFIG_STM32L4_STM32L4X3
|
||||
# define STM32L4_ADC_CDR (STM32L4_ADCCMN_BASE+STM32L4_ADC_CDR_OFFSET)
|
||||
# define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
@@ -286,10 +286,12 @@
|
||||
# define ADC_CFGR2_OVSR_64X (5 << ADC_CFGR2_OVSR_SHIFT) /* 64X oversampling */
|
||||
# define ADC_CFGR2_OVSR_128X (6 << ADC_CFGR2_OVSR_SHIFT) /* 128X oversampling */
|
||||
# define ADC_CFGR2_OVSR_256X (7 << ADC_CFGR2_OVSR_SHIFT) /* 256X oversampling */
|
||||
|
||||
#define ADC_CFGR2_OVSS_SHIFT (5) /* Bits 5-8: Oversampling shift */
|
||||
#define ADC_CFGR2_OVSS_MASK (0xf << ADC_CFGR2_OVSS_SHIFT)
|
||||
# define ADC_CFGR2_OVSS(value) ((value) << ADC_CFGR2_OVSS_SHIFT)
|
||||
/* Value = 0..8 */
|
||||
/* Value = 0..8 */
|
||||
|
||||
#define ADC_CFGR2_TROVS (1 << 9) /* Bit 9: Triggered Regular Oversampling */
|
||||
#define ADC_CFGR2_ROVSM (1 << 10) /* Bit 10: Regular Oversampling mode */
|
||||
|
||||
|
||||
@@ -54,61 +54,61 @@
|
||||
|
||||
/* CAN control and status registers */
|
||||
|
||||
#define STM32L4_CAN_MCR_OFFSET 0x0000 /* CAN master control register */
|
||||
#define STM32L4_CAN_MSR_OFFSET 0x0004 /* CAN master status register */
|
||||
#define STM32L4_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */
|
||||
#define STM32L4_CAN_RFR_OFFSET(m) (0x000c + ((m) << 2))
|
||||
#define STM32L4_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */
|
||||
#define STM32L4_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */
|
||||
#define STM32L4_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */
|
||||
#define STM32L4_CAN_ESR_OFFSET 0x0018 /* CAN error status register */
|
||||
#define STM32L4_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */
|
||||
#define STM32_CAN_MCR_OFFSET 0x0000 /* CAN master control register */
|
||||
#define STM32_CAN_MSR_OFFSET 0x0004 /* CAN master status register */
|
||||
#define STM32_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */
|
||||
#define STM32_CAN_RFR_OFFSET(m) (0x000c + ((m) << 2))
|
||||
#define STM32_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */
|
||||
#define STM32_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */
|
||||
#define STM32_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */
|
||||
#define STM32_CAN_ESR_OFFSET 0x0018 /* CAN error status register */
|
||||
#define STM32_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */
|
||||
|
||||
/* CAN mailbox registers (3 TX and 2 RX) */
|
||||
|
||||
#define STM32L4_CAN_TIR_OFFSET(m) (0x0180 + ((m) << 4))
|
||||
#define STM32L4_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */
|
||||
#define STM32L4_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */
|
||||
#define STM32L4_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */
|
||||
#define STM32_CAN_TIR_OFFSET(m) (0x0180 + ((m) << 4))
|
||||
#define STM32_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */
|
||||
#define STM32_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */
|
||||
#define STM32_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */
|
||||
|
||||
#define STM32L4_CAN_TDTR_OFFSET(m) (0x0184 + ((m) << 4))
|
||||
#define STM32L4_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */
|
||||
#define STM32L4_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */
|
||||
#define STM32L4_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */
|
||||
#define STM32_CAN_TDTR_OFFSET(m) (0x0184 + ((m) << 4))
|
||||
#define STM32_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */
|
||||
#define STM32_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */
|
||||
#define STM32_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */
|
||||
|
||||
#define STM32L4_CAN_TDLR_OFFSET(m) (0x0188 + ((m) << 4))
|
||||
#define STM32L4_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */
|
||||
#define STM32L4_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */
|
||||
#define STM32L4_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */
|
||||
#define STM32_CAN_TDLR_OFFSET(m) (0x0188 + ((m) << 4))
|
||||
#define STM32_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */
|
||||
#define STM32_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */
|
||||
#define STM32_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */
|
||||
|
||||
#define STM32L4_CAN_TDHR_OFFSET(m) (0x018c + ((m) << 4))
|
||||
#define STM32L4_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */
|
||||
#define STM32L4_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */
|
||||
#define STM32L4_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */
|
||||
#define STM32_CAN_TDHR_OFFSET(m) (0x018c + ((m) << 4))
|
||||
#define STM32_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */
|
||||
#define STM32_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */
|
||||
#define STM32_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */
|
||||
|
||||
#define STM32L4_CAN_RIR_OFFSET(m) (0x01b0 + ((m) << 4))
|
||||
#define STM32L4_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */
|
||||
#define STM32L4_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */
|
||||
#define STM32_CAN_RIR_OFFSET(m) (0x01b0 + ((m) << 4))
|
||||
#define STM32_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */
|
||||
#define STM32_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */
|
||||
|
||||
#define STM32L4_CAN_RDTR_OFFSET(m) (0x01b4 + ((m) << 4))
|
||||
#define STM32L4_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */
|
||||
#define STM32L4_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */
|
||||
#define STM32_CAN_RDTR_OFFSET(m) (0x01b4 + ((m) << 4))
|
||||
#define STM32_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */
|
||||
#define STM32_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */
|
||||
|
||||
#define STM32L4_CAN_RDLR_OFFSET(m) (0x01b8 + ((m) << 4))
|
||||
#define STM32L4_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */
|
||||
#define STM32L4_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */
|
||||
#define STM32_CAN_RDLR_OFFSET(m) (0x01b8 + ((m) << 4))
|
||||
#define STM32_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */
|
||||
#define STM32_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */
|
||||
|
||||
#define STM32L4_CAN_RDHR_OFFSET(m) (0x01bc + ((m) << 4))
|
||||
#define STM32L4_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */
|
||||
#define STM32L4_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */
|
||||
#define STM32_CAN_RDHR_OFFSET(m) (0x01bc + ((m) << 4))
|
||||
#define STM32_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */
|
||||
#define STM32_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */
|
||||
|
||||
/* CAN filter registers */
|
||||
|
||||
#define STM32L4_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */
|
||||
#define STM32L4_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */
|
||||
#define STM32L4_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */
|
||||
#define STM32L4_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */
|
||||
#define STM32L4_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */
|
||||
#define STM32_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */
|
||||
#define STM32_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */
|
||||
#define STM32_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */
|
||||
#define STM32_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */
|
||||
#define STM32_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */
|
||||
|
||||
/* There are 14 filter banks on the device. Each filter bank is
|
||||
* composed of two 32-bit registers, CAN_FiR:
|
||||
@@ -119,63 +119,63 @@
|
||||
* ...
|
||||
*/
|
||||
|
||||
#define STM32L4_CAN_FIR_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2))
|
||||
#define STM32_CAN_FIR_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2))
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#if STM32L4_NCAN > 0
|
||||
# define STM32L4_CAN1_MCR (STM32L4_CAN1_BASE+STM32L4_CAN_MCR_OFFSET)
|
||||
# define STM32L4_CAN1_MSR (STM32L4_CAN1_BASE+STM32L4_CAN_MSR_OFFSET)
|
||||
# define STM32L4_CAN1_TSR (STM32L4_CAN1_BASE+STM32L4_CAN_TSR_OFFSET)
|
||||
# define STM32L4_CAN1_RFR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RFR_OFFSET(m))
|
||||
# define STM32L4_CAN1_RF0R (STM32L4_CAN1_BASE+STM32L4_CAN_RF0R_OFFSET)
|
||||
# define STM32L4_CAN1_RF1R (STM32L4_CAN1_BASE+STM32L4_CAN_RF1R_OFFSET)
|
||||
# define STM32L4_CAN1_IER (STM32L4_CAN1_BASE+STM32L4_CAN_IER_OFFSET)
|
||||
# define STM32L4_CAN1_ESR (STM32L4_CAN1_BASE+STM32L4_CAN_ESR_OFFSET)
|
||||
# define STM32L4_CAN1_BTR (STM32L4_CAN1_BASE+STM32L4_CAN_BTR_OFFSET)
|
||||
#if STM32_NCAN > 0
|
||||
# define STM32_CAN1_MCR (STM32_CAN1_BASE+STM32_CAN_MCR_OFFSET)
|
||||
# define STM32_CAN1_MSR (STM32_CAN1_BASE+STM32_CAN_MSR_OFFSET)
|
||||
# define STM32_CAN1_TSR (STM32_CAN1_BASE+STM32_CAN_TSR_OFFSET)
|
||||
# define STM32_CAN1_RFR(m) (STM32_CAN1_BASE+STM32_CAN_RFR_OFFSET(m))
|
||||
# define STM32_CAN1_RF0R (STM32_CAN1_BASE+STM32_CAN_RF0R_OFFSET)
|
||||
# define STM32_CAN1_RF1R (STM32_CAN1_BASE+STM32_CAN_RF1R_OFFSET)
|
||||
# define STM32_CAN1_IER (STM32_CAN1_BASE+STM32_CAN_IER_OFFSET)
|
||||
# define STM32_CAN1_ESR (STM32_CAN1_BASE+STM32_CAN_ESR_OFFSET)
|
||||
# define STM32_CAN1_BTR (STM32_CAN1_BASE+STM32_CAN_BTR_OFFSET)
|
||||
|
||||
# define STM32L4_CAN1_TIR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TIR_OFFSET(m))
|
||||
# define STM32L4_CAN1_TI0R (STM32L4_CAN1_BASE+STM32L4_CAN_TI0R_OFFSET)
|
||||
# define STM32L4_CAN1_TI1R (STM32L4_CAN1_BASE+STM32L4_CAN_TI1R_OFFSET)
|
||||
# define STM32L4_CAN1_TI2R (STM32L4_CAN1_BASE+STM32L4_CAN_TI2R_OFFSET)
|
||||
# define STM32_CAN1_TIR(m) (STM32_CAN1_BASE+STM32_CAN_TIR_OFFSET(m))
|
||||
# define STM32_CAN1_TI0R (STM32_CAN1_BASE+STM32_CAN_TI0R_OFFSET)
|
||||
# define STM32_CAN1_TI1R (STM32_CAN1_BASE+STM32_CAN_TI1R_OFFSET)
|
||||
# define STM32_CAN1_TI2R (STM32_CAN1_BASE+STM32_CAN_TI2R_OFFSET)
|
||||
|
||||
# define STM32L4_CAN1_TDTR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TDTR_OFFSET(m))
|
||||
# define STM32L4_CAN1_TDT0R (STM32L4_CAN1_BASE+STM32L4_CAN_TDT0R_OFFSET)
|
||||
# define STM32L4_CAN1_TDT1R (STM32L4_CAN1_BASE+STM32L4_CAN_TDT1R_OFFSET)
|
||||
# define STM32L4_CAN1_TDT2R (STM32L4_CAN1_BASE+STM32L4_CAN_TDT2R_OFFSET)
|
||||
# define STM32_CAN1_TDTR(m) (STM32_CAN1_BASE+STM32_CAN_TDTR_OFFSET(m))
|
||||
# define STM32_CAN1_TDT0R (STM32_CAN1_BASE+STM32_CAN_TDT0R_OFFSET)
|
||||
# define STM32_CAN1_TDT1R (STM32_CAN1_BASE+STM32_CAN_TDT1R_OFFSET)
|
||||
# define STM32_CAN1_TDT2R (STM32_CAN1_BASE+STM32_CAN_TDT2R_OFFSET)
|
||||
|
||||
# define STM32L4_CAN1_TDLR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TDLR_OFFSET(m))
|
||||
# define STM32L4_CAN1_TDL0R (STM32L4_CAN1_BASE+STM32L4_CAN_TDL0R_OFFSET)
|
||||
# define STM32L4_CAN1_TDL1R (STM32L4_CAN1_BASE+STM32L4_CAN_TDL1R_OFFSET)
|
||||
# define STM32L4_CAN1_TDL2R (STM32L4_CAN1_BASE+STM32L4_CAN_TDL2R_OFFSET)
|
||||
# define STM32_CAN1_TDLR(m) (STM32_CAN1_BASE+STM32_CAN_TDLR_OFFSET(m))
|
||||
# define STM32_CAN1_TDL0R (STM32_CAN1_BASE+STM32_CAN_TDL0R_OFFSET)
|
||||
# define STM32_CAN1_TDL1R (STM32_CAN1_BASE+STM32_CAN_TDL1R_OFFSET)
|
||||
# define STM32_CAN1_TDL2R (STM32_CAN1_BASE+STM32_CAN_TDL2R_OFFSET)
|
||||
|
||||
# define STM32L4_CAN1_TDHR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TDHR_OFFSET(m))
|
||||
# define STM32L4_CAN1_TDH0R (STM32L4_CAN1_BASE+STM32L4_CAN_TDH0R_OFFSET)
|
||||
# define STM32L4_CAN1_TDH1R (STM32L4_CAN1_BASE+STM32L4_CAN_TDH1R_OFFSET)
|
||||
# define STM32L4_CAN1_TDH2R (STM32L4_CAN1_BASE+STM32L4_CAN_TDH2R_OFFSET)
|
||||
# define STM32_CAN1_TDHR(m) (STM32_CAN1_BASE+STM32_CAN_TDHR_OFFSET(m))
|
||||
# define STM32_CAN1_TDH0R (STM32_CAN1_BASE+STM32_CAN_TDH0R_OFFSET)
|
||||
# define STM32_CAN1_TDH1R (STM32_CAN1_BASE+STM32_CAN_TDH1R_OFFSET)
|
||||
# define STM32_CAN1_TDH2R (STM32_CAN1_BASE+STM32_CAN_TDH2R_OFFSET)
|
||||
|
||||
# define STM32L4_CAN1_RIR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RIR_OFFSET(m))
|
||||
# define STM32L4_CAN1_RI0R (STM32L4_CAN1_BASE+STM32L4_CAN_RI0R_OFFSET)
|
||||
# define STM32L4_CAN1_RI1R (STM32L4_CAN1_BASE+STM32L4_CAN_RI1R_OFFSET)
|
||||
# define STM32_CAN1_RIR(m) (STM32_CAN1_BASE+STM32_CAN_RIR_OFFSET(m))
|
||||
# define STM32_CAN1_RI0R (STM32_CAN1_BASE+STM32_CAN_RI0R_OFFSET)
|
||||
# define STM32_CAN1_RI1R (STM32_CAN1_BASE+STM32_CAN_RI1R_OFFSET)
|
||||
|
||||
# define STM32L4_CAN1_RDTR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RDTR_OFFSET(m))
|
||||
# define STM32L4_CAN1_RDT0R (STM32L4_CAN1_BASE+STM32L4_CAN_RDT0R_OFFSET)
|
||||
# define STM32L4_CAN1_RDT1R (STM32L4_CAN1_BASE+STM32L4_CAN_RDT1R_OFFSET)
|
||||
# define STM32_CAN1_RDTR(m) (STM32_CAN1_BASE+STM32_CAN_RDTR_OFFSET(m))
|
||||
# define STM32_CAN1_RDT0R (STM32_CAN1_BASE+STM32_CAN_RDT0R_OFFSET)
|
||||
# define STM32_CAN1_RDT1R (STM32_CAN1_BASE+STM32_CAN_RDT1R_OFFSET)
|
||||
|
||||
# define STM32L4_CAN1_RDLR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RDLR_OFFSET(m))
|
||||
# define STM32L4_CAN1_RDL0R (STM32L4_CAN1_BASE+STM32L4_CAN_RDL0R_OFFSET)
|
||||
# define STM32L4_CAN1_RDL1R (STM32L4_CAN1_BASE+STM32L4_CAN_RDL1R_OFFSET)
|
||||
# define STM32_CAN1_RDLR(m) (STM32_CAN1_BASE+STM32_CAN_RDLR_OFFSET(m))
|
||||
# define STM32_CAN1_RDL0R (STM32_CAN1_BASE+STM32_CAN_RDL0R_OFFSET)
|
||||
# define STM32_CAN1_RDL1R (STM32_CAN1_BASE+STM32_CAN_RDL1R_OFFSET)
|
||||
|
||||
# define STM32L4_CAN1_RDHR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RDHR_OFFSET(m))
|
||||
# define STM32L4_CAN1_RDH0R (STM32L4_CAN1_BASE+STM32L4_CAN_RDH0R_OFFSET)
|
||||
# define STM32L4_CAN1_RDH1R (STM32L4_CAN1_BASE+STM32L4_CAN_RDH1R_OFFSET)
|
||||
# define STM32_CAN1_RDHR(m) (STM32_CAN1_BASE+STM32_CAN_RDHR_OFFSET(m))
|
||||
# define STM32_CAN1_RDH0R (STM32_CAN1_BASE+STM32_CAN_RDH0R_OFFSET)
|
||||
# define STM32_CAN1_RDH1R (STM32_CAN1_BASE+STM32_CAN_RDH1R_OFFSET)
|
||||
|
||||
# define STM32L4_CAN1_FMR (STM32L4_CAN1_BASE+STM32L4_CAN_FMR_OFFSET)
|
||||
# define STM32L4_CAN1_FM1R (STM32L4_CAN1_BASE+STM32L4_CAN_FM1R_OFFSET)
|
||||
# define STM32L4_CAN1_FS1R (STM32L4_CAN1_BASE+STM32L4_CAN_FS1R_OFFSET)
|
||||
# define STM32L4_CAN1_FFA1R (STM32L4_CAN1_BASE+STM32L4_CAN_FFA1R_OFFSET)
|
||||
# define STM32L4_CAN1_FA1R (STM32L4_CAN1_BASE+STM32L4_CAN_FA1R_OFFSET)
|
||||
# define STM32L4_CAN1_FIR(b,i) (STM32L4_CAN1_BASE+STM32L4_CAN_FIR_OFFSET(b,i))
|
||||
# define STM32_CAN1_FMR (STM32_CAN1_BASE+STM32_CAN_FMR_OFFSET)
|
||||
# define STM32_CAN1_FM1R (STM32_CAN1_BASE+STM32_CAN_FM1R_OFFSET)
|
||||
# define STM32_CAN1_FS1R (STM32_CAN1_BASE+STM32_CAN_FS1R_OFFSET)
|
||||
# define STM32_CAN1_FFA1R (STM32_CAN1_BASE+STM32_CAN_FFA1R_OFFSET)
|
||||
# define STM32_CAN1_FA1R (STM32_CAN1_BASE+STM32_CAN_FA1R_OFFSET)
|
||||
# define STM32_CAN1_FIR(b,i) (STM32_CAN1_BASE+STM32_CAN_FIR_OFFSET(b,i))
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
@@ -29,15 +29,15 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_COMP_CSR_OFFSET(n) (((n)-1) << 2)
|
||||
#define STM32L4_COMP1_CSR_OFFSET 0x0000 /* Comparator 1 control and status register */
|
||||
#define STM32L4_COMP2_CSR_OFFSET 0x0004 /* Comparator 2 control and status register */
|
||||
#define STM32_COMP_CSR_OFFSET(n) (((n)-1) << 2)
|
||||
#define STM32_COMP1_CSR_OFFSET 0x0000 /* Comparator 1 control and status register */
|
||||
#define STM32_COMP2_CSR_OFFSET 0x0004 /* Comparator 2 control and status register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_COMP_CSR(n) (STM32L4_COMP_BASE+STM32L4_COMP_CSR_OFFSET(n))
|
||||
#define STM32L4_COMP1_CSR (STM32L4_COMP_BASE+STM32L4_COMP1_CSR_OFFSET)
|
||||
#define STM32L4_COMP2_CSR (STM32L4_COMP_BASE+STM32L4_COMP2_CSR_OFFSET)
|
||||
#define STM32_COMP_CSR(n) (STM32_COMP_BASE+STM32_COMP_CSR_OFFSET(n))
|
||||
#define STM32_COMP1_CSR (STM32_COMP_BASE+STM32_COMP1_CSR_OFFSET)
|
||||
#define STM32_COMP2_CSR (STM32_COMP_BASE+STM32_COMP2_CSR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
@@ -109,7 +109,9 @@
|
||||
# define COMP_CSR_INMESEL_PIN4 (2 << COMP_CSR_INMESEL_SHIFT) /* Input minus pin 4: COMP1=PA4; COMP2=PA4 */
|
||||
# define COMP_CSR_INMESEL_PIN5 (3 << COMP_CSR_INMESEL_SHIFT) /* Input minus pin 5: COMP1=PA5; COMP2=PA5 */
|
||||
#endif
|
||||
/* Bits 27-29: Reserved */
|
||||
|
||||
/* Bits 27-29: Reserved */
|
||||
|
||||
#define COMP_CSR_VALUE (1 << 30) /* Bit 30: Comparator output status bit */
|
||||
#define COMP_CSR_LOCK_MASK (1 << 31) /* Bit 31: CSR register lock bit */
|
||||
# define COMP_CSR_LOCK_RW (0)
|
||||
|
||||
@@ -29,17 +29,17 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_CRS_CR_OFFSET 0x0000 /* CRS control register */
|
||||
#define STM32L4_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */
|
||||
#define STM32L4_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */
|
||||
#define STM32L4_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */
|
||||
#define STM32_CRS_CR_OFFSET 0x0000 /* CRS control register */
|
||||
#define STM32_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */
|
||||
#define STM32_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */
|
||||
#define STM32_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_CRS_CR (STM32L4_CRS_BASE + STM32L4_CRS_CR_OFFSET)
|
||||
#define STM32L4_CRS_CFGR (STM32L4_CRS_BASE + STM32L4_CRS_CFGR_OFFSET)
|
||||
#define STM32L4_CRS_ISR (STM32L4_CRS_BASE + STM32L4_CRS_ISR_OFFSET)
|
||||
#define STM32L4_CRS_ICR (STM32L4_CRS_BASE + STM32L4_CRS_ICR_OFFSET)
|
||||
#define STM32_CRS_CR (STM32_CRS_BASE + STM32_CRS_CR_OFFSET)
|
||||
#define STM32_CRS_CFGR (STM32_CRS_BASE + STM32_CRS_CFGR_OFFSET)
|
||||
#define STM32_CRS_ISR (STM32_CRS_BASE + STM32_CRS_ISR_OFFSET)
|
||||
#define STM32_CRS_ICR (STM32_CRS_BASE + STM32_CRS_ICR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -36,51 +36,51 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_DAC_CR_OFFSET 0x0000 /* DAC control register */
|
||||
#define STM32L4_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */
|
||||
#define STM32L4_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */
|
||||
#define STM32L4_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */
|
||||
#define STM32L4_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */
|
||||
#define STM32L4_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */
|
||||
#define STM32L4_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */
|
||||
#define STM32L4_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */
|
||||
#define STM32L4_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */
|
||||
#define STM32L4_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */
|
||||
#define STM32L4_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */
|
||||
#define STM32L4_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */
|
||||
#define STM32L4_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */
|
||||
#define STM32L4_DAC_SR_OFFSET 0x0034 /* DAC status register */
|
||||
#define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */
|
||||
#define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */
|
||||
#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */
|
||||
#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */
|
||||
#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */
|
||||
#define STM32_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */
|
||||
#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */
|
||||
#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */
|
||||
#define STM32_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */
|
||||
#define STM32_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */
|
||||
#define STM32_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */
|
||||
#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */
|
||||
#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */
|
||||
#define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */
|
||||
|
||||
/* New registers not in STM32L1: */
|
||||
#define STM32L4_DAC_CCR_OFFSET 0x0038 /* DAC calibration control register */
|
||||
#define STM32L4_DAC_MCR_OFFSET 0x003c /* DAC mode control register */
|
||||
#define STM32L4_DAC_SHSR1_OFFSET 0x0040 /* DAC Sample and Hold sample time register 1 */
|
||||
#define STM32L4_DAC_SHSR2_OFFSET 0x0044 /* DAC Sample and Hold sample time register 2 */
|
||||
#define STM32L4_DAC_SHHR_OFFSET 0x0048 /* DAC Sample and Hold hold time register */
|
||||
#define STM32L4_DAC_SHRR_OFFSET 0x004c /* DAC Sample and Hold refresh time register */
|
||||
#define STM32_DAC_CCR_OFFSET 0x0038 /* DAC calibration control register */
|
||||
#define STM32_DAC_MCR_OFFSET 0x003c /* DAC mode control register */
|
||||
#define STM32_DAC_SHSR1_OFFSET 0x0040 /* DAC Sample and Hold sample time register 1 */
|
||||
#define STM32_DAC_SHSR2_OFFSET 0x0044 /* DAC Sample and Hold sample time register 2 */
|
||||
#define STM32_DAC_SHHR_OFFSET 0x0048 /* DAC Sample and Hold hold time register */
|
||||
#define STM32_DAC_SHRR_OFFSET 0x004c /* DAC Sample and Hold refresh time register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_DAC_CR (STM32L4_DAC_BASE+STM32L4_DAC_CR_OFFSET)
|
||||
#define STM32L4_DAC_SWTRIGR (STM32L4_DAC_BASE+STM32L4_DAC_SWTRIGR_OFFSET)
|
||||
#define STM32L4_DAC_DHR12R1 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12R1_OFFSET)
|
||||
#define STM32L4_DAC_DHR12L1 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12L1_OFFSET)
|
||||
#define STM32L4_DAC_DHR8R1 (STM32L4_DAC_BASE+STM32L4_DAC_DHR8R1_OFFSET)
|
||||
#define STM32L4_DAC_DHR12R2 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12R2_OFFSET)
|
||||
#define STM32L4_DAC_DHR12L2 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12L2_OFFSET)
|
||||
#define STM32L4_DAC_DHR8R2 (STM32L4_DAC_BASE+STM32L4_DAC_DHR8R2_OFFSET)
|
||||
#define STM32L4_DAC_DHR12RD (STM32L4_DAC_BASE+STM32L4_DAC_DHR12RD_OFFSET)
|
||||
#define STM32L4_DAC_DHR12LD (STM32L4_DAC_BASE+STM32L4_DAC_DHR12LD_OFFSET)
|
||||
#define STM32L4_DAC_DHR8RD (STM32L4_DAC_BASE+STM32L4_DAC_DHR8RD_OFFSET)
|
||||
#define STM32L4_DAC_DOR1 (STM32L4_DAC_BASE+STM32L4_DAC_DOR1_OFFSET)
|
||||
#define STM32L4_DAC_DOR2 (STM32L4_DAC_BASE+STM32L4_DAC_DOR2_OFFSET)
|
||||
#define STM32L4_DAC_SR (STM32L4_DAC_BASE+STM32L4_DAC_SR_OFFSET)
|
||||
#define STM32L4_DAC_CCR (STM32L4_DAC_BASE+STM32L4_DAC_CCR_OFFSET)
|
||||
#define STM32L4_DAC_MCR (STM32L4_DAC_BASE+STM32L4_DAC_MCR_OFFSET)
|
||||
#define STM32L4_DAC_SHSR1 (STM32L4_DAC_BASE+STM32L4_DAC_SHSR1_OFFSET)
|
||||
#define STM32L4_DAC_SHSR2 (STM32L4_DAC_BASE+STM32L4_DAC_SHSR2_OFFSET)
|
||||
#define STM32L4_DAC_SHHR (STM32L4_DAC_BASE+STM32L4_DAC_SHHR_OFFSET)
|
||||
#define STM32L4_DAC_SHRR (STM32L4_DAC_BASE+STM32L4_DAC_SHRR_OFFSET)
|
||||
#define STM32_DAC_CR (STM32_DAC_BASE+STM32_DAC_CR_OFFSET)
|
||||
#define STM32_DAC_SWTRIGR (STM32_DAC_BASE+STM32_DAC_SWTRIGR_OFFSET)
|
||||
#define STM32_DAC_DHR12R1 (STM32_DAC_BASE+STM32_DAC_DHR12R1_OFFSET)
|
||||
#define STM32_DAC_DHR12L1 (STM32_DAC_BASE+STM32_DAC_DHR12L1_OFFSET)
|
||||
#define STM32_DAC_DHR8R1 (STM32_DAC_BASE+STM32_DAC_DHR8R1_OFFSET)
|
||||
#define STM32_DAC_DHR12R2 (STM32_DAC_BASE+STM32_DAC_DHR12R2_OFFSET)
|
||||
#define STM32_DAC_DHR12L2 (STM32_DAC_BASE+STM32_DAC_DHR12L2_OFFSET)
|
||||
#define STM32_DAC_DHR8R2 (STM32_DAC_BASE+STM32_DAC_DHR8R2_OFFSET)
|
||||
#define STM32_DAC_DHR12RD (STM32_DAC_BASE+STM32_DAC_DHR12RD_OFFSET)
|
||||
#define STM32_DAC_DHR12LD (STM32_DAC_BASE+STM32_DAC_DHR12LD_OFFSET)
|
||||
#define STM32_DAC_DHR8RD (STM32_DAC_BASE+STM32_DAC_DHR8RD_OFFSET)
|
||||
#define STM32_DAC_DOR1 (STM32_DAC_BASE+STM32_DAC_DOR1_OFFSET)
|
||||
#define STM32_DAC_DOR2 (STM32_DAC_BASE+STM32_DAC_DOR2_OFFSET)
|
||||
#define STM32_DAC_SR (STM32_DAC_BASE+STM32_DAC_SR_OFFSET)
|
||||
#define STM32_DAC_CCR (STM32_DAC_BASE+STM32_DAC_CCR_OFFSET)
|
||||
#define STM32_DAC_MCR (STM32_DAC_BASE+STM32_DAC_MCR_OFFSET)
|
||||
#define STM32_DAC_SHSR1 (STM32_DAC_BASE+STM32_DAC_SHSR1_OFFSET)
|
||||
#define STM32_DAC_SHSR2 (STM32_DAC_BASE+STM32_DAC_SHSR2_OFFSET)
|
||||
#define STM32_DAC_SHHR (STM32_DAC_BASE+STM32_DAC_SHHR_OFFSET)
|
||||
#define STM32_DAC_SHRR (STM32_DAC_BASE+STM32_DAC_SHRR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -41,134 +41,134 @@
|
||||
|
||||
/* DFSDM channel y registers (y=0..7 or y=0..3 on STM32L4X3) */
|
||||
|
||||
#define STM32L4_DFSDM_CHCFGR1_OFFSET(y) (0x00 + 0x20 * (y))
|
||||
#define STM32_DFSDM_CHCFGR1_OFFSET(y) (0x00 + 0x20 * (y))
|
||||
|
||||
#define STM32L4_DFSDM_CH0CFGR1_OFFSET 0x0000 /* DFSDM channel configuration 0 register */
|
||||
#define STM32L4_DFSDM_CH1CFGR1_OFFSET 0x0020 /* DFSDM channel configuration 1 register */
|
||||
#define STM32L4_DFSDM_CH2CFGR1_OFFSET 0x0040 /* DFSDM channel configuration 2 register */
|
||||
#define STM32L4_DFSDM_CH3CFGR1_OFFSET 0x0060 /* DFSDM channel configuration 3 register */
|
||||
#define STM32_DFSDM_CH0CFGR1_OFFSET 0x0000 /* DFSDM channel configuration 0 register */
|
||||
#define STM32_DFSDM_CH1CFGR1_OFFSET 0x0020 /* DFSDM channel configuration 1 register */
|
||||
#define STM32_DFSDM_CH2CFGR1_OFFSET 0x0040 /* DFSDM channel configuration 2 register */
|
||||
#define STM32_DFSDM_CH3CFGR1_OFFSET 0x0060 /* DFSDM channel configuration 3 register */
|
||||
#ifndef CONFIG_STM32L4_STM32L4X3
|
||||
# define STM32L4_DFSDM_CH4CFGR1_OFFSET 0x0080 /* DFSDM channel configuration 4 register */
|
||||
# define STM32L4_DFSDM_CH5CFGR1_OFFSET 0x00a0 /* DFSDM channel configuration 5 register */
|
||||
# define STM32L4_DFSDM_CH6CFGR1_OFFSET 0x00c0 /* DFSDM channel configuration 6 register */
|
||||
# define STM32L4_DFSDM_CH7CFGR1_OFFSET 0x00e0 /* DFSDM channel configuration 7 register */
|
||||
# define STM32_DFSDM_CH4CFGR1_OFFSET 0x0080 /* DFSDM channel configuration 4 register */
|
||||
# define STM32_DFSDM_CH5CFGR1_OFFSET 0x00a0 /* DFSDM channel configuration 5 register */
|
||||
# define STM32_DFSDM_CH6CFGR1_OFFSET 0x00c0 /* DFSDM channel configuration 6 register */
|
||||
# define STM32_DFSDM_CH7CFGR1_OFFSET 0x00e0 /* DFSDM channel configuration 7 register */
|
||||
#endif
|
||||
|
||||
#define STM32L4_DFSDM_CHCFGR2_OFFSET(y) (0x04 + 0x20 * (y))
|
||||
#define STM32_DFSDM_CHCFGR2_OFFSET(y) (0x04 + 0x20 * (y))
|
||||
|
||||
#define STM32L4_DFSDM_CH0CFGR2_OFFSET 0x0004 /* DFSDM channel configuration 0 register 2 */
|
||||
#define STM32L4_DFSDM_CH1CFGR2_OFFSET 0x0024 /* DFSDM channel configuration 1 register 2 */
|
||||
#define STM32L4_DFSDM_CH2CFGR2_OFFSET 0x0044 /* DFSDM channel configuration 2 register 2 */
|
||||
#define STM32L4_DFSDM_CH3CFGR2_OFFSET 0x0064 /* DFSDM channel configuration 3 register 2 */
|
||||
#define STM32_DFSDM_CH0CFGR2_OFFSET 0x0004 /* DFSDM channel configuration 0 register 2 */
|
||||
#define STM32_DFSDM_CH1CFGR2_OFFSET 0x0024 /* DFSDM channel configuration 1 register 2 */
|
||||
#define STM32_DFSDM_CH2CFGR2_OFFSET 0x0044 /* DFSDM channel configuration 2 register 2 */
|
||||
#define STM32_DFSDM_CH3CFGR2_OFFSET 0x0064 /* DFSDM channel configuration 3 register 2 */
|
||||
#ifndef CONFIG_STM32L4_STM32L4X3
|
||||
# define STM32L4_DFSDM_CH4CFGR2_OFFSET 0x0084 /* DFSDM channel configuration 4 register 2 */
|
||||
# define STM32L4_DFSDM_CH5CFGR2_OFFSET 0x00a4 /* DFSDM channel configuration 5 register 2 */
|
||||
# define STM32L4_DFSDM_CH6CFGR2_OFFSET 0x00c4 /* DFSDM channel configuration 6 register 2 */
|
||||
# define STM32L4_DFSDM_CH7CFGR2_OFFSET 0x00e4 /* DFSDM channel configuration 7 register 2 */
|
||||
# define STM32_DFSDM_CH4CFGR2_OFFSET 0x0084 /* DFSDM channel configuration 4 register 2 */
|
||||
# define STM32_DFSDM_CH5CFGR2_OFFSET 0x00a4 /* DFSDM channel configuration 5 register 2 */
|
||||
# define STM32_DFSDM_CH6CFGR2_OFFSET 0x00c4 /* DFSDM channel configuration 6 register 2 */
|
||||
# define STM32_DFSDM_CH7CFGR2_OFFSET 0x00e4 /* DFSDM channel configuration 7 register 2 */
|
||||
#endif
|
||||
|
||||
#define STM32L4_DFSDM_CHAWSCDR_OFFSET(y) (0x08 + 0x20 * (y))
|
||||
#define STM32_DFSDM_CHAWSCDR_OFFSET(y) (0x08 + 0x20 * (y))
|
||||
|
||||
#define STM32L4_DFSDM_CH0AWSCDR_OFFSET 0x0008 /* DFSDM channel 0 analog watchdog and short-circuit detector register */
|
||||
#define STM32L4_DFSDM_CH1AWSCDR_OFFSET 0x0028 /* DFSDM channel 1 analog watchdog and short-circuit detector register */
|
||||
#define STM32L4_DFSDM_CH2AWSCDR_OFFSET 0x0048 /* DFSDM channel 2 analog watchdog and short-circuit detector register */
|
||||
#define STM32L4_DFSDM_CH3AWSCDR_OFFSET 0x0068 /* DFSDM channel 3 analog watchdog and short-circuit detector register */
|
||||
#define STM32_DFSDM_CH0AWSCDR_OFFSET 0x0008 /* DFSDM channel 0 analog watchdog and short-circuit detector register */
|
||||
#define STM32_DFSDM_CH1AWSCDR_OFFSET 0x0028 /* DFSDM channel 1 analog watchdog and short-circuit detector register */
|
||||
#define STM32_DFSDM_CH2AWSCDR_OFFSET 0x0048 /* DFSDM channel 2 analog watchdog and short-circuit detector register */
|
||||
#define STM32_DFSDM_CH3AWSCDR_OFFSET 0x0068 /* DFSDM channel 3 analog watchdog and short-circuit detector register */
|
||||
#ifndef CONFIG_STM32L4_STM32L4X3
|
||||
# define STM32L4_DFSDM_CH4AWSCDR_OFFSET 0x0088 /* DFSDM channel 4 analog watchdog and short-circuit detector register */
|
||||
# define STM32L4_DFSDM_CH5AWSCDR_OFFSET 0x00a8 /* DFSDM channel 5 analog watchdog and short-circuit detector register */
|
||||
# define STM32L4_DFSDM_CH6AWSCDR_OFFSET 0x00c8 /* DFSDM channel 6 analog watchdog and short-circuit detector register */
|
||||
# define STM32L4_DFSDM_CH7AWSCDR_OFFSET 0x00e8 /* DFSDM channel 7 analog watchdog and short-circuit detector register */
|
||||
# define STM32_DFSDM_CH4AWSCDR_OFFSET 0x0088 /* DFSDM channel 4 analog watchdog and short-circuit detector register */
|
||||
# define STM32_DFSDM_CH5AWSCDR_OFFSET 0x00a8 /* DFSDM channel 5 analog watchdog and short-circuit detector register */
|
||||
# define STM32_DFSDM_CH6AWSCDR_OFFSET 0x00c8 /* DFSDM channel 6 analog watchdog and short-circuit detector register */
|
||||
# define STM32_DFSDM_CH7AWSCDR_OFFSET 0x00e8 /* DFSDM channel 7 analog watchdog and short-circuit detector register */
|
||||
#endif
|
||||
|
||||
#define STM32L4_DFSDM_CHWDATR_OFFSET(y) (0x0c + 0x20 * (y))
|
||||
#define STM32_DFSDM_CHWDATR_OFFSET(y) (0x0c + 0x20 * (y))
|
||||
|
||||
#define STM32L4_DFSDM_CH0WDATR_OFFSET 0x000c /* DFSDM channel 0 watchdog filter data register */
|
||||
#define STM32L4_DFSDM_CH1WDATR_OFFSET 0x002c /* DFSDM channel 1 watchdog filter data register */
|
||||
#define STM32L4_DFSDM_CH2WDATR_OFFSET 0x004c /* DFSDM channel 2 watchdog filter data register */
|
||||
#define STM32L4_DFSDM_CH3WDATR_OFFSET 0x006c /* DFSDM channel 3 watchdog filter data register */
|
||||
#define STM32_DFSDM_CH0WDATR_OFFSET 0x000c /* DFSDM channel 0 watchdog filter data register */
|
||||
#define STM32_DFSDM_CH1WDATR_OFFSET 0x002c /* DFSDM channel 1 watchdog filter data register */
|
||||
#define STM32_DFSDM_CH2WDATR_OFFSET 0x004c /* DFSDM channel 2 watchdog filter data register */
|
||||
#define STM32_DFSDM_CH3WDATR_OFFSET 0x006c /* DFSDM channel 3 watchdog filter data register */
|
||||
#ifndef CONFIG_STM32L4_STM32L4X3
|
||||
# define STM32L4_DFSDM_CH4WDATR_OFFSET 0x008c /* DFSDM channel 4 watchdog filter data register */
|
||||
# define STM32L4_DFSDM_CH5WDATR_OFFSET 0x00ac /* DFSDM channel 5 watchdog filter data register */
|
||||
# define STM32L4_DFSDM_CH6WDATR_OFFSET 0x00cc /* DFSDM channel 6 watchdog filter data register */
|
||||
# define STM32L4_DFSDM_CH7WDATR_OFFSET 0x00ec /* DFSDM channel 7 watchdog filter data register */
|
||||
# define STM32_DFSDM_CH4WDATR_OFFSET 0x008c /* DFSDM channel 4 watchdog filter data register */
|
||||
# define STM32_DFSDM_CH5WDATR_OFFSET 0x00ac /* DFSDM channel 5 watchdog filter data register */
|
||||
# define STM32_DFSDM_CH6WDATR_OFFSET 0x00cc /* DFSDM channel 6 watchdog filter data register */
|
||||
# define STM32_DFSDM_CH7WDATR_OFFSET 0x00ec /* DFSDM channel 7 watchdog filter data register */
|
||||
#endif
|
||||
|
||||
#define STM32L4_DFSDM_CHDATINR_OFFSET(ch) (0x10 + 0x20 * (ch)) /* DFSDM channel data input register */
|
||||
#define STM32_DFSDM_CHDATINR_OFFSET(ch) (0x10 + 0x20 * (ch)) /* DFSDM channel data input register */
|
||||
|
||||
#define STM32L4_DFSDM_CH0DATINR_OFFSET 0x0010 /* DFSDM channel 0 data input register */
|
||||
#define STM32L4_DFSDM_CH1DATINR_OFFSET 0x0030 /* DFSDM channel 1 data input register */
|
||||
#define STM32L4_DFSDM_CH2DATINR_OFFSET 0x0050 /* DFSDM channel 2 data input register */
|
||||
#define STM32L4_DFSDM_CH3DATINR_OFFSET 0x0070 /* DFSDM channel 3 data input register */
|
||||
#define STM32_DFSDM_CH0DATINR_OFFSET 0x0010 /* DFSDM channel 0 data input register */
|
||||
#define STM32_DFSDM_CH1DATINR_OFFSET 0x0030 /* DFSDM channel 1 data input register */
|
||||
#define STM32_DFSDM_CH2DATINR_OFFSET 0x0050 /* DFSDM channel 2 data input register */
|
||||
#define STM32_DFSDM_CH3DATINR_OFFSET 0x0070 /* DFSDM channel 3 data input register */
|
||||
#ifndef CONFIG_STM32L4_STM32L4X3
|
||||
# define STM32L4_DFSDM_CH4DATINR_OFFSET 0x0090 /* DFSDM channel 4 data input register */
|
||||
# define STM32L4_DFSDM_CH5DATINR_OFFSET 0x00b0 /* DFSDM channel 5 data input register */
|
||||
# define STM32L4_DFSDM_CH6DATINR_OFFSET 0x00d0 /* DFSDM channel 6 data input register */
|
||||
# define STM32L4_DFSDM_CH7DATINR_OFFSET 0x00f0 /* DFSDM channel 7 data input register */
|
||||
# define STM32_DFSDM_CH4DATINR_OFFSET 0x0090 /* DFSDM channel 4 data input register */
|
||||
# define STM32_DFSDM_CH5DATINR_OFFSET 0x00b0 /* DFSDM channel 5 data input register */
|
||||
# define STM32_DFSDM_CH6DATINR_OFFSET 0x00d0 /* DFSDM channel 6 data input register */
|
||||
# define STM32_DFSDM_CH7DATINR_OFFSET 0x00f0 /* DFSDM channel 7 data input register */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_STM32L4XR
|
||||
# define STM32L4_DFSDM_CHDLYR_OFFSET(ch) (0x14 + 0x20 * (ch)) /* DFSDM channel delay register */
|
||||
# define STM32_DFSDM_CHDLYR_OFFSET(ch) (0x14 + 0x20 * (ch)) /* DFSDM channel delay register */
|
||||
|
||||
# define STM32L4_DFSDM_CH0DLYR_OFFSET 0x0014 /* DFSDM channel 0 delay register */
|
||||
# define STM32L4_DFSDM_CH1DLYR_OFFSET 0x0034 /* DFSDM channel 1 delay register */
|
||||
# define STM32L4_DFSDM_CH2DLYR_OFFSET 0x0054 /* DFSDM channel 2 delay register */
|
||||
# define STM32L4_DFSDM_CH3DLYR_OFFSET 0x0074 /* DFSDM channel 3 delay register */
|
||||
# define STM32L4_DFSDM_CH4DLYR_OFFSET 0x0094 /* DFSDM channel 4 delay register */
|
||||
# define STM32L4_DFSDM_CH5DLYR_OFFSET 0x00b4 /* DFSDM channel 5 delay register */
|
||||
# define STM32L4_DFSDM_CH6DLYR_OFFSET 0x00d4 /* DFSDM channel 6 delay register */
|
||||
# define STM32L4_DFSDM_CH7DLYR_OFFSET 0x00f4 /* DFSDM channel 7 delay register */
|
||||
# define STM32_DFSDM_CH0DLYR_OFFSET 0x0014 /* DFSDM channel 0 delay register */
|
||||
# define STM32_DFSDM_CH1DLYR_OFFSET 0x0034 /* DFSDM channel 1 delay register */
|
||||
# define STM32_DFSDM_CH2DLYR_OFFSET 0x0054 /* DFSDM channel 2 delay register */
|
||||
# define STM32_DFSDM_CH3DLYR_OFFSET 0x0074 /* DFSDM channel 3 delay register */
|
||||
# define STM32_DFSDM_CH4DLYR_OFFSET 0x0094 /* DFSDM channel 4 delay register */
|
||||
# define STM32_DFSDM_CH5DLYR_OFFSET 0x00b4 /* DFSDM channel 5 delay register */
|
||||
# define STM32_DFSDM_CH6DLYR_OFFSET 0x00d4 /* DFSDM channel 6 delay register */
|
||||
# define STM32_DFSDM_CH7DLYR_OFFSET 0x00f4 /* DFSDM channel 7 delay register */
|
||||
#endif
|
||||
|
||||
/* DFSDM filter x module registers (x=0..3 or x=0..1 on STM32L4X3) */
|
||||
|
||||
#define STM32L4_DFSDM_FLTCR1_OFFSET(x) (0x100 + 0x80 * (x)) /* DFSDM control register 1 */
|
||||
#define STM32L4_DFSDM_FLTCR2_OFFSET(x) (0x104 + 0x80 * (x)) /* DFSDM control register 2 */
|
||||
#define STM32L4_DFSDM_FLTISR_OFFSET(x) (0x108 + 0x80 * (x)) /* DFSDM interrupt and status register */
|
||||
#define STM32L4_DFSDM_FLTICR_OFFSET(x) (0x10c + 0x80 * (x)) /* DFSDM interrupt flag clear register */
|
||||
#define STM32L4_DFSDM_FLTJCHGR_OFFSET(x) (0x110 + 0x80 * (x)) /* DFSDM injected channel group selection register */
|
||||
#define STM32L4_DFSDM_FLTFCR_OFFSET(x) (0x114 + 0x80 * (x)) /* DFSDM filter control register */
|
||||
#define STM32L4_DFSDM_FLTJDATAR_OFFSET(x) (0x118 + 0x80 * (x)) /* DFSDM data register for injected group */
|
||||
#define STM32L4_DFSDM_FLTRDATAR_OFFSET(x) (0x11c + 0x80 * (x)) /* DFSDM data register for the regular channel */
|
||||
#define STM32L4_DFSDM_FLTAWHTR_OFFSET(x) (0x120 + 0x80 * (x)) /* DFSDM analog watchdog high threshold register */
|
||||
#define STM32L4_DFSDM_FLTAWLTR_OFFSET(x) (0x124 + 0x80 * (x)) /* DFSDM analog watchdog low threshold register */
|
||||
#define STM32L4_DFSDM_FLTAWSR_OFFSET(x) (0x128 + 0x80 * (x)) /* DFSDM analog watchdog status register */
|
||||
#define STM32L4_DFSDM_FLTAWCFR_OFFSET(x) (0x12c + 0x80 * (x)) /* DFSDM analog watchdog clear flag register */
|
||||
#define STM32L4_DFSDM_FLTEXMAX_OFFSET(x) (0x130 + 0x80 * (x)) /* DFSDM Extremes detector maximum register */
|
||||
#define STM32L4_DFSDM_FLTEXMIN_OFFSET(x) (0x134 + 0x80 * (x)) /* DFSDM Extremes detector minimum register */
|
||||
#define STM32L4_DFSDM_FLTCNVTIMR_OFFSET(x) (0x138 + 0x80 * (x)) /* DFSDM conversion timer register */
|
||||
#define STM32_DFSDM_FLTCR1_OFFSET(x) (0x100 + 0x80 * (x)) /* DFSDM control register 1 */
|
||||
#define STM32_DFSDM_FLTCR2_OFFSET(x) (0x104 + 0x80 * (x)) /* DFSDM control register 2 */
|
||||
#define STM32_DFSDM_FLTISR_OFFSET(x) (0x108 + 0x80 * (x)) /* DFSDM interrupt and status register */
|
||||
#define STM32_DFSDM_FLTICR_OFFSET(x) (0x10c + 0x80 * (x)) /* DFSDM interrupt flag clear register */
|
||||
#define STM32_DFSDM_FLTJCHGR_OFFSET(x) (0x110 + 0x80 * (x)) /* DFSDM injected channel group selection register */
|
||||
#define STM32_DFSDM_FLTFCR_OFFSET(x) (0x114 + 0x80 * (x)) /* DFSDM filter control register */
|
||||
#define STM32_DFSDM_FLTJDATAR_OFFSET(x) (0x118 + 0x80 * (x)) /* DFSDM data register for injected group */
|
||||
#define STM32_DFSDM_FLTRDATAR_OFFSET(x) (0x11c + 0x80 * (x)) /* DFSDM data register for the regular channel */
|
||||
#define STM32_DFSDM_FLTAWHTR_OFFSET(x) (0x120 + 0x80 * (x)) /* DFSDM analog watchdog high threshold register */
|
||||
#define STM32_DFSDM_FLTAWLTR_OFFSET(x) (0x124 + 0x80 * (x)) /* DFSDM analog watchdog low threshold register */
|
||||
#define STM32_DFSDM_FLTAWSR_OFFSET(x) (0x128 + 0x80 * (x)) /* DFSDM analog watchdog status register */
|
||||
#define STM32_DFSDM_FLTAWCFR_OFFSET(x) (0x12c + 0x80 * (x)) /* DFSDM analog watchdog clear flag register */
|
||||
#define STM32_DFSDM_FLTEXMAX_OFFSET(x) (0x130 + 0x80 * (x)) /* DFSDM Extremes detector maximum register */
|
||||
#define STM32_DFSDM_FLTEXMIN_OFFSET(x) (0x134 + 0x80 * (x)) /* DFSDM Extremes detector minimum register */
|
||||
#define STM32_DFSDM_FLTCNVTIMR_OFFSET(x) (0x138 + 0x80 * (x)) /* DFSDM conversion timer register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
/* DFSDM channel y registers (y=0..7 or y=0..3 on STM32L4X3) */
|
||||
|
||||
#define STM32L4_DFSDM_CHCFGR1(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHCFGR1_OFFSET(y))
|
||||
#define STM32L4_DFSDM_CH0CFGR1 (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CH0CFGR1_OFFSET)
|
||||
#define STM32_DFSDM_CHCFGR1(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHCFGR1_OFFSET(y))
|
||||
#define STM32_DFSDM_CH0CFGR1 (STM32_DFSDM_BASE + STM32_DFSDM_CH0CFGR1_OFFSET)
|
||||
|
||||
#define STM32L4_DFSDM_CHCFGR2(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHCFGR2_OFFSET(y))
|
||||
#define STM32L4_DFSDM_CHAWSCDR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHAWSCDR_OFFSET(y))
|
||||
#define STM32L4_DFSDM_CHWDATR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHWDATR_OFFSET(y)
|
||||
#define STM32L4_DFSDM_CHDATINR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHDATINR_OFFSET(y))
|
||||
#define STM32_DFSDM_CHCFGR2(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHCFGR2_OFFSET(y))
|
||||
#define STM32_DFSDM_CHAWSCDR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHAWSCDR_OFFSET(y))
|
||||
#define STM32_DFSDM_CHWDATR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHWDATR_OFFSET(y)
|
||||
#define STM32_DFSDM_CHDATINR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHDATINR_OFFSET(y))
|
||||
#ifdef CONFIG_STM32L4_STM32L4XR
|
||||
# define STM32L4_DFSDM_CHDLYR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHDLYR_OFFSET(y))
|
||||
# define STM32_DFSDM_CHDLYR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHDLYR_OFFSET(y))
|
||||
#endif
|
||||
|
||||
/* DFSDM filter x module registers (x=0..3 or x=0..1 on STM32L4X3) */
|
||||
|
||||
#define STM32L4_DFSDM_FLTCR1(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCR1_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTCR2(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCR2_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTISR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTISR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTICR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTICR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTJCHGR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTJCHGR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTFCR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTFCR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTJDATAR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTJDATAR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTRDATAR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTRDATAR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTAWHTR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWHTR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTAWLTR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWLTR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTAWSR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWSR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTAWCFR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWCFR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTEXMAX(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTEXMAX_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTEXMIN(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTEXMIN_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTCNVTIMR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCNVTIMR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTCR1(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTCR1_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTCR2(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTCR2_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTISR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTISR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTICR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTICR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTJCHGR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTJCHGR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTFCR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTFCR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTJDATAR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTJDATAR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTRDATAR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTRDATAR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTAWHTR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWHTR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTAWLTR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWLTR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTAWSR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWSR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTAWCFR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWCFR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTEXMAX(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTEXMAX_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTEXMIN(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTEXMIN_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTCNVTIMR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTCNVTIMR_OFFSET(x))
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -34,44 +34,44 @@
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define STM32L4_NEXTI1 31
|
||||
#define STM32L4_EXTI1_MASK 0xffffffff
|
||||
#define STM32L4_NEXTI2 9
|
||||
#define STM32L4_EXTI2_MASK 0x000001ff
|
||||
#define STM32_NEXTI1 31
|
||||
#define STM32_EXTI1_MASK 0xffffffff
|
||||
#define STM32_NEXTI2 9
|
||||
#define STM32_EXTI2_MASK 0x000001ff
|
||||
|
||||
#define STM32L4_EXTI1_BIT(n) (1 << (n))
|
||||
#define STM32L4_EXTI2_BIT(n) (1 << (n))
|
||||
#define STM32_EXTI1_BIT(n) (1 << (n))
|
||||
#define STM32_EXTI2_BIT(n) (1 << (n))
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_EXTI1_OFFSET 0x0000 /* Offset to EXTI1 registers */
|
||||
#define STM32L4_EXTI2_OFFSET 0x0020 /* Offset to EXTI2 registers */
|
||||
#define STM32_EXTI1_OFFSET 0x0000 /* Offset to EXTI1 registers */
|
||||
#define STM32_EXTI2_OFFSET 0x0020 /* Offset to EXTI2 registers */
|
||||
|
||||
#define STM32L4_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */
|
||||
#define STM32L4_EXTI_EMR_OFFSET 0x0004 /* Event mask register */
|
||||
#define STM32L4_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */
|
||||
#define STM32L4_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */
|
||||
#define STM32L4_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */
|
||||
#define STM32L4_EXTI_PR_OFFSET 0x0014 /* Pending register */
|
||||
#define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */
|
||||
#define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */
|
||||
#define STM32_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */
|
||||
#define STM32_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */
|
||||
#define STM32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */
|
||||
#define STM32_EXTI_PR_OFFSET 0x0014 /* Pending register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_EXTI1_BASE (STM32L4_EXTI_BASE+STM32L4_EXTI1_OFFSET)
|
||||
#define STM32L4_EXTI2_BASE (STM32L4_EXTI_BASE+STM32L4_EXTI2_OFFSET)
|
||||
#define STM32_EXTI1_BASE (STM32_EXTI_BASE+STM32_EXTI1_OFFSET)
|
||||
#define STM32_EXTI2_BASE (STM32_EXTI_BASE+STM32_EXTI2_OFFSET)
|
||||
|
||||
#define STM32L4_EXTI1_IMR (STM32L4_EXTI1_BASE+STM32L4_EXTI_IMR_OFFSET)
|
||||
#define STM32L4_EXTI1_EMR (STM32L4_EXTI1_BASE+STM32L4_EXTI_EMR_OFFSET)
|
||||
#define STM32L4_EXTI1_RTSR (STM32L4_EXTI1_BASE+STM32L4_EXTI_RTSR_OFFSET)
|
||||
#define STM32L4_EXTI1_FTSR (STM32L4_EXTI1_BASE+STM32L4_EXTI_FTSR_OFFSET)
|
||||
#define STM32L4_EXTI1_SWIER (STM32L4_EXTI1_BASE+STM32L4_EXTI_SWIER_OFFSET)
|
||||
#define STM32L4_EXTI1_PR (STM32L4_EXTI1_BASE+STM32L4_EXTI_PR_OFFSET)
|
||||
#define STM32_EXTI1_IMR (STM32_EXTI1_BASE+STM32_EXTI_IMR_OFFSET)
|
||||
#define STM32_EXTI1_EMR (STM32_EXTI1_BASE+STM32_EXTI_EMR_OFFSET)
|
||||
#define STM32_EXTI1_RTSR (STM32_EXTI1_BASE+STM32_EXTI_RTSR_OFFSET)
|
||||
#define STM32_EXTI1_FTSR (STM32_EXTI1_BASE+STM32_EXTI_FTSR_OFFSET)
|
||||
#define STM32_EXTI1_SWIER (STM32_EXTI1_BASE+STM32_EXTI_SWIER_OFFSET)
|
||||
#define STM32_EXTI1_PR (STM32_EXTI1_BASE+STM32_EXTI_PR_OFFSET)
|
||||
|
||||
#define STM32L4_EXTI2_IMR (STM32L4_EXTI2_BASE+STM32L4_EXTI_IMR_OFFSET)
|
||||
#define STM32L4_EXTI2_EMR (STM32L4_EXTI2_BASE+STM32L4_EXTI_EMR_OFFSET)
|
||||
#define STM32L4_EXTI2_RTSR (STM32L4_EXTI2_BASE+STM32L4_EXTI_RTSR_OFFSET)
|
||||
#define STM32L4_EXTI2_FTSR (STM32L4_EXTI2_BASE+STM32L4_EXTI_FTSR_OFFSET)
|
||||
#define STM32L4_EXTI2_SWIER (STM32L4_EXTI2_BASE+STM32L4_EXTI_SWIER_OFFSET)
|
||||
#define STM32L4_EXTI2_PR (STM32L4_EXTI2_BASE+STM32L4_EXTI_PR_OFFSET)
|
||||
#define STM32_EXTI2_IMR (STM32_EXTI2_BASE+STM32_EXTI_IMR_OFFSET)
|
||||
#define STM32_EXTI2_EMR (STM32_EXTI2_BASE+STM32_EXTI_EMR_OFFSET)
|
||||
#define STM32_EXTI2_RTSR (STM32_EXTI2_BASE+STM32_EXTI_RTSR_OFFSET)
|
||||
#define STM32_EXTI2_FTSR (STM32_EXTI2_BASE+STM32_EXTI_FTSR_OFFSET)
|
||||
#define STM32_EXTI2_SWIER (STM32_EXTI2_BASE+STM32_EXTI_SWIER_OFFSET)
|
||||
#define STM32_EXTI2_PR (STM32_EXTI2_BASE+STM32_EXTI_PR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
@@ -105,62 +105,62 @@
|
||||
|
||||
/* Interrupt mask register */
|
||||
|
||||
#define EXTI_IMR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Interrupt request from line x is not masked */
|
||||
#define EXTI_IMR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Interrupt request from line x is not masked */
|
||||
#define EXTI_IMR1_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
|
||||
#define EXTI_IMR1_MASK STM32L4_EXTI1_MASK
|
||||
#define EXTI_IMR1_MASK STM32_EXTI1_MASK
|
||||
|
||||
#define EXTI_IMR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Interrupt request from line x is not masked */
|
||||
#define EXTI_IMR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Interrupt request from line x is not masked */
|
||||
#define EXTI_IMR2_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
|
||||
#define EXTI_IMR2_MASK STM32L4_EXTI2_MASK
|
||||
#define EXTI_IMR2_MASK STM32_EXTI2_MASK
|
||||
|
||||
/* Event mask register */
|
||||
|
||||
#define EXTI_EMR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Event request from line x is not mask */
|
||||
#define EXTI_EMR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Event request from line x is not mask */
|
||||
#define EXTI_EMR1_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
|
||||
#define EXTI_EMR1_MASK STM32L4_EXTI1_MASK
|
||||
#define EXTI_EMR1_MASK STM32_EXTI1_MASK
|
||||
|
||||
#define EXTI_EMR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Event request from line x is not mask */
|
||||
#define EXTI_EMR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Event request from line x is not mask */
|
||||
#define EXTI_EMR2_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
|
||||
#define EXTI_EMR2_MASK STM32L4_EXTI2_MASK
|
||||
#define EXTI_EMR2_MASK STM32_EXTI2_MASK
|
||||
|
||||
/* Rising Trigger selection register */
|
||||
|
||||
#define EXTI_RTSR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_RTSR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_RTSR1_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */
|
||||
#define EXTI_RTSR1_MASK STM32L4_EXTI1_MASK
|
||||
#define EXTI_RTSR1_MASK STM32_EXTI1_MASK
|
||||
|
||||
#define EXTI_RTSR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_RTSR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_RTSR2_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */
|
||||
#define EXTI_RTSR2_MASK STM32L4_EXTI2_MASK
|
||||
#define EXTI_RTSR2_MASK STM32_EXTI2_MASK
|
||||
|
||||
/* Falling Trigger selection register */
|
||||
|
||||
#define EXTI_FTSR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_FTSR1_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
|
||||
#define EXTI_FTSR1_MASK STM32L4_EXTI1_MASK
|
||||
#define EXTI_FTSR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_FTSR1_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
|
||||
#define EXTI_FTSR1_MASK STM32_EXTI1_MASK
|
||||
|
||||
#define EXTI_FTSR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_FTSR2_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
|
||||
#define EXTI_FTSR2_MASK STM32L4_EXTI2_MASK
|
||||
#define EXTI_FTSR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_FTSR2_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
|
||||
#define EXTI_FTSR2_MASK STM32_EXTI2_MASK
|
||||
|
||||
/* Software interrupt event register */
|
||||
|
||||
#define EXTI_SWIER1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */
|
||||
#define EXTI_SWIER1_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
|
||||
#define EXTI_SWIER1_MASK STM32L4_EXTI1_MASK
|
||||
#define EXTI_SWIER1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */
|
||||
#define EXTI_SWIER1_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
|
||||
#define EXTI_SWIER1_MASK STM32_EXTI1_MASK
|
||||
|
||||
#define EXTI_SWIER2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */
|
||||
#define EXTI_SWIER2_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
|
||||
#define EXTI_SWIER2_MASK STM32L4_EXTI2_MASK
|
||||
#define EXTI_SWIER2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */
|
||||
#define EXTI_SWIER2_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
|
||||
#define EXTI_SWIER2_MASK STM32_EXTI2_MASK
|
||||
|
||||
/* Pending register */
|
||||
|
||||
#define EXTI_PR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Selected trigger request occurred */
|
||||
#define EXTI_PR1_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
|
||||
#define EXTI_PR1_MASK STM32L4_EXTI1_MASK
|
||||
#define EXTI_PR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Selected trigger request occurred */
|
||||
#define EXTI_PR1_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
|
||||
#define EXTI_PR1_MASK STM32_EXTI1_MASK
|
||||
|
||||
#define EXTI_PR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Selected trigger request occurred */
|
||||
#define EXTI_PR2_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
|
||||
#define EXTI_PR2_MASK STM32L4_EXTI2_MASK
|
||||
#define EXTI_PR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Selected trigger request occurred */
|
||||
#define EXTI_PR2_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
|
||||
#define EXTI_PR2_MASK STM32_EXTI2_MASK
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_EXTI_H */
|
||||
|
||||
@@ -113,79 +113,79 @@
|
||||
/* Define the valid configuration */
|
||||
|
||||
#if defined(CONFIG_STM32L4_FLASH_CONFIG_8) /* 64 kB */
|
||||
# define STM32L4_FLASH_NPAGES 32
|
||||
# define STM32L4_FLASH_PAGESIZE 2048
|
||||
# define STM32_FLASH_NPAGES 32
|
||||
# define STM32_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_B) /* 128 kB */
|
||||
# define STM32L4_FLASH_NPAGES 64
|
||||
# define STM32L4_FLASH_PAGESIZE 2048
|
||||
# define STM32_FLASH_NPAGES 64
|
||||
# define STM32_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_C) /* 256 kB */
|
||||
# define STM32L4_FLASH_NPAGES 128
|
||||
# define STM32L4_FLASH_PAGESIZE 2048
|
||||
# define STM32_FLASH_NPAGES 128
|
||||
# define STM32_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_E) /* 512 kB */
|
||||
# define STM32L4_FLASH_NPAGES 256
|
||||
# define STM32L4_FLASH_PAGESIZE 2048
|
||||
# define STM32_FLASH_NPAGES 256
|
||||
# define STM32_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_G) /* 1 MB */
|
||||
# define STM32L4_FLASH_NPAGES 512
|
||||
# define STM32L4_FLASH_PAGESIZE 2048
|
||||
# define STM32_FLASH_NPAGES 512
|
||||
# define STM32_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_I) /* 2 MB, STM32L4+ only */
|
||||
# define STM32L4_FLASH_NPAGES 512
|
||||
# define STM32L4_FLASH_PAGESIZE 4096
|
||||
# define STM32_FLASH_NPAGES 512
|
||||
# define STM32_FLASH_PAGESIZE 4096
|
||||
#else
|
||||
# error "unknown flash configuration!"
|
||||
#endif
|
||||
|
||||
#ifdef STM32L4_FLASH_PAGESIZE
|
||||
# define STM32L4_FLASH_SIZE (STM32L4_FLASH_NPAGES * STM32L4_FLASH_PAGESIZE)
|
||||
#ifdef STM32_FLASH_PAGESIZE
|
||||
# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE)
|
||||
#endif
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_FLASH_ACR_OFFSET 0x0000
|
||||
#define STM32L4_FLASH_PDKEYR_OFFSET 0x0004
|
||||
#define STM32L4_FLASH_KEYR_OFFSET 0x0008
|
||||
#define STM32L4_FLASH_OPTKEYR_OFFSET 0x000c
|
||||
#define STM32L4_FLASH_SR_OFFSET 0x0010
|
||||
#define STM32L4_FLASH_CR_OFFSET 0x0014
|
||||
#define STM32L4_FLASH_ECCR_OFFSET 0x0018
|
||||
#define STM32L4_FLASH_OPTR_OFFSET 0x0020
|
||||
#define STM32L4_FLASH_PCROP1SR_OFFSET 0x0024
|
||||
#define STM32L4_FLASH_PCROP1ER_OFFSET 0x0028
|
||||
#define STM32L4_FLASH_WRP1AR_OFFSET 0x002c
|
||||
#define STM32L4_FLASH_WRP1BR_OFFSET 0x0030
|
||||
#define STM32_FLASH_ACR_OFFSET 0x0000
|
||||
#define STM32_FLASH_PDKEYR_OFFSET 0x0004
|
||||
#define STM32_FLASH_KEYR_OFFSET 0x0008
|
||||
#define STM32_FLASH_OPTKEYR_OFFSET 0x000c
|
||||
#define STM32_FLASH_SR_OFFSET 0x0010
|
||||
#define STM32_FLASH_CR_OFFSET 0x0014
|
||||
#define STM32_FLASH_ECCR_OFFSET 0x0018
|
||||
#define STM32_FLASH_OPTR_OFFSET 0x0020
|
||||
#define STM32_FLASH_PCROP1SR_OFFSET 0x0024
|
||||
#define STM32_FLASH_PCROP1ER_OFFSET 0x0028
|
||||
#define STM32_FLASH_WRP1AR_OFFSET 0x002c
|
||||
#define STM32_FLASH_WRP1BR_OFFSET 0x0030
|
||||
#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \
|
||||
defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_FLASH_PCROP2SR_OFFSET 0x0044
|
||||
# define STM32L4_FLASH_PCROP2ER_OFFSET 0x0048
|
||||
# define STM32L4_FLASH_WRP2AR_OFFSET 0x004c
|
||||
# define STM32L4_FLASH_WRP2BR_OFFSET 0x0050
|
||||
# define STM32_FLASH_PCROP2SR_OFFSET 0x0044
|
||||
# define STM32_FLASH_PCROP2ER_OFFSET 0x0048
|
||||
# define STM32_FLASH_WRP2AR_OFFSET 0x004c
|
||||
# define STM32_FLASH_WRP2BR_OFFSET 0x0050
|
||||
#endif
|
||||
#if defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_FLASH_CFGR_OFFSET 0x0130
|
||||
# define STM32_FLASH_CFGR_OFFSET 0x0130
|
||||
#endif
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_FLASH_ACR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_ACR_OFFSET)
|
||||
#define STM32L4_FLASH_PDKEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PDKEYR_OFFSET)
|
||||
#define STM32L4_FLASH_KEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_KEYR_OFFSET)
|
||||
#define STM32L4_FLASH_OPTKEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_OPTKEYR_OFFSET)
|
||||
#define STM32L4_FLASH_SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_SR_OFFSET)
|
||||
#define STM32L4_FLASH_CR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_CR_OFFSET)
|
||||
#define STM32L4_FLASH_ECCR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_ECCR_OFFSET)
|
||||
#define STM32L4_FLASH_OPTR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_OPTR_OFFSET)
|
||||
#define STM32L4_FLASH_PCROP1SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP1SR_OFFSET)
|
||||
#define STM32L4_FLASH_PCROP1ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP1ER_OFFSET)
|
||||
#define STM32L4_FLASH_WRP1AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1AR_OFFSET)
|
||||
#define STM32L4_FLASH_WRP1BR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1BR_OFFSET)
|
||||
#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
|
||||
#define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PDKEYR_OFFSET)
|
||||
#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
|
||||
#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
|
||||
#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
|
||||
#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
|
||||
#define STM32_FLASH_ECCR (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET)
|
||||
#define STM32_FLASH_OPTR (STM32_FLASHIF_BASE+STM32_FLASH_OPTR_OFFSET)
|
||||
#define STM32_FLASH_PCROP1SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1SR_OFFSET)
|
||||
#define STM32_FLASH_PCROP1ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1ER_OFFSET)
|
||||
#define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1AR_OFFSET)
|
||||
#define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1BR_OFFSET)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \
|
||||
defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_FLASH_PCROP2SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2SR_OFFSET)
|
||||
# define STM32L4_FLASH_PCROP2ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2ER_OFFSET)
|
||||
# define STM32L4_FLASH_WRP2AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP2AR_OFFSET)
|
||||
# define STM32L4_FLASH_WRP2BR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP2BR_OFFSET)
|
||||
# define STM32_FLASH_PCROP2SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2SR_OFFSET)
|
||||
# define STM32_FLASH_PCROP2ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2ER_OFFSET)
|
||||
# define STM32_FLASH_WRP2AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2AR_OFFSET)
|
||||
# define STM32_FLASH_WRP2BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2BR_OFFSET)
|
||||
#endif
|
||||
#if defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_FLASH_CFGR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_CFGR_OFFSET)
|
||||
# define STM32_FLASH_CFGR (STM32_FLASHIF_BASE+STM32_FLASH_CFGR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
@@ -36,154 +36,154 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
|
||||
#define STM32L4_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
|
||||
#define STM32L4_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
|
||||
#define STM32L4_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
|
||||
#define STM32L4_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
|
||||
#define STM32L4_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
|
||||
#define STM32L4_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
|
||||
#define STM32L4_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
|
||||
#define STM32L4_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
|
||||
#define STM32L4_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
|
||||
#define STM32L4_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
|
||||
#define STM32L4_GPIO_ASCR_OFFSET 0x002c /* GPIO port analog switch control register */
|
||||
#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
|
||||
#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
|
||||
#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
|
||||
#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
|
||||
#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
|
||||
#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
|
||||
#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
|
||||
#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
|
||||
#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
|
||||
#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
|
||||
#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
|
||||
#define STM32_GPIO_ASCR_OFFSET 0x002c /* GPIO port analog switch control register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#if STM32L4_NPORTS > 0
|
||||
# define STM32L4_GPIOA_MODER (STM32L4_GPIOA_BASE+STM32L4_GPIO_MODER_OFFSET)
|
||||
# define STM32L4_GPIOA_OTYPER (STM32L4_GPIOA_BASE+STM32L4_GPIO_OTYPER_OFFSET)
|
||||
# define STM32L4_GPIOA_OSPEED (STM32L4_GPIOA_BASE+STM32L4_GPIO_OSPEED_OFFSET)
|
||||
# define STM32L4_GPIOA_PUPDR (STM32L4_GPIOA_BASE+STM32L4_GPIO_PUPDR_OFFSET)
|
||||
# define STM32L4_GPIOA_IDR (STM32L4_GPIOA_BASE+STM32L4_GPIO_IDR_OFFSET)
|
||||
# define STM32L4_GPIOA_ODR (STM32L4_GPIOA_BASE+STM32L4_GPIO_ODR_OFFSET)
|
||||
# define STM32L4_GPIOA_BSRR (STM32L4_GPIOA_BASE+STM32L4_GPIO_BSRR_OFFSET)
|
||||
# define STM32L4_GPIOA_LCKR (STM32L4_GPIOA_BASE+STM32L4_GPIO_LCKR_OFFSET)
|
||||
# define STM32L4_GPIOA_AFRL (STM32L4_GPIOA_BASE+STM32L4_GPIO_AFRL_OFFSET)
|
||||
# define STM32L4_GPIOA_AFRH (STM32L4_GPIOA_BASE+STM32L4_GPIO_AFRH_OFFSET)
|
||||
# define STM32L4_GPIOA_BRR (STM32L4_GPIOA_BASE+STM32L4_GPIO_BRR_OFFSET)
|
||||
# define STM32L4_GPIOA_ASCR (STM32L4_GPIOA_BASE+STM32L4_GPIO_ASCR_OFFSET)
|
||||
#if STM32_NPORTS > 0
|
||||
# define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOA_BRR (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
# define STM32_GPIOA_ASCR (STM32_GPIOA_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NPORTS > 1
|
||||
# define STM32L4_GPIOB_MODER (STM32L4_GPIOB_BASE+STM32L4_GPIO_MODER_OFFSET)
|
||||
# define STM32L4_GPIOB_OTYPER (STM32L4_GPIOB_BASE+STM32L4_GPIO_OTYPER_OFFSET)
|
||||
# define STM32L4_GPIOB_OSPEED (STM32L4_GPIOB_BASE+STM32L4_GPIO_OSPEED_OFFSET)
|
||||
# define STM32L4_GPIOB_PUPDR (STM32L4_GPIOB_BASE+STM32L4_GPIO_PUPDR_OFFSET)
|
||||
# define STM32L4_GPIOB_IDR (STM32L4_GPIOB_BASE+STM32L4_GPIO_IDR_OFFSET)
|
||||
# define STM32L4_GPIOB_ODR (STM32L4_GPIOB_BASE+STM32L4_GPIO_ODR_OFFSET)
|
||||
# define STM32L4_GPIOB_BSRR (STM32L4_GPIOB_BASE+STM32L4_GPIO_BSRR_OFFSET)
|
||||
# define STM32L4_GPIOB_LCKR (STM32L4_GPIOB_BASE+STM32L4_GPIO_LCKR_OFFSET)
|
||||
# define STM32L4_GPIOB_AFRL (STM32L4_GPIOB_BASE+STM32L4_GPIO_AFRL_OFFSET)
|
||||
# define STM32L4_GPIOB_AFRH (STM32L4_GPIOB_BASE+STM32L4_GPIO_AFRH_OFFSET)
|
||||
# define STM32L4_GPIOB_BRR (STM32L4_GPIOB_BASE+STM32L4_GPIO_BRR_OFFSET)
|
||||
# define STM32L4_GPIOB_ASCR (STM32L4_GPIOB_BASE+STM32L4_GPIO_ASCR_OFFSET)
|
||||
#if STM32_NPORTS > 1
|
||||
# define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOB_BRR (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
# define STM32_GPIOB_ASCR (STM32_GPIOB_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NPORTS > 2
|
||||
# define STM32L4_GPIOC_MODER (STM32L4_GPIOC_BASE+STM32L4_GPIO_MODER_OFFSET)
|
||||
# define STM32L4_GPIOC_OTYPER (STM32L4_GPIOC_BASE+STM32L4_GPIO_OTYPER_OFFSET)
|
||||
# define STM32L4_GPIOC_OSPEED (STM32L4_GPIOC_BASE+STM32L4_GPIO_OSPEED_OFFSET)
|
||||
# define STM32L4_GPIOC_PUPDR (STM32L4_GPIOC_BASE+STM32L4_GPIO_PUPDR_OFFSET)
|
||||
# define STM32L4_GPIOC_IDR (STM32L4_GPIOC_BASE+STM32L4_GPIO_IDR_OFFSET)
|
||||
# define STM32L4_GPIOC_ODR (STM32L4_GPIOC_BASE+STM32L4_GPIO_ODR_OFFSET)
|
||||
# define STM32L4_GPIOC_BSRR (STM32L4_GPIOC_BASE+STM32L4_GPIO_BSRR_OFFSET)
|
||||
# define STM32L4_GPIOC_LCKR (STM32L4_GPIOC_BASE+STM32L4_GPIO_LCKR_OFFSET)
|
||||
# define STM32L4_GPIOC_AFRL (STM32L4_GPIOC_BASE+STM32L4_GPIO_AFRL_OFFSET)
|
||||
# define STM32L4_GPIOC_AFRH (STM32L4_GPIOC_BASE+STM32L4_GPIO_AFRH_OFFSET)
|
||||
# define STM32L4_GPIOC_BRR (STM32L4_GPIOC_BASE+STM32L4_GPIO_BRR_OFFSET)
|
||||
# define STM32L4_GPIOC_ASCR (STM32L4_GPIOC_BASE+STM32L4_GPIO_ASCR_OFFSET)
|
||||
#if STM32_NPORTS > 2
|
||||
# define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOC_BRR (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
# define STM32_GPIOC_ASCR (STM32_GPIOC_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NPORTS > 3
|
||||
# define STM32L4_GPIOD_MODER (STM32L4_GPIOD_BASE+STM32L4_GPIO_MODER_OFFSET)
|
||||
# define STM32L4_GPIOD_OTYPER (STM32L4_GPIOD_BASE+STM32L4_GPIO_OTYPER_OFFSET)
|
||||
# define STM32L4_GPIOD_OSPEED (STM32L4_GPIOD_BASE+STM32L4_GPIO_OSPEED_OFFSET)
|
||||
# define STM32L4_GPIOD_PUPDR (STM32L4_GPIOD_BASE+STM32L4_GPIO_PUPDR_OFFSET)
|
||||
# define STM32L4_GPIOD_IDR (STM32L4_GPIOD_BASE+STM32L4_GPIO_IDR_OFFSET)
|
||||
# define STM32L4_GPIOD_ODR (STM32L4_GPIOD_BASE+STM32L4_GPIO_ODR_OFFSET)
|
||||
# define STM32L4_GPIOD_BSRR (STM32L4_GPIOD_BASE+STM32L4_GPIO_BSRR_OFFSET)
|
||||
# define STM32L4_GPIOD_LCKR (STM32L4_GPIOD_BASE+STM32L4_GPIO_LCKR_OFFSET)
|
||||
# define STM32L4_GPIOD_AFRL (STM32L4_GPIOD_BASE+STM32L4_GPIO_AFRL_OFFSET)
|
||||
# define STM32L4_GPIOD_AFRH (STM32L4_GPIOD_BASE+STM32L4_GPIO_AFRH_OFFSET)
|
||||
# define STM32L4_GPIOD_BRR (STM32L4_GPIOD_BASE+STM32L4_GPIO_BRR_OFFSET)
|
||||
# define STM32L4_GPIOD_ASCR (STM32L4_GPIOD_BASE+STM32L4_GPIO_ASCR_OFFSET)
|
||||
#if STM32_NPORTS > 3
|
||||
# define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOD_BRR (STM32_GPIOD_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
# define STM32_GPIOD_ASCR (STM32_GPIOD_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NPORTS > 4
|
||||
# define STM32L4_GPIOE_MODER (STM32L4_GPIOE_BASE+STM32L4_GPIO_MODER_OFFSET)
|
||||
# define STM32L4_GPIOE_OTYPER (STM32L4_GPIOE_BASE+STM32L4_GPIO_OTYPER_OFFSET)
|
||||
# define STM32L4_GPIOE_OSPEED (STM32L4_GPIOE_BASE+STM32L4_GPIO_OSPEED_OFFSET)
|
||||
# define STM32L4_GPIOE_PUPDR (STM32L4_GPIOE_BASE+STM32L4_GPIO_PUPDR_OFFSET)
|
||||
# define STM32L4_GPIOE_IDR (STM32L4_GPIOE_BASE+STM32L4_GPIO_IDR_OFFSET)
|
||||
# define STM32L4_GPIOE_ODR (STM32L4_GPIOE_BASE+STM32L4_GPIO_ODR_OFFSET)
|
||||
# define STM32L4_GPIOE_BSRR (STM32L4_GPIOE_BASE+STM32L4_GPIO_BSRR_OFFSET)
|
||||
# define STM32L4_GPIOE_LCKR (STM32L4_GPIOE_BASE+STM32L4_GPIO_LCKR_OFFSET)
|
||||
# define STM32L4_GPIOE_AFRL (STM32L4_GPIOE_BASE+STM32L4_GPIO_AFRL_OFFSET)
|
||||
# define STM32L4_GPIOE_AFRH (STM32L4_GPIOE_BASE+STM32L4_GPIO_AFRH_OFFSET)
|
||||
# define STM32L4_GPIOE_BRR (STM32L4_GPIOE_BASE+STM32L4_GPIO_BRR_OFFSET)
|
||||
# define STM32L4_GPIOE_ASCR (STM32L4_GPIOE_BASE+STM32L4_GPIO_ASCR_OFFSET)
|
||||
#if STM32_NPORTS > 4
|
||||
# define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOE_BRR (STM32_GPIOE_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
# define STM32_GPIOE_ASCR (STM32_GPIOE_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NPORTS > 5
|
||||
# define STM32L4_GPIOF_MODER (STM32L4_GPIOF_BASE+STM32L4_GPIO_MODER_OFFSET)
|
||||
# define STM32L4_GPIOF_OTYPER (STM32L4_GPIOF_BASE+STM32L4_GPIO_OTYPER_OFFSET)
|
||||
# define STM32L4_GPIOF_OSPEED (STM32L4_GPIOF_BASE+STM32L4_GPIO_OSPEED_OFFSET)
|
||||
# define STM32L4_GPIOF_PUPDR (STM32L4_GPIOF_BASE+STM32L4_GPIO_PUPDR_OFFSET)
|
||||
# define STM32L4_GPIOF_IDR (STM32L4_GPIOF_BASE+STM32L4_GPIO_IDR_OFFSET)
|
||||
# define STM32L4_GPIOF_ODR (STM32L4_GPIOF_BASE+STM32L4_GPIO_ODR_OFFSET)
|
||||
# define STM32L4_GPIOF_BSRR (STM32L4_GPIOF_BASE+STM32L4_GPIO_BSRR_OFFSET)
|
||||
# define STM32L4_GPIOF_LCKR (STM32L4_GPIOF_BASE+STM32L4_GPIO_LCKR_OFFSET)
|
||||
# define STM32L4_GPIOF_AFRL (STM32L4_GPIOF_BASE+STM32L4_GPIO_AFRL_OFFSET)
|
||||
# define STM32L4_GPIOF_AFRH (STM32L4_GPIOF_BASE+STM32L4_GPIO_AFRH_OFFSET)
|
||||
# define STM32L4_GPIOF_BRR (STM32L4_GPIOF_BASE+STM32L4_GPIO_BRR_OFFSET)
|
||||
# define STM32L4_GPIOF_ASCR (STM32L4_GPIOF_BASE+STM32L4_GPIO_ASCR_OFFSET)
|
||||
#if STM32_NPORTS > 5
|
||||
# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOF_BRR (STM32_GPIOF_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
# define STM32_GPIOF_ASCR (STM32_GPIOF_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NPORTS > 6
|
||||
# define STM32L4_GPIOG_MODER (STM32L4_GPIOG_BASE+STM32L4_GPIO_MODER_OFFSET)
|
||||
# define STM32L4_GPIOG_OTYPER (STM32L4_GPIOG_BASE+STM32L4_GPIO_OTYPER_OFFSET)
|
||||
# define STM32L4_GPIOG_OSPEED (STM32L4_GPIOG_BASE+STM32L4_GPIO_OSPEED_OFFSET)
|
||||
# define STM32L4_GPIOG_PUPDR (STM32L4_GPIOG_BASE+STM32L4_GPIO_PUPDR_OFFSET)
|
||||
# define STM32L4_GPIOG_IDR (STM32L4_GPIOG_BASE+STM32L4_GPIO_IDR_OFFSET)
|
||||
# define STM32L4_GPIOG_ODR (STM32L4_GPIOG_BASE+STM32L4_GPIO_ODR_OFFSET)
|
||||
# define STM32L4_GPIOG_BSRR (STM32L4_GPIOG_BASE+STM32L4_GPIO_BSRR_OFFSET)
|
||||
# define STM32L4_GPIOG_LCKR (STM32L4_GPIOG_BASE+STM32L4_GPIO_LCKR_OFFSET)
|
||||
# define STM32L4_GPIOG_AFRL (STM32L4_GPIOG_BASE+STM32L4_GPIO_AFRL_OFFSET)
|
||||
# define STM32L4_GPIOG_AFRH (STM32L4_GPIOG_BASE+STM32L4_GPIO_AFRH_OFFSET)
|
||||
# define STM32L4_GPIOG_BRR (STM32L4_GPIOG_BASE+STM32L4_GPIO_BRR_OFFSET)
|
||||
# define STM32L4_GPIOG_ASCR (STM32L4_GPIOG_BASE+STM32L4_GPIO_ASCR_OFFSET)
|
||||
#if STM32_NPORTS > 6
|
||||
# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOG_BRR (STM32_GPIOG_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
# define STM32_GPIOG_ASCR (STM32_GPIOG_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NPORTS > 7
|
||||
# define STM32L4_GPIOH_MODER (STM32L4_GPIOH_BASE+STM32L4_GPIO_MODER_OFFSET)
|
||||
# define STM32L4_GPIOH_OTYPER (STM32L4_GPIOH_BASE+STM32L4_GPIO_OTYPER_OFFSET)
|
||||
# define STM32L4_GPIOH_OSPEED (STM32L4_GPIOH_BASE+STM32L4_GPIO_OSPEED_OFFSET)
|
||||
# define STM32L4_GPIOH_PUPDR (STM32L4_GPIOH_BASE+STM32L4_GPIO_PUPDR_OFFSET)
|
||||
# define STM32L4_GPIOH_IDR (STM32L4_GPIOH_BASE+STM32L4_GPIO_IDR_OFFSET)
|
||||
# define STM32L4_GPIOH_ODR (STM32L4_GPIOH_BASE+STM32L4_GPIO_ODR_OFFSET)
|
||||
# define STM32L4_GPIOH_BSRR (STM32L4_GPIOH_BASE+STM32L4_GPIO_BSRR_OFFSET)
|
||||
# define STM32L4_GPIOH_LCKR (STM32L4_GPIOH_BASE+STM32L4_GPIO_LCKR_OFFSET)
|
||||
# define STM32L4_GPIOH_AFRL (STM32L4_GPIOH_BASE+STM32L4_GPIO_AFRL_OFFSET)
|
||||
# define STM32L4_GPIOH_AFRH (STM32L4_GPIOH_BASE+STM32L4_GPIO_AFRH_OFFSET)
|
||||
# define STM32L4_GPIOH_BRR (STM32L4_GPIOH_BASE+STM32L4_GPIO_BRR_OFFSET)
|
||||
# define STM32L4_GPIOH_ASCR (STM32L4_GPIOH_BASE+STM32L4_GPIO_ASCR_OFFSET)
|
||||
#if STM32_NPORTS > 7
|
||||
# define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOH_BRR (STM32_GPIOH_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
# define STM32_GPIOH_ASCR (STM32_GPIOH_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NPORTS > 8
|
||||
# define STM32L4_GPIOI_MODER (STM32L4_GPIOI_BASE+STM32L4_GPIO_MODER_OFFSET)
|
||||
# define STM32L4_GPIOI_OTYPER (STM32L4_GPIOI_BASE+STM32L4_GPIO_OTYPER_OFFSET)
|
||||
# define STM32L4_GPIOI_OSPEED (STM32L4_GPIOI_BASE+STM32L4_GPIO_OSPEED_OFFSET)
|
||||
# define STM32L4_GPIOI_PUPDR (STM32L4_GPIOI_BASE+STM32L4_GPIO_PUPDR_OFFSET)
|
||||
# define STM32L4_GPIOI_IDR (STM32L4_GPIOI_BASE+STM32L4_GPIO_IDR_OFFSET)
|
||||
# define STM32L4_GPIOI_ODR (STM32L4_GPIOI_BASE+STM32L4_GPIO_ODR_OFFSET)
|
||||
# define STM32L4_GPIOI_BSRR (STM32L4_GPIOI_BASE+STM32L4_GPIO_BSRR_OFFSET)
|
||||
# define STM32L4_GPIOI_LCKR (STM32L4_GPIOI_BASE+STM32L4_GPIO_LCKR_OFFSET)
|
||||
# define STM32L4_GPIOI_AFRL (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRL_OFFSET)
|
||||
# define STM32L4_GPIOI_AFRH (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRH_OFFSET)
|
||||
# define STM32L4_GPIOI_BRR (STM32L4_GPIOI_BASE+STM32L4_GPIO_BRR_OFFSET)
|
||||
# define STM32L4_GPIOI_ASCR (STM32L4_GPIOI_BASE+STM32L4_GPIO_ASCR_OFFSET)
|
||||
#if STM32_NPORTS > 8
|
||||
# define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOI_IDR (STM32_GPIOI_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOI_ODR (STM32_GPIOI_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOI_BRR (STM32_GPIOI_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
# define STM32_GPIOI_ASCR (STM32_GPIOI_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
@@ -29,74 +29,74 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
|
||||
#define STM32L4_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
|
||||
#define STM32L4_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
|
||||
#define STM32L4_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
|
||||
#define STM32L4_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */
|
||||
#define STM32L4_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */
|
||||
#define STM32L4_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */
|
||||
#define STM32L4_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */
|
||||
#define STM32L4_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */
|
||||
#define STM32L4_I2C_RXDR_OFFSET 0x0024 /* Receive data register */
|
||||
#define STM32L4_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */
|
||||
#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
|
||||
#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
|
||||
#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
|
||||
#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
|
||||
#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */
|
||||
#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */
|
||||
#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */
|
||||
#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */
|
||||
#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */
|
||||
#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */
|
||||
#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#if STM32L4_NI2C > 0
|
||||
# define STM32L4_I2C1_CR1 (STM32L4_I2C1_BASE+STM32L4_I2C_CR1_OFFSET)
|
||||
# define STM32L4_I2C1_CR2 (STM32L4_I2C1_BASE+STM32L4_I2C_CR2_OFFSET)
|
||||
# define STM32L4_I2C1_OAR1 (STM32L4_I2C1_BASE+STM32L4_I2C_OAR1_OFFSET)
|
||||
# define STM32L4_I2C1_OAR2 (STM32L4_I2C1_BASE+STM32L4_I2C_OAR2_OFFSET)
|
||||
# define STM32L4_I2C1_TIMINGR (STM32L4_I2C1_BASE+STM32L4_I2C_TIMINGR_OFFSET)
|
||||
# define STM32L4_I2C1_TIMEOUTR (STM32L4_I2C1_BASE+STM32L4_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32L4_I2C1_ISR (STM32L4_I2C1_BASE+STM32L4_I2C_ISR_OFFSET)
|
||||
# define STM32L4_I2C1_ICR (STM32L4_I2C1_BASE+STM32L4_I2C_ICR_OFFSET)
|
||||
# define STM32L4_I2C1_PECR (STM32L4_I2C1_BASE+STM32L4_I2C_PECR_OFFSET)
|
||||
# define STM32L4_I2C1_RXDR (STM32L4_I2C1_BASE+STM32L4_I2C_RXDR_OFFSET)
|
||||
# define STM32L4_I2C1_TXDR (STM32L4_I2C1_BASE+STM32L4_I2C_TXDR_OFFSET)
|
||||
#if STM32_NI2C > 0
|
||||
# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE+STM32_I2C_TIMINGR_OFFSET)
|
||||
# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE+STM32_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32_I2C1_ISR (STM32_I2C1_BASE+STM32_I2C_ISR_OFFSET)
|
||||
# define STM32_I2C1_ICR (STM32_I2C1_BASE+STM32_I2C_ICR_OFFSET)
|
||||
# define STM32_I2C1_PECR (STM32_I2C1_BASE+STM32_I2C_PECR_OFFSET)
|
||||
# define STM32_I2C1_RXDR (STM32_I2C1_BASE+STM32_I2C_RXDR_OFFSET)
|
||||
# define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NI2C > 1
|
||||
# define STM32L4_I2C2_CR1 (STM32L4_I2C2_BASE+STM32L4_I2C_CR1_OFFSET)
|
||||
# define STM32L4_I2C2_CR2 (STM32L4_I2C2_BASE+STM32L4_I2C_CR2_OFFSET)
|
||||
# define STM32L4_I2C2_OAR1 (STM32L4_I2C2_BASE+STM32L4_I2C_OAR1_OFFSET)
|
||||
# define STM32L4_I2C2_OAR2 (STM32L4_I2C2_BASE+STM32L4_I2C_OAR2_OFFSET)
|
||||
# define STM32L4_I2C2_TIMINGR (STM32L4_I2C2_BASE+STM32L4_I2C_TIMINGR_OFFSET)
|
||||
# define STM32L4_I2C2_TIMEOUTR (STM32L4_I2C2_BASE+STM32L4_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32L4_I2C2_ISR (STM32L4_I2C2_BASE+STM32L4_I2C_ISR_OFFSET)
|
||||
# define STM32L4_I2C2_ICR (STM32L4_I2C2_BASE+STM32L4_I2C_ICR_OFFSET)
|
||||
# define STM32L4_I2C2_PECR (STM32L4_I2C2_BASE+STM32L4_I2C_PECR_OFFSET)
|
||||
# define STM32L4_I2C2_RXDR (STM32L4_I2C2_BASE+STM32L4_I2C_RXDR_OFFSET)
|
||||
# define STM32L4_I2C2_TXDR (STM32L4_I2C2_BASE+STM32L4_I2C_TXDR_OFFSET)
|
||||
#if STM32_NI2C > 1
|
||||
# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE+STM32_I2C_TIMINGR_OFFSET)
|
||||
# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE+STM32_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32_I2C2_ISR (STM32_I2C2_BASE+STM32_I2C_ISR_OFFSET)
|
||||
# define STM32_I2C2_ICR (STM32_I2C2_BASE+STM32_I2C_ICR_OFFSET)
|
||||
# define STM32_I2C2_PECR (STM32_I2C2_BASE+STM32_I2C_PECR_OFFSET)
|
||||
# define STM32_I2C2_RXDR (STM32_I2C2_BASE+STM32_I2C_RXDR_OFFSET)
|
||||
# define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NI2C > 2
|
||||
# define STM32L4_I2C3_CR1 (STM32L4_I2C3_BASE+STM32L4_I2C_CR1_OFFSET)
|
||||
# define STM32L4_I2C3_CR2 (STM32L4_I2C3_BASE+STM32L4_I2C_CR2_OFFSET)
|
||||
# define STM32L4_I2C3_OAR1 (STM32L4_I2C3_BASE+STM32L4_I2C_OAR1_OFFSET)
|
||||
# define STM32L4_I2C3_OAR2 (STM32L4_I2C3_BASE+STM32L4_I2C_OAR2_OFFSET)
|
||||
# define STM32L4_I2C3_TIMINGR (STM32L4_I2C3_BASE+STM32L4_I2C_TIMINGR_OFFSET)
|
||||
# define STM32L4_I2C3_TIMEOUTR (STM32L4_I2C3_BASE+STM32L4_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32L4_I2C3_ISR (STM32L4_I2C3_BASE+STM32L4_I2C_ISR_OFFSET)
|
||||
# define STM32L4_I2C3_ICR (STM32L4_I2C3_BASE+STM32L4_I2C_ICR_OFFSET)
|
||||
# define STM32L4_I2C3_PECR (STM32L4_I2C3_BASE+STM32L4_I2C_PECR_OFFSET)
|
||||
# define STM32L4_I2C3_RXDR (STM32L4_I2C3_BASE+STM32L4_I2C_RXDR_OFFSET)
|
||||
# define STM32L4_I2C3_TXDR (STM32L4_I2C3_BASE+STM32L4_I2C_TXDR_OFFSET)
|
||||
#if STM32_NI2C > 2
|
||||
# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE+STM32_I2C_TIMINGR_OFFSET)
|
||||
# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE+STM32_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32_I2C3_ISR (STM32_I2C3_BASE+STM32_I2C_ISR_OFFSET)
|
||||
# define STM32_I2C3_ICR (STM32_I2C3_BASE+STM32_I2C_ICR_OFFSET)
|
||||
# define STM32_I2C3_PECR (STM32_I2C3_BASE+STM32_I2C_PECR_OFFSET)
|
||||
# define STM32_I2C3_RXDR (STM32_I2C3_BASE+STM32_I2C_RXDR_OFFSET)
|
||||
# define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NI2C > 3
|
||||
# define STM32L4_I2C4_CR1 (STM32L4_I2C4_BASE+STM32L4_I2C_CR1_OFFSET)
|
||||
# define STM32L4_I2C4_CR2 (STM32L4_I2C4_BASE+STM32L4_I2C_CR2_OFFSET)
|
||||
# define STM32L4_I2C4_OAR1 (STM32L4_I2C4_BASE+STM32L4_I2C_OAR1_OFFSET)
|
||||
# define STM32L4_I2C4_OAR2 (STM32L4_I2C4_BASE+STM32L4_I2C_OAR2_OFFSET)
|
||||
# define STM32L4_I2C4_TIMINGR (STM32L4_I2C4_BASE+STM32L4_I2C_TIMINGR_OFFSET)
|
||||
# define STM32L4_I2C4_TIMEOUTR (STM32L4_I2C4_BASE+STM32L4_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32L4_I2C4_ISR (STM32L4_I2C4_BASE+STM32L4_I2C_ISR_OFFSET)
|
||||
# define STM32L4_I2C4_ICR (STM32L4_I2C4_BASE+STM32L4_I2C_ICR_OFFSET)
|
||||
# define STM32L4_I2C4_PECR (STM32L4_I2C4_BASE+STM32L4_I2C_PECR_OFFSET)
|
||||
# define STM32L4_I2C4_RXDR (STM32L4_I2C4_BASE+STM32L4_I2C_RXDR_OFFSET)
|
||||
# define STM32L4_I2C4_TXDR (STM32L4_I2C4_BASE+STM32L4_I2C_TXDR_OFFSET)
|
||||
#if STM32_NI2C > 3
|
||||
# define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C4_OAR2 (STM32_I2C4_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C4_TIMINGR (STM32_I2C4_BASE+STM32_I2C_TIMINGR_OFFSET)
|
||||
# define STM32_I2C4_TIMEOUTR (STM32_I2C4_BASE+STM32_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32_I2C4_ISR (STM32_I2C4_BASE+STM32_I2C_ISR_OFFSET)
|
||||
# define STM32_I2C4_ICR (STM32_I2C4_BASE+STM32_I2C_ICR_OFFSET)
|
||||
# define STM32_I2C4_PECR (STM32_I2C4_BASE+STM32_I2C_PECR_OFFSET)
|
||||
# define STM32_I2C4_RXDR (STM32_I2C4_BASE+STM32_I2C_RXDR_OFFSET)
|
||||
# define STM32_I2C4_TXDR (STM32_I2C4_BASE+STM32_I2C_TXDR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
@@ -47,36 +47,36 @@
|
||||
|
||||
/* Basic Timers - TIM6 and TIM7 */
|
||||
|
||||
#define STM32L4_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and Status Register */
|
||||
#define STM32L4_LPTIM_ICR_OFFSET 0x0004 /* Interrupt Clear Register */
|
||||
#define STM32L4_LPTIM_IER_OFFSET 0x0008 /* Interrupt Enable Register */
|
||||
#define STM32L4_LPTIM_CFGR_OFFSET 0x000c /* Configuration Register */
|
||||
#define STM32L4_LPTIM_CR_OFFSET 0x0010 /* Control Register */
|
||||
#define STM32L4_LPTIM_CMP_OFFSET 0x0014 /* Compare Register */
|
||||
#define STM32L4_LPTIM_ARR_OFFSET 0x0018 /* Autoreload Register */
|
||||
#define STM32L4_LPTIM_CNT_OFFSET 0x001c /* Counter Register */
|
||||
#define STM32_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and Status Register */
|
||||
#define STM32_LPTIM_ICR_OFFSET 0x0004 /* Interrupt Clear Register */
|
||||
#define STM32_LPTIM_IER_OFFSET 0x0008 /* Interrupt Enable Register */
|
||||
#define STM32_LPTIM_CFGR_OFFSET 0x000c /* Configuration Register */
|
||||
#define STM32_LPTIM_CR_OFFSET 0x0010 /* Control Register */
|
||||
#define STM32_LPTIM_CMP_OFFSET 0x0014 /* Compare Register */
|
||||
#define STM32_LPTIM_ARR_OFFSET 0x0018 /* Autoreload Register */
|
||||
#define STM32_LPTIM_CNT_OFFSET 0x001c /* Counter Register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
/* Low-Power Timers - LPTIM1 and LPTIM2 */
|
||||
|
||||
#define STM32L4_LPTIM1_ISR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ISR_OFFSET)
|
||||
#define STM32L4_LPTIM1_ICR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ICR_OFFSET)
|
||||
#define STM32L4_LPTIM1_IER (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_IER_OFFSET)
|
||||
#define STM32L4_LPTIM1_CFGR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CFGR_OFFSET)
|
||||
#define STM32L4_LPTIM1_CR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CR_OFFSET)
|
||||
#define STM32L4_LPTIM1_CMP (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CMP_OFFSET)
|
||||
#define STM32L4_LPTIM1_ARR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ARR_OFFSET)
|
||||
#define STM32L4_LPTIM1_CNT (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CNT_OFFSET)
|
||||
#define STM32_LPTIM1_ISR (STM32_LPTIM1_BASE+STM32_LPTIM_ISR_OFFSET)
|
||||
#define STM32_LPTIM1_ICR (STM32_LPTIM1_BASE+STM32_LPTIM_ICR_OFFSET)
|
||||
#define STM32_LPTIM1_IER (STM32_LPTIM1_BASE+STM32_LPTIM_IER_OFFSET)
|
||||
#define STM32_LPTIM1_CFGR (STM32_LPTIM1_BASE+STM32_LPTIM_CFGR_OFFSET)
|
||||
#define STM32_LPTIM1_CR (STM32_LPTIM1_BASE+STM32_LPTIM_CR_OFFSET)
|
||||
#define STM32_LPTIM1_CMP (STM32_LPTIM1_BASE+STM32_LPTIM_CMP_OFFSET)
|
||||
#define STM32_LPTIM1_ARR (STM32_LPTIM1_BASE+STM32_LPTIM_ARR_OFFSET)
|
||||
#define STM32_LPTIM1_CNT (STM32_LPTIM1_BASE+STM32_LPTIM_CNT_OFFSET)
|
||||
|
||||
#define STM32L4_LPTIM2_ISR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ISR_OFFSET)
|
||||
#define STM32L4_LPTIM2_ICR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ICR_OFFSET)
|
||||
#define STM32L4_LPTIM2_IER (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_IER_OFFSET)
|
||||
#define STM32L4_LPTIM2_CFGR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CFGR_OFFSET)
|
||||
#define STM32L4_LPTIM2_CR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CR_OFFSET)
|
||||
#define STM32L4_LPTIM2_CMP (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CMP_OFFSET)
|
||||
#define STM32L4_LPTIM2_ARR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ARR_OFFSET)
|
||||
#define STM32L4_LPTIM2_CNT (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CNT_OFFSET)
|
||||
#define STM32_LPTIM2_ISR (STM32_LPTIM2_BASE+STM32_LPTIM_ISR_OFFSET)
|
||||
#define STM32_LPTIM2_ICR (STM32_LPTIM2_BASE+STM32_LPTIM_ICR_OFFSET)
|
||||
#define STM32_LPTIM2_IER (STM32_LPTIM2_BASE+STM32_LPTIM_IER_OFFSET)
|
||||
#define STM32_LPTIM2_CFGR (STM32_LPTIM2_BASE+STM32_LPTIM_CFGR_OFFSET)
|
||||
#define STM32_LPTIM2_CR (STM32_LPTIM2_BASE+STM32_LPTIM_CR_OFFSET)
|
||||
#define STM32_LPTIM2_CMP (STM32_LPTIM2_BASE+STM32_LPTIM_CMP_OFFSET)
|
||||
#define STM32_LPTIM2_ARR (STM32_LPTIM2_BASE+STM32_LPTIM_ARR_OFFSET)
|
||||
#define STM32_LPTIM2_CNT (STM32_LPTIM2_BASE+STM32_LPTIM_CNT_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -29,60 +29,60 @@
|
||||
|
||||
/* STM32L4XXX Address Blocks ************************************************/
|
||||
|
||||
#define STM32L4_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
|
||||
#define STM32L4_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */
|
||||
#define STM32L4_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
|
||||
#define STM32L4_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */
|
||||
# define STM32L4_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
|
||||
# define STM32L4_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
|
||||
#define STM32L4_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */
|
||||
# define STM32L4_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
|
||||
# define STM32L4_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
|
||||
#define STM32L4_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: FSMC register block */
|
||||
#define STM32L4_QSPI_BASE 0xa0001000 /* 0xa0001000-0xbfffffff: QSPI register block */
|
||||
#define STM32L4_OCTOSPI1_BASE 0xa0001000 /* 0xa0001000-0xa00013ff: OCTOSPI1 register block */
|
||||
#define STM32L4_OCTOSPI2_BASE 0xa0001400 /* 0xa0001400-0xa00017ff: OCTOSPI2 register block */
|
||||
/* 0xc0000000-0xdfffffff: 512Mb (not used) */
|
||||
#define STM32L4_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
|
||||
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
|
||||
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */
|
||||
#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
|
||||
#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */
|
||||
# define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
|
||||
# define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
|
||||
#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */
|
||||
# define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
|
||||
# define STM32_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
|
||||
#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: FSMC register block */
|
||||
#define STM32_QSPI_BASE 0xa0001000 /* 0xa0001000-0xbfffffff: QSPI register block */
|
||||
#define STM32_OCTOSPI1_BASE 0xa0001000 /* 0xa0001000-0xa00013ff: OCTOSPI1 register block */
|
||||
#define STM32_OCTOSPI2_BASE 0xa0001400 /* 0xa0001400-0xa00017ff: OCTOSPI2 register block */
|
||||
/* 0xc0000000-0xdfffffff: 512Mb (not used) */
|
||||
#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
|
||||
|
||||
#define STM32L4_REGION_MASK 0xf0000000
|
||||
#define STM32L4_IS_SRAM(a) ((((uint32_t)(a)) & STM32L4_REGION_MASK) == STM32L4_SRAM_BASE)
|
||||
#define STM32L4_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32L4_REGION_MASK) == STM32L4_FSMC_BANK1)
|
||||
#define STM32_REGION_MASK 0xf0000000
|
||||
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
|
||||
#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1)
|
||||
|
||||
/* Code Base Addresses ******************************************************/
|
||||
|
||||
#define STM32L4_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
|
||||
/* 0x00100000-0x07ffffff: Reserved */
|
||||
#define STM32L4_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */
|
||||
/* 0x08100000-0x0fffffff: Reserved */
|
||||
#define STM32L4_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */
|
||||
#define STM32L4_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 16k to 64k SRAM2 */
|
||||
/* 0x10010000-0x1ffeffff: Reserved */
|
||||
#define STM32L4_SRAM3_BASE 0x20040000 /* 0x20040000-0x3fffffff: SRAM3 (STM32L4R9xx only, 384k) */
|
||||
#define STM32L4_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: System memory */
|
||||
#define STM32L4_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */
|
||||
/* 0x1fff7400-0x1fff77ff: Reserved */
|
||||
#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
|
||||
/* 0x00100000-0x07ffffff: Reserved */
|
||||
#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */
|
||||
/* 0x08100000-0x0fffffff: Reserved */
|
||||
#define STM32_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */
|
||||
#define STM32_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 16k to 64k SRAM2 */
|
||||
/* 0x10010000-0x1ffeffff: Reserved */
|
||||
#define STM32_SRAM3_BASE 0x20040000 /* 0x20040000-0x3fffffff: SRAM3 (STM32L4R9xx only, 384k) */
|
||||
#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: System memory */
|
||||
#define STM32_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */
|
||||
/* 0x1fff7400-0x1fff77ff: Reserved */
|
||||
#ifdef CONFIG_STM32L4_STM32L4XR
|
||||
# define STM32L4_OPTION_BASE 0x1ff00000 /* 0x1ff00000-0x1ff0000f: Option bytes */
|
||||
/* 0x1ff00010-0x1ff00fff: Reserved */
|
||||
# define STM32L4_OPTION2_BASE 0x1ff01000 /* 0x1ff01000-0x1ff0100f: Option bytes 2 */
|
||||
/* 0x1ff01010-0x1ff01fff: Reserved */
|
||||
# define STM32_OPTION_BASE 0x1ff00000 /* 0x1ff00000-0x1ff0000f: Option bytes */
|
||||
/* 0x1ff00010-0x1ff00fff: Reserved */
|
||||
# define STM32_OPTION2_BASE 0x1ff01000 /* 0x1ff01000-0x1ff0100f: Option bytes 2 */
|
||||
/* 0x1ff01010-0x1ff01fff: Reserved */
|
||||
#else
|
||||
# define STM32L4_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff780f: Option bytes */
|
||||
/* 0x1fff7810-0x1ffff7ff: Reserved */
|
||||
# define STM32L4_OPTION2_BASE 0x1ffff800 /* 0x1ffff800-0x1ffff80f: Option bytes 2 */
|
||||
/* 0x1ffff810-0x1fffffff: Reserved */
|
||||
# define STM32_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff780f: Option bytes */
|
||||
/* 0x1fff7810-0x1ffff7ff: Reserved */
|
||||
# define STM32_OPTION2_BASE 0x1ffff800 /* 0x1ffff800-0x1ffff80f: Option bytes 2 */
|
||||
/* 0x1ffff810-0x1fffffff: Reserved */
|
||||
#endif
|
||||
|
||||
/* System Memory Addresses **************************************************/
|
||||
|
||||
#define STM32L4_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */
|
||||
#define STM32L4_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of
|
||||
#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */
|
||||
#define STM32_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of
|
||||
* the device Flash memory expressed in
|
||||
* Kbytes. Example: 0x0400 corresponds
|
||||
* to 1024 Kbytes.
|
||||
*/
|
||||
#define STM32L4_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package
|
||||
#define STM32_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package
|
||||
* type.
|
||||
* 0: LQFP64
|
||||
* 1: WLCSP64
|
||||
@@ -105,123 +105,123 @@
|
||||
/* 0x2001c000-0x2001ffff:
|
||||
* 16Kb aliased by bit-banding
|
||||
*/
|
||||
#define STM32L4_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */
|
||||
#define STM32_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */
|
||||
|
||||
/* Peripheral Base Addresses ************************************************/
|
||||
|
||||
#define STM32L4_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */
|
||||
/* 0x40009800-0x4000ffff: Reserved */
|
||||
#define STM32L4_APB2_BASE 0x40010000 /* 0x40010000-0x400163ff: APB2 */
|
||||
/* 0x40016400-0x4001ffff: Reserved */
|
||||
#define STM32L4_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */
|
||||
/* 0x40024400-0x47ffffff: Reserved */
|
||||
#define STM32L4_AHB2_BASE 0x48000000 /* 0x48000000-0x50060bff: AHB2 */
|
||||
/* 0x50060c00-0x5fffffff: Reserved */
|
||||
#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */
|
||||
/* 0x40009800-0x4000ffff: Reserved */
|
||||
#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400163ff: APB2 */
|
||||
/* 0x40016400-0x4001ffff: Reserved */
|
||||
#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */
|
||||
/* 0x40024400-0x47ffffff: Reserved */
|
||||
#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x50060bff: AHB2 */
|
||||
/* 0x50060c00-0x5fffffff: Reserved */
|
||||
|
||||
/* FSMC/QSPI Base Addresses *************************************************/
|
||||
|
||||
#define STM32L4_AHB3_BASE 0x60000000 /* 0x60000000-0xa0000fff: AHB3 */
|
||||
#define STM32_AHB3_BASE 0x60000000 /* 0x60000000-0xa0000fff: AHB3 */
|
||||
|
||||
/* in datasheet order */
|
||||
|
||||
/* APB1 Base Addresses ******************************************************/
|
||||
|
||||
#define STM32L4_LPTIM2_BASE 0x40009400
|
||||
#define STM32L4_SWPMI1_BASE 0x40008800
|
||||
#define STM32L4_I2C4_BASE 0x40008400
|
||||
#define STM32L4_LPUART1_BASE 0x40008000
|
||||
#define STM32L4_LPTIM1_BASE 0x40007c00
|
||||
#define STM32L4_OPAMP_BASE 0x40007800
|
||||
#define STM32L4_DAC_BASE 0x40007400
|
||||
#define STM32L4_PWR_BASE 0x40007000
|
||||
#define STM32_LPTIM2_BASE 0x40009400
|
||||
#define STM32_SWPMI1_BASE 0x40008800
|
||||
#define STM32_I2C4_BASE 0x40008400
|
||||
#define STM32_LPUART1_BASE 0x40008000
|
||||
#define STM32_LPTIM1_BASE 0x40007c00
|
||||
#define STM32_OPAMP_BASE 0x40007800
|
||||
#define STM32_DAC_BASE 0x40007400
|
||||
#define STM32_PWR_BASE 0x40007000
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3)
|
||||
# define STM32L4_USB_SRAM_BASE 0x40006c00
|
||||
# define STM32L4_USB_FS_BASE 0x40006800
|
||||
# define STM32_USB_SRAM_BASE 0x40006c00
|
||||
# define STM32_USB_FS_BASE 0x40006800
|
||||
#else
|
||||
# define STM32L4_CAN2_BASE 0x40006800
|
||||
# define STM32_CAN2_BASE 0x40006800
|
||||
#endif
|
||||
#define STM32L4_CAN1_BASE 0x40006400
|
||||
#define STM32L4_CRS_BASE 0x40006000
|
||||
#define STM32L4_I2C3_BASE 0x40005c00
|
||||
#define STM32L4_I2C2_BASE 0x40005800
|
||||
#define STM32L4_I2C1_BASE 0x40005400
|
||||
#define STM32L4_UART5_BASE 0x40005000
|
||||
#define STM32L4_UART4_BASE 0x40004c00
|
||||
#define STM32L4_USART3_BASE 0x40004800
|
||||
#define STM32L4_USART2_BASE 0x40004400
|
||||
#define STM32L4_SPI3_BASE 0x40003c00
|
||||
#define STM32L4_SPI2_BASE 0x40003800
|
||||
#define STM32L4_IWDG_BASE 0x40003000
|
||||
#define STM32L4_WWDG_BASE 0x40002c00
|
||||
#define STM32L4_RTC_BASE 0x40002800
|
||||
#define STM32L4_LCD_BASE 0x40002400
|
||||
#define STM32L4_TIM7_BASE 0x40001400
|
||||
#define STM32L4_TIM6_BASE 0x40001000
|
||||
#define STM32L4_TIM5_BASE 0x40000c00
|
||||
#define STM32L4_TIM4_BASE 0x40000800
|
||||
#define STM32L4_TIM3_BASE 0x40000400
|
||||
#define STM32L4_TIM2_BASE 0x40000000
|
||||
#define STM32_CAN1_BASE 0x40006400
|
||||
#define STM32_CRS_BASE 0x40006000
|
||||
#define STM32_I2C3_BASE 0x40005c00
|
||||
#define STM32_I2C2_BASE 0x40005800
|
||||
#define STM32_I2C1_BASE 0x40005400
|
||||
#define STM32_UART5_BASE 0x40005000
|
||||
#define STM32_UART4_BASE 0x40004c00
|
||||
#define STM32_USART3_BASE 0x40004800
|
||||
#define STM32_USART2_BASE 0x40004400
|
||||
#define STM32_SPI3_BASE 0x40003c00
|
||||
#define STM32_SPI2_BASE 0x40003800
|
||||
#define STM32_IWDG_BASE 0x40003000
|
||||
#define STM32_WWDG_BASE 0x40002c00
|
||||
#define STM32_RTC_BASE 0x40002800
|
||||
#define STM32_LCD_BASE 0x40002400
|
||||
#define STM32_TIM7_BASE 0x40001400
|
||||
#define STM32_TIM6_BASE 0x40001000
|
||||
#define STM32_TIM5_BASE 0x40000c00
|
||||
#define STM32_TIM4_BASE 0x40000800
|
||||
#define STM32_TIM3_BASE 0x40000400
|
||||
#define STM32_TIM2_BASE 0x40000000
|
||||
|
||||
/* APB2 Base Addresses ******************************************************/
|
||||
|
||||
#define STM32L4_DSI_BASE 0x40016c00
|
||||
#define STM32L4_LTDC_BASE 0x40016800
|
||||
#define STM32L4_DFSDM_BASE 0x40016000
|
||||
#define STM32L4_SAI2_BASE 0x40015800
|
||||
#define STM32L4_SAI1_BASE 0x40015400
|
||||
#define STM32L4_TIM17_BASE 0x40014800
|
||||
#define STM32L4_TIM16_BASE 0x40014400
|
||||
#define STM32L4_TIM15_BASE 0x40014000
|
||||
#define STM32L4_USART1_BASE 0x40013800
|
||||
#define STM32L4_TIM8_BASE 0x40013400
|
||||
#define STM32L4_SPI1_BASE 0x40013000
|
||||
#define STM32L4_TIM1_BASE 0x40012c00
|
||||
#define STM32_DSI_BASE 0x40016c00
|
||||
#define STM32_LTDC_BASE 0x40016800
|
||||
#define STM32_DFSDM_BASE 0x40016000
|
||||
#define STM32_SAI2_BASE 0x40015800
|
||||
#define STM32_SAI1_BASE 0x40015400
|
||||
#define STM32_TIM17_BASE 0x40014800
|
||||
#define STM32_TIM16_BASE 0x40014400
|
||||
#define STM32_TIM15_BASE 0x40014000
|
||||
#define STM32_USART1_BASE 0x40013800
|
||||
#define STM32_TIM8_BASE 0x40013400
|
||||
#define STM32_SPI1_BASE 0x40013000
|
||||
#define STM32_TIM1_BASE 0x40012c00
|
||||
#ifndef CONFIG_STM32L4_STM32L4XR
|
||||
# define STM32L4_SDMMC1_BASE 0x40012800
|
||||
# define STM32_SDMMC1_BASE 0x40012800
|
||||
#endif
|
||||
#define STM32L4_FIREWALL_BASE 0x40011c00
|
||||
#define STM32L4_EXTI_BASE 0x40010400
|
||||
#define STM32L4_COMP_BASE 0x40010200
|
||||
#define STM32L4_VREFBUF_BASE 0x40010030
|
||||
#define STM32L4_SYSCFG_BASE 0x40010000
|
||||
#define STM32_FIREWALL_BASE 0x40011c00
|
||||
#define STM32_EXTI_BASE 0x40010400
|
||||
#define STM32_COMP_BASE 0x40010200
|
||||
#define STM32_VREFBUF_BASE 0x40010030
|
||||
#define STM32_SYSCFG_BASE 0x40010000
|
||||
|
||||
/* AHB1 Base Addresses ******************************************************/
|
||||
|
||||
#define STM32L4_GFXMMU_BASE 0x4002c000
|
||||
#define STM32L4_DMA2D_BASE 0x4002b000
|
||||
#define STM32L4_TSC_BASE 0x40024000
|
||||
#define STM32L4_CRC_BASE 0x40023000
|
||||
#define STM32L4_FLASHIF_BASE 0x40022000
|
||||
#define STM32L4_RCC_BASE 0x40021000
|
||||
#define STM32L4_DMAMUX1_BASE 0x40020800
|
||||
#define STM32L4_DMA2_BASE 0x40020400
|
||||
#define STM32L4_DMA1_BASE 0x40020000
|
||||
#define STM32_GFXMMU_BASE 0x4002c000
|
||||
#define STM32_DMA2D_BASE 0x4002b000
|
||||
#define STM32_TSC_BASE 0x40024000
|
||||
#define STM32_CRC_BASE 0x40023000
|
||||
#define STM32_FLASHIF_BASE 0x40022000
|
||||
#define STM32_RCC_BASE 0x40021000
|
||||
#define STM32_DMAMUX1_BASE 0x40020800
|
||||
#define STM32_DMA2_BASE 0x40020400
|
||||
#define STM32_DMA1_BASE 0x40020000
|
||||
|
||||
/* AHB2 Base Addresses ******************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32L4_STM32L4XR
|
||||
# define STM32L4_SDMMC1_BASE 0x50062400
|
||||
# define STM32_SDMMC1_BASE 0x50062400
|
||||
#endif
|
||||
#define STM32L4_OCTOSPIIOM_BASE 0x50061c00
|
||||
#define STM32L4_RNG_BASE 0x50060800
|
||||
#define STM32L4_HASH_BASE 0x50060400
|
||||
#define STM32L4_AES_BASE 0x50060000
|
||||
#define STM32L4_DCMI_BASE 0x50050000
|
||||
#define STM32L4_ADC_BASE 0x50040000
|
||||
# define STM32L4_ADC1_BASE 0x50040000 /* ADC1 */
|
||||
# define STM32L4_ADC2_BASE 0x50040100 /* ADC2 */
|
||||
# define STM32L4_ADC3_BASE 0x50040200 /* ADC3 */
|
||||
# define STM32L4_ADCCMN_BASE 0x50040300 /* Common */
|
||||
#define STM32L4_OTGFS_BASE 0x50000000
|
||||
#define STM32L4_GPIOI_BASE 0x48002000
|
||||
#define STM32L4_GPIOH_BASE 0x48001c00
|
||||
#define STM32L4_GPIOG_BASE 0x48001800
|
||||
#define STM32L4_GPIOF_BASE 0x48001400
|
||||
#define STM32L4_GPIOE_BASE 0x48001000
|
||||
#define STM32L4_GPIOD_BASE 0x48000c00
|
||||
#define STM32L4_GPIOC_BASE 0x48000800
|
||||
#define STM32L4_GPIOB_BASE 0x48000400
|
||||
#define STM32L4_GPIOA_BASE 0x48000000
|
||||
#define STM32_OCTOSPIIOM_BASE 0x50061c00
|
||||
#define STM32_RNG_BASE 0x50060800
|
||||
#define STM32_HASH_BASE 0x50060400
|
||||
#define STM32_AES_BASE 0x50060000
|
||||
#define STM32_DCMI_BASE 0x50050000
|
||||
#define STM32_ADC_BASE 0x50040000
|
||||
# define STM32_ADC1_BASE 0x50040000 /* ADC1 */
|
||||
# define STM32_ADC2_BASE 0x50040100 /* ADC2 */
|
||||
# define STM32_ADC3_BASE 0x50040200 /* ADC3 */
|
||||
# define STM32_ADCCMN_BASE 0x50040300 /* Common */
|
||||
#define STM32_OTGFS_BASE 0x50000000
|
||||
#define STM32_GPIOI_BASE 0x48002000
|
||||
#define STM32_GPIOH_BASE 0x48001c00
|
||||
#define STM32_GPIOG_BASE 0x48001800
|
||||
#define STM32_GPIOF_BASE 0x48001400
|
||||
#define STM32_GPIOE_BASE 0x48001000
|
||||
#define STM32_GPIOD_BASE 0x48000c00
|
||||
#define STM32_GPIOC_BASE 0x48000800
|
||||
#define STM32_GPIOB_BASE 0x48000400
|
||||
#define STM32_GPIOA_BASE 0x48000000
|
||||
|
||||
/* Cortex-M4 Base Addresses *************************************************/
|
||||
|
||||
@@ -229,7 +229,7 @@
|
||||
* this address range
|
||||
*/
|
||||
|
||||
#define STM32L4_SCS_BASE 0xe000e000
|
||||
#define STM32L4_DEBUGMCU_BASE 0xe0042000
|
||||
#define STM32_SCS_BASE 0xe000e000
|
||||
#define STM32_DEBUGMCU_BASE 0xe0042000
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_MEMORYMAP_H */
|
||||
|
||||
@@ -36,64 +36,64 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */
|
||||
#define STM32L4_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */
|
||||
#define STM32L4_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */
|
||||
#define STM32L4_PWR_CR4_OFFSET 0x000C /* Power control register 4 */
|
||||
#define STM32L4_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */
|
||||
#define STM32L4_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */
|
||||
#define STM32L4_PWR_SCR_OFFSET 0x0018 /* Power status clear register */
|
||||
#define STM32L4_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */
|
||||
#define STM32L4_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */
|
||||
#define STM32L4_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */
|
||||
#define STM32L4_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */
|
||||
#define STM32L4_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */
|
||||
#define STM32L4_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */
|
||||
#define STM32L4_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */
|
||||
#define STM32L4_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */
|
||||
#define STM32L4_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */
|
||||
#define STM32L4_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */
|
||||
#define STM32L4_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */
|
||||
#define STM32L4_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */
|
||||
#define STM32L4_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */
|
||||
#define STM32L4_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */
|
||||
#define STM32L4_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */
|
||||
#define STM32L4_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */
|
||||
#define STM32L4_PWR_PUCRI_OFFSET 0x0060 /* Power Port I pull-up control register */
|
||||
#define STM32L4_PWR_PDCRI_OFFSET 0x0064 /* Power Port I pull-down control register */
|
||||
#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */
|
||||
#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */
|
||||
#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */
|
||||
#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */
|
||||
#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */
|
||||
#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */
|
||||
#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */
|
||||
#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */
|
||||
#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */
|
||||
#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */
|
||||
#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */
|
||||
#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */
|
||||
#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */
|
||||
#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */
|
||||
#define STM32_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */
|
||||
#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */
|
||||
#define STM32_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */
|
||||
#define STM32_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */
|
||||
#define STM32_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */
|
||||
#define STM32_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */
|
||||
#define STM32_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */
|
||||
#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */
|
||||
#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */
|
||||
#define STM32_PWR_PUCRI_OFFSET 0x0060 /* Power Port I pull-up control register */
|
||||
#define STM32_PWR_PDCRI_OFFSET 0x0064 /* Power Port I pull-down control register */
|
||||
#if defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_PWR_CR5_OFFSET 0x0080 /* Power control register 5 */
|
||||
# define STM32_PWR_CR5_OFFSET 0x0080 /* Power control register 5 */
|
||||
#endif
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_PWR_CR1 (STM32L4_PWR_BASE+STM32L4_PWR_CR1_OFFSET)
|
||||
#define STM32L4_PWR_CR2 (STM32L4_PWR_BASE+STM32L4_PWR_CR2_OFFSET)
|
||||
#define STM32L4_PWR_CR3 (STM32L4_PWR_BASE+STM32L4_PWR_CR3_OFFSET)
|
||||
#define STM32L4_PWR_CR4 (STM32L4_PWR_BASE+STM32L4_PWR_CR4_OFFSET)
|
||||
#define STM32L4_PWR_SR1 (STM32L4_PWR_BASE+STM32L4_PWR_SR1_OFFSET)
|
||||
#define STM32L4_PWR_SR2 (STM32L4_PWR_BASE+STM32L4_PWR_SR2_OFFSET)
|
||||
#define STM32L4_PWR_SCR (STM32L4_PWR_BASE+STM32L4_PWR_SCR_OFFSET)
|
||||
#define STM32L4_PWR_PUCRA (STM32L4_PWR_BASE+STM32L4_PWR_PUCRA_OFFSET)
|
||||
#define STM32L4_PWR_PDCRA (STM32L4_PWR_BASE+STM32L4_PWR_PDCRA_OFFSET)
|
||||
#define STM32L4_PWR_PUCRB (STM32L4_PWR_BASE+STM32L4_PWR_PUCRB_OFFSET)
|
||||
#define STM32L4_PWR_PDCRB (STM32L4_PWR_BASE+STM32L4_PWR_PDCRB_OFFSET)
|
||||
#define STM32L4_PWR_PUCRC (STM32L4_PWR_BASE+STM32L4_PWR_PUCRC_OFFSET)
|
||||
#define STM32L4_PWR_PDCRC (STM32L4_PWR_BASE+STM32L4_PWR_PDCRC_OFFSET)
|
||||
#define STM32L4_PWR_PUCRD (STM32L4_PWR_BASE+STM32L4_PWR_PUCRD_OFFSET)
|
||||
#define STM32L4_PWR_PDCRD (STM32L4_PWR_BASE+STM32L4_PWR_PDCRD_OFFSET)
|
||||
#define STM32L4_PWR_PUCRE (STM32L4_PWR_BASE+STM32L4_PWR_PUCRE_OFFSET)
|
||||
#define STM32L4_PWR_PDCRE (STM32L4_PWR_BASE+STM32L4_PWR_PDCRE_OFFSET)
|
||||
#define STM32L4_PWR_PUCRF (STM32L4_PWR_BASE+STM32L4_PWR_PUCRF_OFFSET)
|
||||
#define STM32L4_PWR_PDCRF (STM32L4_PWR_BASE+STM32L4_PWR_PDCRF_OFFSET)
|
||||
#define STM32L4_PWR_PUCRG (STM32L4_PWR_BASE+STM32L4_PWR_PUCRG_OFFSET)
|
||||
#define STM32L4_PWR_PDCRG (STM32L4_PWR_BASE+STM32L4_PWR_PDCRG_OFFSET)
|
||||
#define STM32L4_PWR_PUCRH (STM32L4_PWR_BASE+STM32L4_PWR_PUCRH_OFFSET)
|
||||
#define STM32L4_PWR_PDCRH (STM32L4_PWR_BASE+STM32L4_PWR_PDCRH_OFFSET)
|
||||
#define STM32L4_PWR_PUCRI (STM32L4_PWR_BASE+STM32L4_PWR_PUCRI_OFFSET)
|
||||
#define STM32L4_PWR_PDCRI (STM32L4_PWR_BASE+STM32L4_PWR_PDCRI_OFFSET)
|
||||
#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET)
|
||||
#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET)
|
||||
#define STM32_PWR_CR3 (STM32_PWR_BASE+STM32_PWR_CR3_OFFSET)
|
||||
#define STM32_PWR_CR4 (STM32_PWR_BASE+STM32_PWR_CR4_OFFSET)
|
||||
#define STM32_PWR_SR1 (STM32_PWR_BASE+STM32_PWR_SR1_OFFSET)
|
||||
#define STM32_PWR_SR2 (STM32_PWR_BASE+STM32_PWR_SR2_OFFSET)
|
||||
#define STM32_PWR_SCR (STM32_PWR_BASE+STM32_PWR_SCR_OFFSET)
|
||||
#define STM32_PWR_PUCRA (STM32_PWR_BASE+STM32_PWR_PUCRA_OFFSET)
|
||||
#define STM32_PWR_PDCRA (STM32_PWR_BASE+STM32_PWR_PDCRA_OFFSET)
|
||||
#define STM32_PWR_PUCRB (STM32_PWR_BASE+STM32_PWR_PUCRB_OFFSET)
|
||||
#define STM32_PWR_PDCRB (STM32_PWR_BASE+STM32_PWR_PDCRB_OFFSET)
|
||||
#define STM32_PWR_PUCRC (STM32_PWR_BASE+STM32_PWR_PUCRC_OFFSET)
|
||||
#define STM32_PWR_PDCRC (STM32_PWR_BASE+STM32_PWR_PDCRC_OFFSET)
|
||||
#define STM32_PWR_PUCRD (STM32_PWR_BASE+STM32_PWR_PUCRD_OFFSET)
|
||||
#define STM32_PWR_PDCRD (STM32_PWR_BASE+STM32_PWR_PDCRD_OFFSET)
|
||||
#define STM32_PWR_PUCRE (STM32_PWR_BASE+STM32_PWR_PUCRE_OFFSET)
|
||||
#define STM32_PWR_PDCRE (STM32_PWR_BASE+STM32_PWR_PDCRE_OFFSET)
|
||||
#define STM32_PWR_PUCRF (STM32_PWR_BASE+STM32_PWR_PUCRF_OFFSET)
|
||||
#define STM32_PWR_PDCRF (STM32_PWR_BASE+STM32_PWR_PDCRF_OFFSET)
|
||||
#define STM32_PWR_PUCRG (STM32_PWR_BASE+STM32_PWR_PUCRG_OFFSET)
|
||||
#define STM32_PWR_PDCRG (STM32_PWR_BASE+STM32_PWR_PDCRG_OFFSET)
|
||||
#define STM32_PWR_PUCRH (STM32_PWR_BASE+STM32_PWR_PUCRH_OFFSET)
|
||||
#define STM32_PWR_PDCRH (STM32_PWR_BASE+STM32_PWR_PDCRH_OFFSET)
|
||||
#define STM32_PWR_PUCRI (STM32_PWR_BASE+STM32_PWR_PUCRI_OFFSET)
|
||||
#define STM32_PWR_PDCRI (STM32_PWR_BASE+STM32_PWR_PDCRI_OFFSET)
|
||||
#if defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_PWR_CR5 (STM32L4_PWR_BASE+STM32L4_PWR_CR5_OFFSET)
|
||||
# define STM32_PWR_CR5 (STM32_PWR_BASE+STM32_PWR_CR5_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
@@ -38,40 +38,40 @@
|
||||
|
||||
/* General Characteristics **************************************************/
|
||||
|
||||
#define STM32L4_QSPI_MINBITS 8 /* Minimum word width */
|
||||
#define STM32L4_QSPI_MAXBITS 32 /* Maximum word width */
|
||||
#define STM32_QSPI_MINBITS 8 /* Minimum word width */
|
||||
#define STM32_QSPI_MAXBITS 32 /* Maximum word width */
|
||||
|
||||
/* QSPI register offsets ****************************************************/
|
||||
|
||||
#define STM32L4_QUADSPI_CR_OFFSET 0x0000 /* Control Register */
|
||||
#define STM32L4_QUADSPI_DCR_OFFSET 0x0004 /* Device Configuration Register */
|
||||
#define STM32L4_QUADSPI_SR_OFFSET 0x0008 /* Status Register */
|
||||
#define STM32L4_QUADSPI_FCR_OFFSET 0x000c /* Flag Clear Register */
|
||||
#define STM32L4_QUADSPI_DLR_OFFSET 0x0010 /* Data Length Register */
|
||||
#define STM32L4_QUADSPI_CCR_OFFSET 0x0014 /* Communication Configuration Register */
|
||||
#define STM32L4_QUADSPI_AR_OFFSET 0x0018 /* Address Register */
|
||||
#define STM32L4_QUADSPI_ABR_OFFSET 0x001c /* Alternate Bytes Register */
|
||||
#define STM32L4_QUADSPI_DR_OFFSET 0x0020 /* Data Register */
|
||||
#define STM32L4_QUADSPI_PSMKR_OFFSET 0x0024 /* Polling Status mask Register */
|
||||
#define STM32L4_QUADSPI_PSMAR_OFFSET 0x0028 /* Polling Status match Register */
|
||||
#define STM32L4_QUADSPI_PIR_OFFSET 0x002c /* Polling Interval Register */
|
||||
#define STM32L4_QUADSPI_LPTR_OFFSET 0x0030 /* Low-Power Timeout Register */
|
||||
#define STM32_QUADSPI_CR_OFFSET 0x0000 /* Control Register */
|
||||
#define STM32_QUADSPI_DCR_OFFSET 0x0004 /* Device Configuration Register */
|
||||
#define STM32_QUADSPI_SR_OFFSET 0x0008 /* Status Register */
|
||||
#define STM32_QUADSPI_FCR_OFFSET 0x000c /* Flag Clear Register */
|
||||
#define STM32_QUADSPI_DLR_OFFSET 0x0010 /* Data Length Register */
|
||||
#define STM32_QUADSPI_CCR_OFFSET 0x0014 /* Communication Configuration Register */
|
||||
#define STM32_QUADSPI_AR_OFFSET 0x0018 /* Address Register */
|
||||
#define STM32_QUADSPI_ABR_OFFSET 0x001c /* Alternate Bytes Register */
|
||||
#define STM32_QUADSPI_DR_OFFSET 0x0020 /* Data Register */
|
||||
#define STM32_QUADSPI_PSMKR_OFFSET 0x0024 /* Polling Status mask Register */
|
||||
#define STM32_QUADSPI_PSMAR_OFFSET 0x0028 /* Polling Status match Register */
|
||||
#define STM32_QUADSPI_PIR_OFFSET 0x002c /* Polling Interval Register */
|
||||
#define STM32_QUADSPI_LPTR_OFFSET 0x0030 /* Low-Power Timeout Register */
|
||||
|
||||
/* QSPI register addresses **************************************************/
|
||||
|
||||
#define STM32L4_QUADSPI_CR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_CR_OFFSET) /* Control Register */
|
||||
#define STM32L4_QUADSPI_DCR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DCR_OFFSET) /* Device Configuration Register */
|
||||
#define STM32L4_QUADSPI_SR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_SR_OFFSET) /* Status Register */
|
||||
#define STM32L4_QUADSPI_FCR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_FCR_OFFSET) /* Flag Clear Register */
|
||||
#define STM32L4_QUADSPI_DLR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DLR_OFFSET) /* Data Length Register */
|
||||
#define STM32L4_QUADSPI_CCR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_CCR_OFFSET) /* Communication Configuration Register */
|
||||
#define STM32L4_QUADSPI_AR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_AR_OFFSET) /* Address Register */
|
||||
#define STM32L4_QUADSPI_ABR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_ABR_OFFSET) /* Alternate Bytes Register */
|
||||
#define STM32L4_QUADSPI_DR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DR_OFFSET) /* Data Register */
|
||||
#define STM32L4_QUADSPI_PSMKR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PSMKR_OFFSET) /* Polling Status mask Register */
|
||||
#define STM32L4_QUADSPI_PSMAR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PSMAR_OFFSET) /* Polling Status match Register */
|
||||
#define STM32L4_QUADSPI_PIR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PIR_OFFSET) /* Polling Interval Register */
|
||||
#define STM32L4_QUADSPI_LPTR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_LPTR_OFFSET) /* Low-Power Timeout Register */
|
||||
#define STM32_QUADSPI_CR (STM32_QSPI_BASE+STM32_QUADSPI_CR_OFFSET) /* Control Register */
|
||||
#define STM32_QUADSPI_DCR (STM32_QSPI_BASE+STM32_QUADSPI_DCR_OFFSET) /* Device Configuration Register */
|
||||
#define STM32_QUADSPI_SR (STM32_QSPI_BASE+STM32_QUADSPI_SR_OFFSET) /* Status Register */
|
||||
#define STM32_QUADSPI_FCR (STM32_QSPI_BASE+STM32_QUADSPI_FCR_OFFSET) /* Flag Clear Register */
|
||||
#define STM32_QUADSPI_DLR (STM32_QSPI_BASE+STM32_QUADSPI_DLR_OFFSET) /* Data Length Register */
|
||||
#define STM32_QUADSPI_CCR (STM32_QSPI_BASE+STM32_QUADSPI_CCR_OFFSET) /* Communication Configuration Register */
|
||||
#define STM32_QUADSPI_AR (STM32_QSPI_BASE+STM32_QUADSPI_AR_OFFSET) /* Address Register */
|
||||
#define STM32_QUADSPI_ABR (STM32_QSPI_BASE+STM32_QUADSPI_ABR_OFFSET) /* Alternate Bytes Register */
|
||||
#define STM32_QUADSPI_DR (STM32_QSPI_BASE+STM32_QUADSPI_DR_OFFSET) /* Data Register */
|
||||
#define STM32_QUADSPI_PSMKR (STM32_QSPI_BASE+STM32_QUADSPI_PSMKR_OFFSET) /* Polling Status mask Register */
|
||||
#define STM32_QUADSPI_PSMAR (STM32_QSPI_BASE+STM32_QUADSPI_PSMAR_OFFSET) /* Polling Status match Register */
|
||||
#define STM32_QUADSPI_PIR (STM32_QSPI_BASE+STM32_QUADSPI_PIR_OFFSET) /* Polling Interval Register */
|
||||
#define STM32_QUADSPI_LPTR (STM32_QSPI_BASE+STM32_QUADSPI_LPTR_OFFSET) /* Low-Power Timeout Register */
|
||||
|
||||
/* QSPI register bit definitions ********************************************/
|
||||
|
||||
|
||||
@@ -36,15 +36,15 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_RNG_CR_OFFSET 0x0000 /* RNG Control Register */
|
||||
#define STM32L4_RNG_SR_OFFSET 0x0004 /* RNG Status Register */
|
||||
#define STM32L4_RNG_DR_OFFSET 0x0008 /* RNG Data Register */
|
||||
#define STM32_RNG_CR_OFFSET 0x0000 /* RNG Control Register */
|
||||
#define STM32_RNG_SR_OFFSET 0x0004 /* RNG Status Register */
|
||||
#define STM32_RNG_DR_OFFSET 0x0008 /* RNG Data Register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_RNG_CR (STM32L4_RNG_BASE+STM32L4_RNG_CR_OFFSET)
|
||||
#define STM32L4_RNG_SR (STM32L4_RNG_BASE+STM32L4_RNG_SR_OFFSET)
|
||||
#define STM32L4_RNG_DR (STM32L4_RNG_BASE+STM32L4_RNG_DR_OFFSET)
|
||||
#define STM32_RNG_CR (STM32_RNG_BASE+STM32_RNG_CR_OFFSET)
|
||||
#define STM32_RNG_SR (STM32_RNG_BASE+STM32_RNG_SR_OFFSET)
|
||||
#define STM32_RNG_DR (STM32_RNG_BASE+STM32_RNG_DR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -29,117 +29,117 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_RTC_TR_OFFSET 0x0000 /* RTC time register */
|
||||
#define STM32L4_RTC_DR_OFFSET 0x0004 /* RTC date register */
|
||||
#define STM32L4_RTC_CR_OFFSET 0x0008 /* RTC control register */
|
||||
#define STM32L4_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */
|
||||
#define STM32L4_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */
|
||||
#define STM32L4_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */
|
||||
#define STM32L4_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */
|
||||
#define STM32L4_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */
|
||||
#define STM32L4_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */
|
||||
#define STM32L4_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */
|
||||
#define STM32L4_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */
|
||||
#define STM32L4_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */
|
||||
#define STM32L4_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */
|
||||
#define STM32L4_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */
|
||||
#define STM32L4_RTC_CALR_OFFSET 0x003c /* RTC calibration register */
|
||||
#define STM32L4_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */
|
||||
#define STM32L4_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */
|
||||
#define STM32L4_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */
|
||||
#define STM32L4_RTC_OR_OFFSET 0x004c /* RTC option register */
|
||||
#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */
|
||||
#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */
|
||||
#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */
|
||||
#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */
|
||||
#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */
|
||||
#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */
|
||||
#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */
|
||||
#define STM32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */
|
||||
#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */
|
||||
#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */
|
||||
#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */
|
||||
#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */
|
||||
#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */
|
||||
#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */
|
||||
#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */
|
||||
#define STM32_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */
|
||||
#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */
|
||||
#define STM32_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */
|
||||
#define STM32_RTC_OR_OFFSET 0x004c /* RTC option register */
|
||||
|
||||
#define STM32L4_RTC_BKR_OFFSET(n) (0x0050+((n)<<2))
|
||||
#define STM32L4_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */
|
||||
#define STM32L4_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */
|
||||
#define STM32L4_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */
|
||||
#define STM32L4_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */
|
||||
#define STM32L4_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */
|
||||
#define STM32L4_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */
|
||||
#define STM32L4_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */
|
||||
#define STM32L4_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */
|
||||
#define STM32L4_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */
|
||||
#define STM32L4_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */
|
||||
#define STM32L4_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */
|
||||
#define STM32L4_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */
|
||||
#define STM32L4_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */
|
||||
#define STM32L4_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */
|
||||
#define STM32L4_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */
|
||||
#define STM32L4_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */
|
||||
#define STM32L4_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */
|
||||
#define STM32L4_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */
|
||||
#define STM32L4_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */
|
||||
#define STM32L4_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */
|
||||
#define STM32L4_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */
|
||||
#define STM32L4_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */
|
||||
#define STM32L4_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */
|
||||
#define STM32L4_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */
|
||||
#define STM32L4_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */
|
||||
#define STM32L4_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */
|
||||
#define STM32L4_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */
|
||||
#define STM32L4_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */
|
||||
#define STM32L4_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */
|
||||
#define STM32L4_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */
|
||||
#define STM32L4_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */
|
||||
#define STM32L4_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */
|
||||
#define STM32_RTC_BKR_OFFSET(n) (0x0050+((n)<<2))
|
||||
#define STM32_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */
|
||||
#define STM32_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */
|
||||
#define STM32_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */
|
||||
#define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */
|
||||
#define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */
|
||||
#define STM32_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */
|
||||
#define STM32_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */
|
||||
#define STM32_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */
|
||||
#define STM32_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */
|
||||
#define STM32_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */
|
||||
#define STM32_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */
|
||||
#define STM32_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */
|
||||
#define STM32_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */
|
||||
#define STM32_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */
|
||||
#define STM32_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */
|
||||
#define STM32_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */
|
||||
#define STM32_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */
|
||||
#define STM32_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */
|
||||
#define STM32_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */
|
||||
#define STM32_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */
|
||||
#define STM32_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */
|
||||
#define STM32_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */
|
||||
#define STM32_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */
|
||||
#define STM32_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */
|
||||
#define STM32_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */
|
||||
#define STM32_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */
|
||||
#define STM32_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */
|
||||
#define STM32_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */
|
||||
#define STM32_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */
|
||||
#define STM32_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */
|
||||
#define STM32_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */
|
||||
#define STM32_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_RTC_TR (STM32L4_RTC_BASE+STM32L4_RTC_TR_OFFSET)
|
||||
#define STM32L4_RTC_DR (STM32L4_RTC_BASE+STM32L4_RTC_DR_OFFSET)
|
||||
#define STM32L4_RTC_CR (STM32L4_RTC_BASE+STM32L4_RTC_CR_OFFSET)
|
||||
#define STM32L4_RTC_ISR (STM32L4_RTC_BASE+STM32L4_RTC_ISR_OFFSET)
|
||||
#define STM32L4_RTC_PRER (STM32L4_RTC_BASE+STM32L4_RTC_PRER_OFFSET)
|
||||
#define STM32L4_RTC_WUTR (STM32L4_RTC_BASE+STM32L4_RTC_WUTR_OFFSET)
|
||||
#define STM32L4_RTC_ALRMAR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMAR_OFFSET)
|
||||
#define STM32L4_RTC_ALRMBR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMBR_OFFSET)
|
||||
#define STM32L4_RTC_WPR (STM32L4_RTC_BASE+STM32L4_RTC_WPR_OFFSET)
|
||||
#define STM32L4_RTC_SSR (STM32L4_RTC_BASE+STM32L4_RTC_SSR_OFFSET)
|
||||
#define STM32L4_RTC_SHIFTR (STM32L4_RTC_BASE+STM32L4_RTC_SHIFTR_OFFSET)
|
||||
#define STM32L4_RTC_TSTR (STM32L4_RTC_BASE+STM32L4_RTC_TSTR_OFFSET)
|
||||
#define STM32L4_RTC_TSDR (STM32L4_RTC_BASE+STM32L4_RTC_TSDR_OFFSET)
|
||||
#define STM32L4_RTC_TSSSR (STM32L4_RTC_BASE+STM32L4_RTC_TSSSR_OFFSET)
|
||||
#define STM32L4_RTC_CALR (STM32L4_RTC_BASE+STM32L4_RTC_CALR_OFFSET)
|
||||
#define STM32L4_RTC_TAMPCR (STM32L4_RTC_BASE+STM32L4_RTC_TAMPCR_OFFSET)
|
||||
#define STM32L4_RTC_ALRMASSR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMASSR_OFFSET)
|
||||
#define STM32L4_RTC_ALRMBSSR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMBSSR_OFFSET)
|
||||
#define STM32L4_RTC_OR (STM32L4_RTC_BASE+STM32L4_RTC_OR_OFFSET)
|
||||
#define STM32_RTC_TR (STM32_RTC_BASE+STM32_RTC_TR_OFFSET)
|
||||
#define STM32_RTC_DR (STM32_RTC_BASE+STM32_RTC_DR_OFFSET)
|
||||
#define STM32_RTC_CR (STM32_RTC_BASE+STM32_RTC_CR_OFFSET)
|
||||
#define STM32_RTC_ISR (STM32_RTC_BASE+STM32_RTC_ISR_OFFSET)
|
||||
#define STM32_RTC_PRER (STM32_RTC_BASE+STM32_RTC_PRER_OFFSET)
|
||||
#define STM32_RTC_WUTR (STM32_RTC_BASE+STM32_RTC_WUTR_OFFSET)
|
||||
#define STM32_RTC_ALRMAR (STM32_RTC_BASE+STM32_RTC_ALRMAR_OFFSET)
|
||||
#define STM32_RTC_ALRMBR (STM32_RTC_BASE+STM32_RTC_ALRMBR_OFFSET)
|
||||
#define STM32_RTC_WPR (STM32_RTC_BASE+STM32_RTC_WPR_OFFSET)
|
||||
#define STM32_RTC_SSR (STM32_RTC_BASE+STM32_RTC_SSR_OFFSET)
|
||||
#define STM32_RTC_SHIFTR (STM32_RTC_BASE+STM32_RTC_SHIFTR_OFFSET)
|
||||
#define STM32_RTC_TSTR (STM32_RTC_BASE+STM32_RTC_TSTR_OFFSET)
|
||||
#define STM32_RTC_TSDR (STM32_RTC_BASE+STM32_RTC_TSDR_OFFSET)
|
||||
#define STM32_RTC_TSSSR (STM32_RTC_BASE+STM32_RTC_TSSSR_OFFSET)
|
||||
#define STM32_RTC_CALR (STM32_RTC_BASE+STM32_RTC_CALR_OFFSET)
|
||||
#define STM32_RTC_TAMPCR (STM32_RTC_BASE+STM32_RTC_TAMPCR_OFFSET)
|
||||
#define STM32_RTC_ALRMASSR (STM32_RTC_BASE+STM32_RTC_ALRMASSR_OFFSET)
|
||||
#define STM32_RTC_ALRMBSSR (STM32_RTC_BASE+STM32_RTC_ALRMBSSR_OFFSET)
|
||||
#define STM32_RTC_OR (STM32_RTC_BASE+STM32_RTC_OR_OFFSET)
|
||||
|
||||
#define STM32L4_RTC_BKR(n) (STM32L4_RTC_BASE+STM32L4_RTC_BKR_OFFSET(n))
|
||||
#define STM32L4_RTC_BK0R (STM32L4_RTC_BASE+STM32L4_RTC_BK0R_OFFSET)
|
||||
#define STM32L4_RTC_BK1R (STM32L4_RTC_BASE+STM32L4_RTC_BK1R_OFFSET)
|
||||
#define STM32L4_RTC_BK2R (STM32L4_RTC_BASE+STM32L4_RTC_BK2R_OFFSET)
|
||||
#define STM32L4_RTC_BK3R (STM32L4_RTC_BASE+STM32L4_RTC_BK3R_OFFSET)
|
||||
#define STM32L4_RTC_BK4R (STM32L4_RTC_BASE+STM32L4_RTC_BK4R_OFFSET)
|
||||
#define STM32L4_RTC_BK5R (STM32L4_RTC_BASE+STM32L4_RTC_BK5R_OFFSET)
|
||||
#define STM32L4_RTC_BK6R (STM32L4_RTC_BASE+STM32L4_RTC_BK6R_OFFSET)
|
||||
#define STM32L4_RTC_BK7R (STM32L4_RTC_BASE+STM32L4_RTC_BK7R_OFFSET)
|
||||
#define STM32L4_RTC_BK8R (STM32L4_RTC_BASE+STM32L4_RTC_BK8R_OFFSET)
|
||||
#define STM32L4_RTC_BK9R (STM32L4_RTC_BASE+STM32L4_RTC_BK9R_OFFSET)
|
||||
#define STM32L4_RTC_BK10R (STM32L4_RTC_BASE+STM32L4_RTC_BK10R_OFFSET)
|
||||
#define STM32L4_RTC_BK11R (STM32L4_RTC_BASE+STM32L4_RTC_BK11R_OFFSET)
|
||||
#define STM32L4_RTC_BK12R (STM32L4_RTC_BASE+STM32L4_RTC_BK12R_OFFSET)
|
||||
#define STM32L4_RTC_BK13R (STM32L4_RTC_BASE+STM32L4_RTC_BK13R_OFFSET)
|
||||
#define STM32L4_RTC_BK14R (STM32L4_RTC_BASE+STM32L4_RTC_BK14R_OFFSET)
|
||||
#define STM32L4_RTC_BK15R (STM32L4_RTC_BASE+STM32L4_RTC_BK15R_OFFSET)
|
||||
#define STM32L4_RTC_BK16R (STM32L4_RTC_BASE+STM32L4_RTC_BK16R_OFFSET)
|
||||
#define STM32L4_RTC_BK17R (STM32L4_RTC_BASE+STM32L4_RTC_BK17R_OFFSET)
|
||||
#define STM32L4_RTC_BK18R (STM32L4_RTC_BASE+STM32L4_RTC_BK18R_OFFSET)
|
||||
#define STM32L4_RTC_BK19R (STM32L4_RTC_BASE+STM32L4_RTC_BK19R_OFFSET)
|
||||
#define STM32L4_RTC_BK20R (STM32L4_RTC_BASE+STM32L4_RTC_BK20R_OFFSET)
|
||||
#define STM32L4_RTC_BK21R (STM32L4_RTC_BASE+STM32L4_RTC_BK21R_OFFSET)
|
||||
#define STM32L4_RTC_BK22R (STM32L4_RTC_BASE+STM32L4_RTC_BK22R_OFFSET)
|
||||
#define STM32L4_RTC_BK23R (STM32L4_RTC_BASE+STM32L4_RTC_BK23R_OFFSET)
|
||||
#define STM32L4_RTC_BK24R (STM32L4_RTC_BASE+STM32L4_RTC_BK24R_OFFSET)
|
||||
#define STM32L4_RTC_BK25R (STM32L4_RTC_BASE+STM32L4_RTC_BK25R_OFFSET)
|
||||
#define STM32L4_RTC_BK26R (STM32L4_RTC_BASE+STM32L4_RTC_BK26R_OFFSET)
|
||||
#define STM32L4_RTC_BK27R (STM32L4_RTC_BASE+STM32L4_RTC_BK27R_OFFSET)
|
||||
#define STM32L4_RTC_BK28R (STM32L4_RTC_BASE+STM32L4_RTC_BK28R_OFFSET)
|
||||
#define STM32L4_RTC_BK29R (STM32L4_RTC_BASE+STM32L4_RTC_BK29R_OFFSET)
|
||||
#define STM32L4_RTC_BK30R (STM32L4_RTC_BASE+STM32L4_RTC_BK30R_OFFSET)
|
||||
#define STM32L4_RTC_BK31R (STM32L4_RTC_BASE+STM32L4_RTC_BK31R_OFFSET)
|
||||
#define STM32_RTC_BKR(n) (STM32_RTC_BASE+STM32_RTC_BKR_OFFSET(n))
|
||||
#define STM32_RTC_BK0R (STM32_RTC_BASE+STM32_RTC_BK0R_OFFSET)
|
||||
#define STM32_RTC_BK1R (STM32_RTC_BASE+STM32_RTC_BK1R_OFFSET)
|
||||
#define STM32_RTC_BK2R (STM32_RTC_BASE+STM32_RTC_BK2R_OFFSET)
|
||||
#define STM32_RTC_BK3R (STM32_RTC_BASE+STM32_RTC_BK3R_OFFSET)
|
||||
#define STM32_RTC_BK4R (STM32_RTC_BASE+STM32_RTC_BK4R_OFFSET)
|
||||
#define STM32_RTC_BK5R (STM32_RTC_BASE+STM32_RTC_BK5R_OFFSET)
|
||||
#define STM32_RTC_BK6R (STM32_RTC_BASE+STM32_RTC_BK6R_OFFSET)
|
||||
#define STM32_RTC_BK7R (STM32_RTC_BASE+STM32_RTC_BK7R_OFFSET)
|
||||
#define STM32_RTC_BK8R (STM32_RTC_BASE+STM32_RTC_BK8R_OFFSET)
|
||||
#define STM32_RTC_BK9R (STM32_RTC_BASE+STM32_RTC_BK9R_OFFSET)
|
||||
#define STM32_RTC_BK10R (STM32_RTC_BASE+STM32_RTC_BK10R_OFFSET)
|
||||
#define STM32_RTC_BK11R (STM32_RTC_BASE+STM32_RTC_BK11R_OFFSET)
|
||||
#define STM32_RTC_BK12R (STM32_RTC_BASE+STM32_RTC_BK12R_OFFSET)
|
||||
#define STM32_RTC_BK13R (STM32_RTC_BASE+STM32_RTC_BK13R_OFFSET)
|
||||
#define STM32_RTC_BK14R (STM32_RTC_BASE+STM32_RTC_BK14R_OFFSET)
|
||||
#define STM32_RTC_BK15R (STM32_RTC_BASE+STM32_RTC_BK15R_OFFSET)
|
||||
#define STM32_RTC_BK16R (STM32_RTC_BASE+STM32_RTC_BK16R_OFFSET)
|
||||
#define STM32_RTC_BK17R (STM32_RTC_BASE+STM32_RTC_BK17R_OFFSET)
|
||||
#define STM32_RTC_BK18R (STM32_RTC_BASE+STM32_RTC_BK18R_OFFSET)
|
||||
#define STM32_RTC_BK19R (STM32_RTC_BASE+STM32_RTC_BK19R_OFFSET)
|
||||
#define STM32_RTC_BK20R (STM32_RTC_BASE+STM32_RTC_BK20R_OFFSET)
|
||||
#define STM32_RTC_BK21R (STM32_RTC_BASE+STM32_RTC_BK21R_OFFSET)
|
||||
#define STM32_RTC_BK22R (STM32_RTC_BASE+STM32_RTC_BK22R_OFFSET)
|
||||
#define STM32_RTC_BK23R (STM32_RTC_BASE+STM32_RTC_BK23R_OFFSET)
|
||||
#define STM32_RTC_BK24R (STM32_RTC_BASE+STM32_RTC_BK24R_OFFSET)
|
||||
#define STM32_RTC_BK25R (STM32_RTC_BASE+STM32_RTC_BK25R_OFFSET)
|
||||
#define STM32_RTC_BK26R (STM32_RTC_BASE+STM32_RTC_BK26R_OFFSET)
|
||||
#define STM32_RTC_BK27R (STM32_RTC_BASE+STM32_RTC_BK27R_OFFSET)
|
||||
#define STM32_RTC_BK28R (STM32_RTC_BASE+STM32_RTC_BK28R_OFFSET)
|
||||
#define STM32_RTC_BK29R (STM32_RTC_BASE+STM32_RTC_BK29R_OFFSET)
|
||||
#define STM32_RTC_BK30R (STM32_RTC_BASE+STM32_RTC_BK30R_OFFSET)
|
||||
#define STM32_RTC_BK31R (STM32_RTC_BASE+STM32_RTC_BK31R_OFFSET)
|
||||
|
||||
# define STM32L4_RTC_BKCOUNT 32
|
||||
# define STM32_RTC_BKCOUNT 32
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -36,67 +36,67 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */
|
||||
#define STM32_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */
|
||||
|
||||
#define STM32L4_SAI_A_OFFSET 0x0004
|
||||
#define STM32L4_SAI_B_OFFSET 0x0024
|
||||
#define STM32_SAI_A_OFFSET 0x0004
|
||||
#define STM32_SAI_B_OFFSET 0x0024
|
||||
|
||||
#define STM32L4_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */
|
||||
#define STM32L4_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */
|
||||
#define STM32L4_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */
|
||||
#define STM32L4_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */
|
||||
#define STM32L4_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */
|
||||
#define STM32L4_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */
|
||||
#define STM32L4_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */
|
||||
#define STM32L4_SAI_DR_OFFSET 0x001c /* SAI Data Register A */
|
||||
#define STM32_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */
|
||||
#define STM32_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */
|
||||
#define STM32_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */
|
||||
#define STM32_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */
|
||||
#define STM32_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */
|
||||
#define STM32_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */
|
||||
#define STM32_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */
|
||||
#define STM32_SAI_DR_OFFSET 0x001c /* SAI Data Register A */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_SAI1_GCR (STM32L4_SAI_GCR_OFFSET)
|
||||
#define STM32_SAI1_GCR (STM32_SAI_GCR_OFFSET)
|
||||
|
||||
#define STM32L4_SAI1_A_BASE (STM32L4_SAI1_BASE+STM32L4_SAI_A_OFFSET)
|
||||
#define STM32L4_SAI1_B_BASE (STM32L4_SAI1_BASE+STM32L4_SAI_B_OFFSET)
|
||||
#define STM32_SAI1_A_BASE (STM32_SAI1_BASE+STM32_SAI_A_OFFSET)
|
||||
#define STM32_SAI1_B_BASE (STM32_SAI1_BASE+STM32_SAI_B_OFFSET)
|
||||
|
||||
#define STM32L4_SAI1_ACR1 (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACR1_OFFSET)
|
||||
#define STM32L4_SAI1_ACR2 (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACR2_OFFSET)
|
||||
#define STM32L4_SAI1_AFRCR (STM32L4_SAI1_A_BASE+STM32L4_SAI_AFRCR_OFFSET)
|
||||
#define STM32L4_SAI1_ASLOTR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ASLOTR_OFFSET)
|
||||
#define STM32L4_SAI1_AIM (STM32L4_SAI1_A_BASE+STM32L4_SAI_AIM_OFFSET)
|
||||
#define STM32L4_SAI1_ASR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ASR_OFFSET)
|
||||
#define STM32L4_SAI1_ACLRFR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACLRFR_OFFSET)
|
||||
#define STM32L4_SAI1_ADR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ADR_OFFSET)
|
||||
#define STM32_SAI1_ACR1 (STM32_SAI1_A_BASE+STM32_SAI_ACR1_OFFSET)
|
||||
#define STM32_SAI1_ACR2 (STM32_SAI1_A_BASE+STM32_SAI_ACR2_OFFSET)
|
||||
#define STM32_SAI1_AFRCR (STM32_SAI1_A_BASE+STM32_SAI_AFRCR_OFFSET)
|
||||
#define STM32_SAI1_ASLOTR (STM32_SAI1_A_BASE+STM32_SAI_ASLOTR_OFFSET)
|
||||
#define STM32_SAI1_AIM (STM32_SAI1_A_BASE+STM32_SAI_AIM_OFFSET)
|
||||
#define STM32_SAI1_ASR (STM32_SAI1_A_BASE+STM32_SAI_ASR_OFFSET)
|
||||
#define STM32_SAI1_ACLRFR (STM32_SAI1_A_BASE+STM32_SAI_ACLRFR_OFFSET)
|
||||
#define STM32_SAI1_ADR (STM32_SAI1_A_BASE+STM32_SAI_ADR_OFFSET)
|
||||
|
||||
#define STM32L4_SAI1_BCR1 (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCR1_OFFSET)
|
||||
#define STM32L4_SAI1_BCR2 (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCR2_OFFSET)
|
||||
#define STM32L4_SAI1_BFRCR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BFRCR_OFFSET)
|
||||
#define STM32L4_SAI1_BSLOTR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BSLOTR_OFFSET)
|
||||
#define STM32L4_SAI1_BIM (STM32L4_SAI1_B_BASE+STM32L4_SAI_BIM_OFFSET)
|
||||
#define STM32L4_SAI1_BSR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BSR_OFFSET)
|
||||
#define STM32L4_SAI1_BCLRFR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCLRFR_OFFSET)
|
||||
#define STM32L4_SAI1_BDR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BDR_OFFSET)
|
||||
#define STM32_SAI1_BCR1 (STM32_SAI1_B_BASE+STM32_SAI_BCR1_OFFSET)
|
||||
#define STM32_SAI1_BCR2 (STM32_SAI1_B_BASE+STM32_SAI_BCR2_OFFSET)
|
||||
#define STM32_SAI1_BFRCR (STM32_SAI1_B_BASE+STM32_SAI_BFRCR_OFFSET)
|
||||
#define STM32_SAI1_BSLOTR (STM32_SAI1_B_BASE+STM32_SAI_BSLOTR_OFFSET)
|
||||
#define STM32_SAI1_BIM (STM32_SAI1_B_BASE+STM32_SAI_BIM_OFFSET)
|
||||
#define STM32_SAI1_BSR (STM32_SAI1_B_BASE+STM32_SAI_BSR_OFFSET)
|
||||
#define STM32_SAI1_BCLRFR (STM32_SAI1_B_BASE+STM32_SAI_BCLRFR_OFFSET)
|
||||
#define STM32_SAI1_BDR (STM32_SAI1_B_BASE+STM32_SAI_BDR_OFFSET)
|
||||
|
||||
#define STM32L4_SAI2_GCR (STM32L4_SAI2_BASE+STM32L4_SAI_GCR_OFFSET)
|
||||
#define STM32_SAI2_GCR (STM32_SAI2_BASE+STM32_SAI_GCR_OFFSET)
|
||||
|
||||
#define STM32L4_SAI2_A_BASE (STM32L4_SAI2_BASE+STM32L4_SAI_A_OFFSET)
|
||||
#define STM32L4_SAI2_B_BASE (STM32L4_SAI2_BASE+STM32L4_SAI_B_OFFSET)
|
||||
#define STM32_SAI2_A_BASE (STM32_SAI2_BASE+STM32_SAI_A_OFFSET)
|
||||
#define STM32_SAI2_B_BASE (STM32_SAI2_BASE+STM32_SAI_B_OFFSET)
|
||||
|
||||
#define STM32L4_SAI2_ACR1 (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACR1_OFFSET)
|
||||
#define STM32L4_SAI2_ACR2 (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACR2_OFFSET)
|
||||
#define STM32L4_SAI2_AFRCR (STM32L4_SAI2_A_BASE+STM32L4_SAI_AFRCR_OFFSET)
|
||||
#define STM32L4_SAI2_ASLOTR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ASLOTR_OFFSET)
|
||||
#define STM32L4_SAI2_AIM (STM32L4_SAI2_A_BASE+STM32L4_SAI_AIM_OFFSET)
|
||||
#define STM32L4_SAI2_ASR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ASR_OFFSET)
|
||||
#define STM32L4_SAI2_ACLRFR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACLRFR_OFFSET)
|
||||
#define STM32L4_SAI2_ADR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ADR_OFFSET)
|
||||
#define STM32_SAI2_ACR1 (STM32_SAI2_A_BASE+STM32_SAI_ACR1_OFFSET)
|
||||
#define STM32_SAI2_ACR2 (STM32_SAI2_A_BASE+STM32_SAI_ACR2_OFFSET)
|
||||
#define STM32_SAI2_AFRCR (STM32_SAI2_A_BASE+STM32_SAI_AFRCR_OFFSET)
|
||||
#define STM32_SAI2_ASLOTR (STM32_SAI2_A_BASE+STM32_SAI_ASLOTR_OFFSET)
|
||||
#define STM32_SAI2_AIM (STM32_SAI2_A_BASE+STM32_SAI_AIM_OFFSET)
|
||||
#define STM32_SAI2_ASR (STM32_SAI2_A_BASE+STM32_SAI_ASR_OFFSET)
|
||||
#define STM32_SAI2_ACLRFR (STM32_SAI2_A_BASE+STM32_SAI_ACLRFR_OFFSET)
|
||||
#define STM32_SAI2_ADR (STM32_SAI2_A_BASE+STM32_SAI_ADR_OFFSET)
|
||||
|
||||
#define STM32L4_SAI2_BCR1 (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCR1_OFFSET)
|
||||
#define STM32L4_SAI2_BCR2 (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCR2_OFFSET)
|
||||
#define STM32L4_SAI2_BFRCR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BFRCR_OFFSET)
|
||||
#define STM32L4_SAI2_BSLOTR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BSLOTR_OFFSET)
|
||||
#define STM32L4_SAI2_BIM (STM32L4_SAI2_B_BASE+STM32L4_SAI_BIM_OFFSET)
|
||||
#define STM32L4_SAI2_BSR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BSR_OFFSET)
|
||||
#define STM32L4_SAI2_BCLRFR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCLRFR_OFFSET)
|
||||
#define STM32L4_SAI2_BDR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BDR_OFFSET)
|
||||
#define STM32_SAI2_BCR1 (STM32_SAI2_B_BASE+STM32_SAI_BCR1_OFFSET)
|
||||
#define STM32_SAI2_BCR2 (STM32_SAI2_B_BASE+STM32_SAI_BCR2_OFFSET)
|
||||
#define STM32_SAI2_BFRCR (STM32_SAI2_B_BASE+STM32_SAI_BFRCR_OFFSET)
|
||||
#define STM32_SAI2_BSLOTR (STM32_SAI2_B_BASE+STM32_SAI_BSLOTR_OFFSET)
|
||||
#define STM32_SAI2_BIM (STM32_SAI2_B_BASE+STM32_SAI_BIM_OFFSET)
|
||||
#define STM32_SAI2_BSR (STM32_SAI2_B_BASE+STM32_SAI_BSR_OFFSET)
|
||||
#define STM32_SAI2_BCLRFR (STM32_SAI2_B_BASE+STM32_SAI_BCLRFR_OFFSET)
|
||||
#define STM32_SAI2_BDR (STM32_SAI2_B_BASE+STM32_SAI_BDR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -36,48 +36,48 @@
|
||||
|
||||
/* Maximum allowed speed as per specifications for all SPIs */
|
||||
|
||||
#define STM32L4_SPI_CLK_MAX 40000000UL
|
||||
#define STM32_SPI_CLK_MAX 40000000UL
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
|
||||
#define STM32L4_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
|
||||
#define STM32L4_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
|
||||
#define STM32L4_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
|
||||
#define STM32L4_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
|
||||
#define STM32L4_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
|
||||
#define STM32L4_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
|
||||
#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
|
||||
#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
|
||||
#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
|
||||
#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
|
||||
#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
|
||||
#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
|
||||
#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#if STM32L4_NSPI > 0
|
||||
# define STM32L4_SPI1_CR1 (STM32L4_SPI1_BASE+STM32L4_SPI_CR1_OFFSET)
|
||||
# define STM32L4_SPI1_CR2 (STM32L4_SPI1_BASE+STM32L4_SPI_CR2_OFFSET)
|
||||
# define STM32L4_SPI1_SR (STM32L4_SPI1_BASE+STM32L4_SPI_SR_OFFSET)
|
||||
# define STM32L4_SPI1_DR (STM32L4_SPI1_BASE+STM32L4_SPI_DR_OFFSET)
|
||||
# define STM32L4_SPI1_CRCPR (STM32L4_SPI1_BASE+STM32L4_SPI_CRCPR_OFFSET)
|
||||
# define STM32L4_SPI1_RXCRCR (STM32L4_SPI1_BASE+STM32L4_SPI_RXCRCR_OFFSET)
|
||||
# define STM32L4_SPI1_TXCRCR (STM32L4_SPI1_BASE+STM32L4_SPI_TXCRCR_OFFSET)
|
||||
#if STM32_NSPI > 0
|
||||
# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NSPI > 1
|
||||
# define STM32L4_SPI2_CR1 (STM32L4_SPI2_BASE+STM32L4_SPI_CR1_OFFSET)
|
||||
# define STM32L4_SPI2_CR2 (STM32L4_SPI2_BASE+STM32L4_SPI_CR2_OFFSET)
|
||||
# define STM32L4_SPI2_SR (STM32L4_SPI2_BASE+STM32L4_SPI_SR_OFFSET)
|
||||
# define STM32L4_SPI2_DR (STM32L4_SPI2_BASE+STM32L4_SPI_DR_OFFSET)
|
||||
# define STM32L4_SPI2_CRCPR (STM32L4_SPI2_BASE+STM32L4_SPI_CRCPR_OFFSET)
|
||||
# define STM32L4_SPI2_RXCRCR (STM32L4_SPI2_BASE+STM32L4_SPI_RXCRCR_OFFSET)
|
||||
# define STM32L4_SPI2_TXCRCR (STM32L4_SPI2_BASE+STM32L4_SPI_TXCRCR_OFFSET)
|
||||
#if STM32_NSPI > 1
|
||||
# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NSPI > 2
|
||||
# define STM32L4_SPI3_CR1 (STM32L4_SPI3_BASE+STM32L4_SPI_CR1_OFFSET)
|
||||
# define STM32L4_SPI3_CR2 (STM32L4_SPI3_BASE+STM32L4_SPI_CR2_OFFSET)
|
||||
# define STM32L4_SPI3_SR (STM32L4_SPI3_BASE+STM32L4_SPI_SR_OFFSET)
|
||||
# define STM32L4_SPI3_DR (STM32L4_SPI3_BASE+STM32L4_SPI_DR_OFFSET)
|
||||
# define STM32L4_SPI3_CRCPR (STM32L4_SPI3_BASE+STM32L4_SPI_CRCPR_OFFSET)
|
||||
# define STM32L4_SPI3_RXCRCR (STM32L4_SPI3_BASE+STM32L4_SPI_RXCRCR_OFFSET)
|
||||
# define STM32L4_SPI3_TXCRCR (STM32L4_SPI3_BASE+STM32L4_SPI_TXCRCR_OFFSET)
|
||||
#if STM32_NSPI > 2
|
||||
# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI3_DR (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -37,88 +37,88 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_USART_CR1_OFFSET 0x0000 /* Control register 1 */
|
||||
#define STM32L4_USART_CR2_OFFSET 0x0004 /* Control register 2 */
|
||||
#define STM32L4_USART_CR3_OFFSET 0x0008 /* Control register 3 */
|
||||
#define STM32L4_USART_BRR_OFFSET 0x000c /* Baud Rate register */
|
||||
#define STM32L4_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
|
||||
#define STM32L4_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
|
||||
#define STM32L4_USART_RQR_OFFSET 0x0018 /* Request register */
|
||||
#define STM32L4_USART_ISR_OFFSET 0x001c /* Interrupt and status register */
|
||||
#define STM32L4_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
|
||||
#define STM32L4_USART_RDR_OFFSET 0x0024 /* Receive Data register */
|
||||
#define STM32L4_USART_TDR_OFFSET 0x0028 /* Transmit Data register */
|
||||
#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */
|
||||
#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */
|
||||
#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */
|
||||
#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */
|
||||
#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
|
||||
#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
|
||||
#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */
|
||||
#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */
|
||||
#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
|
||||
#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */
|
||||
#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#if STM32L4_NUSART > 0
|
||||
# define STM32L4_USART1_CR1 (STM32L4_USART1_BASE+STM32L4_USART_CR1_OFFSET)
|
||||
# define STM32L4_USART1_CR2 (STM32L4_USART1_BASE+STM32L4_USART_CR2_OFFSET)
|
||||
# define STM32L4_USART1_CR3 (STM32L4_USART1_BASE+STM32L4_USART_CR3_OFFSET)
|
||||
# define STM32L4_USART1_BRR (STM32L4_USART1_BASE+STM32L4_USART_BRR_OFFSET)
|
||||
# define STM32L4_USART1_GTPR (STM32L4_USART1_BASE+STM32L4_USART_GTPR_OFFSET)
|
||||
# define STM32L4_USART1_RTOR (STM32L4_USART1_BASE+STM32L4_USART_RTOR_OFFSET)
|
||||
# define STM32L4_USART1_RQR (STM32L4_USART1_BASE+STM32L4_USART_RQR_OFFSET)
|
||||
# define STM32L4_USART1_ISR (STM32L4_USART1_BASE+STM32L4_USART_ISR_OFFSET)
|
||||
# define STM32L4_USART1_ICR (STM32L4_USART1_BASE+STM32L4_USART_ICR_OFFSET)
|
||||
# define STM32L4_USART1_RDR (STM32L4_USART1_BASE+STM32L4_USART_RDR_OFFSET)
|
||||
# define STM32L4_USART1_TDR (STM32L4_USART1_BASE+STM32L4_USART_TDR_OFFSET)
|
||||
#if STM32_NUSART > 0
|
||||
# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NUSART > 1
|
||||
# define STM32L4_USART2_CR1 (STM32L4_USART2_BASE+STM32L4_USART_CR1_OFFSET)
|
||||
# define STM32L4_USART2_CR2 (STM32L4_USART2_BASE+STM32L4_USART_CR2_OFFSET)
|
||||
# define STM32L4_USART2_CR3 (STM32L4_USART2_BASE+STM32L4_USART_CR3_OFFSET)
|
||||
# define STM32L4_USART2_BRR (STM32L4_USART2_BASE+STM32L4_USART_BRR_OFFSET)
|
||||
# define STM32L4_USART2_GTPR (STM32L4_USART2_BASE+STM32L4_USART_GTPR_OFFSET)
|
||||
# define STM32L4_USART2_RTOR (STM32L4_USART2_BASE+STM32L4_USART_RTOR_OFFSET)
|
||||
# define STM32L4_USART2_RQR (STM32L4_USART2_BASE+STM32L4_USART_RQR_OFFSET)
|
||||
# define STM32L4_USART2_ISR (STM32L4_USART2_BASE+STM32L4_USART_ISR_OFFSET)
|
||||
# define STM32L4_USART2_ICR (STM32L4_USART2_BASE+STM32L4_USART_ICR_OFFSET)
|
||||
# define STM32L4_USART2_RDR (STM32L4_USART2_BASE+STM32L4_USART_RDR_OFFSET)
|
||||
# define STM32L4_USART2_TDR (STM32L4_USART2_BASE+STM32L4_USART_TDR_OFFSET)
|
||||
#if STM32_NUSART > 1
|
||||
# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NUSART > 2
|
||||
# define STM32L4_USART3_CR1 (STM32L4_USART3_BASE+STM32L4_USART_CR1_OFFSET)
|
||||
# define STM32L4_USART3_CR2 (STM32L4_USART3_BASE+STM32L4_USART_CR2_OFFSET)
|
||||
# define STM32L4_USART3_CR3 (STM32L4_USART3_BASE+STM32L4_USART_CR3_OFFSET)
|
||||
# define STM32L4_USART3_BRR (STM32L4_USART3_BASE+STM32L4_USART_BRR_OFFSET)
|
||||
# define STM32L4_USART3_GTPR (STM32L4_USART3_BASE+STM32L4_USART_GTPR_OFFSET)
|
||||
# define STM32L4_USART3_RTOR (STM32L4_USART3_BASE+STM32L4_USART_RTOR_OFFSET)
|
||||
# define STM32L4_USART3_RQR (STM32L4_USART3_BASE+STM32L4_USART_RQR_OFFSET)
|
||||
# define STM32L4_USART3_ISR (STM32L4_USART3_BASE+STM32L4_USART_ISR_OFFSET)
|
||||
# define STM32L4_USART3_ICR (STM32L4_USART3_BASE+STM32L4_USART_ICR_OFFSET)
|
||||
# define STM32L4_USART3_RDR (STM32L4_USART3_BASE+STM32L4_USART_RDR_OFFSET)
|
||||
# define STM32L4_USART3_TDR (STM32L4_USART3_BASE+STM32L4_USART_TDR_OFFSET)
|
||||
#if STM32_NUSART > 2
|
||||
# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART3_RTOR (STM32_USART3_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART3_RQR (STM32_USART3_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART3_ISR (STM32_USART3_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART3_ICR (STM32_USART3_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART3_RDR (STM32_USART3_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NUSART > 3
|
||||
# define STM32L4_UART4_CR1 (STM32L4_UART4_BASE+STM32L4_USART_CR1_OFFSET)
|
||||
# define STM32L4_UART4_CR2 (STM32L4_UART4_BASE+STM32L4_USART_CR2_OFFSET)
|
||||
# define STM32L4_UART4_CR3 (STM32L4_UART4_BASE+STM32L4_USART_CR3_OFFSET)
|
||||
# define STM32L4_UART4_BRR (STM32L4_UART4_BASE+STM32L4_USART_BRR_OFFSET)
|
||||
# define STM32L4_UART4_GTPR (STM32L4_UART4_BASE+STM32L4_USART_GTPR_OFFSET)
|
||||
# define STM32L4_UART4_RTOR (STM32L4_UART4_BASE+STM32L4_USART_RTOR_OFFSET)
|
||||
# define STM32L4_UART4_RQR (STM32L4_UART4_BASE+STM32L4_USART_RQR_OFFSET)
|
||||
# define STM32L4_UART4_ISR (STM32L4_UART4_BASE+STM32L4_USART_ISR_OFFSET)
|
||||
# define STM32L4_UART4_ICR (STM32L4_UART4_BASE+STM32L4_USART_ICR_OFFSET)
|
||||
# define STM32L4_UART4_RDR (STM32L4_UART4_BASE+STM32L4_USART_RDR_OFFSET)
|
||||
# define STM32L4_UART4_TDR (STM32L4_UART4_BASE+STM32L4_USART_TDR_OFFSET)
|
||||
#if STM32_NUSART > 3
|
||||
# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART4_RTOR (STM32_UART4_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_UART4_RQR (STM32_UART4_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_UART4_ISR (STM32_UART4_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_UART4_ICR (STM32_UART4_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_UART4_RDR (STM32_UART4_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NUSART > 4
|
||||
# define STM32L4_UART5_CR1 (STM32L4_UART5_BASE+STM32L4_USART_CR1_OFFSET)
|
||||
# define STM32L4_UART5_CR2 (STM32L4_UART5_BASE+STM32L4_USART_CR2_OFFSET)
|
||||
# define STM32L4_UART5_CR3 (STM32L4_UART5_BASE+STM32L4_USART_CR3_OFFSET)
|
||||
# define STM32L4_UART5_BRR (STM32L4_UART5_BASE+STM32L4_USART_BRR_OFFSET)
|
||||
# define STM32L4_UART5_GTPR (STM32L4_UART5_BASE+STM32L4_USART_GTPR_OFFSET)
|
||||
# define STM32L4_UART5_RTOR (STM32L4_UART5_BASE+STM32L4_USART_RTOR_OFFSET)
|
||||
# define STM32L4_UART5_RQR (STM32L4_UART5_BASE+STM32L4_USART_RQR_OFFSET)
|
||||
# define STM32L4_UART5_ISR (STM32L4_UART5_BASE+STM32L4_USART_ISR_OFFSET)
|
||||
# define STM32L4_UART5_ICR (STM32L4_UART5_BASE+STM32L4_USART_ICR_OFFSET)
|
||||
# define STM32L4_UART5_RDR (STM32L4_UART5_BASE+STM32L4_USART_RDR_OFFSET)
|
||||
# define STM32L4_UART5_TDR (STM32L4_UART5_BASE+STM32L4_USART_TDR_OFFSET)
|
||||
#if STM32_NUSART > 4
|
||||
# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART5_RTOR (STM32_UART5_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_UART5_RQR (STM32_UART5_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_UART5_ISR (STM32_UART5_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_UART5_ICR (STM32_UART5_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_UART5_RDR (STM32_UART5_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
@@ -40,71 +40,71 @@
|
||||
|
||||
/* Endpoint Registers */
|
||||
|
||||
#define STM32L4_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */
|
||||
#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */
|
||||
|
||||
#define STM32L4_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */
|
||||
#define STM32L4_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */
|
||||
#define STM32L4_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */
|
||||
#define STM32L4_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */
|
||||
#define STM32L4_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */
|
||||
#define STM32L4_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */
|
||||
#define STM32L4_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */
|
||||
#define STM32L4_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */
|
||||
#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */
|
||||
#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */
|
||||
#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */
|
||||
#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */
|
||||
#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */
|
||||
#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */
|
||||
#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */
|
||||
#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */
|
||||
|
||||
/* Common Registers */
|
||||
|
||||
#define STM32L4_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */
|
||||
#define STM32L4_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */
|
||||
#define STM32L4_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */
|
||||
#define STM32L4_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */
|
||||
#define STM32L4_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */
|
||||
#define STM32L4_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */
|
||||
#define STM32L4_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */
|
||||
#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */
|
||||
#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */
|
||||
#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */
|
||||
#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */
|
||||
#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */
|
||||
#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */
|
||||
#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */
|
||||
|
||||
/* Buffer Descriptor Table (Relatative to BTABLE address) */
|
||||
|
||||
#define STM32L4_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */
|
||||
#define STM32L4_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */
|
||||
#define STM32L4_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */
|
||||
#define STM32L4_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */
|
||||
#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */
|
||||
#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */
|
||||
#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */
|
||||
#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */
|
||||
|
||||
#define STM32L4_USB_BTABLE_RADDR(ep,o) (((uint32_t)getreg16(STM32L4_USB_BTABLE) + ((ep) << 3)) + (o))
|
||||
#define STM32L4_USB_ADDR_TX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_ADDR_TX_WOFFSET)
|
||||
#define STM32L4_USB_COUNT_TX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_COUNT_TX_WOFFSET)
|
||||
#define STM32L4_USB_ADDR_RX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_ADDR_RX_WOFFSET)
|
||||
#define STM32L4_USB_COUNT_RX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_COUNT_RX_WOFFSET)
|
||||
#define STM32_USB_BTABLE_RADDR(ep,o) (((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o))
|
||||
#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET)
|
||||
#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET)
|
||||
#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET)
|
||||
#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET)
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
/* Endpoint Registers */
|
||||
|
||||
#define STM32L4_USB_EPR(n) (STM32L4_USB_FS_BASE + STM32L4_USB_EPR_OFFSET(n))
|
||||
#define STM32L4_USB_EP0R (STM32L4_USB_FS_BASE + STM32L4_USB_EP0R_OFFSET)
|
||||
#define STM32L4_USB_EP1R (STM32L4_USB_FS_BASE + STM32L4_USB_EP1R_OFFSET)
|
||||
#define STM32L4_USB_EP2R (STM32L4_USB_FS_BASE + STM32L4_USB_EP2R_OFFSET)
|
||||
#define STM32L4_USB_EP3R (STM32L4_USB_FS_BASE + STM32L4_USB_EP3R_OFFSET)
|
||||
#define STM32L4_USB_EP4R (STM32L4_USB_FS_BASE + STM32L4_USB_EP4R_OFFSET)
|
||||
#define STM32L4_USB_EP5R (STM32L4_USB_FS_BASE + STM32L4_USB_EP5R_OFFSET)
|
||||
#define STM32L4_USB_EP6R (STM32L4_USB_FS_BASE + STM32L4_USB_EP6R_OFFSET)
|
||||
#define STM32L4_USB_EP7R (STM32L4_USB_FS_BASE + STM32L4_USB_EP7R_OFFSET)
|
||||
#define STM32_USB_EPR(n) (STM32_USB_FS_BASE + STM32_USB_EPR_OFFSET(n))
|
||||
#define STM32_USB_EP0R (STM32_USB_FS_BASE + STM32_USB_EP0R_OFFSET)
|
||||
#define STM32_USB_EP1R (STM32_USB_FS_BASE + STM32_USB_EP1R_OFFSET)
|
||||
#define STM32_USB_EP2R (STM32_USB_FS_BASE + STM32_USB_EP2R_OFFSET)
|
||||
#define STM32_USB_EP3R (STM32_USB_FS_BASE + STM32_USB_EP3R_OFFSET)
|
||||
#define STM32_USB_EP4R (STM32_USB_FS_BASE + STM32_USB_EP4R_OFFSET)
|
||||
#define STM32_USB_EP5R (STM32_USB_FS_BASE + STM32_USB_EP5R_OFFSET)
|
||||
#define STM32_USB_EP6R (STM32_USB_FS_BASE + STM32_USB_EP6R_OFFSET)
|
||||
#define STM32_USB_EP7R (STM32_USB_FS_BASE + STM32_USB_EP7R_OFFSET)
|
||||
|
||||
/* Common Registers */
|
||||
|
||||
#define STM32L4_USB_CNTR (STM32L4_USB_FS_BASE + STM32L4_USB_CNTR_OFFSET)
|
||||
#define STM32L4_USB_ISTR (STM32L4_USB_FS_BASE + STM32L4_USB_ISTR_OFFSET)
|
||||
#define STM32L4_USB_FNR (STM32L4_USB_FS_BASE + STM32L4_USB_FNR_OFFSET)
|
||||
#define STM32L4_USB_DADDR (STM32L4_USB_FS_BASE + STM32L4_USB_DADDR_OFFSET)
|
||||
#define STM32L4_USB_BTABLE (STM32L4_USB_FS_BASE + STM32L4_USB_BTABLE_OFFSET)
|
||||
#define STM32L4_USB_LPMCSR (STM32L4_USB_FS_BASE + STM32L4_USB_LPMCSR_OFFSET)
|
||||
#define STM32L4_USB_BCDR (STM32L4_USB_FS_BASE + STM32L4_USB_BCDR_OFFSET)
|
||||
#define STM32_USB_CNTR (STM32_USB_FS_BASE + STM32_USB_CNTR_OFFSET)
|
||||
#define STM32_USB_ISTR (STM32_USB_FS_BASE + STM32_USB_ISTR_OFFSET)
|
||||
#define STM32_USB_FNR (STM32_USB_FS_BASE + STM32_USB_FNR_OFFSET)
|
||||
#define STM32_USB_DADDR (STM32_USB_FS_BASE + STM32_USB_DADDR_OFFSET)
|
||||
#define STM32_USB_BTABLE (STM32_USB_FS_BASE + STM32_USB_BTABLE_OFFSET)
|
||||
#define STM32_USB_LPMCSR (STM32_USB_FS_BASE + STM32_USB_LPMCSR_OFFSET)
|
||||
#define STM32_USB_BCDR (STM32_USB_FS_BASE + STM32_USB_BCDR_OFFSET)
|
||||
|
||||
/* Buffer Descriptor Table (Relatative to BTABLE address) */
|
||||
|
||||
#define STM32L4_USB_BTABLE_ADDR(ep,o) (STM32L4_USB_SRAM_BASE + STM32L4_USB_BTABLE_RADDR(ep,o))
|
||||
#define STM32L4_USB_ADDR_TX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_ADDR_TX_WOFFSET)
|
||||
#define STM32L4_USB_COUNT_TX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_COUNT_TX_WOFFSET)
|
||||
#define STM32L4_USB_ADDR_RX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_ADDR_RX_WOFFSET)
|
||||
#define STM32L4_USB_COUNT_RX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_COUNT_RX_WOFFSET)
|
||||
#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USB_SRAM_BASE + STM32_USB_BTABLE_RADDR(ep,o))
|
||||
#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET)
|
||||
#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET)
|
||||
#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET)
|
||||
#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -37,27 +37,27 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */
|
||||
#define STM32L4_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */
|
||||
#define STM32L4_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */
|
||||
#define STM32L4_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */
|
||||
#define STM32L4_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */
|
||||
#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */
|
||||
#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */
|
||||
#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */
|
||||
#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */
|
||||
#define STM32_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */
|
||||
|
||||
#define STM32L4_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */
|
||||
#define STM32L4_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */
|
||||
#define STM32L4_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */
|
||||
#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */
|
||||
#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */
|
||||
#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_IWDG_KR (STM32L4_IWDG_BASE+STM32L4_IWDG_KR_OFFSET)
|
||||
#define STM32L4_IWDG_PR (STM32L4_IWDG_BASE+STM32L4_IWDG_PR_OFFSET)
|
||||
#define STM32L4_IWDG_RLR (STM32L4_IWDG_BASE+STM32L4_IWDG_RLR_OFFSET)
|
||||
#define STM32L4_IWDG_SR (STM32L4_IWDG_BASE+STM32L4_IWDG_SR_OFFSET)
|
||||
#define STM32L4_IWDG_WINR (STM32L4_IWDG_BASE+STM32L4_IWDG_WINR_OFFSET)
|
||||
#define STM32_IWDG_KR (STM32_IWDG_BASE+STM32_IWDG_KR_OFFSET)
|
||||
#define STM32_IWDG_PR (STM32_IWDG_BASE+STM32_IWDG_PR_OFFSET)
|
||||
#define STM32_IWDG_RLR (STM32_IWDG_BASE+STM32_IWDG_RLR_OFFSET)
|
||||
#define STM32_IWDG_SR (STM32_IWDG_BASE+STM32_IWDG_SR_OFFSET)
|
||||
#define STM32_IWDG_WINR (STM32_IWDG_BASE+STM32_IWDG_WINR_OFFSET)
|
||||
|
||||
#define STM32L4_WWDG_CR (STM32L4_WWDG_BASE+STM32L4_WWDG_CR_OFFSET)
|
||||
#define STM32L4_WWDG_CFR (STM32L4_WWDG_BASE+STM32L4_WWDG_CFR_OFFSET)
|
||||
#define STM32L4_WWDG_SR (STM32L4_WWDG_BASE+STM32L4_WWDG_SR_OFFSET)
|
||||
#define STM32_WWDG_CR (STM32_WWDG_BASE+STM32_WWDG_CR_OFFSET)
|
||||
#define STM32_WWDG_CFR (STM32_WWDG_BASE+STM32_WWDG_CFR_OFFSET)
|
||||
#define STM32_WWDG_SR (STM32_WWDG_BASE+STM32_WWDG_SR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -38,23 +38,23 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32L4_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32L4_FIREWALL_CR_OFFSET 0x0020
|
||||
#define STM32_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32_FIREWALL_CR_OFFSET 0x0020
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET)
|
||||
#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET)
|
||||
#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET)
|
||||
#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET)
|
||||
#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET)
|
||||
#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET)
|
||||
#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET)
|
||||
#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -37,73 +37,73 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
|
||||
#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */
|
||||
#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */
|
||||
#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */
|
||||
#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
|
||||
#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */
|
||||
#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */
|
||||
#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET)
|
||||
#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET)
|
||||
#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET)
|
||||
#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET)
|
||||
#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET)
|
||||
#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET)
|
||||
#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET)
|
||||
#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET)
|
||||
#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET)
|
||||
#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET)
|
||||
#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET)
|
||||
#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET)
|
||||
#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET)
|
||||
#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
|
||||
#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET)
|
||||
#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
|
||||
#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET)
|
||||
#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET)
|
||||
#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET)
|
||||
#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET)
|
||||
#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET)
|
||||
#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET)
|
||||
#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET)
|
||||
#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
|
||||
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
|
||||
#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET)
|
||||
#define STM32_RCC_CCIPR2 (STM32_RCC_BASE+STM32_RCC_CCIPR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -38,33 +38,33 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
|
||||
#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
|
||||
#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET)
|
||||
#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -38,23 +38,23 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32L4_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32L4_FIREWALL_CR_OFFSET 0x0020
|
||||
#define STM32_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32_FIREWALL_CR_OFFSET 0x0020
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET)
|
||||
#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET)
|
||||
#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET)
|
||||
#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET)
|
||||
#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET)
|
||||
#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET)
|
||||
#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET)
|
||||
#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -48,182 +48,182 @@
|
||||
|
||||
/* Core global control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */
|
||||
#define STM32L4_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */
|
||||
#define STM32L4_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */
|
||||
#define STM32L4_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */
|
||||
#define STM32L4_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */
|
||||
#define STM32L4_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */
|
||||
#define STM32L4_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */
|
||||
#define STM32L4_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */
|
||||
#define STM32L4_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */
|
||||
#define STM32L4_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */
|
||||
#define STM32L4_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */
|
||||
#define STM32L4_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */
|
||||
#define STM32L4_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */
|
||||
#define STM32L4_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */
|
||||
#define STM32L4_OTGFS_CID_OFFSET 0x003c /* Core ID register */
|
||||
#define STM32L4_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */
|
||||
#define STM32L4_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */
|
||||
#define STM32L4_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */
|
||||
#define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */
|
||||
#define STM32_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */
|
||||
#define STM32_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */
|
||||
#define STM32_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */
|
||||
#define STM32_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */
|
||||
#define STM32_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */
|
||||
#define STM32_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */
|
||||
#define STM32_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */
|
||||
#define STM32_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */
|
||||
#define STM32_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */
|
||||
#define STM32_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */
|
||||
#define STM32_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */
|
||||
#define STM32_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */
|
||||
#define STM32_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */
|
||||
#define STM32_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */
|
||||
#define STM32_OTGFS_CID_OFFSET 0x003c /* Core ID register */
|
||||
#define STM32_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */
|
||||
#define STM32_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */
|
||||
#define STM32_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */
|
||||
#define STM32_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */
|
||||
|
||||
#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2))
|
||||
#define STM32_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2))
|
||||
|
||||
/* Host-mode control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */
|
||||
#define STM32L4_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */
|
||||
#define STM32L4_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */
|
||||
#define STM32L4_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */
|
||||
#define STM32L4_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */
|
||||
#define STM32L4_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */
|
||||
#define STM32L4_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */
|
||||
#define STM32_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */
|
||||
#define STM32_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */
|
||||
#define STM32_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */
|
||||
#define STM32_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */
|
||||
#define STM32_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */
|
||||
#define STM32_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */
|
||||
#define STM32_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */
|
||||
|
||||
#define STM32L4_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5)
|
||||
#define STM32L4_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */
|
||||
#define STM32L4_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */
|
||||
#define STM32L4_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */
|
||||
#define STM32L4_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */
|
||||
#define STM32_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5)
|
||||
#define STM32_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */
|
||||
#define STM32_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */
|
||||
#define STM32_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */
|
||||
#define STM32_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */
|
||||
|
||||
#define STM32L4_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5))
|
||||
#define STM32_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5))
|
||||
#define STM32_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5))
|
||||
#define STM32_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5))
|
||||
#define STM32_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5))
|
||||
|
||||
/* Device-mode control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */
|
||||
#define STM32L4_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */
|
||||
#define STM32L4_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */
|
||||
#define STM32L4_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */
|
||||
#define STM32L4_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */
|
||||
#define STM32L4_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */
|
||||
#define STM32L4_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */
|
||||
#define STM32L4_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */
|
||||
#define STM32L4_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */
|
||||
#define STM32L4_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */
|
||||
#define STM32_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */
|
||||
#define STM32_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */
|
||||
#define STM32_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */
|
||||
#define STM32_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */
|
||||
#define STM32_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */
|
||||
#define STM32_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */
|
||||
#define STM32_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */
|
||||
#define STM32_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */
|
||||
#define STM32_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */
|
||||
#define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */
|
||||
|
||||
#define STM32L4_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5))
|
||||
#define STM32L4_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */
|
||||
#define STM32L4_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */
|
||||
#define STM32L4_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */
|
||||
#define STM32L4_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */
|
||||
#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5))
|
||||
#define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */
|
||||
#define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */
|
||||
#define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */
|
||||
#define STM32_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */
|
||||
|
||||
#define STM32L4_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5))
|
||||
#define STM32_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5))
|
||||
#define STM32_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5))
|
||||
#define STM32_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5))
|
||||
#define STM32_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5))
|
||||
#define STM32L4_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */
|
||||
#define STM32L4_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */
|
||||
#define STM32L4_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */
|
||||
#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5))
|
||||
#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */
|
||||
#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */
|
||||
#define STM32_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */
|
||||
|
||||
#define STM32L4_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5))
|
||||
#define STM32_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5))
|
||||
#define STM32_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5))
|
||||
#define STM32_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5))
|
||||
|
||||
/* Power and clock gating registers */
|
||||
|
||||
#define STM32L4_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */
|
||||
#define STM32_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */
|
||||
|
||||
/* Data FIFO (DFIFO) access registers */
|
||||
|
||||
#define STM32L4_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12))
|
||||
#define STM32L4_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12))
|
||||
#define STM32_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12))
|
||||
#define STM32_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12))
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_OTGFS_GOTGCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGCTL_OFFSET)
|
||||
#define STM32L4_OTGFS_GOTGINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGINT_OFFSET)
|
||||
#define STM32L4_OTGFS_GAHBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GAHBCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_GUSBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GUSBCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_GRSTCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRSTCTL_OFFSET)
|
||||
#define STM32L4_OTGFS_GINTSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTSTS_OFFSET)
|
||||
#define STM32L4_OTGFS_GINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_GRXSTSR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSR_OFFSET)
|
||||
#define STM32L4_OTGFS_GRXSTSP (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSP_OFFSET)
|
||||
#define STM32L4_OTGFS_GRXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXFSIZ_OFFSET)
|
||||
#define STM32L4_OTGFS_HNPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXFSIZ_OFFSET)
|
||||
#define STM32L4_OTGFS_DIEPTXF0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF0_OFFSET)
|
||||
#define STM32L4_OTGFS_HNPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXSTS_OFFSET)
|
||||
#define STM32L4_OTGFS_GCCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GCCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_CID (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CID_OFFSET)
|
||||
#define STM32L4_OTGFS_GLPMCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GLPMCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_GPWRDN (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GPWRDN_OFFSET)
|
||||
#define STM32L4_OTGFS_GADPCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GADPCTL_OFSSET)
|
||||
#define STM32L4_OTGFS_HPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXFSIZ_OFFSET)
|
||||
#define STM32_OTGFS_GOTGCTL (STM32_OTGFS_BASE+STM32_OTGFS_GOTGCTL_OFFSET)
|
||||
#define STM32_OTGFS_GOTGINT (STM32_OTGFS_BASE+STM32_OTGFS_GOTGINT_OFFSET)
|
||||
#define STM32_OTGFS_GAHBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GAHBCFG_OFFSET)
|
||||
#define STM32_OTGFS_GUSBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GUSBCFG_OFFSET)
|
||||
#define STM32_OTGFS_GRSTCTL (STM32_OTGFS_BASE+STM32_OTGFS_GRSTCTL_OFFSET)
|
||||
#define STM32_OTGFS_GINTSTS (STM32_OTGFS_BASE+STM32_OTGFS_GINTSTS_OFFSET)
|
||||
#define STM32_OTGFS_GINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_GINTMSK_OFFSET)
|
||||
#define STM32_OTGFS_GRXSTSR (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSR_OFFSET)
|
||||
#define STM32_OTGFS_GRXSTSP (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSP_OFFSET)
|
||||
#define STM32_OTGFS_GRXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_GRXFSIZ_OFFSET)
|
||||
#define STM32_OTGFS_HNPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXFSIZ_OFFSET)
|
||||
#define STM32_OTGFS_DIEPTXF0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF0_OFFSET)
|
||||
#define STM32_OTGFS_HNPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXSTS_OFFSET)
|
||||
#define STM32_OTGFS_GCCFG (STM32_OTGFS_BASE+STM32_OTGFS_GCCFG_OFFSET)
|
||||
#define STM32_OTGFS_CID (STM32_OTGFS_BASE+STM32_OTGFS_CID_OFFSET)
|
||||
#define STM32_OTGFS_GLPMCFG (STM32_OTGFS_BASE+STM32_OTGFS_GLPMCFG_OFFSET)
|
||||
#define STM32_OTGFS_GPWRDN (STM32_OTGFS_BASE+STM32_OTGFS_GPWRDN_OFFSET)
|
||||
#define STM32_OTGFS_GADPCTL (STM32_OTGFS_BASE+STM32_OTGFS_GADPCTL_OFSSET)
|
||||
#define STM32_OTGFS_HPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HPTXFSIZ_OFFSET)
|
||||
|
||||
#define STM32L4_OTGFS_DIEPTXF(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEPTXF(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF_OFFSET(n))
|
||||
|
||||
/* Host-mode control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_HCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_HFIR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFIR_OFFSET)
|
||||
#define STM32L4_OTGFS_HFNUM (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFNUM_OFFSET)
|
||||
#define STM32L4_OTGFS_HPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXSTS_OFFSET)
|
||||
#define STM32L4_OTGFS_HAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINT_OFFSET)
|
||||
#define STM32L4_OTGFS_HAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINTMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_HPRT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPRT_OFFSET)
|
||||
#define STM32_OTGFS_HCFG (STM32_OTGFS_BASE+STM32_OTGFS_HCFG_OFFSET)
|
||||
#define STM32_OTGFS_HFIR (STM32_OTGFS_BASE+STM32_OTGFS_HFIR_OFFSET)
|
||||
#define STM32_OTGFS_HFNUM (STM32_OTGFS_BASE+STM32_OTGFS_HFNUM_OFFSET)
|
||||
#define STM32_OTGFS_HPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HPTXSTS_OFFSET)
|
||||
#define STM32_OTGFS_HAINT (STM32_OTGFS_BASE+STM32_OTGFS_HAINT_OFFSET)
|
||||
#define STM32_OTGFS_HAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_HAINTMSK_OFFSET)
|
||||
#define STM32_OTGFS_HPRT (STM32_OTGFS_BASE+STM32_OTGFS_HPRT_OFFSET)
|
||||
|
||||
#define STM32L4_OTGFS_CHAN(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CHAN_OFFSET(n))
|
||||
#define STM32_OTGFS_CHAN(n) (STM32_OTGFS_BASE+STM32_OTGFS_CHAN_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_HCCHAR(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR_OFFSET(n))
|
||||
#define STM32_OTGFS_HCCHAR(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_HCINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT_OFFSET(n))
|
||||
#define STM32_OTGFS_HCINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINT_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_HCINTMSK(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK_OFFSET(n))
|
||||
#define STM32_OTGFS_HCINTMSK(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_HCTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ_OFFSET(n))
|
||||
#define STM32_OTGFS_HCTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ_OFFSET(n))
|
||||
|
||||
/* Device-mode control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_DCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_DCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCTL_OFFSET)
|
||||
#define STM32L4_OTGFS_DSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DSTS_OFFSET)
|
||||
#define STM32L4_OTGFS_DIEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_DOEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_DAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINT_OFFSET)
|
||||
#define STM32L4_OTGFS_DAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINTMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_DVBUSDIS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSDIS_OFFSET)
|
||||
#define STM32L4_OTGFS_DVBUSPULSE (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSPULSE_OFFSET)
|
||||
#define STM32L4_OTGFS_DIEPEMPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPEMPMSK_OFFSET)
|
||||
#define STM32_OTGFS_DCFG (STM32_OTGFS_BASE+STM32_OTGFS_DCFG_OFFSET)
|
||||
#define STM32_OTGFS_DCTL (STM32_OTGFS_BASE+STM32_OTGFS_DCTL_OFFSET)
|
||||
#define STM32_OTGFS_DSTS (STM32_OTGFS_BASE+STM32_OTGFS_DSTS_OFFSET)
|
||||
#define STM32_OTGFS_DIEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPMSK_OFFSET)
|
||||
#define STM32_OTGFS_DOEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DOEPMSK_OFFSET)
|
||||
#define STM32_OTGFS_DAINT (STM32_OTGFS_BASE+STM32_OTGFS_DAINT_OFFSET)
|
||||
#define STM32_OTGFS_DAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_DAINTMSK_OFFSET)
|
||||
#define STM32_OTGFS_DVBUSDIS (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSDIS_OFFSET)
|
||||
#define STM32_OTGFS_DVBUSPULSE (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSPULSE_OFFSET)
|
||||
#define STM32_OTGFS_DIEPEMPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPEMPMSK_OFFSET)
|
||||
|
||||
#define STM32L4_OTGFS_DIEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEP_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEP_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DTXFSTS(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS_OFFSET(n))
|
||||
#define STM32_OTGFS_DTXFSTS(n) (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DOEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEP_OFFSET(n))
|
||||
#define STM32_OTGFS_DOEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEP_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL_OFFSET(n))
|
||||
#define STM32_OTGFS_DOEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT_OFFSET(n))
|
||||
#define STM32_OTGFS_DOEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ_OFFSET(n))
|
||||
#define STM32_OTGFS_DOEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ_OFFSET(n))
|
||||
|
||||
/* Power and clock gating registers */
|
||||
|
||||
#define STM32L4_OTGFS_PCGCCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_PCGCCTL_OFFSET)
|
||||
#define STM32_OTGFS_PCGCCTL (STM32_OTGFS_BASE+STM32_OTGFS_PCGCCTL_OFFSET)
|
||||
|
||||
/* Data FIFO (DFIFO) access registers */
|
||||
|
||||
#define STM32L4_OTGFS_DFIFO_DEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP_OFFSET(n))
|
||||
#define STM32L4_OTGFS_DFIFO_HCH(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH_OFFSET(n))
|
||||
#define STM32_OTGFS_DFIFO_DEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP_OFFSET(n))
|
||||
#define STM32_OTGFS_DFIFO_HCH(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH_OFFSET(n))
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
@@ -741,7 +741,7 @@
|
||||
#define OTGFS_DSTS_SOFFN_ODD OTGFS_DSTS_SOFFN0
|
||||
#define OTGFS_DSTS_DEVLNSTS_SHIFT (22) /* Bits 22-23: XXX */
|
||||
#define OTGFS_DSTS_DEVLNSTS_MASK (0x3 << OTGFS_DSTS_DEVLNSTS_SHIFT)
|
||||
/* Bits 24-31: Reserved, must be kept at reset value */
|
||||
/* Bits 24-31: Reserved, must be kept at reset value */
|
||||
|
||||
/* Device IN endpoint common interrupt mask register */
|
||||
|
||||
|
||||
@@ -37,69 +37,69 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
|
||||
#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */
|
||||
#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
|
||||
#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */
|
||||
#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET)
|
||||
#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET)
|
||||
#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET)
|
||||
#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET)
|
||||
#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET)
|
||||
#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET)
|
||||
#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET)
|
||||
#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET)
|
||||
#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET)
|
||||
#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET)
|
||||
#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET)
|
||||
#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
|
||||
#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET)
|
||||
#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
|
||||
#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET)
|
||||
#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET)
|
||||
#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET)
|
||||
#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET)
|
||||
#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET)
|
||||
#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET)
|
||||
#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET)
|
||||
#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
|
||||
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -38,33 +38,33 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
|
||||
#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
|
||||
#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET)
|
||||
#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -38,23 +38,23 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32L4_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32L4_FIREWALL_CR_OFFSET 0x0020
|
||||
#define STM32_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32_FIREWALL_CR_OFFSET 0x0020
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET)
|
||||
#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET)
|
||||
#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET)
|
||||
#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET)
|
||||
#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET)
|
||||
#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET)
|
||||
#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET)
|
||||
#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -48,182 +48,182 @@
|
||||
|
||||
/* Core global control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */
|
||||
#define STM32L4_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */
|
||||
#define STM32L4_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */
|
||||
#define STM32L4_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */
|
||||
#define STM32L4_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */
|
||||
#define STM32L4_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */
|
||||
#define STM32L4_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */
|
||||
#define STM32L4_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */
|
||||
#define STM32L4_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */
|
||||
#define STM32L4_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */
|
||||
#define STM32L4_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */
|
||||
#define STM32L4_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */
|
||||
#define STM32L4_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */
|
||||
#define STM32L4_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */
|
||||
#define STM32L4_OTGFS_CID_OFFSET 0x003c /* Core ID register */
|
||||
#define STM32L4_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */
|
||||
#define STM32L4_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */
|
||||
#define STM32L4_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */
|
||||
#define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */
|
||||
#define STM32_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */
|
||||
#define STM32_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */
|
||||
#define STM32_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */
|
||||
#define STM32_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */
|
||||
#define STM32_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */
|
||||
#define STM32_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */
|
||||
#define STM32_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */
|
||||
#define STM32_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */
|
||||
#define STM32_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */
|
||||
#define STM32_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */
|
||||
#define STM32_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */
|
||||
#define STM32_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */
|
||||
#define STM32_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */
|
||||
#define STM32_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */
|
||||
#define STM32_OTGFS_CID_OFFSET 0x003c /* Core ID register */
|
||||
#define STM32_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */
|
||||
#define STM32_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */
|
||||
#define STM32_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */
|
||||
#define STM32_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */
|
||||
|
||||
#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2))
|
||||
#define STM32_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2))
|
||||
|
||||
/* Host-mode control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */
|
||||
#define STM32L4_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */
|
||||
#define STM32L4_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */
|
||||
#define STM32L4_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */
|
||||
#define STM32L4_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */
|
||||
#define STM32L4_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */
|
||||
#define STM32L4_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */
|
||||
#define STM32_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */
|
||||
#define STM32_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */
|
||||
#define STM32_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */
|
||||
#define STM32_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */
|
||||
#define STM32_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */
|
||||
#define STM32_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */
|
||||
#define STM32_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */
|
||||
|
||||
#define STM32L4_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5)
|
||||
#define STM32L4_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */
|
||||
#define STM32L4_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */
|
||||
#define STM32L4_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */
|
||||
#define STM32L4_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */
|
||||
#define STM32_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5)
|
||||
#define STM32_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */
|
||||
#define STM32_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */
|
||||
#define STM32_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */
|
||||
#define STM32_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */
|
||||
|
||||
#define STM32L4_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5))
|
||||
#define STM32_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5))
|
||||
#define STM32_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5))
|
||||
#define STM32_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5))
|
||||
#define STM32_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5))
|
||||
|
||||
/* Device-mode control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */
|
||||
#define STM32L4_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */
|
||||
#define STM32L4_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */
|
||||
#define STM32L4_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */
|
||||
#define STM32L4_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */
|
||||
#define STM32L4_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */
|
||||
#define STM32L4_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */
|
||||
#define STM32L4_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */
|
||||
#define STM32L4_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */
|
||||
#define STM32L4_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */
|
||||
#define STM32_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */
|
||||
#define STM32_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */
|
||||
#define STM32_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */
|
||||
#define STM32_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */
|
||||
#define STM32_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */
|
||||
#define STM32_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */
|
||||
#define STM32_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */
|
||||
#define STM32_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */
|
||||
#define STM32_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */
|
||||
#define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */
|
||||
|
||||
#define STM32L4_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5))
|
||||
#define STM32L4_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */
|
||||
#define STM32L4_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */
|
||||
#define STM32L4_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */
|
||||
#define STM32L4_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */
|
||||
#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5))
|
||||
#define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */
|
||||
#define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */
|
||||
#define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */
|
||||
#define STM32_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */
|
||||
|
||||
#define STM32L4_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5))
|
||||
#define STM32_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5))
|
||||
#define STM32_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5))
|
||||
#define STM32_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5))
|
||||
#define STM32_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5))
|
||||
#define STM32L4_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */
|
||||
#define STM32L4_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */
|
||||
#define STM32L4_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */
|
||||
#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5))
|
||||
#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */
|
||||
#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */
|
||||
#define STM32_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */
|
||||
|
||||
#define STM32L4_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5))
|
||||
#define STM32_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5))
|
||||
#define STM32_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5))
|
||||
#define STM32_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5))
|
||||
|
||||
/* Power and clock gating registers */
|
||||
|
||||
#define STM32L4_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */
|
||||
#define STM32_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */
|
||||
|
||||
/* Data FIFO (DFIFO) access registers */
|
||||
|
||||
#define STM32L4_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12))
|
||||
#define STM32L4_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12))
|
||||
#define STM32_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12))
|
||||
#define STM32_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12))
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_OTGFS_GOTGCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGCTL_OFFSET)
|
||||
#define STM32L4_OTGFS_GOTGINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGINT_OFFSET)
|
||||
#define STM32L4_OTGFS_GAHBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GAHBCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_GUSBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GUSBCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_GRSTCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRSTCTL_OFFSET)
|
||||
#define STM32L4_OTGFS_GINTSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTSTS_OFFSET)
|
||||
#define STM32L4_OTGFS_GINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_GRXSTSR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSR_OFFSET)
|
||||
#define STM32L4_OTGFS_GRXSTSP (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSP_OFFSET)
|
||||
#define STM32L4_OTGFS_GRXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXFSIZ_OFFSET)
|
||||
#define STM32L4_OTGFS_HNPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXFSIZ_OFFSET)
|
||||
#define STM32L4_OTGFS_DIEPTXF0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF0_OFFSET)
|
||||
#define STM32L4_OTGFS_HNPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXSTS_OFFSET)
|
||||
#define STM32L4_OTGFS_GCCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GCCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_CID (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CID_OFFSET)
|
||||
#define STM32L4_OTGFS_GLPMCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GLPMCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_GPWRDN (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GPWRDN_OFFSET)
|
||||
#define STM32L4_OTGFS_GADPCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GADPCTL_OFSSET)
|
||||
#define STM32L4_OTGFS_HPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXFSIZ_OFFSET)
|
||||
#define STM32_OTGFS_GOTGCTL (STM32_OTGFS_BASE+STM32_OTGFS_GOTGCTL_OFFSET)
|
||||
#define STM32_OTGFS_GOTGINT (STM32_OTGFS_BASE+STM32_OTGFS_GOTGINT_OFFSET)
|
||||
#define STM32_OTGFS_GAHBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GAHBCFG_OFFSET)
|
||||
#define STM32_OTGFS_GUSBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GUSBCFG_OFFSET)
|
||||
#define STM32_OTGFS_GRSTCTL (STM32_OTGFS_BASE+STM32_OTGFS_GRSTCTL_OFFSET)
|
||||
#define STM32_OTGFS_GINTSTS (STM32_OTGFS_BASE+STM32_OTGFS_GINTSTS_OFFSET)
|
||||
#define STM32_OTGFS_GINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_GINTMSK_OFFSET)
|
||||
#define STM32_OTGFS_GRXSTSR (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSR_OFFSET)
|
||||
#define STM32_OTGFS_GRXSTSP (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSP_OFFSET)
|
||||
#define STM32_OTGFS_GRXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_GRXFSIZ_OFFSET)
|
||||
#define STM32_OTGFS_HNPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXFSIZ_OFFSET)
|
||||
#define STM32_OTGFS_DIEPTXF0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF0_OFFSET)
|
||||
#define STM32_OTGFS_HNPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXSTS_OFFSET)
|
||||
#define STM32_OTGFS_GCCFG (STM32_OTGFS_BASE+STM32_OTGFS_GCCFG_OFFSET)
|
||||
#define STM32_OTGFS_CID (STM32_OTGFS_BASE+STM32_OTGFS_CID_OFFSET)
|
||||
#define STM32_OTGFS_GLPMCFG (STM32_OTGFS_BASE+STM32_OTGFS_GLPMCFG_OFFSET)
|
||||
#define STM32_OTGFS_GPWRDN (STM32_OTGFS_BASE+STM32_OTGFS_GPWRDN_OFFSET)
|
||||
#define STM32_OTGFS_GADPCTL (STM32_OTGFS_BASE+STM32_OTGFS_GADPCTL_OFSSET)
|
||||
#define STM32_OTGFS_HPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HPTXFSIZ_OFFSET)
|
||||
|
||||
#define STM32L4_OTGFS_DIEPTXF(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEPTXF(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF_OFFSET(n))
|
||||
|
||||
/* Host-mode control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_HCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_HFIR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFIR_OFFSET)
|
||||
#define STM32L4_OTGFS_HFNUM (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFNUM_OFFSET)
|
||||
#define STM32L4_OTGFS_HPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXSTS_OFFSET)
|
||||
#define STM32L4_OTGFS_HAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINT_OFFSET)
|
||||
#define STM32L4_OTGFS_HAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINTMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_HPRT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPRT_OFFSET)
|
||||
#define STM32_OTGFS_HCFG (STM32_OTGFS_BASE+STM32_OTGFS_HCFG_OFFSET)
|
||||
#define STM32_OTGFS_HFIR (STM32_OTGFS_BASE+STM32_OTGFS_HFIR_OFFSET)
|
||||
#define STM32_OTGFS_HFNUM (STM32_OTGFS_BASE+STM32_OTGFS_HFNUM_OFFSET)
|
||||
#define STM32_OTGFS_HPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HPTXSTS_OFFSET)
|
||||
#define STM32_OTGFS_HAINT (STM32_OTGFS_BASE+STM32_OTGFS_HAINT_OFFSET)
|
||||
#define STM32_OTGFS_HAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_HAINTMSK_OFFSET)
|
||||
#define STM32_OTGFS_HPRT (STM32_OTGFS_BASE+STM32_OTGFS_HPRT_OFFSET)
|
||||
|
||||
#define STM32L4_OTGFS_CHAN(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CHAN_OFFSET(n))
|
||||
#define STM32_OTGFS_CHAN(n) (STM32_OTGFS_BASE+STM32_OTGFS_CHAN_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_HCCHAR(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR_OFFSET(n))
|
||||
#define STM32_OTGFS_HCCHAR(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_HCINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT_OFFSET(n))
|
||||
#define STM32_OTGFS_HCINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINT_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_HCINTMSK(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK_OFFSET(n))
|
||||
#define STM32_OTGFS_HCINTMSK(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_HCTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ_OFFSET(n))
|
||||
#define STM32_OTGFS_HCTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ_OFFSET(n))
|
||||
|
||||
/* Device-mode control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_DCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_DCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCTL_OFFSET)
|
||||
#define STM32L4_OTGFS_DSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DSTS_OFFSET)
|
||||
#define STM32L4_OTGFS_DIEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_DOEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_DAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINT_OFFSET)
|
||||
#define STM32L4_OTGFS_DAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINTMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_DVBUSDIS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSDIS_OFFSET)
|
||||
#define STM32L4_OTGFS_DVBUSPULSE (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSPULSE_OFFSET)
|
||||
#define STM32L4_OTGFS_DIEPEMPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPEMPMSK_OFFSET)
|
||||
#define STM32_OTGFS_DCFG (STM32_OTGFS_BASE+STM32_OTGFS_DCFG_OFFSET)
|
||||
#define STM32_OTGFS_DCTL (STM32_OTGFS_BASE+STM32_OTGFS_DCTL_OFFSET)
|
||||
#define STM32_OTGFS_DSTS (STM32_OTGFS_BASE+STM32_OTGFS_DSTS_OFFSET)
|
||||
#define STM32_OTGFS_DIEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPMSK_OFFSET)
|
||||
#define STM32_OTGFS_DOEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DOEPMSK_OFFSET)
|
||||
#define STM32_OTGFS_DAINT (STM32_OTGFS_BASE+STM32_OTGFS_DAINT_OFFSET)
|
||||
#define STM32_OTGFS_DAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_DAINTMSK_OFFSET)
|
||||
#define STM32_OTGFS_DVBUSDIS (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSDIS_OFFSET)
|
||||
#define STM32_OTGFS_DVBUSPULSE (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSPULSE_OFFSET)
|
||||
#define STM32_OTGFS_DIEPEMPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPEMPMSK_OFFSET)
|
||||
|
||||
#define STM32L4_OTGFS_DIEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEP_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEP_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DTXFSTS(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS_OFFSET(n))
|
||||
#define STM32_OTGFS_DTXFSTS(n) (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DOEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEP_OFFSET(n))
|
||||
#define STM32_OTGFS_DOEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEP_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL_OFFSET(n))
|
||||
#define STM32_OTGFS_DOEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT_OFFSET(n))
|
||||
#define STM32_OTGFS_DOEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ_OFFSET(n))
|
||||
#define STM32_OTGFS_DOEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ_OFFSET(n))
|
||||
|
||||
/* Power and clock gating registers */
|
||||
|
||||
#define STM32L4_OTGFS_PCGCCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_PCGCCTL_OFFSET)
|
||||
#define STM32_OTGFS_PCGCCTL (STM32_OTGFS_BASE+STM32_OTGFS_PCGCCTL_OFFSET)
|
||||
|
||||
/* Data FIFO (DFIFO) access registers */
|
||||
|
||||
#define STM32L4_OTGFS_DFIFO_DEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP_OFFSET(n))
|
||||
#define STM32L4_OTGFS_DFIFO_HCH(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH_OFFSET(n))
|
||||
#define STM32_OTGFS_DFIFO_DEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP_OFFSET(n))
|
||||
#define STM32_OTGFS_DFIFO_HCH(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH_OFFSET(n))
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -37,73 +37,73 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
|
||||
#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */
|
||||
#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */
|
||||
#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */
|
||||
#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
|
||||
#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */
|
||||
#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */
|
||||
#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET)
|
||||
#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET)
|
||||
#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET)
|
||||
#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET)
|
||||
#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET)
|
||||
#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET)
|
||||
#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET)
|
||||
#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET)
|
||||
#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET)
|
||||
#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET)
|
||||
#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET)
|
||||
#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET)
|
||||
#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET)
|
||||
#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
|
||||
#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET)
|
||||
#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
|
||||
#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET)
|
||||
#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET)
|
||||
#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET)
|
||||
#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET)
|
||||
#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET)
|
||||
#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET)
|
||||
#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET)
|
||||
#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
|
||||
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
|
||||
#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET)
|
||||
#define STM32_RCC_CCIPR2 (STM32_RCC_BASE+STM32_RCC_CCIPR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -38,35 +38,35 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
|
||||
#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
|
||||
#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
#define STM32L4_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */
|
||||
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
#define STM32_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET)
|
||||
#define STM32L4_SYSCFG_SWPR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR2_OFFSET)
|
||||
#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET)
|
||||
#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -41,139 +41,139 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
|
||||
#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
|
||||
#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
|
||||
#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
|
||||
|
||||
#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n))
|
||||
#define STM32L4_DMACHAN1_OFFSET 0x0000
|
||||
#define STM32L4_DMACHAN2_OFFSET 0x0014
|
||||
#define STM32L4_DMACHAN3_OFFSET 0x0028
|
||||
#define STM32L4_DMACHAN4_OFFSET 0x003c
|
||||
#define STM32L4_DMACHAN5_OFFSET 0x0050
|
||||
#define STM32L4_DMACHAN6_OFFSET 0x0064
|
||||
#define STM32L4_DMACHAN7_OFFSET 0x0078
|
||||
#define STM32_DMACHAN_OFFSET(n) (0x0014*(n))
|
||||
#define STM32_DMACHAN1_OFFSET 0x0000
|
||||
#define STM32_DMACHAN2_OFFSET 0x0014
|
||||
#define STM32_DMACHAN3_OFFSET 0x0028
|
||||
#define STM32_DMACHAN4_OFFSET 0x003c
|
||||
#define STM32_DMACHAN5_OFFSET 0x0050
|
||||
#define STM32_DMACHAN6_OFFSET 0x0064
|
||||
#define STM32_DMACHAN7_OFFSET 0x0078
|
||||
|
||||
#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
|
||||
#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
|
||||
#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
|
||||
#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */
|
||||
#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
|
||||
#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
|
||||
#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
|
||||
#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */
|
||||
|
||||
#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
|
||||
#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
|
||||
#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
|
||||
#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
|
||||
#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
|
||||
#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
|
||||
#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
|
||||
#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
|
||||
#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
|
||||
#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
|
||||
#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
|
||||
#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
|
||||
#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
|
||||
#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
|
||||
#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
|
||||
|
||||
#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
|
||||
#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
|
||||
#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
|
||||
#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
|
||||
#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
|
||||
#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
|
||||
#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
|
||||
#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
|
||||
#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
|
||||
#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
|
||||
#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
|
||||
#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
|
||||
#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
|
||||
#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
|
||||
|
||||
#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
|
||||
#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
|
||||
#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
|
||||
#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
|
||||
#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
|
||||
#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
|
||||
#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
|
||||
#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
|
||||
|
||||
#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
|
||||
#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
|
||||
#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
|
||||
#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
|
||||
#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
|
||||
#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
|
||||
#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
|
||||
#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
|
||||
#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
|
||||
#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
|
||||
#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
|
||||
#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
|
||||
#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
|
||||
#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET)
|
||||
#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET)
|
||||
#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET)
|
||||
#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET)
|
||||
#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET)
|
||||
#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET)
|
||||
#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET)
|
||||
#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET)
|
||||
#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET)
|
||||
#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET)
|
||||
#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET)
|
||||
#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET)
|
||||
#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET)
|
||||
#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET)
|
||||
#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET)
|
||||
#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET)
|
||||
#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET)
|
||||
#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET)
|
||||
#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET)
|
||||
#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET)
|
||||
#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET)
|
||||
#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET)
|
||||
#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET)
|
||||
#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET)
|
||||
#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET)
|
||||
#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET)
|
||||
#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET)
|
||||
#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET)
|
||||
#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET)
|
||||
#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET)
|
||||
#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET)
|
||||
#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET)
|
||||
#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET)
|
||||
#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET)
|
||||
#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET)
|
||||
#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET)
|
||||
#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -39,64 +39,65 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX1 request line multiplexer channel x configuration register */
|
||||
#define STM32L4_DMAMUX_C0CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(0)
|
||||
#define STM32L4_DMAMUX_C1CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(1)
|
||||
#define STM32L4_DMAMUX_C2CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(2)
|
||||
#define STM32L4_DMAMUX_C3CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(3)
|
||||
#define STM32L4_DMAMUX_C4CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(4)
|
||||
#define STM32L4_DMAMUX_C5CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(5)
|
||||
#define STM32L4_DMAMUX_C6CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(6)
|
||||
#define STM32L4_DMAMUX_C7CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(7)
|
||||
#define STM32L4_DMAMUX_C8CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(8)
|
||||
#define STM32L4_DMAMUX_C9CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(9)
|
||||
#define STM32L4_DMAMUX_C10CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(10)
|
||||
#define STM32L4_DMAMUX_C11CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(11)
|
||||
#define STM32L4_DMAMUX_C12CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(12)
|
||||
#define STM32L4_DMAMUX_C13CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(13)
|
||||
/* 0x034-0x07C: Reserved */
|
||||
#define STM32L4_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */
|
||||
#define STM32L4_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */
|
||||
/* 0x088-0x0FC: Reserved */
|
||||
#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX1 request line multiplexer channel x configuration register */
|
||||
#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0)
|
||||
#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1)
|
||||
#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2)
|
||||
#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3)
|
||||
#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4)
|
||||
#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5)
|
||||
#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6)
|
||||
#define STM32_DMAMUX_C7CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(7)
|
||||
#define STM32_DMAMUX_C8CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(8)
|
||||
#define STM32_DMAMUX_C9CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(9)
|
||||
#define STM32_DMAMUX_C10CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(10)
|
||||
#define STM32_DMAMUX_C11CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(11)
|
||||
#define STM32_DMAMUX_C12CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(12)
|
||||
#define STM32_DMAMUX_C13CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(13)
|
||||
/* 0x034-0x07C: Reserved */
|
||||
|
||||
#define STM32L4_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX1 request generator channel x configuration register */
|
||||
#define STM32L4_DMAMUX_RG0CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(0)
|
||||
#define STM32L4_DMAMUX_RG1CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(1)
|
||||
#define STM32L4_DMAMUX_RG2CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(2)
|
||||
#define STM32L4_DMAMUX_RG3CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(3)
|
||||
#define STM32L4_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */
|
||||
#define STM32L4_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */
|
||||
/* 0x148-0x3FC: Reserved */
|
||||
#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */
|
||||
#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */
|
||||
/* 0x088-0x0FC: Reserved */
|
||||
|
||||
#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX1 request generator channel x configuration register */
|
||||
#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0)
|
||||
#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1)
|
||||
#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2)
|
||||
#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3)
|
||||
#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */
|
||||
#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */
|
||||
/* 0x148-0x3FC: Reserved */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_DMAMUX1_CXCR(x) (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_CXCR_OFFSET(x))
|
||||
#define STM32L4_DMAMUX1_C0CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C0CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C1CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C1CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C2CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C2CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C3CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C3CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C4CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C4CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C5CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C5CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C6CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C6CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C7CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C7CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C8CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C8CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C9CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C9CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C10CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C10CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C11CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C11CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C12CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C12CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C13CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C13CR_OFFSET)
|
||||
#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_CXCR_OFFSET(x))
|
||||
#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C0CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C1CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C2CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C3CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C4CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C5CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C6CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C7CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C7CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C8CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C8CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C9CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C9CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C10CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C10CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C11CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C11CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C12CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C12CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C13CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C13CR_OFFSET)
|
||||
|
||||
#define STM32L4_DMAMUX1_CSR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_CSR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_CFR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_CFR_OFFSET)
|
||||
#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CSR_OFFSET)
|
||||
#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CFR_OFFSET)
|
||||
|
||||
#define STM32L4_DMAMUX1_RGXCR(x) (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RGXCR_OFFSET(x))
|
||||
#define STM32L4_DMAMUX1_RG0CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG0CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_RG1CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG1CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_RG2CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG2CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_RG3CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG3CR_OFFSET)
|
||||
#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGXCR_OFFSET(x))
|
||||
#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG0CR_OFFSET)
|
||||
#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG1CR_OFFSET)
|
||||
#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG2CR_OFFSET)
|
||||
#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG3CR_OFFSET)
|
||||
|
||||
#define STM32L4_DMAMUX1_RGSR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RGSR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_RGCFR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RGCFR_OFFSET)
|
||||
#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGSR_OFFSET)
|
||||
#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGCFR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -38,23 +38,23 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32L4_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32L4_FIREWALL_CR_OFFSET 0x0020
|
||||
#define STM32_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32_FIREWALL_CR_OFFSET 0x0020
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET)
|
||||
#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET)
|
||||
#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET)
|
||||
#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET)
|
||||
#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET)
|
||||
#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET)
|
||||
#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET)
|
||||
#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -37,73 +37,73 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
|
||||
#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */
|
||||
#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */
|
||||
#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */
|
||||
#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
|
||||
#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */
|
||||
#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */
|
||||
#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET)
|
||||
#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET)
|
||||
#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET)
|
||||
#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET)
|
||||
#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET)
|
||||
#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET)
|
||||
#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET)
|
||||
#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET)
|
||||
#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET)
|
||||
#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET)
|
||||
#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET)
|
||||
#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET)
|
||||
#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET)
|
||||
#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
|
||||
#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET)
|
||||
#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
|
||||
#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET)
|
||||
#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET)
|
||||
#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET)
|
||||
#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET)
|
||||
#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET)
|
||||
#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET)
|
||||
#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET)
|
||||
#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
|
||||
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
|
||||
#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET)
|
||||
#define STM32_RCC_CCIPR2 (STM32_RCC_BASE+STM32_RCC_CCIPR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -38,35 +38,35 @@
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
|
||||
#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
|
||||
#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
#define STM32L4_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */
|
||||
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
#define STM32_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET)
|
||||
#define STM32L4_SYSCFG_SWPR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR2_OFFSET)
|
||||
#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET)
|
||||
#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
||||
@@ -176,10 +176,10 @@ static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain,
|
||||
|
||||
static const struct stm32_1wire_config_s stm32_1wire1_config =
|
||||
{
|
||||
.usartbase = STM32L4_USART1_BASE,
|
||||
.apbclock = STM32L4_PCLK2_FREQUENCY,
|
||||
.usartbase = STM32_USART1_BASE,
|
||||
.apbclock = STM32_PCLK2_FREQUENCY,
|
||||
.data_pin = PIN_OPENDRAIN(GPIO_USART1_TX),
|
||||
.irq = STM32L4_IRQ_USART1,
|
||||
.irq = STM32_IRQ_USART1,
|
||||
};
|
||||
|
||||
static struct stm32_1wire_priv_s stm32_1wire1_priv =
|
||||
@@ -200,10 +200,10 @@ static struct stm32_1wire_priv_s stm32_1wire1_priv =
|
||||
|
||||
static const struct stm32_1wire_config_s stm32_1wire2_config =
|
||||
{
|
||||
.usartbase = STM32L4_USART2_BASE,
|
||||
.apbclock = STM32L4_PCLK1_FREQUENCY,
|
||||
.usartbase = STM32_USART2_BASE,
|
||||
.apbclock = STM32_PCLK1_FREQUENCY,
|
||||
.data_pin = PIN_OPENDRAIN(GPIO_USART2_TX),
|
||||
.irq = STM32L4_IRQ_USART2,
|
||||
.irq = STM32_IRQ_USART2,
|
||||
};
|
||||
|
||||
static struct stm32_1wire_priv_s stm32_1wire2_priv =
|
||||
@@ -224,10 +224,10 @@ static struct stm32_1wire_priv_s stm32_1wire2_priv =
|
||||
|
||||
static const struct stm32_1wire_config_s stm32_1wire3_config =
|
||||
{
|
||||
.usartbase = STM32L4_USART3_BASE,
|
||||
.apbclock = STM32L4_PCLK1_FREQUENCY,
|
||||
.usartbase = STM32_USART3_BASE,
|
||||
.apbclock = STM32_PCLK1_FREQUENCY,
|
||||
.data_pin = PIN_OPENDRAIN(GPIO_USART3_TX),
|
||||
.irq = STM32L4_IRQ_USART3,
|
||||
.irq = STM32_IRQ_USART3,
|
||||
};
|
||||
|
||||
static struct stm32_1wire_priv_s stm32_1wire3_priv =
|
||||
@@ -248,10 +248,10 @@ static struct stm32_1wire_priv_s stm32_1wire3_priv =
|
||||
|
||||
static const struct stm32_1wire_config_s stm32_1wire4_config =
|
||||
{
|
||||
.usartbase = STM32L4_UART4_BASE,
|
||||
.apbclock = STM32L4_PCLK1_FREQUENCY,
|
||||
.usartbase = STM32_UART4_BASE,
|
||||
.apbclock = STM32_PCLK1_FREQUENCY,
|
||||
.data_pin = PIN_OPENDRAIN(GPIO_UART4_TX),
|
||||
.irq = STM32L4_IRQ_UART4,
|
||||
.irq = STM32_IRQ_UART4,
|
||||
};
|
||||
|
||||
static struct stm32_1wire_priv_s stm32_1wire4_priv =
|
||||
@@ -272,10 +272,10 @@ static struct stm32_1wire_priv_s stm32_1wire4_priv =
|
||||
|
||||
static const struct stm32_1wire_config_s stm32_1wire5_config =
|
||||
{
|
||||
.usartbase = STM32L4_UART5_BASE,
|
||||
.apbclock = STM32L4_PCLK1_FREQUENCY,
|
||||
.usartbase = STM32_UART5_BASE,
|
||||
.apbclock = STM32_PCLK1_FREQUENCY,
|
||||
.data_pin = PIN_OPENDRAIN(GPIO_UART5_TX),
|
||||
.irq = STM32L4_IRQ_UART5,
|
||||
.irq = STM32_IRQ_UART5,
|
||||
};
|
||||
|
||||
static struct stm32_1wire_priv_s stm32_1wire5_priv =
|
||||
@@ -338,7 +338,7 @@ static inline void stm32_1wire_out(struct stm32_1wire_priv_s *priv,
|
||||
|
||||
static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv)
|
||||
{
|
||||
return stm32_1wire_in(priv, STM32L4_USART_RDR_OFFSET) & 0xff;
|
||||
return stm32_1wire_in(priv, STM32_USART_RDR_OFFSET) & 0xff;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -351,7 +351,7 @@ static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv)
|
||||
|
||||
static void stm32_1wire_send(struct stm32_1wire_priv_s *priv, int ch)
|
||||
{
|
||||
stm32_1wire_out(priv, STM32L4_USART_TDR_OFFSET, (uint32_t)(ch & 0xff));
|
||||
stm32_1wire_out(priv, STM32_USART_TDR_OFFSET, (uint32_t)(ch & 0xff));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -377,13 +377,13 @@ static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv)
|
||||
* for baud changing.
|
||||
*/
|
||||
|
||||
cr1 = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET);
|
||||
cr1 = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET);
|
||||
|
||||
enabled = cr1 & USART_CR1_UE;
|
||||
if (enabled)
|
||||
{
|
||||
cr1 &= ~USART_CR1_UE;
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, cr1);
|
||||
stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1);
|
||||
}
|
||||
|
||||
/* In case of oversampling by 8, the equation is:
|
||||
@@ -428,12 +428,12 @@ static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv)
|
||||
cr1 |= USART_CR1_OVER8;
|
||||
}
|
||||
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, cr1);
|
||||
stm32_1wire_out(priv, STM32L4_USART_BRR_OFFSET, brr);
|
||||
stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1);
|
||||
stm32_1wire_out(priv, STM32_USART_BRR_OFFSET, brr);
|
||||
|
||||
if (enabled)
|
||||
{
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, cr1 | USART_CR1_UE);
|
||||
stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_UE);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -464,37 +464,37 @@ static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv,
|
||||
return;
|
||||
|
||||
#ifdef CONFIG_STM32L4_USART1_1WIREDRIVER
|
||||
case STM32L4_USART1_BASE:
|
||||
case STM32_USART1_BASE:
|
||||
rcc_en = RCC_APB2ENR_USART1EN;
|
||||
regaddr = STM32L4_RCC_APB2ENR;
|
||||
regaddr = STM32_RCC_APB2ENR;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_USART2_1WIREDRIVER
|
||||
case STM32L4_USART2_BASE:
|
||||
case STM32_USART2_BASE:
|
||||
rcc_en = RCC_APB1ENR1_USART2EN;
|
||||
regaddr = STM32L4_RCC_APB1ENR1;
|
||||
regaddr = STM32_RCC_APB1ENR1;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_USART3_1WIREDRIVER
|
||||
case STM32L4_USART3_BASE:
|
||||
case STM32_USART3_BASE:
|
||||
rcc_en = RCC_APB1ENR1_USART3EN;
|
||||
regaddr = STM32L4_RCC_APB1ENR1;
|
||||
regaddr = STM32_RCC_APB1ENR1;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_UART4_1WIREDRIVER
|
||||
case STM32L4_UART4_BASE:
|
||||
case STM32_UART4_BASE:
|
||||
rcc_en = RCC_APB1ENR1_UART4EN;
|
||||
regaddr = STM32L4_RCC_APB1ENR1;
|
||||
regaddr = STM32_RCC_APB1ENR1;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_UART5_1WIREDRIVER
|
||||
case STM32L4_UART5_BASE:
|
||||
case STM32_UART5_BASE:
|
||||
rcc_en = RCC_APB1ENR1_UART5EN;
|
||||
regaddr = STM32L4_RCC_APB1ENR1;
|
||||
regaddr = STM32_RCC_APB1ENR1;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
@@ -534,33 +534,33 @@ static int stm32_1wire_init(struct stm32_1wire_priv_s *priv)
|
||||
* Set LBDIE
|
||||
*/
|
||||
|
||||
regval = stm32_1wire_in(priv, STM32L4_USART_CR2_OFFSET);
|
||||
regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET);
|
||||
regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL |
|
||||
USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE);
|
||||
regval |= USART_CR2_LBDIE;
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR2_OFFSET, regval);
|
||||
stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval);
|
||||
|
||||
/* Configure CR1
|
||||
* Clear TE, REm, all interrupt enable bits, PCE, PS and M
|
||||
* Set RXNEIE
|
||||
*/
|
||||
|
||||
regval = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET);
|
||||
regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET);
|
||||
regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS |
|
||||
USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1);
|
||||
regval |= USART_CR1_RXNEIE;
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, regval);
|
||||
stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval);
|
||||
|
||||
/* Configure CR3
|
||||
* Clear CTSE, RTSE, and all interrupt enable bits
|
||||
* Set ONEBIT, HDSEL and EIE
|
||||
*/
|
||||
|
||||
regval = stm32_1wire_in(priv, STM32L4_USART_CR3_OFFSET);
|
||||
regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET);
|
||||
regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE |
|
||||
USART_CR3_EIE);
|
||||
regval |= (USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE);
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR3_OFFSET, regval);
|
||||
stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval);
|
||||
|
||||
/* Set baud rate */
|
||||
|
||||
@@ -569,9 +569,9 @@ static int stm32_1wire_init(struct stm32_1wire_priv_s *priv)
|
||||
|
||||
/* Enable Rx, Tx, and the USART */
|
||||
|
||||
regval = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET);
|
||||
regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET);
|
||||
regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, regval);
|
||||
stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval);
|
||||
|
||||
/* Configure pins for USART use */
|
||||
|
||||
@@ -608,21 +608,21 @@ static int stm32_1wire_deinit(struct stm32_1wire_priv_s *priv)
|
||||
|
||||
/* Disable RXNEIE, Rx, Tx, and the USART */
|
||||
|
||||
regval = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET);
|
||||
regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET);
|
||||
regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE);
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, regval);
|
||||
stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval);
|
||||
|
||||
/* Clear LBDIE */
|
||||
|
||||
regval = stm32_1wire_in(priv, STM32L4_USART_CR2_OFFSET);
|
||||
regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET);
|
||||
regval &= ~USART_CR2_LBDIE;
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR2_OFFSET, regval);
|
||||
stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval);
|
||||
|
||||
/* Clear ONEBIT, HDSEL and EIE */
|
||||
|
||||
regval = stm32_1wire_in(priv, STM32L4_USART_CR3_OFFSET);
|
||||
regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET);
|
||||
regval &= ~(USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE);
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR3_OFFSET, regval);
|
||||
stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval);
|
||||
|
||||
/* Disable USART APB1/2 clock */
|
||||
|
||||
@@ -765,7 +765,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg)
|
||||
|
||||
/* Get the masked USART status word. */
|
||||
|
||||
sr = stm32_1wire_in(priv, STM32L4_USART_ISR_OFFSET);
|
||||
sr = stm32_1wire_in(priv, STM32_USART_ISR_OFFSET);
|
||||
|
||||
/* Receive loop */
|
||||
|
||||
@@ -858,7 +858,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg)
|
||||
* interrupt clear register (ICR).
|
||||
*/
|
||||
|
||||
stm32_1wire_out(priv, STM32L4_USART_ICR_OFFSET,
|
||||
stm32_1wire_out(priv, STM32_USART_ICR_OFFSET,
|
||||
(USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF));
|
||||
|
||||
if (priv->msgs != NULL)
|
||||
@@ -873,7 +873,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg)
|
||||
|
||||
if ((sr & USART_ISR_LBDF) != 0)
|
||||
{
|
||||
stm32_1wire_out(priv, STM32L4_USART_ICR_OFFSET, USART_ICR_LBDCF);
|
||||
stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, USART_ICR_LBDCF);
|
||||
|
||||
if (priv->msgs != NULL)
|
||||
{
|
||||
|
||||
+119
-119
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user