mirror of
https://github.com/apache/nuttx.git
synced 2026-05-30 21:36:28 +08:00
functions and definitions renamed from lm_ to tiva_
This commit is contained in:
Gregory Nutt
@@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/include/tiva/chip.h
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*
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* Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* Jose Pablo Carballo <jcarballo@nx-engineering.com>
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*
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@@ -34,8 +34,8 @@
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_LM_CHIP_H
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#define __ARCH_ARM_INCLUDE_LM_CHIP_H
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#ifndef __ARCH_ARM_INCLUDE_TIVA_CHIP_H
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#define __ARCH_ARM_INCLUDE_TIVA_CHIP_H
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/************************************************************************************
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* Included Files
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@@ -50,94 +50,100 @@
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/* Get customizations for each supported chip (only the LM3S6918 and 65 right now) */
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#if defined(CONFIG_ARCH_CHIP_LM3S6918)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# define LM_NTIMERS 4 /* Four general purpose timers */
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# define LM_NWIDETIMERS 0 /* No general purpose wide timers */
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# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef LM_ETHTS /* No timestamp register */
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# define LM_NSSI 2 /* Two SSI modules */
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# define LM_NUARTS 2 /* Two UART modules */
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# define LM_NI2C 2 /* Two I2C modules */
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# define LM_NADC 1 /* One ADC module */
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# define LM_NPWM 0 /* No PWM generator modules */
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# define LM_NQEI 0 /* No quadrature encoders */
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# define LM_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */
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# define LM_NCANCONTROLLER 0 /* No CAN controllers */
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# undef TM4C /* Not TM4C family */
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# define TIVA_NTIMERS 4 /* Four general purpose timers */
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# define TIVA_NWIDETIMERS 0 /* No general purpose wide timers */
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# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef TIVA_ETHTS /* No timestamp register */
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# define TIVA_NSSI 2 /* Two SSI modules */
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# define TIVA_NUARTS 2 /* Two UART modules */
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# define TIVA_NI2C 2 /* Two I2C modules */
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# define TIVA_NADC 1 /* One ADC module */
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# define TIVA_NPWM 0 /* No PWM generator modules */
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# define TIVA_NQEI 0 /* No quadrature encoders */
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# define TIVA_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */
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# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
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#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# define LM_NTIMERS 3 /* Three general purpose timers */
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# define LM_NWIDETIMERS 0 /* No general purpose wide timers */
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# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef LM_ETHTS /* No timestamp register */
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# define LM_NSSI 1 /* One SSI module */
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# define LM_NUARTS 2 /* Two UART modules */
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# define LM_NI2C 1 /* Two I2C modules */
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# define LM_NADC 1 /* One ADC module */
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# define LM_NPWM 1 /* One PWM generator module */
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# define LM_NQEI 0 /* No quadrature encoders */
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# define LM_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
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# define LM_NCANCONTROLLER 0 /* No CAN controllers */
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# undef TM4C /* Not TM4C family */
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# define TIVA_NTIMERS 3 /* Three general purpose timers */
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# define TIVA_NWIDETIMERS 0 /* No general purpose wide timers */
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# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef TIVA_ETHTS /* No timestamp register */
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# define TIVA_NSSI 1 /* One SSI module */
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# define TIVA_NUARTS 2 /* Two UART modules */
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# define TIVA_NI2C 1 /* Two I2C modules */
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# define TIVA_NADC 1 /* One ADC module */
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# define TIVA_NPWM 1 /* One PWM generator module */
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# define TIVA_NQEI 0 /* No quadrature encoders */
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# define TIVA_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
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# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
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#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# define LM_NTIMERS 4 /* Four general purpose timers */
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# define LM_NWIDETIMERS 0 /* No general purpose wide timers */
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# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef LM_ETHTS /* No timestamp register */
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# define LM_NSSI 1 /* One SSI module */
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# define LM_NUARTS 3 /* Three UART modules */
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# define LM_NI2C 2 /* Two I2C modules */
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# define LM_NADC 1 /* One ADC module */
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# define LM_NPWM 3 /* Three PWM generator modules */
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# define LM_NQEI 2 /* Two quadrature encoders */
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# define LM_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
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# define LM_NCANCONTROLLER 0 /* No CAN controllers */
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# undef TM4C /* Not TM4C family */
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# define TIVA_NTIMERS 4 /* Four general purpose timers */
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# define TIVA_NWIDETIMERS 0 /* No general purpose wide timers */
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# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef TIVA_ETHTS /* No timestamp register */
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# define TIVA_NSSI 1 /* One SSI module */
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# define TIVA_NUARTS 3 /* Three UART modules */
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# define TIVA_NI2C 2 /* Two I2C modules */
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# define TIVA_NADC 1 /* One ADC module */
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# define TIVA_NPWM 3 /* Three PWM generator modules */
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# define TIVA_NQEI 2 /* Two quadrature encoders */
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# define TIVA_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
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# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
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#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# define LM_NTIMERS 4 /* Four general purpose timers */
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# define LM_NWIDETIMERS 0 /* No general purpose wide timers */
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# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef LM_ETHTS /* No timestamp register */
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# define LM_NSSI 2 /* Two SSI modules */
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# define LM_NUARTS 3 /* Three UART modules */
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# define LM_NI2C 2 /* Two I2C modules */
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# define LM_NADC 2 /* Two ADC module */
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# define LM_CAN 2 /* Two CAN module */
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# define LM_NPWM 4 /* Four PWM generator modules */
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# define LM_NQEI 2 /* Two quadrature encoders */
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# define LM_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
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# define LM_NCANCONTROLLER 0 /* No CAN controllers */
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# undef TM4C /* Not TM4C family */
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# define TIVA_NTIMERS 4 /* Four general purpose timers */
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# define TIVA_NWIDETIMERS 0 /* No general purpose wide timers */
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# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef TIVA_ETHTS /* No timestamp register */
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# define TIVA_NSSI 2 /* Two SSI modules */
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# define TIVA_NUARTS 3 /* Three UART modules */
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# define TIVA_NI2C 2 /* Two I2C modules */
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# define TIVA_NADC 2 /* Two ADC module */
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# define TIVA_CAN 2 /* Two CAN module */
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# define TIVA_NPWM 4 /* Four PWM generator modules */
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# define TIVA_NQEI 2 /* Two quadrature encoders */
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# define TIVA_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
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# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
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#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# define LM_NTIMERS 6 /* Four general purpose timers */
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# define LM_NWIDETIMERS 0 /* No general purpose wide timers */
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# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
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# define LM_NSSI 1 /* One SSI module */
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# define LM_NUARTS 3 /* Two UART modules */
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# define LM_NI2C 2 /* One I2C module */
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# define LM_NADC 1 /* One ADC module */
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# define LM_NPWM 3 /* Three PWM generator modules */
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# define LM_NQEI 2 /* Two quadrature encoders */
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# define LM_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */
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# define LM_NCANCONTROLLER 1 /* One CAN controller */
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# undef TM4C /* Not TM4C family */
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# define TIVA_NTIMERS 6 /* Four general purpose timers */
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# define TIVA_NWIDETIMERS 0 /* No general purpose wide timers */
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# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
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# define TIVA_NSSI 1 /* One SSI module */
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# define TIVA_NUARTS 3 /* Two UART modules */
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# define TIVA_NI2C 2 /* One I2C module */
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# define TIVA_NADC 1 /* One ADC module */
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# define TIVA_NPWM 3 /* Three PWM generator modules */
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# define TIVA_NQEI 2 /* Two quadrature encoders */
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# define TIVA_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */
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# define TIVA_NCANCONTROLLER 1 /* One CAN controller */
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#elif defined(CONFIG_ARCH_CHIP_LM4F120)
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# undef LM3S /* Not LM3S family */
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# define LM4F 1 /* LM4F family */
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# define LM_NTIMERS 6 /* Six general purpose timers */
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# define LM_NWIDETIMERS 6 /* Six general purpose wide timers */
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# define LM_NETHCONTROLLERS 0 /* No Ethernet controller */
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# define LM_NSSI 4 /* Four SSI module */
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# define LM_NUARTS 8 /* Eight UART modules */
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# define LM_NI2C 4 /* Four I2C modules */
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# define LM_NADC 2 /* Two ADC modules */
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# define LM_NPWM 0 /* No PWM generator modules */
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# define LM_NQEI 0 /* No quadrature encoders */
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# define LM_NPORTS 6 /* 6 Ports (GPIOA-F), 0-43 GPIOs */
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# define LM_NCANCONTROLLER 1 /* One CAN controller */
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# undef LM3S /* Not LM3S family */
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# define LM4F 1 /* LM4F family */
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# undef TM4C /* Not TM4C family */
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# define TIVA_NTIMERS 6 /* Six general purpose timers */
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# define TIVA_NWIDETIMERS 6 /* Six general purpose wide timers */
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# define TIVA_NETHCONTROLLERS 0 /* No Ethernet controller */
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# define TIVA_NSSI 4 /* Four SSI module */
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# define TIVA_NUARTS 8 /* Eight UART modules */
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# define TIVA_NI2C 4 /* Four I2C modules */
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# define TIVA_NADC 2 /* Two ADC modules */
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# define TIVA_NPWM 0 /* No PWM generator modules */
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# define TIVA_NQEI 0 /* No quadrature encoders */
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# define TIVA_NPORTS 6 /* 6 Ports (GPIOA-F), 0-43 GPIOs */
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# define TIVA_NCANCONTROLLER 1 /* One CAN controller */
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#else
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# error "Capabilities not specified for this Stellaris chip"
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#endif
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@@ -214,4 +220,4 @@
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* Public Function Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_LM_CHIP_H */
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#endif /* __ARCH_ARM_INCLUDE_TIVA_CHIP_H */
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+134
-134
@@ -33,8 +33,8 @@
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_LM_IRQ_H
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#define __ARCH_ARM_INCLUDE_LM_IRQ_H
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#ifndef __ARCH_ARM_INCLUDE_TIVA_IRQ_H
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#define __ARCH_ARM_INCLUDE_TIVA_IRQ_H
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/************************************************************************************
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* Included Files
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@@ -49,41 +49,41 @@
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************************************************************************************/
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/* Mark GPIO interrupts as disabled for non-existent GPIO ports. */
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#if LM_NPORTS < 1 && !defined(CONFIG_LM_DISABLE_GPIOA_IRQS)
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# define CONFIG_LM_DISABLE_GPIOA_IRQS
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#elif LM_NPORTS < 2 && !defined(CONFIG_LM_DISABLE_GPIOB_IRQS)
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# define CONFIG_LM_DISABLE_GPIOB_IRQS
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#elif LM_NPORTS < 3 && !defined(CONFIG_LM_DISABLE_GPIOC_IRQS)
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# define CONFIG_LM_DISABLE_GPIOC_IRQS
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#elif LM_NPORTS < 4 && !defined(CONFIG_LM_DISABLE_GPIOD_IRQS)
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# define CONFIG_LM_DISABLE_GPIOD_IRQS
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#elif LM_NPORTS < 5 && !defined(CONFIG_LM_DISABLE_GPIOE_IRQS)
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# define CONFIG_LM_DISABLE_GPIOE_IRQS
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#elif LM_NPORTS < 6 && !defined(CONFIG_LM_DISABLE_GPIOF_IRQS)
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# define CONFIG_LM_DISABLE_GPIOF_IRQS
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#elif LM_NPORTS < 7 && !defined(CONFIG_LM_DISABLE_GPIOG_IRQS)
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# define CONFIG_LM_DISABLE_GPIOG_IRQS
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#elif LM_NPORTS < 8 && !defined(CONFIG_LM_DISABLE_GPIOH_IRQS)
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# define CONFIG_LM_DISABLE_GPIOH_IRQS
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#elif LM_NPORTS < 9 && !defined(CONFIG_LM_DISABLE_GPIOJ_IRQS)
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# define CONFIG_LM_DISABLE_GPIOJ_IRQS
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#if TIVA_NPORTS < 1 && !defined(CONFIG_TIVA_DISABLE_GPIOA_IRQS)
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# define CONFIG_TIVA_DISABLE_GPIOA_IRQS
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#elif TIVA_NPORTS < 2 && !defined(CONFIG_TIVA_DISABLE_GPIOB_IRQS)
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# define CONFIG_TIVA_DISABLE_GPIOB_IRQS
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#elif TIVA_NPORTS < 3 && !defined(CONFIG_TIVA_DISABLE_GPIOC_IRQS)
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# define CONFIG_TIVA_DISABLE_GPIOC_IRQS
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#elif TIVA_NPORTS < 4 && !defined(CONFIG_TIVA_DISABLE_GPIOD_IRQS)
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# define CONFIG_TIVA_DISABLE_GPIOD_IRQS
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#elif TIVA_NPORTS < 5 && !defined(CONFIG_TIVA_DISABLE_GPIOE_IRQS)
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# define CONFIG_TIVA_DISABLE_GPIOE_IRQS
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#elif TIVA_NPORTS < 6 && !defined(CONFIG_TIVA_DISABLE_GPIOF_IRQS)
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# define CONFIG_TIVA_DISABLE_GPIOF_IRQS
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#elif TIVA_NPORTS < 7 && !defined(CONFIG_TIVA_DISABLE_GPIOG_IRQS)
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# define CONFIG_TIVA_DISABLE_GPIOG_IRQS
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#elif TIVA_NPORTS < 8 && !defined(CONFIG_TIVA_DISABLE_GPIOH_IRQS)
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# define CONFIG_TIVA_DISABLE_GPIOH_IRQS
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#elif TIVA_NPORTS < 9 && !defined(CONFIG_TIVA_DISABLE_GPIOJ_IRQS)
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# define CONFIG_TIVA_DISABLE_GPIOJ_IRQS
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#endif
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/* Processor Exceptions (vectors 0-15) */
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#define LM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define LM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define LM_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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#define LM_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
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#define LM_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
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#define LM_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
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#define LM_IRQ_SVCALL (11) /* Vector 11: SVC call */
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#define LM_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
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/* Vector 13: Reserved */
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#define LM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define LM_IRQ_SYSTICK (15) /* Vector 15: System tick */
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#define TIVA_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define TIVA_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define TIVA_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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#define TIVA_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
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#define TIVA_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
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#define TIVA_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
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#define TIVA_IRQ_SVCALL (11) /* Vector 11: SVC call */
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#define TIVA_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
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/* Vector 13: Reserved */
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#define TIVA_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define TIVA_IRQ_SYSTICK (15) /* Vector 15: System tick */
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#if defined(CONFIG_ARCH_CHIP_LM3S)
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# include <arch/tiva/lm3s_irq.h>
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@@ -97,133 +97,133 @@
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* be disabled in order to reduce the size of the implemenation.
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*/
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#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
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# define LM_IRQ_GPIOA_0 (NR_IRQS + 0)
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# define LM_IRQ_GPIOA_1 (NR_IRQS + 1)
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# define LM_IRQ_GPIOA_2 (NR_IRQS + 2)
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# define LM_IRQ_GPIOA_3 (NR_IRQS + 3)
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# define LM_IRQ_GPIOA_4 (NR_IRQS + 4)
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# define LM_IRQ_GPIOA_5 (NR_IRQS + 5)
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# define LM_IRQ_GPIOA_6 (NR_IRQS + 6)
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# define LM_IRQ_GPIOA_7 (NR_IRQS + 7)
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# define _NGPIOAIRQS (NR_IRQS + 8)
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#ifndef CONFIG_TIVA_DISABLE_GPIOA_IRQS
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# define TIVA_IRQ_GPIOA_0 (NR_IRQS + 0)
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# define TIVA_IRQ_GPIOA_1 (NR_IRQS + 1)
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# define TIVA_IRQ_GPIOA_2 (NR_IRQS + 2)
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# define TIVA_IRQ_GPIOA_3 (NR_IRQS + 3)
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# define TIVA_IRQ_GPIOA_4 (NR_IRQS + 4)
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# define TIVA_IRQ_GPIOA_5 (NR_IRQS + 5)
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# define TIVA_IRQ_GPIOA_6 (NR_IRQS + 6)
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# define TIVA_IRQ_GPIOA_7 (NR_IRQS + 7)
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# define _NGPIOAIRQS (NR_IRQS + 8)
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#else
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# define _NGPIOAIRQS NR_IRQS
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# define _NGPIOAIRQS NR_IRQS
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#endif
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#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
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# define LM_IRQ_GPIOB_0 (_NGPIOAIRQS + 0)
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# define LM_IRQ_GPIOB_1 (_NGPIOAIRQS + 1)
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# define LM_IRQ_GPIOB_2 (_NGPIOAIRQS + 2)
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# define LM_IRQ_GPIOB_3 (_NGPIOAIRQS + 3)
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# define LM_IRQ_GPIOB_4 (_NGPIOAIRQS + 4)
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# define LM_IRQ_GPIOB_5 (_NGPIOAIRQS + 5)
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# define LM_IRQ_GPIOB_6 (_NGPIOAIRQS + 6)
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# define LM_IRQ_GPIOB_7 (_NGPIOAIRQS + 7)
|
||||
# define _NGPIOBIRQS (_NGPIOAIRQS + 8)
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOB_IRQS
|
||||
# define TIVA_IRQ_GPIOB_0 (_NGPIOAIRQS + 0)
|
||||
# define TIVA_IRQ_GPIOB_1 (_NGPIOAIRQS + 1)
|
||||
# define TIVA_IRQ_GPIOB_2 (_NGPIOAIRQS + 2)
|
||||
# define TIVA_IRQ_GPIOB_3 (_NGPIOAIRQS + 3)
|
||||
# define TIVA_IRQ_GPIOB_4 (_NGPIOAIRQS + 4)
|
||||
# define TIVA_IRQ_GPIOB_5 (_NGPIOAIRQS + 5)
|
||||
# define TIVA_IRQ_GPIOB_6 (_NGPIOAIRQS + 6)
|
||||
# define TIVA_IRQ_GPIOB_7 (_NGPIOAIRQS + 7)
|
||||
# define _NGPIOBIRQS (_NGPIOAIRQS + 8)
|
||||
#else
|
||||
# define _NGPIOBIRQS _NGPIOAIRQS
|
||||
# define _NGPIOBIRQS _NGPIOAIRQS
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
|
||||
# define LM_IRQ_GPIOC_0 (_NGPIOBIRQS + 0)
|
||||
# define LM_IRQ_GPIOC_1 (_NGPIOBIRQS + 1)
|
||||
# define LM_IRQ_GPIOC_2 (_NGPIOBIRQS + 2)
|
||||
# define LM_IRQ_GPIOC_3 (_NGPIOBIRQS + 3)
|
||||
# define LM_IRQ_GPIOC_4 (_NGPIOBIRQS + 4)
|
||||
# define LM_IRQ_GPIOC_5 (_NGPIOBIRQS + 5)
|
||||
# define LM_IRQ_GPIOC_6 (_NGPIOBIRQS + 6)
|
||||
# define LM_IRQ_GPIOC_7 (_NGPIOBIRQS + 7)
|
||||
# define _NGPIOCIRQS (_NGPIOBIRQS + 8)
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOC_IRQS
|
||||
# define TIVA_IRQ_GPIOC_0 (_NGPIOBIRQS + 0)
|
||||
# define TIVA_IRQ_GPIOC_1 (_NGPIOBIRQS + 1)
|
||||
# define TIVA_IRQ_GPIOC_2 (_NGPIOBIRQS + 2)
|
||||
# define TIVA_IRQ_GPIOC_3 (_NGPIOBIRQS + 3)
|
||||
# define TIVA_IRQ_GPIOC_4 (_NGPIOBIRQS + 4)
|
||||
# define TIVA_IRQ_GPIOC_5 (_NGPIOBIRQS + 5)
|
||||
# define TIVA_IRQ_GPIOC_6 (_NGPIOBIRQS + 6)
|
||||
# define TIVA_IRQ_GPIOC_7 (_NGPIOBIRQS + 7)
|
||||
# define _NGPIOCIRQS (_NGPIOBIRQS + 8)
|
||||
#else
|
||||
# define _NGPIOCIRQS _NGPIOBIRQS
|
||||
# define _NGPIOCIRQS _NGPIOBIRQS
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
|
||||
# define LM_IRQ_GPIOD_0 (_NGPIOCIRQS + 0)
|
||||
# define LM_IRQ_GPIOD_1 (_NGPIOCIRQS + 1)
|
||||
# define LM_IRQ_GPIOD_2 (_NGPIOCIRQS + 2)
|
||||
# define LM_IRQ_GPIOD_3 (_NGPIOCIRQS + 3)
|
||||
# define LM_IRQ_GPIOD_4 (_NGPIOCIRQS + 4)
|
||||
# define LM_IRQ_GPIOD_5 (_NGPIOCIRQS + 5)
|
||||
# define LM_IRQ_GPIOD_6 (_NGPIOCIRQS + 6)
|
||||
# define LM_IRQ_GPIOD_7 (_NGPIOCIRQS + 7)
|
||||
# define _NGPIODIRQS (_NGPIOCIRQS + 8)
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOD_IRQS
|
||||
# define TIVA_IRQ_GPIOD_0 (_NGPIOCIRQS + 0)
|
||||
# define TIVA_IRQ_GPIOD_1 (_NGPIOCIRQS + 1)
|
||||
# define TIVA_IRQ_GPIOD_2 (_NGPIOCIRQS + 2)
|
||||
# define TIVA_IRQ_GPIOD_3 (_NGPIOCIRQS + 3)
|
||||
# define TIVA_IRQ_GPIOD_4 (_NGPIOCIRQS + 4)
|
||||
# define TIVA_IRQ_GPIOD_5 (_NGPIOCIRQS + 5)
|
||||
# define TIVA_IRQ_GPIOD_6 (_NGPIOCIRQS + 6)
|
||||
# define TIVA_IRQ_GPIOD_7 (_NGPIOCIRQS + 7)
|
||||
# define _NGPIODIRQS (_NGPIOCIRQS + 8)
|
||||
#else
|
||||
# define _NGPIODIRQS _NGPIOCIRQS
|
||||
# define _NGPIODIRQS _NGPIOCIRQS
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
|
||||
# define LM_IRQ_GPIOE_0 (_NGPIODIRQS + 0)
|
||||
# define LM_IRQ_GPIOE_1 (_NGPIODIRQS + 1)
|
||||
# define LM_IRQ_GPIOE_2 (_NGPIODIRQS + 2)
|
||||
# define LM_IRQ_GPIOE_3 (_NGPIODIRQS + 3)
|
||||
# define LM_IRQ_GPIOE_4 (_NGPIODIRQS + 4)
|
||||
# define LM_IRQ_GPIOE_5 (_NGPIODIRQS + 5)
|
||||
# define LM_IRQ_GPIOE_6 (_NGPIODIRQS + 6)
|
||||
# define LM_IRQ_GPIOE_7 (_NGPIODIRQS + 7)
|
||||
# define _NGPIOEIRQS (_NGPIODIRQS + 8)
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOE_IRQS
|
||||
# define TIVA_IRQ_GPIOE_0 (_NGPIODIRQS + 0)
|
||||
# define TIVA_IRQ_GPIOE_1 (_NGPIODIRQS + 1)
|
||||
# define TIVA_IRQ_GPIOE_2 (_NGPIODIRQS + 2)
|
||||
# define TIVA_IRQ_GPIOE_3 (_NGPIODIRQS + 3)
|
||||
# define TIVA_IRQ_GPIOE_4 (_NGPIODIRQS + 4)
|
||||
# define TIVA_IRQ_GPIOE_5 (_NGPIODIRQS + 5)
|
||||
# define TIVA_IRQ_GPIOE_6 (_NGPIODIRQS + 6)
|
||||
# define TIVA_IRQ_GPIOE_7 (_NGPIODIRQS + 7)
|
||||
# define _NGPIOEIRQS (_NGPIODIRQS + 8)
|
||||
#else
|
||||
# define _NGPIOEIRQS _NGPIODIRQS
|
||||
# define _NGPIOEIRQS _NGPIODIRQS
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
|
||||
# define LM_IRQ_GPIOF_0 (_NGPIOEIRQS + 0)
|
||||
# define LM_IRQ_GPIOF_1 (_NGPIOEIRQS + 1)
|
||||
# define LM_IRQ_GPIOF_2 (_NGPIOEIRQS + 2)
|
||||
# define LM_IRQ_GPIOF_3 (_NGPIOEIRQS + 3)
|
||||
# define LM_IRQ_GPIOF_4 (_NGPIOEIRQS + 4)
|
||||
# define LM_IRQ_GPIOF_5 (_NGPIOEIRQS + 5)
|
||||
# define LM_IRQ_GPIOF_6 (_NGPIOEIRQS + 6)
|
||||
# define LM_IRQ_GPIOF_7 (_NGPIOEIRQS + 7)
|
||||
# define _NGPIOFIRQS (_NGPIOEIRQS + 8)
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOF_IRQS
|
||||
# define TIVA_IRQ_GPIOF_0 (_NGPIOEIRQS + 0)
|
||||
# define TIVA_IRQ_GPIOF_1 (_NGPIOEIRQS + 1)
|
||||
# define TIVA_IRQ_GPIOF_2 (_NGPIOEIRQS + 2)
|
||||
# define TIVA_IRQ_GPIOF_3 (_NGPIOEIRQS + 3)
|
||||
# define TIVA_IRQ_GPIOF_4 (_NGPIOEIRQS + 4)
|
||||
# define TIVA_IRQ_GPIOF_5 (_NGPIOEIRQS + 5)
|
||||
# define TIVA_IRQ_GPIOF_6 (_NGPIOEIRQS + 6)
|
||||
# define TIVA_IRQ_GPIOF_7 (_NGPIOEIRQS + 7)
|
||||
# define _NGPIOFIRQS (_NGPIOEIRQS + 8)
|
||||
#else
|
||||
# define _NGPIOFIRQS _NGPIOEIRQS
|
||||
# define _NGPIOFIRQS _NGPIOEIRQS
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
|
||||
# define LM_IRQ_GPIOG_0 (_NGPIOFIRQS + 0)
|
||||
# define LM_IRQ_GPIOG_1 (_NGPIOFIRQS + 1)
|
||||
# define LM_IRQ_GPIOG_2 (_NGPIOFIRQS + 2)
|
||||
# define LM_IRQ_GPIOG_3 (_NGPIOFIRQS + 3)
|
||||
# define LM_IRQ_GPIOG_4 (_NGPIOFIRQS + 4)
|
||||
# define LM_IRQ_GPIOG_5 (_NGPIOFIRQS + 5)
|
||||
# define LM_IRQ_GPIOG_6 (_NGPIOFIRQS + 6)
|
||||
# define LM_IRQ_GPIOG_7 (_NGPIOFIRQS + 7)
|
||||
# define _NGPIOGIRQS (_NGPIOFIRQS + 8)
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOG_IRQS
|
||||
# define TIVA_IRQ_GPIOG_0 (_NGPIOFIRQS + 0)
|
||||
# define TIVA_IRQ_GPIOG_1 (_NGPIOFIRQS + 1)
|
||||
# define TIVA_IRQ_GPIOG_2 (_NGPIOFIRQS + 2)
|
||||
# define TIVA_IRQ_GPIOG_3 (_NGPIOFIRQS + 3)
|
||||
# define TIVA_IRQ_GPIOG_4 (_NGPIOFIRQS + 4)
|
||||
# define TIVA_IRQ_GPIOG_5 (_NGPIOFIRQS + 5)
|
||||
# define TIVA_IRQ_GPIOG_6 (_NGPIOFIRQS + 6)
|
||||
# define TIVA_IRQ_GPIOG_7 (_NGPIOFIRQS + 7)
|
||||
# define _NGPIOGIRQS (_NGPIOFIRQS + 8)
|
||||
#else
|
||||
# define _NGPIOGIRQS _NGPIOFIRQS
|
||||
# define _NGPIOGIRQS _NGPIOFIRQS
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
|
||||
# define LM_IRQ_GPIOH_0 (_NGPIOGIRQS + 0)
|
||||
# define LM_IRQ_GPIOH_1 (_NGPIOGIRQS + 1)
|
||||
# define LM_IRQ_GPIOH_2 (_NGPIOGIRQS + 2)
|
||||
# define LM_IRQ_GPIOH_3 (_NGPIOGIRQS + 3)
|
||||
# define LM_IRQ_GPIOH_4 (_NGPIOGIRQS + 4)
|
||||
# define LM_IRQ_GPIOH_5 (_NGPIOGIRQS + 5)
|
||||
# define LM_IRQ_GPIOH_6 (_NGPIOGIRQS + 6)
|
||||
# define LM_IRQ_GPIOH_7 (_NGPIOGIRQS + 7)
|
||||
# define _NGPIOHIRQS (_NGPIOGIRQS + 8)
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOH_IRQS
|
||||
# define TIVA_IRQ_GPIOH_0 (_NGPIOGIRQS + 0)
|
||||
# define TIVA_IRQ_GPIOH_1 (_NGPIOGIRQS + 1)
|
||||
# define TIVA_IRQ_GPIOH_2 (_NGPIOGIRQS + 2)
|
||||
# define TIVA_IRQ_GPIOH_3 (_NGPIOGIRQS + 3)
|
||||
# define TIVA_IRQ_GPIOH_4 (_NGPIOGIRQS + 4)
|
||||
# define TIVA_IRQ_GPIOH_5 (_NGPIOGIRQS + 5)
|
||||
# define TIVA_IRQ_GPIOH_6 (_NGPIOGIRQS + 6)
|
||||
# define TIVA_IRQ_GPIOH_7 (_NGPIOGIRQS + 7)
|
||||
# define _NGPIOHIRQS (_NGPIOGIRQS + 8)
|
||||
#else
|
||||
# define _NGPIOHIRQS _NGPIOGIRQS
|
||||
# define _NGPIOHIRQS _NGPIOGIRQS
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
|
||||
# define LM_IRQ_GPIOJ_0 (_NGPIOHIRQS + 0)
|
||||
# define LM_IRQ_GPIOJ_1 (_NGPIOHIRQS + 1)
|
||||
# define LM_IRQ_GPIOJ_2 (_NGPIOHIRQS + 2)
|
||||
# define LM_IRQ_GPIOJ_3 (_NGPIOHIRQS + 3)
|
||||
# define LM_IRQ_GPIOJ_4 (_NGPIOHIRQS + 4)
|
||||
# define LM_IRQ_GPIOJ_5 (_NGPIOHIRQS + 5)
|
||||
# define LM_IRQ_GPIOJ_6 (_NGPIOHIRQS + 6)
|
||||
# define LM_IRQ_GPIOJ_7 (_NGPIOHIRQS + 7)
|
||||
# define _NGPIOJIRQS (_NGPIOHIRQS + 8)
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOJ_IRQS
|
||||
# define TIVA_IRQ_GPIOJ_0 (_NGPIOHIRQS + 0)
|
||||
# define TIVA_IRQ_GPIOJ_1 (_NGPIOHIRQS + 1)
|
||||
# define TIVA_IRQ_GPIOJ_2 (_NGPIOHIRQS + 2)
|
||||
# define TIVA_IRQ_GPIOJ_3 (_NGPIOHIRQS + 3)
|
||||
# define TIVA_IRQ_GPIOJ_4 (_NGPIOHIRQS + 4)
|
||||
# define TIVA_IRQ_GPIOJ_5 (_NGPIOHIRQS + 5)
|
||||
# define TIVA_IRQ_GPIOJ_6 (_NGPIOHIRQS + 6)
|
||||
# define TIVA_IRQ_GPIOJ_7 (_NGPIOHIRQS + 7)
|
||||
# define _NGPIOJIRQS (_NGPIOHIRQS + 8)
|
||||
#else
|
||||
# define _NGPIOJIRQS _NGPIOHIRQS
|
||||
# define _NGPIOJIRQS _NGPIOHIRQS
|
||||
#endif
|
||||
|
||||
#define NR_GPIO_IRQS (_NGPIOJIRQS - NR_IRQS)
|
||||
#define NR_GPIO_IRQS (_NGPIOJIRQS - NR_IRQS)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
@@ -279,4 +279,4 @@ void gpio_irqdisable(int irq);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_LM_IRQ_H */
|
||||
#endif /* __ARCH_ARM_INCLUDE_TIVA_IRQ_H */
|
||||
|
||||
+290
-291
File diff suppressed because it is too large
Load Diff
+145
-145
@@ -33,8 +33,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_LM_LM4F_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_LM_LM4F_IRQ_H
|
||||
#ifndef __ARCH_ARM_INCLUDE_TIVA_LM4F_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_TIVA_LM4F_IRQ_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@@ -53,166 +53,166 @@
|
||||
|
||||
/* External interrupts (vectors >= 16) */
|
||||
|
||||
#define LM_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
|
||||
#define TIVA_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_LM4F120)
|
||||
|
||||
# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
|
||||
# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
|
||||
# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
|
||||
# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
|
||||
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
|
||||
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
|
||||
# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
|
||||
# define TIVA_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
|
||||
|
||||
# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
|
||||
# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */
|
||||
# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */
|
||||
# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
|
||||
# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
|
||||
# define LM_RESERVED_25 (25) /* Vector 25: Reserved */
|
||||
# define LM_RESERVED_26 (26) /* Vector 26: Reserved */
|
||||
# define LM_RESERVED_27 (27) /* Vector 27: Reserved */
|
||||
# define LM_RESERVED_28 (28) /* Vector 28: Reserved */
|
||||
# define LM_RESERVED_29 (29) /* Vector 29: Reserved */
|
||||
# define TIVA_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
|
||||
# define TIVA_IRQ_UART0 (21) /* Vector 21: UART 0 */
|
||||
# define TIVA_IRQ_UART1 (22) /* Vector 22: UART 1 */
|
||||
# define TIVA_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
|
||||
# define TIVA_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
|
||||
# define TIVA_RESERVED_25 (25) /* Vector 25: Reserved */
|
||||
# define TIVA_RESERVED_26 (26) /* Vector 26: Reserved */
|
||||
# define TIVA_RESERVED_27 (27) /* Vector 27: Reserved */
|
||||
# define TIVA_RESERVED_28 (28) /* Vector 28: Reserved */
|
||||
# define TIVA_RESERVED_29 (29) /* Vector 29: Reserved */
|
||||
|
||||
# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
|
||||
# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
|
||||
# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
|
||||
# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
|
||||
# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timers 0 and 1 */
|
||||
# define LM_IRQ_TIMER0A (35) /* Vector 35: 16/32-Bit Timer 0 A */
|
||||
# define LM_IRQ_TIMER0B (36) /* Vector 36: 16/32-Bit Timer 0 B */
|
||||
# define LM_IRQ_TIMER1A (37) /* Vector 37: 16/32-Bit Timer 1 A */
|
||||
# define LM_IRQ_TIMER1B (38) /* Vector 38: 16/32-Bit Timer 1 B */
|
||||
# define LM_IRQ_TIMER2A (39) /* Vector 39: 16/32-Bit Timer 2 A */
|
||||
# define TIVA_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
|
||||
# define TIVA_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
|
||||
# define TIVA_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
|
||||
# define TIVA_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
|
||||
# define TIVA_IRQ_WDOG (34) /* Vector 34: Watchdog Timers 0 and 1 */
|
||||
# define TIVA_IRQ_TIMER0A (35) /* Vector 35: 16/32-Bit Timer 0 A */
|
||||
# define TIVA_IRQ_TIMER0B (36) /* Vector 36: 16/32-Bit Timer 0 B */
|
||||
# define TIVA_IRQ_TIMER1A (37) /* Vector 37: 16/32-Bit Timer 1 A */
|
||||
# define TIVA_IRQ_TIMER1B (38) /* Vector 38: 16/32-Bit Timer 1 B */
|
||||
# define TIVA_IRQ_TIMER2A (39) /* Vector 39: 16/32-Bit Timer 2 A */
|
||||
|
||||
# define LM_IRQ_TIMER2B (40) /* Vector 40: 16/32-Bit Timer 2 B */
|
||||
# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
|
||||
# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
|
||||
# define LM_RESERVED_43 (43) /* Vector 43: Reserved */
|
||||
# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */
|
||||
# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH and EEPROM Control */
|
||||
# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
|
||||
# define LM_RESERVED_47 (47) /* Vector 47: Reserved */
|
||||
# define LM_RESERVED_48 (48) /* Vector 48: Reserved */
|
||||
# define LM_IRQ_UART2 (49) /* Vector 22: UART 2 */
|
||||
# define TIVA_IRQ_TIMER2B (40) /* Vector 40: 16/32-Bit Timer 2 B */
|
||||
# define TIVA_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
|
||||
# define TIVA_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
|
||||
# define TIVA_RESERVED_43 (43) /* Vector 43: Reserved */
|
||||
# define TIVA_IRQ_SYSCON (44) /* Vector 44: System Control */
|
||||
# define TIVA_IRQ_FLASHCON (45) /* Vector 45: FLASH and EEPROM Control */
|
||||
# define TIVA_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
|
||||
# define TIVA_RESERVED_47 (47) /* Vector 47: Reserved */
|
||||
# define TIVA_RESERVED_48 (48) /* Vector 48: Reserved */
|
||||
# define TIVA_IRQ_UART2 (49) /* Vector 22: UART 2 */
|
||||
|
||||
# define LM_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
|
||||
# define LM_IRQ_TIMER3A (51) /* Vector 51: 16/32-Bit Timer 3 A */
|
||||
# define LM_IRQ_TIMER3B (52) /* Vector 52: 16/32-Bit Timer 3 B */
|
||||
# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
|
||||
# define LM_RESERVED_54 (54) /* Vector 54: Reserved */
|
||||
# define LM_IRQ_CAN0 (55) /* Vector 55: CAN 0 */
|
||||
# define LM_RESERVED_56 (56) /* Vector 56: Reserved */
|
||||
# define LM_RESERVED_57 (57) /* Vector 57: Reserved */
|
||||
# define LM_RESERVED_58 (58) /* Vector 58: Reserved */
|
||||
# define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
|
||||
# define TIVA_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
|
||||
# define TIVA_IRQ_TIMER3A (51) /* Vector 51: 16/32-Bit Timer 3 A */
|
||||
# define TIVA_IRQ_TIMER3B (52) /* Vector 52: 16/32-Bit Timer 3 B */
|
||||
# define TIVA_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
|
||||
# define TIVA_RESERVED_54 (54) /* Vector 54: Reserved */
|
||||
# define TIVA_IRQ_CAN0 (55) /* Vector 55: CAN 0 */
|
||||
# define TIVA_RESERVED_56 (56) /* Vector 56: Reserved */
|
||||
# define TIVA_RESERVED_57 (57) /* Vector 57: Reserved */
|
||||
# define TIVA_RESERVED_58 (58) /* Vector 58: Reserved */
|
||||
# define TIVA_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
|
||||
|
||||
# define LM_IRQ_USB (60) /* Vector 60: USB */
|
||||
# define LM_RESERVED_61 (61) /* Vector 61: Reserved */
|
||||
# define LM_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */
|
||||
# define LM_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
|
||||
# define LM_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */
|
||||
# define LM_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */
|
||||
# define LM_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */
|
||||
# define LM_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */
|
||||
# define LM_RESERVED_68 (68) /* Vector 68: Reserved */
|
||||
# define LM_RESERVED_69 (69) /* Vector 69: Reserved */
|
||||
# define TIVA_IRQ_USB (60) /* Vector 60: USB */
|
||||
# define TIVA_RESERVED_61 (61) /* Vector 61: Reserved */
|
||||
# define TIVA_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */
|
||||
# define TIVA_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
|
||||
# define TIVA_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */
|
||||
# define TIVA_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */
|
||||
# define TIVA_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */
|
||||
# define TIVA_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */
|
||||
# define TIVA_RESERVED_68 (68) /* Vector 68: Reserved */
|
||||
# define TIVA_RESERVED_69 (69) /* Vector 69: Reserved */
|
||||
|
||||
# define LM_RESERVED_70 (70) /* Vector 70: Reserved */
|
||||
# define LM_RESERVED_71 (71) /* Vector 71: Reserved */
|
||||
# define LM_RESERVED_72 (72) /* Vector 72: Reserved */
|
||||
# define LM_IRQ_SSI2 (73) /* Vector 73: SSI 2 */
|
||||
# define LM_IRQ_SSI3 (74) /* Vector 74: SSI 3 */
|
||||
# define LM_IRQ_UART3 (75) /* Vector 75: UART 3 */
|
||||
# define LM_IRQ_UART4 (76) /* Vector 76: UART 4 */
|
||||
# define LM_IRQ_UART5 (77) /* Vector 77: UART 5 */
|
||||
# define LM_IRQ_UART6 (78) /* Vector 78: UART 6 */
|
||||
# define LM_IRQ_UART7 (79) /* Vector 79: UART 7 */
|
||||
# define TIVA_RESERVED_70 (70) /* Vector 70: Reserved */
|
||||
# define TIVA_RESERVED_71 (71) /* Vector 71: Reserved */
|
||||
# define TIVA_RESERVED_72 (72) /* Vector 72: Reserved */
|
||||
# define TIVA_IRQ_SSI2 (73) /* Vector 73: SSI 2 */
|
||||
# define TIVA_IRQ_SSI3 (74) /* Vector 74: SSI 3 */
|
||||
# define TIVA_IRQ_UART3 (75) /* Vector 75: UART 3 */
|
||||
# define TIVA_IRQ_UART4 (76) /* Vector 76: UART 4 */
|
||||
# define TIVA_IRQ_UART5 (77) /* Vector 77: UART 5 */
|
||||
# define TIVA_IRQ_UART6 (78) /* Vector 78: UART 6 */
|
||||
# define TIVA_IRQ_UART7 (79) /* Vector 79: UART 7 */
|
||||
|
||||
# define LM_RESERVED_80 (80) /* Vector 80: Reserved */
|
||||
# define LM_RESERVED_81 (81) /* Vector 81: Reserved */
|
||||
# define LM_RESERVED_82 (82) /* Vector 82: Reserved */
|
||||
# define LM_RESERVED_83 (83) /* Vector 83: Reserved */
|
||||
# define LM_IRQ_I2C2 (84) /* Vector 84: I2C 2 */
|
||||
# define LM_IRQ_I2C3 (85) /* Vector 85: I2C 3 */
|
||||
# define LM_IRQ_TIMER4A (86) /* Vector 86: 16/32-Bit Timer 4 A */
|
||||
# define LM_IRQ_TIMER4B (87) /* Vector 87: 16/32-Bit Timer 4 B */
|
||||
# define LM_RESERVED_88 (88) /* Vector 88: Reserved */
|
||||
# define LM_RESERVED_89 (89) /* Vector 89: Reserved */
|
||||
# define TIVA_RESERVED_80 (80) /* Vector 80: Reserved */
|
||||
# define TIVA_RESERVED_81 (81) /* Vector 81: Reserved */
|
||||
# define TIVA_RESERVED_82 (82) /* Vector 82: Reserved */
|
||||
# define TIVA_RESERVED_83 (83) /* Vector 83: Reserved */
|
||||
# define TIVA_IRQ_I2C2 (84) /* Vector 84: I2C 2 */
|
||||
# define TIVA_IRQ_I2C3 (85) /* Vector 85: I2C 3 */
|
||||
# define TIVA_IRQ_TIMER4A (86) /* Vector 86: 16/32-Bit Timer 4 A */
|
||||
# define TIVA_IRQ_TIMER4B (87) /* Vector 87: 16/32-Bit Timer 4 B */
|
||||
# define TIVA_RESERVED_88 (88) /* Vector 88: Reserved */
|
||||
# define TIVA_RESERVED_89 (89) /* Vector 89: Reserved */
|
||||
|
||||
# define LM_RESERVED_90 (90) /* Vector 90: Reserved */
|
||||
# define LM_RESERVED_91 (91) /* Vector 91: Reserved */
|
||||
# define LM_RESERVED_92 (92) /* Vector 92: Reserved */
|
||||
# define LM_RESERVED_93 (93) /* Vector 93: Reserved */
|
||||
# define LM_RESERVED_94 (94) /* Vector 94: Reserved */
|
||||
# define LM_RESERVED_95 (95) /* Vector 95: Reserved */
|
||||
# define LM_RESERVED_96 (96) /* Vector 96: Reserved */
|
||||
# define LM_RESERVED_97 (97) /* Vector 97: Reserved */
|
||||
# define LM_RESERVED_98 (98) /* Vector 98: Reserved */
|
||||
# define LM_RESERVED_99 (99) /* Vector 99: Reserved */
|
||||
# define TIVA_RESERVED_90 (90) /* Vector 90: Reserved */
|
||||
# define TIVA_RESERVED_91 (91) /* Vector 91: Reserved */
|
||||
# define TIVA_RESERVED_92 (92) /* Vector 92: Reserved */
|
||||
# define TIVA_RESERVED_93 (93) /* Vector 93: Reserved */
|
||||
# define TIVA_RESERVED_94 (94) /* Vector 94: Reserved */
|
||||
# define TIVA_RESERVED_95 (95) /* Vector 95: Reserved */
|
||||
# define TIVA_RESERVED_96 (96) /* Vector 96: Reserved */
|
||||
# define TIVA_RESERVED_97 (97) /* Vector 97: Reserved */
|
||||
# define TIVA_RESERVED_98 (98) /* Vector 98: Reserved */
|
||||
# define TIVA_RESERVED_99 (99) /* Vector 99: Reserved */
|
||||
|
||||
# define LM_RESERVED_100 (100) /* Vector 100: Reserved */
|
||||
# define LM_RESERVED_101 (101) /* Vector 101: Reserved */
|
||||
# define LM_RESERVED_102 (102) /* Vector 102: Reserved */
|
||||
# define LM_RESERVED_103 (103) /* Vector 103: Reserved */
|
||||
# define LM_RESERVED_104 (104) /* Vector 104: Reserved */
|
||||
# define LM_RESERVED_105 (105) /* Vector 105: Reserved */
|
||||
# define LM_RESERVED_106 (106) /* Vector 106: Reserved */
|
||||
# define LM_RESERVED_107 (107) /* Vector 107: Reserved */
|
||||
# define LM_IRQ_TIMER5A (108) /* Vector 108: 16/32-Bit Timer 5 A */
|
||||
# define LM_IRQ_TIMER5B (109) /* Vector 109: 16/32-Bit Timer 5 B */
|
||||
# define TIVA_RESERVED_100 (100) /* Vector 100: Reserved */
|
||||
# define TIVA_RESERVED_101 (101) /* Vector 101: Reserved */
|
||||
# define TIVA_RESERVED_102 (102) /* Vector 102: Reserved */
|
||||
# define TIVA_RESERVED_103 (103) /* Vector 103: Reserved */
|
||||
# define TIVA_RESERVED_104 (104) /* Vector 104: Reserved */
|
||||
# define TIVA_RESERVED_105 (105) /* Vector 105: Reserved */
|
||||
# define TIVA_RESERVED_106 (106) /* Vector 106: Reserved */
|
||||
# define TIVA_RESERVED_107 (107) /* Vector 107: Reserved */
|
||||
# define TIVA_IRQ_TIMER5A (108) /* Vector 108: 16/32-Bit Timer 5 A */
|
||||
# define TIVA_IRQ_TIMER5B (109) /* Vector 109: 16/32-Bit Timer 5 B */
|
||||
|
||||
# define LM_IRQ_WTIMER0A (110) /* Vector 110: 32/64-Bit Timer 0 A */
|
||||
# define LM_IRQ_WTIMER0B (111) /* Vector 111: 32/64-Bit Timer 0 B */
|
||||
# define LM_IRQ_WTIMER1A (112) /* Vector 112: 32/64-Bit Timer 1 A */
|
||||
# define LM_IRQ_WTIMER1B (113) /* Vector 113: 32/64-Bit Timer 1 B */
|
||||
# define LM_IRQ_WTIMER2A (114) /* Vector 114: 32/64-Bit Timer 2 A */
|
||||
# define LM_IRQ_WTIMER2B (115) /* Vector 115: 32/64-Bit Timer 2 B */
|
||||
# define LM_IRQ_WTIMER3A (116) /* Vector 116: 32/64-Bit Timer 3 A */
|
||||
# define LM_IRQ_WTIMER3B (117) /* Vector 117: 32/64-Bit Timer 3 B */
|
||||
# define LM_IRQ_WTIMER4A (118) /* Vector 118: 32/64-Bit Timer 4 A */
|
||||
# define LM_IRQ_WTIMER4B (119) /* Vector 119: 32/64-Bit Timer 4 B */
|
||||
# define TIVA_IRQ_WTIMER0A (110) /* Vector 110: 32/64-Bit Timer 0 A */
|
||||
# define TIVA_IRQ_WTIMER0B (111) /* Vector 111: 32/64-Bit Timer 0 B */
|
||||
# define TIVA_IRQ_WTIMER1A (112) /* Vector 112: 32/64-Bit Timer 1 A */
|
||||
# define TIVA_IRQ_WTIMER1B (113) /* Vector 113: 32/64-Bit Timer 1 B */
|
||||
# define TIVA_IRQ_WTIMER2A (114) /* Vector 114: 32/64-Bit Timer 2 A */
|
||||
# define TIVA_IRQ_WTIMER2B (115) /* Vector 115: 32/64-Bit Timer 2 B */
|
||||
# define TIVA_IRQ_WTIMER3A (116) /* Vector 116: 32/64-Bit Timer 3 A */
|
||||
# define TIVA_IRQ_WTIMER3B (117) /* Vector 117: 32/64-Bit Timer 3 B */
|
||||
# define TIVA_IRQ_WTIMER4A (118) /* Vector 118: 32/64-Bit Timer 4 A */
|
||||
# define TIVA_IRQ_WTIMER4B (119) /* Vector 119: 32/64-Bit Timer 4 B */
|
||||
|
||||
# define LM_IRQ_WTIMER5A (120) /* Vector 120: 32/64-Bit Timer 5 A */
|
||||
# define LM_IRQ_WTIMER5B (121) /* Vector 121: 32/64-Bit Timer 5 B */
|
||||
# define LM_IRQ_SYSTEM (122) /* Vector 122: System Exception (imprecise) */
|
||||
# define LM_RESERVED_123 (123) /* Vector 123: Reserved */
|
||||
# define LM_RESERVED_124 (124) /* Vector 124: Reserved */
|
||||
# define LM_RESERVED_125 (125) /* Vector 125: Reserved */
|
||||
# define LM_RESERVED_126 (126) /* Vector 126: Reserved */
|
||||
# define LM_RESERVED_127 (127) /* Vector 127: Reserved */
|
||||
# define LM_RESERVED_128 (128) /* Vector 128: Reserved */
|
||||
# define LM_RESERVED_129 (129) /* Vector 129: Reserved */
|
||||
# define TIVA_IRQ_WTIMER5A (120) /* Vector 120: 32/64-Bit Timer 5 A */
|
||||
# define TIVA_IRQ_WTIMER5B (121) /* Vector 121: 32/64-Bit Timer 5 B */
|
||||
# define TIVA_IRQ_SYSTEM (122) /* Vector 122: System Exception (imprecise) */
|
||||
# define TIVA_RESERVED_123 (123) /* Vector 123: Reserved */
|
||||
# define TIVA_RESERVED_124 (124) /* Vector 124: Reserved */
|
||||
# define TIVA_RESERVED_125 (125) /* Vector 125: Reserved */
|
||||
# define TIVA_RESERVED_126 (126) /* Vector 126: Reserved */
|
||||
# define TIVA_RESERVED_127 (127) /* Vector 127: Reserved */
|
||||
# define TIVA_RESERVED_128 (128) /* Vector 128: Reserved */
|
||||
# define TIVA_RESERVED_129 (129) /* Vector 129: Reserved */
|
||||
|
||||
# define LM_RESERVED_130 (130) /* Vector 130: Reserved */
|
||||
# define LM_RESERVED_131 (131) /* Vector 131: Reserved */
|
||||
# define LM_RESERVED_132 (132) /* Vector 132: Reserved */
|
||||
# define LM_RESERVED_133 (133) /* Vector 133: Reserved */
|
||||
# define LM_RESERVED_134 (134) /* Vector 134: Reserved */
|
||||
# define LM_RESERVED_135 (135) /* Vector 135: Reserved */
|
||||
# define LM_RESERVED_136 (136) /* Vector 136: Reserved */
|
||||
# define LM_RESERVED_137 (137) /* Vector 137: Reserved */
|
||||
# define LM_RESERVED_138 (138) /* Vector 138: Reserved */
|
||||
# define LM_RESERVED_139 (139) /* Vector 139: Reserved */
|
||||
# define TIVA_RESERVED_130 (130) /* Vector 130: Reserved */
|
||||
# define TIVA_RESERVED_131 (131) /* Vector 131: Reserved */
|
||||
# define TIVA_RESERVED_132 (132) /* Vector 132: Reserved */
|
||||
# define TIVA_RESERVED_133 (133) /* Vector 133: Reserved */
|
||||
# define TIVA_RESERVED_134 (134) /* Vector 134: Reserved */
|
||||
# define TIVA_RESERVED_135 (135) /* Vector 135: Reserved */
|
||||
# define TIVA_RESERVED_136 (136) /* Vector 136: Reserved */
|
||||
# define TIVA_RESERVED_137 (137) /* Vector 137: Reserved */
|
||||
# define TIVA_RESERVED_138 (138) /* Vector 138: Reserved */
|
||||
# define TIVA_RESERVED_139 (139) /* Vector 139: Reserved */
|
||||
|
||||
# define LM_RESERVED_140 (140) /* Vector 140: Reserved */
|
||||
# define LM_RESERVED_141 (141) /* Vector 141: Reserved */
|
||||
# define LM_RESERVED_142 (142) /* Vector 142: Reserved */
|
||||
# define LM_RESERVED_143 (143) /* Vector 143: Reserved */
|
||||
# define LM_RESERVED_144 (144) /* Vector 144: Reserved */
|
||||
# define LM_RESERVED_145 (145) /* Vector 145: Reserved */
|
||||
# define LM_RESERVED_146 (146) /* Vector 146: Reserved */
|
||||
# define LM_RESERVED_147 (147) /* Vector 147: Reserved */
|
||||
# define LM_RESERVED_148 (148) /* Vector 148: Reserved */
|
||||
# define LM_RESERVED_149 (149) /* Vector 149: Reserved */
|
||||
# define TIVA_RESERVED_140 (140) /* Vector 140: Reserved */
|
||||
# define TIVA_RESERVED_141 (141) /* Vector 141: Reserved */
|
||||
# define TIVA_RESERVED_142 (142) /* Vector 142: Reserved */
|
||||
# define TIVA_RESERVED_143 (143) /* Vector 143: Reserved */
|
||||
# define TIVA_RESERVED_144 (144) /* Vector 144: Reserved */
|
||||
# define TIVA_RESERVED_145 (145) /* Vector 145: Reserved */
|
||||
# define TIVA_RESERVED_146 (146) /* Vector 146: Reserved */
|
||||
# define TIVA_RESERVED_147 (147) /* Vector 147: Reserved */
|
||||
# define TIVA_RESERVED_148 (148) /* Vector 148: Reserved */
|
||||
# define TIVA_RESERVED_149 (149) /* Vector 149: Reserved */
|
||||
|
||||
# define LM_RESERVED_150 (150) /* Vector 150: Reserved */
|
||||
# define LM_RESERVED_151 (151) /* Vector 151: Reserved */
|
||||
# define LM_RESERVED_152 (152) /* Vector 152: Reserved */
|
||||
# define LM_RESERVED_153 (153) /* Vector 153: Reserved */
|
||||
# define LM_RESERVED_154 (154) /* Vector 154: Reserved */
|
||||
# define TIVA_RESERVED_150 (150) /* Vector 150: Reserved */
|
||||
# define TIVA_RESERVED_151 (151) /* Vector 151: Reserved */
|
||||
# define TIVA_RESERVED_152 (152) /* Vector 152: Reserved */
|
||||
# define TIVA_RESERVED_153 (153) /* Vector 153: Reserved */
|
||||
# define TIVA_RESERVED_154 (154) /* Vector 154: Reserved */
|
||||
|
||||
# define NR_VECTORS (155)
|
||||
# define NR_IRQS (123) /* (Really fewer because of reserved vectors) */
|
||||
# define NR_VECTORS (155)
|
||||
# define NR_IRQS (123) /* (Really fewer because of reserved vectors) */
|
||||
|
||||
#else
|
||||
# error "IRQ Numbers not known for this Stellaris chip"
|
||||
@@ -241,5 +241,5 @@ extern "C"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_LM_LM4F_IRQ_H */
|
||||
#endif /* __ARCH_ARM_INCLUDE_TIVA_LM4F_IRQ_H */
|
||||
|
||||
|
||||
+34
-33
@@ -15,7 +15,7 @@ config ARCH_CHIP_LM3S6918
|
||||
depends on ARCH_CHIP_LM
|
||||
select ARCH_CORTEXM3
|
||||
select ARCH_CHIP_LM3S
|
||||
select LM_HAVE_SSI1
|
||||
select TIVA_HAVE_SSI1
|
||||
|
||||
config ARCH_CHIP_LM3S9B96
|
||||
bool "LM3S9B96"
|
||||
@@ -61,58 +61,59 @@ config ARCH_CHIP_LM4F
|
||||
config ARCH_CHIP_TM4C
|
||||
bool
|
||||
|
||||
config LM_HAVE_SSI1
|
||||
config TIVA_HAVE_SSI1
|
||||
bool
|
||||
|
||||
config LM_REVA2
|
||||
bool "Rev A2"
|
||||
default n
|
||||
depends on ARCH_CHIP_LM
|
||||
---help---
|
||||
Some early silicon returned an increase LDO voltage or 2.75V to work
|
||||
around a PLL bug
|
||||
|
||||
menu "Tiva/Stellaris Peripheral Support"
|
||||
|
||||
config LM_UART0
|
||||
config TIVA_UART0
|
||||
bool "UART0"
|
||||
select ARCH_HAVE_UART0
|
||||
default n
|
||||
|
||||
config LM_UART1
|
||||
config TIVA_UART1
|
||||
bool "UART1"
|
||||
select ARCH_HAVE_UART1
|
||||
default n
|
||||
|
||||
config LM_UART2
|
||||
config TIVA_UART2
|
||||
bool "UART2"
|
||||
select ARCH_HAVE_UART2
|
||||
default n
|
||||
|
||||
config LM_UART3
|
||||
config TIVA_UART3
|
||||
bool "UART3"
|
||||
default n
|
||||
depends on ARCH_CHIP_LM4F || ARCH_CHIP_TM4C
|
||||
select ARCH_HAVE_UART3
|
||||
|
||||
config LM_UART4
|
||||
config TIVA_UART4
|
||||
bool "UART4"
|
||||
default n
|
||||
depends on ARCH_CHIP_LM4F || ARCH_CHIP_TM4C
|
||||
select ARCH_HAVE_UART4
|
||||
|
||||
config LM_UART5
|
||||
config TIVA_UART5
|
||||
bool "UART5"
|
||||
default n
|
||||
depends on ARCH_CHIP_LM4F || ARCH_CHIP_TM4C
|
||||
select ARCH_HAVE_UART5
|
||||
|
||||
config LM_UART6
|
||||
config TIVA_UART6
|
||||
bool "UART6"
|
||||
default n
|
||||
depends on ARCH_CHIP_LM4F || ARCH_CHIP_TM4C
|
||||
select ARCH_HAVE_UART6
|
||||
|
||||
config LM_UART7
|
||||
config TIVA_UART7
|
||||
bool "UART7"
|
||||
default n
|
||||
depends on ARCH_CHIP_LM4F || ARCH_CHIP_TM4C
|
||||
@@ -126,14 +127,14 @@ config SSI1_DISABLE
|
||||
bool "Disable SSI1"
|
||||
default y
|
||||
|
||||
config LM_ETHERNET
|
||||
config TIVA_ETHERNET
|
||||
bool "Ethernet"
|
||||
default n
|
||||
select NETDEVICES
|
||||
---help---
|
||||
This must be set (along with NET) to build the Stellaris Ethernet driver.
|
||||
|
||||
config LM_FLASH
|
||||
config TIVA_FLASH
|
||||
bool "Internal FLASH driver"
|
||||
default n
|
||||
---help---
|
||||
@@ -143,95 +144,95 @@ endmenu
|
||||
|
||||
menu "Disable GPIO Interrupts"
|
||||
|
||||
config LM_DISABLE_GPIOA_IRQS
|
||||
config TIVA_DISABLE_GPIOA_IRQS
|
||||
bool "Disable GPIOA IRQs"
|
||||
default n
|
||||
|
||||
config LM_DISABLE_GPIOB_IRQS
|
||||
config TIVA_DISABLE_GPIOB_IRQS
|
||||
bool "Disable GPIOB IRQs"
|
||||
default n
|
||||
|
||||
config LM_DISABLE_GPIOC_IRQS
|
||||
config TIVA_DISABLE_GPIOC_IRQS
|
||||
bool "Disable GPIOC IRQs"
|
||||
default n
|
||||
|
||||
config LM_DISABLE_GPIOD_IRQS
|
||||
config TIVA_DISABLE_GPIOD_IRQS
|
||||
bool "Disable GPIOD IRQs"
|
||||
default n
|
||||
|
||||
config LM_DISABLE_GPIOE_IRQS
|
||||
config TIVA_DISABLE_GPIOE_IRQS
|
||||
bool "Disable GPIOE IRQs"
|
||||
default n
|
||||
|
||||
config LM_DISABLE_GPIOF_IRQS
|
||||
config TIVA_DISABLE_GPIOF_IRQS
|
||||
bool "Disable GPIOF IRQs"
|
||||
default n
|
||||
|
||||
config LM_DISABLE_GPIOG_IRQS
|
||||
config TIVA_DISABLE_GPIOG_IRQS
|
||||
bool "Disable GPIOG IRQs"
|
||||
default n
|
||||
|
||||
config LM_DISABLE_GPIOH_IRQS
|
||||
config TIVA_DISABLE_GPIOH_IRQS
|
||||
bool "Disable GPIOH IRQs"
|
||||
default n
|
||||
|
||||
config LM_DISABLE_GPIOJ_IRQS
|
||||
config TIVA_DISABLE_GPIOJ_IRQS
|
||||
bool "Disable GPIOJ IRQs"
|
||||
default n
|
||||
|
||||
endmenu
|
||||
|
||||
if LM_ETHERNET
|
||||
if TIVA_ETHERNET
|
||||
menu "Tiva/Stellaris Ethernet Configuration"
|
||||
|
||||
config LM_ETHLEDS
|
||||
config TIVA_ETHLEDS
|
||||
bool "Ethernet LEDs"
|
||||
default n
|
||||
---help---
|
||||
Enable to use Ethernet LEDs on the board.
|
||||
|
||||
config LM_BOARDMAC
|
||||
config TIVA_BOARDMAC
|
||||
bool "Board MAC"
|
||||
default n
|
||||
---help---
|
||||
If the board-specific logic can provide a MAC address (via
|
||||
tiva_ethernetmac()), then this should be selected.
|
||||
|
||||
config LM_ETHHDUPLEX
|
||||
config TIVA_ETHHDUPLEX
|
||||
bool "Force Half Duplex"
|
||||
default n
|
||||
---help---
|
||||
Set to force half duplex operation
|
||||
|
||||
config LM_ETHNOAUTOCRC
|
||||
config TIVA_ETHNOAUTOCRC
|
||||
bool "Disable auto-CRC"
|
||||
default n
|
||||
---help---
|
||||
Set to suppress auto-CRC generation
|
||||
|
||||
config LM_ETHNOPAD
|
||||
config TIVA_ETHNOPAD
|
||||
bool "Disable Tx Padding"
|
||||
default n
|
||||
---help---
|
||||
Set to suppress Tx padding
|
||||
|
||||
config LM_MULTICAST
|
||||
config TIVA_MULTICAST
|
||||
bool "Enable Multicast"
|
||||
default n
|
||||
---help---
|
||||
Set to enable multicast frames
|
||||
|
||||
config LM_PROMISCUOUS
|
||||
config TIVA_PROMISCUOUS
|
||||
bool "Enable Promiscuous Mode"
|
||||
default n
|
||||
---help---
|
||||
Set to enable promiscuous mode
|
||||
|
||||
config LM_TIMESTAMP
|
||||
config TIVA_TIMESTAMP
|
||||
bool "Enable Timestamping"
|
||||
default n
|
||||
|
||||
config LM_BADCRC
|
||||
config TIVA_BADCRC
|
||||
bool "Enable Bad CRC Rejection"
|
||||
default n
|
||||
---help---
|
||||
@@ -262,10 +263,10 @@ config SSI_TXLIMIT
|
||||
endmenu
|
||||
endif
|
||||
|
||||
if LM_FLASH
|
||||
if TIVA_FLASH
|
||||
menu "Tiva/Stellaris Internal Flash Driver Configuration"
|
||||
|
||||
config LM_FLASH_STARTPAGE
|
||||
config TIVA_FLASH_STARTPAGE
|
||||
int "First page accessible by the MTD driver"
|
||||
default 250
|
||||
---help---
|
||||
|
||||
@@ -81,6 +81,6 @@ ifdef CONFIG_NET
|
||||
CHIP_CSRCS += tiva_ethernet.c
|
||||
endif
|
||||
|
||||
ifdef CONFIG_LM_FLASH
|
||||
ifdef CONFIG_TIVA_FLASH
|
||||
CHIP_CSRCS += tiva_flash.c
|
||||
endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -48,67 +48,67 @@
|
||||
|
||||
/* System Control Register Offsets **************************************************/
|
||||
|
||||
#define LM_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */
|
||||
#define LM_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */
|
||||
#define LM_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */
|
||||
#define LM_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */
|
||||
#define LM_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */
|
||||
#define LM_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */
|
||||
#define LM_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */
|
||||
#define LM_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */
|
||||
#define LM_SYSCON_LDOPCTL_OFFSET 0x034 /* LDO Power Control */
|
||||
#define LM_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */
|
||||
#define LM_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */
|
||||
#define LM_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2*/
|
||||
#define LM_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */
|
||||
#define LM_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */
|
||||
#define LM_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */
|
||||
#define LM_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */
|
||||
#define LM_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */
|
||||
#define LM_SYSCON_PLLCFG_OFFSET 0x064 /* XTAL to PLL Translation */
|
||||
#define LM_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */
|
||||
#define LM_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */
|
||||
#define LM_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */
|
||||
#define LM_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */
|
||||
#define LM_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */
|
||||
#define LM_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */
|
||||
#define LM_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */
|
||||
#define LM_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
|
||||
#define LM_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
|
||||
#define LM_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
|
||||
#define LM_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/
|
||||
#define TIVA_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */
|
||||
#define TIVA_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */
|
||||
#define TIVA_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */
|
||||
#define TIVA_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */
|
||||
#define TIVA_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */
|
||||
#define TIVA_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */
|
||||
#define TIVA_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */
|
||||
#define TIVA_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */
|
||||
#define TIVA_SYSCON_LDOPCTL_OFFSET 0x034 /* LDO Power Control */
|
||||
#define TIVA_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */
|
||||
#define TIVA_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */
|
||||
#define TIVA_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2*/
|
||||
#define TIVA_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */
|
||||
#define TIVA_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */
|
||||
#define TIVA_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */
|
||||
#define TIVA_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */
|
||||
#define TIVA_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */
|
||||
#define TIVA_SYSCON_PLLCFG_OFFSET 0x064 /* XTAL to PLL Translation */
|
||||
#define TIVA_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */
|
||||
#define TIVA_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */
|
||||
#define TIVA_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */
|
||||
#define TIVA_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */
|
||||
#define TIVA_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */
|
||||
#define TIVA_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */
|
||||
#define TIVA_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */
|
||||
#define TIVA_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
|
||||
#define TIVA_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
|
||||
#define TIVA_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
|
||||
#define TIVA_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/
|
||||
|
||||
/* System Control Register Addresses ************************************************/
|
||||
|
||||
#define LM_SYSCON_DID0 (LM_SYSCON_BASE + LM_SYSCON_DID0_OFFSET)
|
||||
#define LM_SYSCON_DID1 (LM_SYSCON_BASE + LM_SYSCON_DID1_OFFSET)
|
||||
#define LM_SYSCON_DC0 (LM_SYSCON_BASE + LM_SYSCON_DC0_OFFSET)
|
||||
#define LM_SYSCON_DC1 (LM_SYSCON_BASE + LM_SYSCON_DC1_OFFSET)
|
||||
#define LM_SYSCON_DC2 (LM_SYSCON_BASE + LM_SYSCON_DC2_OFFSET)
|
||||
#define LM_SYSCON_DC3 (LM_SYSCON_BASE + LM_SYSCON_DC3_OFFSET)
|
||||
#define LM_SYSCON_DC4 (LM_SYSCON_BASE + LM_SYSCON_DC4_OFFSET)
|
||||
#define LM_SYSCON_PBORCTL (LM_SYSCON_BASE + LM_SYSCON_PBORCTL_OFFSET)
|
||||
#define LM_SYSCON_LDOPCTL (LM_SYSCON_BASE + LM_SYSCON_LDOPCTL_OFFSET)
|
||||
#define LM_SYSCON_SRCR0 (LM_SYSCON_BASE + LM_SYSCON_SRCR0_OFFSET)
|
||||
#define LM_SYSCON_SRCR1 (LM_SYSCON_BASE + LM_SYSCON_SRCR1_OFFSET)
|
||||
#define LM_SYSCON_SRCR2 (LM_SYSCON_BASE + LM_SYSCON_SRCR2_OFFSET)
|
||||
#define LM_SYSCON_RIS (LM_SYSCON_BASE + LM_SYSCON_RIS_OFFSET)
|
||||
#define LM_SYSCON_IMC (LM_SYSCON_BASE + LM_SYSCON_IMC_OFFSET)
|
||||
#define LM_SYSCON_MISC (LM_SYSCON_BASE + LM_SYSCON_MISC_OFFSET)
|
||||
#define LM_SYSCON_RESC (LM_SYSCON_BASE + LM_SYSCON_RESC_OFFSET)
|
||||
#define LM_SYSCON_RCC (LM_SYSCON_BASE + LM_SYSCON_RCC_OFFSET)
|
||||
#define LM_SYSCON_PLLCFG (LM_SYSCON_BASE + LM_SYSCON_PLLCFG_OFFSET)
|
||||
#define LM_SYSCON_RCC2 (LM_SYSCON_BASE + LM_SYSCON_RCC2_OFFSET)
|
||||
#define LM_SYSCON_RCGC0 (LM_SYSCON_BASE + LM_SYSCON_RCGC0_OFFSET)
|
||||
#define LM_SYSCON_RCGC1 (LM_SYSCON_BASE + LM_SYSCON_RCGC1_OFFSET)
|
||||
#define LM_SYSCON_RCGC2 (LM_SYSCON_BASE + LM_SYSCON_RCGC2_OFFSET)
|
||||
#define LM_SYSCON_SCGC0 (LM_SYSCON_BASE + LM_SYSCON_SCGC0_OFFSET)
|
||||
#define LM_SYSCON_SCGC1 (LM_SYSCON_BASE + LM_SYSCON_SCGC1_OFFSET)
|
||||
#define LM_SYSCON_SCGC2 (LM_SYSCON_BASE + LM_SYSCON_SCGC2_OFFSET)
|
||||
#define LM_SYSCON_DCGC0 (LM_SYSCON_BASE + LM_SYSCON_DCGC0_OFFSET)
|
||||
#define LM_SYSCON_DCGC1 (LM_SYSCON_BASE + LM_SYSCON_DCGC1_OFFSET)
|
||||
#define LM_SYSCON_DCGC2 (LM_SYSCON_BASE + LM_SYSCON_DCGC2_OFFSET)
|
||||
#define LM_SYSCON_DSLPCLKCFG (LM_SYSCON_BASE + LM_SYSCON_DSLPCLKCFG_OFFSET)
|
||||
#define TIVA_SYSCON_DID0 (TIVA_SYSCON_BASE + TIVA_SYSCON_DID0_OFFSET)
|
||||
#define TIVA_SYSCON_DID1 (TIVA_SYSCON_BASE + TIVA_SYSCON_DID1_OFFSET)
|
||||
#define TIVA_SYSCON_DC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC0_OFFSET)
|
||||
#define TIVA_SYSCON_DC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC1_OFFSET)
|
||||
#define TIVA_SYSCON_DC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC2_OFFSET)
|
||||
#define TIVA_SYSCON_DC3 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC3_OFFSET)
|
||||
#define TIVA_SYSCON_DC4 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC4_OFFSET)
|
||||
#define TIVA_SYSCON_PBORCTL (TIVA_SYSCON_BASE + TIVA_SYSCON_PBORCTL_OFFSET)
|
||||
#define TIVA_SYSCON_LDOPCTL (TIVA_SYSCON_BASE + TIVA_SYSCON_LDOPCTL_OFFSET)
|
||||
#define TIVA_SYSCON_SRCR0 (TIVA_SYSCON_BASE + TIVA_SYSCON_SRCR0_OFFSET)
|
||||
#define TIVA_SYSCON_SRCR1 (TIVA_SYSCON_BASE + TIVA_SYSCON_SRCR1_OFFSET)
|
||||
#define TIVA_SYSCON_SRCR2 (TIVA_SYSCON_BASE + TIVA_SYSCON_SRCR2_OFFSET)
|
||||
#define TIVA_SYSCON_RIS (TIVA_SYSCON_BASE + TIVA_SYSCON_RIS_OFFSET)
|
||||
#define TIVA_SYSCON_IMC (TIVA_SYSCON_BASE + TIVA_SYSCON_IMC_OFFSET)
|
||||
#define TIVA_SYSCON_MISC (TIVA_SYSCON_BASE + TIVA_SYSCON_MISC_OFFSET)
|
||||
#define TIVA_SYSCON_RESC (TIVA_SYSCON_BASE + TIVA_SYSCON_RESC_OFFSET)
|
||||
#define TIVA_SYSCON_RCC (TIVA_SYSCON_BASE + TIVA_SYSCON_RCC_OFFSET)
|
||||
#define TIVA_SYSCON_PLLCFG (TIVA_SYSCON_BASE + TIVA_SYSCON_PLLCFG_OFFSET)
|
||||
#define TIVA_SYSCON_RCC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_RCC2_OFFSET)
|
||||
#define TIVA_SYSCON_RCGC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGC0_OFFSET)
|
||||
#define TIVA_SYSCON_RCGC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGC1_OFFSET)
|
||||
#define TIVA_SYSCON_RCGC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGC2_OFFSET)
|
||||
#define TIVA_SYSCON_SCGC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGC0_OFFSET)
|
||||
#define TIVA_SYSCON_SCGC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGC1_OFFSET)
|
||||
#define TIVA_SYSCON_SCGC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGC2_OFFSET)
|
||||
#define TIVA_SYSCON_DCGC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGC0_OFFSET)
|
||||
#define TIVA_SYSCON_DCGC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGC1_OFFSET)
|
||||
#define TIVA_SYSCON_DCGC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGC2_OFFSET)
|
||||
#define TIVA_SYSCON_DSLPCLKCFG (TIVA_SYSCON_BASE + TIVA_SYSCON_DSLPCLKCFG_OFFSET)
|
||||
|
||||
/* System Control Register Bit Definitions ******************************************/
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -50,26 +50,26 @@
|
||||
/* Memory map ***********************************************************************/
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_LM4F120)
|
||||
# define LM_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */
|
||||
/* -0x00ffffff: Reserved */
|
||||
# define LM_ROM_BASE 0x01000000 /* -0x1fffffff: Reserved for ROM */
|
||||
# define LM_SRAM_BASE 0x20000000 /* -0x20007fff: Bit-banded on-chip SRAM */
|
||||
/* -0x21ffffff: Reserved */
|
||||
# define LM_ASRAM_BASE 0x22000000 /* -0x220fffff: Bit-band alias of 20000000- */
|
||||
/* -0x3fffffff: Reserved */
|
||||
# define LM_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */
|
||||
/* -0x41ffffff: Peripherals */
|
||||
# define LM_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alias of 40000000- */
|
||||
/* -0xdfffffff: Reserved */
|
||||
# define LM_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
|
||||
# define LM_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
|
||||
# define LM_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
|
||||
/* -0xe000dfff: Reserved */
|
||||
# define LM_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
|
||||
/* -0xe003ffff: Reserved */
|
||||
# define LM_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
|
||||
# define LM_ETM_BASE 0xe0041000 /* -0xe0041fff: Embedded Trace Macrocell */
|
||||
/* -0xffffffff: Reserved */
|
||||
# define TIVA_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */
|
||||
/* -0x00ffffff: Reserved */
|
||||
# define TIVA_ROM_BASE 0x01000000 /* -0x1fffffff: Reserved for ROM */
|
||||
# define TIVA_SRAM_BASE 0x20000000 /* -0x20007fff: Bit-banded on-chip SRAM */
|
||||
/* -0x21ffffff: Reserved */
|
||||
# define TIVA_ASRAM_BASE 0x22000000 /* -0x220fffff: Bit-band alias of 20000000- */
|
||||
/* -0x3fffffff: Reserved */
|
||||
# define TIVA_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */
|
||||
/* -0x41ffffff: Peripherals */
|
||||
# define TIVA_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alias of 40000000- */
|
||||
/* -0xdfffffff: Reserved */
|
||||
# define TIVA_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
|
||||
# define TIVA_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
|
||||
# define TIVA_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
|
||||
/* -0xe000dfff: Reserved */
|
||||
# define TIVA_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
|
||||
/* -0xe003ffff: Reserved */
|
||||
# define TIVA_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
|
||||
# define TIVA_ETM_BASE 0xe0041000 /* -0xe0041fff: Embedded Trace Macrocell */
|
||||
/* -0xffffffff: Reserved */
|
||||
#else
|
||||
# error "Memory map not specified for this LM4F chip"
|
||||
#endif
|
||||
@@ -79,79 +79,79 @@
|
||||
#if defined(CONFIG_ARCH_CHIP_LM4F120)
|
||||
/* FiRM Peripheral Base Addresses */
|
||||
|
||||
# define LM_WDOG0_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer 0 */
|
||||
# define LM_WDOG1_BASE (LM_PERIPH_BASE + 0x01000) /* -0x00fff: Watchdog Timer 1 */
|
||||
/* -0x03fff: Reserved */
|
||||
# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
|
||||
# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
|
||||
# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
|
||||
# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
|
||||
# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
|
||||
# define LM_SSI1_BASE (LM_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
|
||||
# define LM_SSI2_BASE (LM_PERIPH_BASE + 0x0a000) /* -0x0afff: SSI2 */
|
||||
# define LM_SSI3_BASE (LM_PERIPH_BASE + 0x0b000) /* -0x0bfff: SSI3 */
|
||||
# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
|
||||
# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
|
||||
# define LM_UART2_BASE (LM_PERIPH_BASE + 0x0e000) /* -0x0efff: UART2 */
|
||||
# define LM_UART3_BASE (LM_PERIPH_BASE + 0x0f000) /* -0x0ffff: UART3 */
|
||||
# define LM_UART4_BASE (LM_PERIPH_BASE + 0x10000) /* -0x10fff: UART4 */
|
||||
# define LM_UART5_BASE (LM_PERIPH_BASE + 0x11000) /* -0x11fff: UART5 */
|
||||
# define LM_UART6_BASE (LM_PERIPH_BASE + 0x12000) /* -0x12fff: UART6 */
|
||||
# define LM_UART7_BASE (LM_PERIPH_BASE + 0x13000) /* -0x13fff: UART7 */
|
||||
/* -0x1ffff: Reserved */
|
||||
# define TIVA_WDOG0_BASE (TIVA_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer 0 */
|
||||
# define TIVA_WDOG1_BASE (TIVA_PERIPH_BASE + 0x01000) /* -0x00fff: Watchdog Timer 1 */
|
||||
/* -0x03fff: Reserved */
|
||||
# define TIVA_GPIOA_BASE (TIVA_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
|
||||
# define TIVA_GPIOB_BASE (TIVA_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
|
||||
# define TIVA_GPIOC_BASE (TIVA_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
|
||||
# define TIVA_GPIOD_BASE (TIVA_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
|
||||
# define TIVA_SSI0_BASE (TIVA_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
|
||||
# define TIVA_SSI1_BASE (TIVA_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
|
||||
# define TIVA_SSI2_BASE (TIVA_PERIPH_BASE + 0x0a000) /* -0x0afff: SSI2 */
|
||||
# define TIVA_SSI3_BASE (TIVA_PERIPH_BASE + 0x0b000) /* -0x0bfff: SSI3 */
|
||||
# define TIVA_UART0_BASE (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
|
||||
# define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
|
||||
# define TIVA_UART2_BASE (TIVA_PERIPH_BASE + 0x0e000) /* -0x0efff: UART2 */
|
||||
# define TIVA_UART3_BASE (TIVA_PERIPH_BASE + 0x0f000) /* -0x0ffff: UART3 */
|
||||
# define TIVA_UART4_BASE (TIVA_PERIPH_BASE + 0x10000) /* -0x10fff: UART4 */
|
||||
# define TIVA_UART5_BASE (TIVA_PERIPH_BASE + 0x11000) /* -0x11fff: UART5 */
|
||||
# define TIVA_UART6_BASE (TIVA_PERIPH_BASE + 0x12000) /* -0x12fff: UART6 */
|
||||
# define TIVA_UART7_BASE (TIVA_PERIPH_BASE + 0x13000) /* -0x13fff: UART7 */
|
||||
/* -0x1ffff: Reserved */
|
||||
/* Peripheral Base Addresses */
|
||||
|
||||
# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
|
||||
# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fbf: I2C Slave 0 */
|
||||
# define LM_I2CSC0_BASE (LM_PERIPH_BASE + 0x20fc0) /* -0x20fff: I2C Status and Control 0 */
|
||||
# define LM_I2CM1_BASE (LM_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
|
||||
# define LM_I2CS1_BASE (LM_PERIPH_BASE + 0x21800) /* -0x21fbf: I2C Slave 1 */
|
||||
# define LM_I2CSC1_BASE (LM_PERIPH_BASE + 0x21fc0) /* -0x21fff: I2C Status and Control 1 */
|
||||
# define LM_I2CM2_BASE (LM_PERIPH_BASE + 0x22000) /* -0x227ff: I2C Master 2 */
|
||||
# define LM_I2CS2_BASE (LM_PERIPH_BASE + 0x22800) /* -0x22fbf: I2C Slave 2 */
|
||||
# define LM_I2CSC2_BASE (LM_PERIPH_BASE + 0x22fc0) /* -0x22fff: I2C Status and Control 2 */
|
||||
# define LM_I2CM3_BASE (LM_PERIPH_BASE + 0x23000) /* -0x237ff: I2C Master 3 */
|
||||
# define LM_I2CS3_BASE (LM_PERIPH_BASE + 0x23800) /* -0x23fbf: I2C Slave 3 */
|
||||
# define LM_I2CSC3_BASE (LM_PERIPH_BASE + 0x23fc0) /* -0x23fff: I2C Status and Control 3 */
|
||||
# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
|
||||
# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
|
||||
/* -0x2ffff: Reserved */
|
||||
# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: 16/32 Timer 0 */
|
||||
# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: 16/32 Timer 1 */
|
||||
# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: 16/32 Timer 2 */
|
||||
# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: 16/32 Timer 3 */
|
||||
# define LM_TIMER4_BASE (LM_PERIPH_BASE + 0x34000) /* -0x34fff: 16/32 Timer 4 */
|
||||
# define LM_TIMER5_BASE (LM_PERIPH_BASE + 0x35000) /* -0x35fff: 16/32 Timer 5 */
|
||||
# define LM_WTIMER0_BASE (LM_PERIPH_BASE + 0x36000) /* -0x36fff: 32/64 Wide Timer 0 */
|
||||
# define LM_WTIMER1_BASE (LM_PERIPH_BASE + 0x37000) /* -0x37fff: 32/64 Wide Timer 1 */
|
||||
# define LM_ADC0_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
|
||||
# define LM_ADC1_BASE (LM_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
|
||||
/* -0x3bfff: Reserved */
|
||||
# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
|
||||
/* -0x43fff: Reserved */
|
||||
# define LM_CANCON_BASE (LM_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller */
|
||||
/* -0x4bfff: Reserved */
|
||||
# define LM_WTIMER2_BASE (LM_PERIPH_BASE + 0x4c000) /* -0x4cfff: 32/64 Wide Timer 2 */
|
||||
# define LM_WTIMER3_BASE (LM_PERIPH_BASE + 0x4d000) /* -0x4dfff: 32/64 Wide Timer 3 */
|
||||
# define LM_WTIMER4_BASE (LM_PERIPH_BASE + 0x4e000) /* -0x4efff: 32/64 Wide Timer 4 */
|
||||
# define LM_WTIMER5_BASE (LM_PERIPH_BASE + 0x4f000) /* -0x4ffff: 32/64 Wide Timer 5 */
|
||||
# define LM_USB_BASE (LM_PERIPH_BASE + 0x50000) /* -0x50fff: USB */
|
||||
/* -0x57fff: Reserved */
|
||||
# define LM_GPIOAAHB_BASE (LM_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */
|
||||
# define LM_GPIOBAHB_BASE (LM_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */
|
||||
# define LM_GPIOCAHB_BASE (LM_PERIPH_BASE + 0x5A000) /* -0x5afff: GPIO Port C (AHB aperture) */
|
||||
# define LM_GPIODAHB_BASE (LM_PERIPH_BASE + 0x5B000) /* -0x5bfff: GPIO Port D (AHB aperture) */
|
||||
# define LM_GPIOEAHB_BASE (LM_PERIPH_BASE + 0x5C000) /* -0x5cfff: GPIO Port E (AHB aperture) */
|
||||
# define LM_GPIOFAHB_BASE (LM_PERIPH_BASE + 0x5D000) /* -0x5dfff: GPIO Port F (AHB aperture) */
|
||||
/* -0xaefff: Reserved */
|
||||
# define LM_EEPROM_BASE (LM_PERIPH_BASE + 0xaf000) /* -0xaffff: EEPROM and Key Locker */
|
||||
/* -0xf8fff: Reserved */
|
||||
# define LM_SYSEXC_BASE (LM_PERIPH_BASE + 0xf9000) /* -0xf9fff: System Exception Control */
|
||||
/* -0xfbfff: Reserved */
|
||||
# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
|
||||
# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
|
||||
# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
|
||||
# define LM_UDMA_BASE (LM_PERIPH_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */
|
||||
# define TIVA_I2CM0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
|
||||
# define TIVA_I2CS0_BASE (TIVA_PERIPH_BASE + 0x20800) /* -0x20fbf: I2C Slave 0 */
|
||||
# define TIVA_I2CSC0_BASE (TIVA_PERIPH_BASE + 0x20fc0) /* -0x20fff: I2C Status and Control 0 */
|
||||
# define TIVA_I2CM1_BASE (TIVA_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
|
||||
# define TIVA_I2CS1_BASE (TIVA_PERIPH_BASE + 0x21800) /* -0x21fbf: I2C Slave 1 */
|
||||
# define TIVA_I2CSC1_BASE (TIVA_PERIPH_BASE + 0x21fc0) /* -0x21fff: I2C Status and Control 1 */
|
||||
# define TIVA_I2CM2_BASE (TIVA_PERIPH_BASE + 0x22000) /* -0x227ff: I2C Master 2 */
|
||||
# define TIVA_I2CS2_BASE (TIVA_PERIPH_BASE + 0x22800) /* -0x22fbf: I2C Slave 2 */
|
||||
# define TIVA_I2CSC2_BASE (TIVA_PERIPH_BASE + 0x22fc0) /* -0x22fff: I2C Status and Control 2 */
|
||||
# define TIVA_I2CM3_BASE (TIVA_PERIPH_BASE + 0x23000) /* -0x237ff: I2C Master 3 */
|
||||
# define TIVA_I2CS3_BASE (TIVA_PERIPH_BASE + 0x23800) /* -0x23fbf: I2C Slave 3 */
|
||||
# define TIVA_I2CSC3_BASE (TIVA_PERIPH_BASE + 0x23fc0) /* -0x23fff: I2C Status and Control 3 */
|
||||
# define TIVA_GPIOE_BASE (TIVA_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
|
||||
# define TIVA_GPIOF_BASE (TIVA_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
|
||||
/* -0x2ffff: Reserved */
|
||||
# define TIVA_TIMER0_BASE (TIVA_PERIPH_BASE + 0x30000) /* -0x30fff: 16/32 Timer 0 */
|
||||
# define TIVA_TIMER1_BASE (TIVA_PERIPH_BASE + 0x31000) /* -0x31fff: 16/32 Timer 1 */
|
||||
# define TIVA_TIMER2_BASE (TIVA_PERIPH_BASE + 0x32000) /* -0x32fff: 16/32 Timer 2 */
|
||||
# define TIVA_TIMER3_BASE (TIVA_PERIPH_BASE + 0x33000) /* -0x33fff: 16/32 Timer 3 */
|
||||
# define TIVA_TIMER4_BASE (TIVA_PERIPH_BASE + 0x34000) /* -0x34fff: 16/32 Timer 4 */
|
||||
# define TIVA_TIMER5_BASE (TIVA_PERIPH_BASE + 0x35000) /* -0x35fff: 16/32 Timer 5 */
|
||||
# define TIVA_WTIMER0_BASE (TIVA_PERIPH_BASE + 0x36000) /* -0x36fff: 32/64 Wide Timer 0 */
|
||||
# define TIVA_WTIMER1_BASE (TIVA_PERIPH_BASE + 0x37000) /* -0x37fff: 32/64 Wide Timer 1 */
|
||||
# define TIVA_ADC0_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
|
||||
# define TIVA_ADC1_BASE (TIVA_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
|
||||
/* -0x3bfff: Reserved */
|
||||
# define TIVA_COMPARE_BASE (TIVA_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
|
||||
/* -0x43fff: Reserved */
|
||||
# define TIVA_CANCON_BASE (TIVA_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller */
|
||||
/* -0x4bfff: Reserved */
|
||||
# define TIVA_WTIMER2_BASE (TIVA_PERIPH_BASE + 0x4c000) /* -0x4cfff: 32/64 Wide Timer 2 */
|
||||
# define TIVA_WTIMER3_BASE (TIVA_PERIPH_BASE + 0x4d000) /* -0x4dfff: 32/64 Wide Timer 3 */
|
||||
# define TIVA_WTIMER4_BASE (TIVA_PERIPH_BASE + 0x4e000) /* -0x4efff: 32/64 Wide Timer 4 */
|
||||
# define TIVA_WTIMER5_BASE (TIVA_PERIPH_BASE + 0x4f000) /* -0x4ffff: 32/64 Wide Timer 5 */
|
||||
# define TIVA_USB_BASE (TIVA_PERIPH_BASE + 0x50000) /* -0x50fff: USB */
|
||||
/* -0x57fff: Reserved */
|
||||
# define TIVA_GPIOAAHB_BASE (TIVA_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */
|
||||
# define TIVA_GPIOBAHB_BASE (TIVA_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */
|
||||
# define TIVA_GPIOCAHB_BASE (TIVA_PERIPH_BASE + 0x5A000) /* -0x5afff: GPIO Port C (AHB aperture) */
|
||||
# define TIVA_GPIODAHB_BASE (TIVA_PERIPH_BASE + 0x5B000) /* -0x5bfff: GPIO Port D (AHB aperture) */
|
||||
# define TIVA_GPIOEAHB_BASE (TIVA_PERIPH_BASE + 0x5C000) /* -0x5cfff: GPIO Port E (AHB aperture) */
|
||||
# define TIVA_GPIOFAHB_BASE (TIVA_PERIPH_BASE + 0x5D000) /* -0x5dfff: GPIO Port F (AHB aperture) */
|
||||
/* -0xaefff: Reserved */
|
||||
# define TIVA_EEPROM_BASE (TIVA_PERIPH_BASE + 0xaf000) /* -0xaffff: EEPROM and Key Locker */
|
||||
/* -0xf8fff: Reserved */
|
||||
# define TIVA_SYSEXC_BASE (TIVA_PERIPH_BASE + 0xf9000) /* -0xf9fff: System Exception Control */
|
||||
/* -0xfbfff: Reserved */
|
||||
# define TIVA_HIBERNATE_BASE (TIVA_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
|
||||
# define TIVA_FLASHCON_BASE (TIVA_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
|
||||
# define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
|
||||
# define TIVA_UDMA_BASE (TIVA_PERIPH_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */
|
||||
#else
|
||||
# error "Peripheral base addresses not specified for this Stellaris chip"
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -41,10 +41,10 @@
|
||||
* Vectors
|
||||
************************************************************************************/
|
||||
|
||||
/* This file is included by lm_vectors.S. It provides the macro VECTOR that
|
||||
/* This file is included by tiva_vectors.S. It provides the macro VECTOR that
|
||||
* supplies ach Stellaris vector in terms of a (lower-case) ISR label and an
|
||||
* (upper-case) IRQ number as defined in arch/arm/include/lm/lm4f_irq.h.
|
||||
* lm_vectors.S will define the VECTOR in different ways in order to generate
|
||||
* tiva_vectors.S will define the VECTOR in different ways in order to generate
|
||||
* the interrupt vectors and handlers in their final form.
|
||||
*/
|
||||
|
||||
@@ -62,159 +62,159 @@ ARMV7M_PERIPHERAL_INTERRUPTS 155
|
||||
|
||||
# else
|
||||
|
||||
VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */
|
||||
VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */
|
||||
VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */
|
||||
VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */
|
||||
VECTOR(tiva_gpioa, TIVA_IRQ_GPIOA) /* Vector 16: GPIO Port A */
|
||||
VECTOR(tiva_gpiob, TIVA_IRQ_GPIOB) /* Vector 17: GPIO Port B */
|
||||
VECTOR(tiva_gpioc, TIVA_IRQ_GPIOC) /* Vector 18: GPIO Port C */
|
||||
VECTOR(tiva_gpiod, TIVA_IRQ_GPIOD) /* Vector 19: GPIO Port D */
|
||||
|
||||
VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */
|
||||
VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */
|
||||
VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */
|
||||
VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */
|
||||
VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */
|
||||
UNUSED(LM_RESERVED_25) /* Vector 25: Reserved */
|
||||
UNUSED(LM_RESERVED_26) /* Vector 26: Reserved */
|
||||
UNUSED(LM_RESERVED_27) /* Vector 27: Reserved */
|
||||
UNUSED(LM_RESERVED_28) /* Vector 28: Reserved */
|
||||
UNUSED(LM_RESERVED_29) /* Vector 29: Reserved */
|
||||
VECTOR(tiva_gpioe, TIVA_IRQ_GPIOE) /* Vector 20: GPIO Port E */
|
||||
VECTOR(tiva_uart0, TIVA_IRQ_UART0) /* Vector 21: UART 0 */
|
||||
VECTOR(tiva_uart1, TIVA_IRQ_UART1) /* Vector 22: UART 1 */
|
||||
VECTOR(tiva_ssi0, TIVA_IRQ_SSI0) /* Vector 23: SSI 0 */
|
||||
VECTOR(tiva_i2c0, TIVA_IRQ_I2C0) /* Vector 24: I2C 0 */
|
||||
UNUSED(TIVA_RESERVED_25) /* Vector 25: Reserved */
|
||||
UNUSED(TIVA_RESERVED_26) /* Vector 26: Reserved */
|
||||
UNUSED(TIVA_RESERVED_27) /* Vector 27: Reserved */
|
||||
UNUSED(TIVA_RESERVED_28) /* Vector 28: Reserved */
|
||||
UNUSED(TIVA_RESERVED_29) /* Vector 29: Reserved */
|
||||
|
||||
VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
|
||||
VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
|
||||
VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
|
||||
VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
|
||||
VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timers 0 and 1 */
|
||||
VECTOR(lm_timer0a, LM_IRQ_TIMER0A) /* Vector 35: 16/32-Bit Timer 0 A */
|
||||
VECTOR(lm_timer0b, LM_IRQ_TIMER0B) /* Vector 36: 16/32-Bit Timer 0 B */
|
||||
VECTOR(lm_timer1a, LM_IRQ_TIMER1A) /* Vector 37: 16/32-Bit Timer 1 A */
|
||||
VECTOR(lm_timer1b, LM_IRQ_TIMER1B) /* Vector 38: 16/32-Bit Timer 1 B */
|
||||
VECTOR(lm_timer2a, LM_IRQ_TIMER2A) /* Vector 39: 16/32-Bit Timer 2 A */
|
||||
VECTOR(tiva_adc0, TIVA_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
|
||||
VECTOR(tiva_adc1, TIVA_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
|
||||
VECTOR(tiva_adc2, TIVA_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
|
||||
VECTOR(tiva_adc3, TIVA_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
|
||||
VECTOR(tiva_wdog, TIVA_IRQ_WDOG) /* Vector 34: Watchdog Timers 0 and 1 */
|
||||
VECTOR(tiva_timer0a, TIVA_IRQ_TIMER0A) /* Vector 35: 16/32-Bit Timer 0 A */
|
||||
VECTOR(tiva_timer0b, TIVA_IRQ_TIMER0B) /* Vector 36: 16/32-Bit Timer 0 B */
|
||||
VECTOR(tiva_timer1a, TIVA_IRQ_TIMER1A) /* Vector 37: 16/32-Bit Timer 1 A */
|
||||
VECTOR(tiva_timer1b, TIVA_IRQ_TIMER1B) /* Vector 38: 16/32-Bit Timer 1 B */
|
||||
VECTOR(tiva_timer2a, TIVA_IRQ_TIMER2A) /* Vector 39: 16/32-Bit Timer 2 A */
|
||||
|
||||
VECTOR(lm_timer2b, LM_IRQ_TIMER2B) /* Vector 40: 16/32-Bit Timer 2 B */
|
||||
VECTOR(lm_compare0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
|
||||
VECTOR(lm_compare1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */
|
||||
UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */
|
||||
VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */
|
||||
VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH and EEPROM Control */
|
||||
VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */
|
||||
UNUSED(LM_RESERVED_47) /* Vector 47: Reserved */
|
||||
UNUSED(LM_RESERVED_48) /* Vector 48: Reserved */
|
||||
VECTOR(lm_uart2, LM_IRQ_UART2) /* Vector 22: UART 2 */
|
||||
VECTOR(tiva_timer2b, TIVA_IRQ_TIMER2B) /* Vector 40: 16/32-Bit Timer 2 B */
|
||||
VECTOR(tiva_compare0, TIVA_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
|
||||
VECTOR(tiva_compare1, TIVA_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */
|
||||
UNUSED(TIVA_RESERVED_43) /* Vector 43: Reserved */
|
||||
VECTOR(tiva_syscon, TIVA_IRQ_SYSCON) /* Vector 44: System Control */
|
||||
VECTOR(tiva_flashcon, TIVA_IRQ_FLASHCON) /* Vector 45: FLASH and EEPROM Control */
|
||||
VECTOR(tiva_gpiof, TIVA_IRQ_GPIOF) /* Vector 46: GPIO Port F */
|
||||
UNUSED(TIVA_RESERVED_47) /* Vector 47: Reserved */
|
||||
UNUSED(TIVA_RESERVED_48) /* Vector 48: Reserved */
|
||||
VECTOR(tiva_uart2, TIVA_IRQ_UART2) /* Vector 22: UART 2 */
|
||||
|
||||
VECTOR(lm_ssi1, LM_IRQ_SSI1) /* Vector 50: SSI 1 */
|
||||
VECTOR(lm_timer3a, LM_IRQ_TIMER3A) /* Vector 51: 16/32-Bit Timer 3 A */
|
||||
VECTOR(lm_timer3b, LM_IRQ_TIMER3B) /* Vector 52: 16/32-Bit Timer 3 B */
|
||||
VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */
|
||||
UNUSED(LM_RESERVED_54) /* Vector 54: Reserved */
|
||||
VECTOR(lm_can0, LM_IRQ_CAN0) /* Vector 55: CAN 0 */
|
||||
UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */
|
||||
UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */
|
||||
UNUSED(LM_RESERVED_58) /* Vector 58: Reserved */
|
||||
VECTOR(lm_hibernate, LM_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */
|
||||
VECTOR(tiva_ssi1, TIVA_IRQ_SSI1) /* Vector 50: SSI 1 */
|
||||
VECTOR(tiva_timer3a, TIVA_IRQ_TIMER3A) /* Vector 51: 16/32-Bit Timer 3 A */
|
||||
VECTOR(tiva_timer3b, TIVA_IRQ_TIMER3B) /* Vector 52: 16/32-Bit Timer 3 B */
|
||||
VECTOR(tiva_i2c1, TIVA_IRQ_I2C1) /* Vector 53: I2C 1 */
|
||||
UNUSED(TIVA_RESERVED_54) /* Vector 54: Reserved */
|
||||
VECTOR(tiva_can0, TIVA_IRQ_CAN0) /* Vector 55: CAN 0 */
|
||||
UNUSED(TIVA_RESERVED_56) /* Vector 56: Reserved */
|
||||
UNUSED(TIVA_RESERVED_57) /* Vector 57: Reserved */
|
||||
UNUSED(TIVA_RESERVED_58) /* Vector 58: Reserved */
|
||||
VECTOR(tiva_hibernate, TIVA_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */
|
||||
|
||||
VECTOR(lm_usb, LM_IRQ_USB) /* Vector 60: USB */
|
||||
UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */
|
||||
VECTOR(lm_udmasoft, LM_IRQ_UDMASOFT) /* Vector 62: uDMA Software */
|
||||
VECTOR(lm_udmaerro, LM_IRQ_UDMAERROR) /* Vector 63: uDMA Error */
|
||||
VECTOR(lm_adc1_0, LM_IRQ_ADC1_0) /* Vector 64: ADC1 Sequence 0 */
|
||||
VECTOR(lm_adc1_1, LM_IRQ_ADC1_1) /* Vector 65: ADC1 Sequence 1 */
|
||||
VECTOR(lm_adc1_2, LM_IRQ_ADC1_2) /* Vector 66: ADC1 Sequence 2 */
|
||||
VECTOR(lm_adc1_3, LM_IRQ_ADC1_3) /* Vector 67: ADC1 Sequence 3 */
|
||||
UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */
|
||||
UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */
|
||||
VECTOR(tiva_usb, TIVA_IRQ_USB) /* Vector 60: USB */
|
||||
UNUSED(TIVA_RESERVED_61) /* Vector 61: Reserved */
|
||||
VECTOR(tiva_udmasoft, TIVA_IRQ_UDMASOFT) /* Vector 62: uDMA Software */
|
||||
VECTOR(tiva_udmaerro, TIVA_IRQ_UDMAERROR) /* Vector 63: uDMA Error */
|
||||
VECTOR(tiva_adc1_0, TIVA_IRQ_ADC1_0) /* Vector 64: ADC1 Sequence 0 */
|
||||
VECTOR(tiva_adc1_1, TIVA_IRQ_ADC1_1) /* Vector 65: ADC1 Sequence 1 */
|
||||
VECTOR(tiva_adc1_2, TIVA_IRQ_ADC1_2) /* Vector 66: ADC1 Sequence 2 */
|
||||
VECTOR(tiva_adc1_3, TIVA_IRQ_ADC1_3) /* Vector 67: ADC1 Sequence 3 */
|
||||
UNUSED(TIVA_RESERVED_68) /* Vector 68: Reserved */
|
||||
UNUSED(TIVA_RESERVED_69) /* Vector 69: Reserved */
|
||||
|
||||
UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */
|
||||
UNUSED(LM_RESERVED_71) /* Vector 71: Reserved */
|
||||
UNUSED(LM_RESERVED_72) /* Vector 72: Reserved */
|
||||
VECTOR(lm_ssi2, LM_IRQ_SSI2) /* Vector 73: SSI 2 */
|
||||
VECTOR(lm_ssi3, LM_IRQ_SSI3) /* Vector 74: SSI 3 */
|
||||
VECTOR(lm_uart3, LM_IRQ_UART3) /* Vector 75: UART 3 */
|
||||
VECTOR(lm_uart4, LM_IRQ_UART4) /* Vector 76: UART 4 */
|
||||
VECTOR(lm_uart5, LM_IRQ_UART5) /* Vector 77: UART 5 */
|
||||
VECTOR(lm_uart6, LM_IRQ_UART6) /* Vector 78: UART 6 */
|
||||
VECTOR(lm_uart7, LM_IRQ_UART7) /* Vector 79: UART 7 */
|
||||
UNUSED(TIVA_RESERVED_70) /* Vector 70: Reserved */
|
||||
UNUSED(TIVA_RESERVED_71) /* Vector 71: Reserved */
|
||||
UNUSED(TIVA_RESERVED_72) /* Vector 72: Reserved */
|
||||
VECTOR(tiva_ssi2, TIVA_IRQ_SSI2) /* Vector 73: SSI 2 */
|
||||
VECTOR(tiva_ssi3, TIVA_IRQ_SSI3) /* Vector 74: SSI 3 */
|
||||
VECTOR(tiva_uart3, TIVA_IRQ_UART3) /* Vector 75: UART 3 */
|
||||
VECTOR(tiva_uart4, TIVA_IRQ_UART4) /* Vector 76: UART 4 */
|
||||
VECTOR(tiva_uart5, TIVA_IRQ_UART5) /* Vector 77: UART 5 */
|
||||
VECTOR(tiva_uart6, TIVA_IRQ_UART6) /* Vector 78: UART 6 */
|
||||
VECTOR(tiva_uart7, TIVA_IRQ_UART7) /* Vector 79: UART 7 */
|
||||
|
||||
UNUSED(LM_RESERVED_80) /* Vector 80: Reserved */
|
||||
UNUSED(LM_RESERVED_81) /* Vector 81: Reserved */
|
||||
UNUSED(LM_RESERVED_82) /* Vector 82: Reserved */
|
||||
UNUSED(LM_RESERVED_83) /* Vector 83: Reserved */
|
||||
VECTOR(lm_i2c2, LM_IRQ_I2C2) /* Vector 84: I2C 2 */
|
||||
VECTOR(lm_i2c3, LM_IRQ_I2C3) /* Vector 85: I2C 3 */
|
||||
VECTOR(lm_timer4a, LM_IRQ_TIMER4A) /* Vector 86: 16/32-Bit Timer 4 A */
|
||||
VECTOR(lm_timer4b, LM_IRQ_TIMER4B) /* Vector 87: 16/32-Bit Timer 4 B */
|
||||
UNUSED(LM_RESERVED_88) /* Vector 88: Reserved */
|
||||
UNUSED(LM_RESERVED_89) /* Vector 89: Reserved */
|
||||
UNUSED(TIVA_RESERVED_80) /* Vector 80: Reserved */
|
||||
UNUSED(TIVA_RESERVED_81) /* Vector 81: Reserved */
|
||||
UNUSED(TIVA_RESERVED_82) /* Vector 82: Reserved */
|
||||
UNUSED(TIVA_RESERVED_83) /* Vector 83: Reserved */
|
||||
VECTOR(tiva_i2c2, TIVA_IRQ_I2C2) /* Vector 84: I2C 2 */
|
||||
VECTOR(tiva_i2c3, TIVA_IRQ_I2C3) /* Vector 85: I2C 3 */
|
||||
VECTOR(tiva_timer4a, TIVA_IRQ_TIMER4A) /* Vector 86: 16/32-Bit Timer 4 A */
|
||||
VECTOR(tiva_timer4b, TIVA_IRQ_TIMER4B) /* Vector 87: 16/32-Bit Timer 4 B */
|
||||
UNUSED(TIVA_RESERVED_88) /* Vector 88: Reserved */
|
||||
UNUSED(TIVA_RESERVED_89) /* Vector 89: Reserved */
|
||||
|
||||
UNUSED(LM_RESERVED_90) /* Vector 90: Reserved */
|
||||
UNUSED(LM_RESERVED_91) /* Vector 91: Reserved */
|
||||
UNUSED(LM_RESERVED_92) /* Vector 92: Reserved */
|
||||
UNUSED(LM_RESERVED_93) /* Vector 93: Reserved */
|
||||
UNUSED(LM_RESERVED_94) /* Vector 94: Reserved */
|
||||
UNUSED(LM_RESERVED_95) /* Vector 95: Reserved */
|
||||
UNUSED(LM_RESERVED_96) /* Vector 96: Reserved */
|
||||
UNUSED(LM_RESERVED_97) /* Vector 97: Reserved */
|
||||
UNUSED(LM_RESERVED_98) /* Vector 98: Reserved */
|
||||
UNUSED(LM_RESERVED_99) /* Vector 99: Reserved */
|
||||
UNUSED(TIVA_RESERVED_90) /* Vector 90: Reserved */
|
||||
UNUSED(TIVA_RESERVED_91) /* Vector 91: Reserved */
|
||||
UNUSED(TIVA_RESERVED_92) /* Vector 92: Reserved */
|
||||
UNUSED(TIVA_RESERVED_93) /* Vector 93: Reserved */
|
||||
UNUSED(TIVA_RESERVED_94) /* Vector 94: Reserved */
|
||||
UNUSED(TIVA_RESERVED_95) /* Vector 95: Reserved */
|
||||
UNUSED(TIVA_RESERVED_96) /* Vector 96: Reserved */
|
||||
UNUSED(TIVA_RESERVED_97) /* Vector 97: Reserved */
|
||||
UNUSED(TIVA_RESERVED_98) /* Vector 98: Reserved */
|
||||
UNUSED(TIVA_RESERVED_99) /* Vector 99: Reserved */
|
||||
|
||||
UNUSED(LM_RESERVED_100) /* Vector 100: Reserved */
|
||||
UNUSED(LM_RESERVED_101) /* Vector 101: Reserved */
|
||||
UNUSED(LM_RESERVED_102) /* Vector 102: Reserved */
|
||||
UNUSED(LM_RESERVED_103) /* Vector 103: Reserved */
|
||||
UNUSED(LM_RESERVED_104) /* Vector 104: Reserved */
|
||||
UNUSED(LM_RESERVED_105) /* Vector 105: Reserved */
|
||||
UNUSED(LM_RESERVED_106) /* Vector 106: Reserved */
|
||||
UNUSED(LM_RESERVED_107) /* Vector 107: Reserved */
|
||||
VECTOR(lm_timer5a, LM_IRQ_TIMER5A) /* Vector 108: 16/32-Bit Timer 5 A */
|
||||
VECTOR(lm_timer5b, LM_IRQ_TIMER5B) /* Vector 109: 16/32-Bit Timer 5 B */
|
||||
UNUSED(TIVA_RESERVED_100) /* Vector 100: Reserved */
|
||||
UNUSED(TIVA_RESERVED_101) /* Vector 101: Reserved */
|
||||
UNUSED(TIVA_RESERVED_102) /* Vector 102: Reserved */
|
||||
UNUSED(TIVA_RESERVED_103) /* Vector 103: Reserved */
|
||||
UNUSED(TIVA_RESERVED_104) /* Vector 104: Reserved */
|
||||
UNUSED(TIVA_RESERVED_105) /* Vector 105: Reserved */
|
||||
UNUSED(TIVA_RESERVED_106) /* Vector 106: Reserved */
|
||||
UNUSED(TIVA_RESERVED_107) /* Vector 107: Reserved */
|
||||
VECTOR(tiva_timer5a, TIVA_IRQ_TIMER5A) /* Vector 108: 16/32-Bit Timer 5 A */
|
||||
VECTOR(tiva_timer5b, TIVA_IRQ_TIMER5B) /* Vector 109: 16/32-Bit Timer 5 B */
|
||||
|
||||
VECTOR(lm_wtimer0a, LM_IRQ_WTIMER0A) /* Vector 110: 32/64-Bit Timer 0 A */
|
||||
VECTOR(lm_wtimer0b, LM_IRQ_WTIMER0B) /* Vector 111: 32/64-Bit Timer 0 B */
|
||||
VECTOR(lm_wtimer1a, LM_IRQ_WTIMER1A) /* Vector 112: 32/64-Bit Timer 1 A */
|
||||
VECTOR(lm_wtimer1b, LM_IRQ_WTIMER1B) /* Vector 113: 32/64-Bit Timer 1 B */
|
||||
VECTOR(lm_wtimer2a, LM_IRQ_WTIMER2A) /* Vector 114: 32/64-Bit Timer 2 A */
|
||||
VECTOR(lm_wtimer2b, LM_IRQ_WTIMER2B) /* Vector 115: 32/64-Bit Timer 2 B */
|
||||
VECTOR(lm_wtimer3a, LM_IRQ_WTIMER3A) /* Vector 116: 32/64-Bit Timer 3 A */
|
||||
VECTOR(lm_wtimer3b, LM_IRQ_WTIMER3B) /* Vector 117: 32/64-Bit Timer 3 B */
|
||||
VECTOR(lm_wtimer4a, LM_IRQ_WTIMER4A) /* Vector 118: 32/64-Bit Timer 4 A */
|
||||
VECTOR(lm_WTIMER4B, LM_IRQ_WTIMER4B) /* Vector 119: 32/64-Bit Timer 4 B */
|
||||
VECTOR(tiva_wtimer0a, TIVA_IRQ_WTIMER0A) /* Vector 110: 32/64-Bit Timer 0 A */
|
||||
VECTOR(tiva_wtimer0b, TIVA_IRQ_WTIMER0B) /* Vector 111: 32/64-Bit Timer 0 B */
|
||||
VECTOR(tiva_wtimer1a, TIVA_IRQ_WTIMER1A) /* Vector 112: 32/64-Bit Timer 1 A */
|
||||
VECTOR(tiva_wtimer1b, TIVA_IRQ_WTIMER1B) /* Vector 113: 32/64-Bit Timer 1 B */
|
||||
VECTOR(tiva_wtimer2a, TIVA_IRQ_WTIMER2A) /* Vector 114: 32/64-Bit Timer 2 A */
|
||||
VECTOR(tiva_wtimer2b, TIVA_IRQ_WTIMER2B) /* Vector 115: 32/64-Bit Timer 2 B */
|
||||
VECTOR(tiva_wtimer3a, TIVA_IRQ_WTIMER3A) /* Vector 116: 32/64-Bit Timer 3 A */
|
||||
VECTOR(tiva_wtimer3b, TIVA_IRQ_WTIMER3B) /* Vector 117: 32/64-Bit Timer 3 B */
|
||||
VECTOR(tiva_wtimer4a, TIVA_IRQ_WTIMER4A) /* Vector 118: 32/64-Bit Timer 4 A */
|
||||
VECTOR(tiva_WTIMER4B, TIVA_IRQ_WTIMER4B) /* Vector 119: 32/64-Bit Timer 4 B */
|
||||
|
||||
VECTOR(lm_wtimer5a, LM_IRQ_WTIMER5A) /* Vector 120: 32/64-Bit Timer 5 A */
|
||||
VECTOR(lm_wtimer5b, LM_IRQ_WTIMER5B) /* Vector 121: 32/64-Bit Timer 5 B */
|
||||
VECTOR(lm_system, LM_IRQ_SYSTEM) /* Vector 122: System Exception (imprecise) */
|
||||
UNUSED(LM_RESERVED_123) /* Vector 123: Reserved */
|
||||
UNUSED(LM_RESERVED_124) /* Vector 124: Reserved */
|
||||
UNUSED(LM_RESERVED_125) /* Vector 125: Reserved */
|
||||
UNUSED(LM_RESERVED_126) /* Vector 126: Reserved */
|
||||
UNUSED(LM_RESERVED_127) /* Vector 127: Reserved */
|
||||
UNUSED(LM_RESERVED_128) /* Vector 128: Reserved */
|
||||
UNUSED(LM_RESERVED_129) /* Vector 129: Reserved */
|
||||
VECTOR(tiva_wtimer5a, TIVA_IRQ_WTIMER5A) /* Vector 120: 32/64-Bit Timer 5 A */
|
||||
VECTOR(tiva_wtimer5b, TIVA_IRQ_WTIMER5B) /* Vector 121: 32/64-Bit Timer 5 B */
|
||||
VECTOR(tiva_system, TIVA_IRQ_SYSTEM) /* Vector 122: System Exception (imprecise) */
|
||||
UNUSED(TIVA_RESERVED_123) /* Vector 123: Reserved */
|
||||
UNUSED(TIVA_RESERVED_124) /* Vector 124: Reserved */
|
||||
UNUSED(TIVA_RESERVED_125) /* Vector 125: Reserved */
|
||||
UNUSED(TIVA_RESERVED_126) /* Vector 126: Reserved */
|
||||
UNUSED(TIVA_RESERVED_127) /* Vector 127: Reserved */
|
||||
UNUSED(TIVA_RESERVED_128) /* Vector 128: Reserved */
|
||||
UNUSED(TIVA_RESERVED_129) /* Vector 129: Reserved */
|
||||
|
||||
UNUSED(LM_RESERVED_130) /* Vector 130: Reserved */
|
||||
UNUSED(LM_RESERVED_131) /* Vector 131: Reserved */
|
||||
UNUSED(LM_RESERVED_132) /* Vector 132: Reserved */
|
||||
UNUSED(LM_RESERVED_133) /* Vector 133: Reserved */
|
||||
UNUSED(LM_RESERVED_134) /* Vector 134: Reserved */
|
||||
UNUSED(LM_RESERVED_135) /* Vector 135: Reserved */
|
||||
UNUSED(LM_RESERVED_136) /* Vector 136: Reserved */
|
||||
UNUSED(LM_RESERVED_137) /* Vector 137: Reserved */
|
||||
UNUSED(LM_RESERVED_138) /* Vector 138: Reserved */
|
||||
UNUSED(LM_RESERVED_139) /* Vector 139: Reserved */
|
||||
UNUSED(TIVA_RESERVED_130) /* Vector 130: Reserved */
|
||||
UNUSED(TIVA_RESERVED_131) /* Vector 131: Reserved */
|
||||
UNUSED(TIVA_RESERVED_132) /* Vector 132: Reserved */
|
||||
UNUSED(TIVA_RESERVED_133) /* Vector 133: Reserved */
|
||||
UNUSED(TIVA_RESERVED_134) /* Vector 134: Reserved */
|
||||
UNUSED(TIVA_RESERVED_135) /* Vector 135: Reserved */
|
||||
UNUSED(TIVA_RESERVED_136) /* Vector 136: Reserved */
|
||||
UNUSED(TIVA_RESERVED_137) /* Vector 137: Reserved */
|
||||
UNUSED(TIVA_RESERVED_138) /* Vector 138: Reserved */
|
||||
UNUSED(TIVA_RESERVED_139) /* Vector 139: Reserved */
|
||||
|
||||
UNUSED(LM_RESERVED_140) /* Vector 140: Reserved */
|
||||
UNUSED(LM_RESERVED_141) /* Vector 141: Reserved */
|
||||
UNUSED(LM_RESERVED_142) /* Vector 142: Reserved */
|
||||
UNUSED(LM_RESERVED_143) /* Vector 143: Reserved */
|
||||
UNUSED(LM_RESERVED_144) /* Vector 144: Reserved */
|
||||
UNUSED(LM_RESERVED_145) /* Vector 145: Reserved */
|
||||
UNUSED(LM_RESERVED_146) /* Vector 146: Reserved */
|
||||
UNUSED(LM_RESERVED_147) /* Vector 147: Reserved */
|
||||
UNUSED(LM_RESERVED_148) /* Vector 148: Reserved */
|
||||
UNUSED(LM_RESERVED_149) /* Vector 149: Reserved */
|
||||
UNUSED(TIVA_RESERVED_140) /* Vector 140: Reserved */
|
||||
UNUSED(TIVA_RESERVED_141) /* Vector 141: Reserved */
|
||||
UNUSED(TIVA_RESERVED_142) /* Vector 142: Reserved */
|
||||
UNUSED(TIVA_RESERVED_143) /* Vector 143: Reserved */
|
||||
UNUSED(TIVA_RESERVED_144) /* Vector 144: Reserved */
|
||||
UNUSED(TIVA_RESERVED_145) /* Vector 145: Reserved */
|
||||
UNUSED(TIVA_RESERVED_146) /* Vector 146: Reserved */
|
||||
UNUSED(TIVA_RESERVED_147) /* Vector 147: Reserved */
|
||||
UNUSED(TIVA_RESERVED_148) /* Vector 148: Reserved */
|
||||
UNUSED(TIVA_RESERVED_149) /* Vector 149: Reserved */
|
||||
|
||||
UNUSED(LM_RESERVED_150) /* Vector 150: Reserved */
|
||||
UNUSED(LM_RESERVED_151) /* Vector 151: Reserved */
|
||||
UNUSED(LM_RESERVED_152) /* Vector 152: Reserved */
|
||||
UNUSED(LM_RESERVED_153) /* Vector 153: Reserved */
|
||||
UNUSED(LM_RESERVED_154) /* Vector 154: Reserved */
|
||||
UNUSED(TIVA_RESERVED_150) /* Vector 150: Reserved */
|
||||
UNUSED(TIVA_RESERVED_151) /* Vector 151: Reserved */
|
||||
UNUSED(TIVA_RESERVED_152) /* Vector 152: Reserved */
|
||||
UNUSED(TIVA_RESERVED_153) /* Vector 153: Reserved */
|
||||
UNUSED(TIVA_RESERVED_154) /* Vector 154: Reserved */
|
||||
|
||||
# endif /* CONFIG_ARMV7M_CMNVECTOR */
|
||||
|
||||
|
||||
@@ -53,63 +53,63 @@
|
||||
|
||||
/* Ethernet MAC Register Offsets */
|
||||
|
||||
#define LM_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */
|
||||
#define LM_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */
|
||||
#define LM_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */
|
||||
#define LM_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */
|
||||
#define LM_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */
|
||||
#define LM_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */
|
||||
#define LM_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */
|
||||
#define LM_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */
|
||||
#define LM_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */
|
||||
#define LM_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */
|
||||
#define LM_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */
|
||||
#define LM_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */
|
||||
#define LM_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */
|
||||
#define LM_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */
|
||||
#define LM_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */
|
||||
#ifdef LM_ETHTS
|
||||
# define LM_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */
|
||||
#define TIVA_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */
|
||||
#define TIVA_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */
|
||||
#define TIVA_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */
|
||||
#define TIVA_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */
|
||||
#define TIVA_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */
|
||||
#define TIVA_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */
|
||||
#define TIVA_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */
|
||||
#define TIVA_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */
|
||||
#define TIVA_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */
|
||||
#define TIVA_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */
|
||||
#define TIVA_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */
|
||||
#define TIVA_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */
|
||||
#define TIVA_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */
|
||||
#define TIVA_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */
|
||||
#define TIVA_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */
|
||||
#ifdef TIVA_ETHTS
|
||||
# define TIVA_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */
|
||||
#endif
|
||||
|
||||
/* MII Management Register Offsets (see include/nuttx/net/mii.h) */
|
||||
|
||||
/* Ethernet Controller Register Addresses *******************************************/
|
||||
|
||||
#define LM_MAC_RIS (LM_ETHCON_BASE + LM_MAC_RIS_OFFSET)
|
||||
#define LM_MAC_IACK (LM_ETHCON_BASE + LM_MAC_IACK_OFFSET)
|
||||
#define LM_MAC_IM (LM_ETHCON_BASE + LM_MAC_IM_OFFSET)
|
||||
#define LM_MAC_RCTL (LM_ETHCON_BASE + LM_MAC_RCTL_OFFSET)
|
||||
#define LM_MAC_TCTL (LM_ETHCON_BASE + LM_MAC_TCTL_OFFSET)
|
||||
#define LM_MAC_DATA (LM_ETHCON_BASE + LM_MAC_DATA_OFFSET)
|
||||
#define LM_MAC_IA0 (LM_ETHCON_BASE + LM_MAC_IA0_OFFSET)
|
||||
#define LM_MAC_IA1 (LM_ETHCON_BASE + LM_MAC_IA1_OFFSET)
|
||||
#define LM_MAC_THR (LM_ETHCON_BASE + LM_MAC_THR_OFFSET)
|
||||
#define LM_MAC_MCTL (LM_ETHCON_BASE + LM_MAC_MCTL_OFFSET)
|
||||
#define LM_MAC_MDV (LM_ETHCON_BASE + LM_MAC_MDV_OFFSET)
|
||||
#define LM_MAC_MTXD (LM_ETHCON_BASE + LM_MAC_MTXD_OFFSET)
|
||||
#define LM_MAC_MRXD (LM_ETHCON_BASE + LM_MAC_MRXD_OFFSET)
|
||||
#define LM_MAC_NP (LM_ETHCON_BASE + LM_MAC_NP_OFFSET)
|
||||
#define LM_MAC_TR (LM_ETHCON_BASE + LM_MAC_TR_OFFSET)
|
||||
#ifdef LM_ETHTS
|
||||
# define LM_MAC_TS (LM_ETHCON_BASE + LM_MAC_TS_OFFSET)
|
||||
#define TIVA_MAC_RIS (TIVA_ETHCON_BASE + TIVA_MAC_RIS_OFFSET)
|
||||
#define TIVA_MAC_IACK (TIVA_ETHCON_BASE + TIVA_MAC_IACK_OFFSET)
|
||||
#define TIVA_MAC_IM (TIVA_ETHCON_BASE + TIVA_MAC_IM_OFFSET)
|
||||
#define TIVA_MAC_RCTL (TIVA_ETHCON_BASE + TIVA_MAC_RCTL_OFFSET)
|
||||
#define TIVA_MAC_TCTL (TIVA_ETHCON_BASE + TIVA_MAC_TCTL_OFFSET)
|
||||
#define TIVA_MAC_DATA (TIVA_ETHCON_BASE + TIVA_MAC_DATA_OFFSET)
|
||||
#define TIVA_MAC_IA0 (TIVA_ETHCON_BASE + TIVA_MAC_IA0_OFFSET)
|
||||
#define TIVA_MAC_IA1 (TIVA_ETHCON_BASE + TIVA_MAC_IA1_OFFSET)
|
||||
#define TIVA_MAC_THR (TIVA_ETHCON_BASE + TIVA_MAC_THR_OFFSET)
|
||||
#define TIVA_MAC_MCTL (TIVA_ETHCON_BASE + TIVA_MAC_MCTL_OFFSET)
|
||||
#define TIVA_MAC_MDV (TIVA_ETHCON_BASE + TIVA_MAC_MDV_OFFSET)
|
||||
#define TIVA_MAC_MTXD (TIVA_ETHCON_BASE + TIVA_MAC_MTXD_OFFSET)
|
||||
#define TIVA_MAC_MRXD (TIVA_ETHCON_BASE + TIVA_MAC_MRXD_OFFSET)
|
||||
#define TIVA_MAC_NP (TIVA_ETHCON_BASE + TIVA_MAC_NP_OFFSET)
|
||||
#define TIVA_MAC_TR (TIVA_ETHCON_BASE + TIVA_MAC_TR_OFFSET)
|
||||
#ifdef TIVA_ETHTS
|
||||
# define TIVA_MAC_TS (TIVA_ETHCON_BASE + TIVA_MAC_TS_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Memory Mapped MII Management Registers */
|
||||
|
||||
#define MAC_MII_MCR (LM_ETHCON_BASE + MII_MCR)
|
||||
#define MAC_MII_MSR (LM_ETHCON_BASE + MII_MSR)
|
||||
#define MAC_MII_PHYID1 (LM_ETHCON_BASE + MII_PHYID1)
|
||||
#define MAC_MII_PHYID2 (LM_ETHCON_BASE + MII_PHYID2)
|
||||
#define MAC_MII_ADVERTISE (LM_ETHCON_BASE + MII_ADVERTISE)
|
||||
#define MAC_MII_LPA (LM_ETHCON_BASE + MII_LPA)
|
||||
#define MAC_MII_EXPANSION (LM_ETHCON_BASE + MII_EXPANSION)
|
||||
#define MAC_MII_VSPECIFIC (LM_ETHCON_BASE + MII_LM_VSPECIFIC)
|
||||
#define MAC_MII_INTCS (LM_ETHCON_BASE + MII_LM_INTCS)
|
||||
#define MAC_MII_DIAGNOSTIC (LM_ETHCON_BASE + MII_LM_DIAGNOSTIC)
|
||||
#define MAC_MII_XCVRCONTROL (LM_ETHCON_BASE + MII_LM_XCVRCONTROL)
|
||||
#define MAC_MII_LEDCONFIG (LM_ETHCON_BASE + MII_LM_LEDCONFIG)
|
||||
#define MAC_MII_MDICONTROL (LM_ETHCON_BASE + MII_LM_MDICONTROL)
|
||||
#define MAC_MII_MCR (TIVA_ETHCON_BASE + MII_MCR)
|
||||
#define MAC_MII_MSR (TIVA_ETHCON_BASE + MII_MSR)
|
||||
#define MAC_MII_PHYID1 (TIVA_ETHCON_BASE + MII_PHYID1)
|
||||
#define MAC_MII_PHYID2 (TIVA_ETHCON_BASE + MII_PHYID2)
|
||||
#define MAC_MII_ADVERTISE (TIVA_ETHCON_BASE + MII_ADVERTISE)
|
||||
#define MAC_MII_LPA (TIVA_ETHCON_BASE + MII_LPA)
|
||||
#define MAC_MII_EXPANSION (TIVA_ETHCON_BASE + MII_EXPANSION)
|
||||
#define MAC_MII_VSPECIFIC (TIVA_ETHCON_BASE + MII_TIVA_VSPECIFIC)
|
||||
#define MAC_MII_INTCS (TIVA_ETHCON_BASE + MII_TIVA_INTCS)
|
||||
#define MAC_MII_DIAGNOSTIC (TIVA_ETHCON_BASE + MII_TIVA_DIAGNOSTIC)
|
||||
#define MAC_MII_XCVRCONTROL (TIVA_ETHCON_BASE + MII_TIVA_XCVRCONTROL)
|
||||
#define MAC_MII_LEDCONFIG (TIVA_ETHCON_BASE + MII_TIVA_LEDCONFIG)
|
||||
#define MAC_MII_MDICONTROL (TIVA_ETHCON_BASE + MII_TIVA_MDICONTROL)
|
||||
|
||||
/* Ethernet Controller Register Bit Definitions *************************************/
|
||||
|
||||
|
||||
@@ -48,81 +48,81 @@
|
||||
|
||||
/* FLASH dimensions ****************************************************************/
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM4F120)
|
||||
# define LM_FLASH_NPAGES 256
|
||||
# define LM_FLASH_PAGESIZE 1024
|
||||
#if defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM4F120) || \
|
||||
defined(CONFIG_ARCH_CHIP_LM3S8962) || defined(CONFIG_ARCH_CHIP_LM3S9B96)
|
||||
# define TIVA_FLASH_NPAGES 256
|
||||
# define TIVA_FLASH_PAGESIZE 1024
|
||||
#else
|
||||
# error "No flash dimensions defined for selected chip."
|
||||
# warning "No flash dimensions defined for selected chip."
|
||||
#endif
|
||||
|
||||
#define LM_FLASH_SIZE (LM_FLASH_NPAGES * LM_FLASH_PAGESIZE)
|
||||
|
||||
#define TIVA_FLASH_SIZE (TIVA_FLASH_NPAGES * TIVA_FLASH_PAGESIZE)
|
||||
|
||||
/* FLASH register offsets ***********************************************************/
|
||||
|
||||
/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
|
||||
* control base address of LM_FLASHCON_BASE.
|
||||
* control base address of TIVA_FLASHCON_BASE.
|
||||
*/
|
||||
|
||||
#define LM_FLASH_FMA_OFFSET 0x000 /* Flash memory address */
|
||||
#define LM_FLASH_FMD_OFFSET 0x004 /* Flash memory data */
|
||||
#define LM_FLASH_FMC_OFFSET 0x008 /* Flash memory control */
|
||||
#define LM_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */
|
||||
#define LM_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */
|
||||
#define LM_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */
|
||||
#define TIVA_FLASH_FMA_OFFSET 0x000 /* Flash memory address */
|
||||
#define TIVA_FLASH_FMD_OFFSET 0x004 /* Flash memory data */
|
||||
#define TIVA_FLASH_FMC_OFFSET 0x008 /* Flash memory control */
|
||||
#define TIVA_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */
|
||||
#define TIVA_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */
|
||||
#define TIVA_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */
|
||||
|
||||
/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
|
||||
* System Control base address of LM_SYSCON_BASE
|
||||
* System Control base address of TIVA_SYSCON_BASE
|
||||
*/
|
||||
|
||||
#define LM_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */
|
||||
#define LM_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */
|
||||
#define LM_FLASH_USECRL_OFFSET 0x140 /* USec Reload */
|
||||
#define LM_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */
|
||||
#define LM_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */
|
||||
#define LM_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */
|
||||
#define LM_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */
|
||||
#define LM_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */
|
||||
#define LM_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */
|
||||
#define LM_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */
|
||||
#define LM_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */
|
||||
#define LM_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */
|
||||
#define LM_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */
|
||||
#define LM_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */
|
||||
#define TIVA_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */
|
||||
#define TIVA_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */
|
||||
#define TIVA_FLASH_USECRL_OFFSET 0x140 /* USec Reload */
|
||||
#define TIVA_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */
|
||||
#define TIVA_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */
|
||||
#define TIVA_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */
|
||||
#define TIVA_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */
|
||||
#define TIVA_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */
|
||||
#define TIVA_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */
|
||||
#define TIVA_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */
|
||||
#define TIVA_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */
|
||||
#define TIVA_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */
|
||||
#define TIVA_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */
|
||||
#define TIVA_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */
|
||||
|
||||
/* FLASH register addresses *********************************************************/
|
||||
|
||||
/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
|
||||
* control base address of LM_FLASHCON_BASE.
|
||||
* control base address of TIVA_FLASHCON_BASE.
|
||||
*/
|
||||
|
||||
#define LM_FLASH_FMA (LM_FLASHCON_BASE + LM_FLASH_FMA_OFFSET)
|
||||
#define LM_FLASH_FMD (LM_FLASHCON_BASE + LM_FLASH_FMD_OFFSET)
|
||||
#define LM_FLASH_FMC (LM_FLASHCON_BASE + LM_FLASH_FMC_OFFSET)
|
||||
#define LM_FLASH_FCRIS (LM_FLASHCON_BASE + LM_FLASH_FCRIS_OFFSET)
|
||||
#define LM_FLASH_FCIM (LM_FLASHCON_BASE + LM_FLASH_FCIM_OFFSET)
|
||||
#define LM_FLASH_FCMISC (LM_FLASHCON_BASE + LM_FLASH_FCMISC_OFFSET)
|
||||
#define TIVA_FLASH_FMA (TIVA_FLASHCON_BASE + TIVA_FLASH_FMA_OFFSET)
|
||||
#define TIVA_FLASH_FMD (TIVA_FLASHCON_BASE + TIVA_FLASH_FMD_OFFSET)
|
||||
#define TIVA_FLASH_FMC (TIVA_FLASHCON_BASE + TIVA_FLASH_FMC_OFFSET)
|
||||
#define TIVA_FLASH_FCRIS (TIVA_FLASHCON_BASE + TIVA_FLASH_FCRIS_OFFSET)
|
||||
#define TIVA_FLASH_FCIM (TIVA_FLASHCON_BASE + TIVA_FLASH_FCIM_OFFSET)
|
||||
#define TIVA_FLASH_FCMISC (TIVA_FLASHCON_BASE + TIVA_FLASH_FCMISC_OFFSET)
|
||||
|
||||
/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
|
||||
* System Control base address of LM_SYSCON_BASE
|
||||
* System Control base address of TIVA_SYSCON_BASE
|
||||
*/
|
||||
|
||||
#define LM_FLASH_FMPRE (LM_SYSCON_BASE + LM_FLASH_FMPRE_OFFSET)
|
||||
#define LM_FLASH_FMPPE (LM_SYSCON_BASE + LM_FLASH_FMPPE_OFFSET)
|
||||
#define LM_FLASH_USECRL (LM_SYSCON_BASE + LM_FLASH_USECRL_OFFSET)
|
||||
#define LM_FLASH_USERDBG (LM_SYSCON_BASE + LM_FLASH_USERDBG_OFFSET)
|
||||
#define LM_FLASH_USERREG0 (LM_SYSCON_BASE + LM_FLASH_USERREG0_OFFSET)
|
||||
#define LM_FLASH_USERREG1 (LM_SYSCON_BASE + LM_FLASH_USERREG1_OFFSET)
|
||||
#define LM_FLASH_FMPRE0 (LM_SYSCON_BASE + LM_FLASH_FMPRE0_OFFSET)
|
||||
#define LM_FLASH_FMPRE1 (LM_SYSCON_BASE + LM_FLASH_FMPRE1_OFFSET)
|
||||
#define LM_FLASH_FMPRE2 (LM_SYSCON_BASE + LM_FLASH_FMPRE2_OFFSET)
|
||||
#define LM_FLASH_FMPRE3 (LM_SYSCON_BASE + LM_FLASH_FMPRE3_OFFSET)
|
||||
#define LM_FLASH_FMPPE0 (LM_SYSCON_BASE + LM_FLASH_FMPPE0_OFFSET)
|
||||
#define LM_FLASH_FMPPE1 (LM_SYSCON_BASE + LM_FLASH_FMPPE1_OFFSET)
|
||||
#define LM_FLASH_FMPPE2 (LM_SYSCON_BASE + LM_FLASH_FMPPE2_OFFSET)
|
||||
#define LM_FLASH_FMPPE3 (LM_SYSCON_BASE + LM_FLASH_FMPPE3_OFFSET)
|
||||
#define TIVA_FLASH_FMPRE (TIVA_SYSCON_BASE + TIVA_FLASH_FMPRE_OFFSET)
|
||||
#define TIVA_FLASH_FMPPE (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE_OFFSET)
|
||||
#define TIVA_FLASH_USECRL (TIVA_SYSCON_BASE + TIVA_FLASH_USECRL_OFFSET)
|
||||
#define TIVA_FLASH_USERDBG (TIVA_SYSCON_BASE + TIVA_FLASH_USERDBG_OFFSET)
|
||||
#define TIVA_FLASH_USERREG0 (TIVA_SYSCON_BASE + TIVA_FLASH_USERREG0_OFFSET)
|
||||
#define TIVA_FLASH_USERREG1 (TIVA_SYSCON_BASE + TIVA_FLASH_USERREG1_OFFSET)
|
||||
#define TIVA_FLASH_FMPRE0 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPRE0_OFFSET)
|
||||
#define TIVA_FLASH_FMPRE1 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPRE1_OFFSET)
|
||||
#define TIVA_FLASH_FMPRE2 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPRE2_OFFSET)
|
||||
#define TIVA_FLASH_FMPRE3 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPRE3_OFFSET)
|
||||
#define TIVA_FLASH_FMPPE0 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE0_OFFSET)
|
||||
#define TIVA_FLASH_FMPPE1 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE1_OFFSET)
|
||||
#define TIVA_FLASH_FMPPE2 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE2_OFFSET)
|
||||
#define TIVA_FLASH_FMPPE3 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE3_OFFSET)
|
||||
|
||||
/* FLASH register bit defitiions ****************************************************/
|
||||
/* FLASH register bit definitions ***************************************************/
|
||||
|
||||
#define FLASH_FMA_OFFSET_SHIFT 0 /* Bits 17-0: Address Offset */
|
||||
#define FLASH_FMA_OFFSET_MASK (0x0003ffff << FLASH_FMA_OFFSET_SHIFT)
|
||||
@@ -141,7 +141,6 @@
|
||||
#define FLASH_FMC_WRKEY_MASK (0xffff << FLASH_FMC_WRKEY_SHIFT)
|
||||
#define FLASH_FMC_WRKEY (0xa442 << FLASH_FMC_WRKEY_SHIFT) /* Magic write key */
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
+370
-370
File diff suppressed because it is too large
Load Diff
@@ -50,99 +50,99 @@
|
||||
|
||||
/* I2C Master */
|
||||
|
||||
#define LM_I2CM_SA_OFFSET 0x000 /* I2C Master Slave Address */
|
||||
#define LM_I2CM_CS_OFFSET 0x004 /* I2C Master Control/Status */
|
||||
#define LM_I2CM_DR_OFFSET 0x008 /* I2C Master Data */
|
||||
#define LM_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */
|
||||
#define LM_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */
|
||||
#define LM_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */
|
||||
#define LM_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */
|
||||
#define LM_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */
|
||||
#define LM_I2CM_CR_OFFSET 0x020 /* I2C Master Configuration */
|
||||
#define TIVA_I2CM_SA_OFFSET 0x000 /* I2C Master Slave Address */
|
||||
#define TIVA_I2CM_CS_OFFSET 0x004 /* I2C Master Control/Status */
|
||||
#define TIVA_I2CM_DR_OFFSET 0x008 /* I2C Master Data */
|
||||
#define TIVA_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */
|
||||
#define TIVA_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */
|
||||
#define TIVA_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */
|
||||
#define TIVA_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */
|
||||
#define TIVA_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */
|
||||
#define TIVA_I2CM_CR_OFFSET 0x020 /* I2C Master Configuration */
|
||||
|
||||
/* I2C Slave */
|
||||
|
||||
#define LM_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */
|
||||
#define LM_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */
|
||||
#define LM_I2CS_DR_OFFSET 0x008 /* I2C Slave Data */
|
||||
#define LM_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */
|
||||
#define LM_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */
|
||||
#define LM_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */
|
||||
#define LM_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */
|
||||
#define TIVA_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */
|
||||
#define TIVA_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */
|
||||
#define TIVA_I2CS_DR_OFFSET 0x008 /* I2C Slave Data */
|
||||
#define TIVA_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */
|
||||
#define TIVA_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */
|
||||
#define TIVA_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */
|
||||
#define TIVA_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */
|
||||
|
||||
/* I2C Register Addresses ***********************************************************/
|
||||
|
||||
#if LM_NI2C > 0
|
||||
#if TIVA_NI2C > 0
|
||||
|
||||
/* I2C Master */
|
||||
|
||||
#define LM_I2CM_BASE(n) (LM_I2CM0_BASE + (n)*0x1000)
|
||||
#define LM_I2CM_SA(n) (LM_I2CM_BASE(n) + LM_I2CM_SA_OFFSET)
|
||||
#define LM_I2CM_CS(n) (LM_I2CM_BASE(n) + LM_I2CM_CS_OFFSET)
|
||||
#define LM_I2CM_DR(n) (LM_I2CM_BASE(n) + LM_I2CM_DR_OFFSET)
|
||||
#define LM_I2CM_TPR(n) (LM_I2CM_BASE(n) + LM_I2CM_TPR_OFFSET)
|
||||
#define LM_I2CM_IMR(n) (LM_I2CM_BASE(n) + LM_I2CM_IMR_OFFSET)
|
||||
#define LM_I2CM_RIS(n) (LM_I2CM_BASE(n) + LM_I2CM_RIS_OFFSET)
|
||||
#define LM_I2CM_MIS(n) (LM_I2CM_BASE(n) + LM_I2CM_MIS_OFFSET)
|
||||
#define LM_I2CM_ICR(n) (LM_I2CM_BASE(n) + LM_I2CM_ICR_OFFSET)
|
||||
#define LM_I2CM_CR(n) (LM_I2CM_BASE(n) + LM_I2CM_CR_OFFSET)
|
||||
#define TIVA_I2CM_BASE(n) (TIVA_I2CM0_BASE + (n)*0x1000)
|
||||
#define TIVA_I2CM_SA(n) (TIVA_I2CM_BASE(n) + TIVA_I2CM_SA_OFFSET)
|
||||
#define TIVA_I2CM_CS(n) (TIVA_I2CM_BASE(n) + TIVA_I2CM_CS_OFFSET)
|
||||
#define TIVA_I2CM_DR(n) (TIVA_I2CM_BASE(n) + TIVA_I2CM_DR_OFFSET)
|
||||
#define TIVA_I2CM_TPR(n) (TIVA_I2CM_BASE(n) + TIVA_I2CM_TPR_OFFSET)
|
||||
#define TIVA_I2CM_IMR(n) (TIVA_I2CM_BASE(n) + TIVA_I2CM_IMR_OFFSET)
|
||||
#define TIVA_I2CM_RIS(n) (TIVA_I2CM_BASE(n) + TIVA_I2CM_RIS_OFFSET)
|
||||
#define TIVA_I2CM_MIS(n) (TIVA_I2CM_BASE(n) + TIVA_I2CM_MIS_OFFSET)
|
||||
#define TIVA_I2CM_ICR(n) (TIVA_I2CM_BASE(n) + TIVA_I2CM_ICR_OFFSET)
|
||||
#define TIVA_I2CM_CR(n) (TIVA_I2CM_BASE(n) + TIVA_I2CM_CR_OFFSET)
|
||||
|
||||
/* I2C Slave */
|
||||
|
||||
#define LM_I2CS_BASE(n) (LM_I2CS0_BASE + (n)*0x1000)
|
||||
#define LM_I2CS_OAR(n) (LM_I2CS_BASE(n) + LM_I2CS_OAR_OFFSET)
|
||||
#define LM_I2CS_CSR(n) (LM_I2CS_BASE(n) + LM_I2CS_CSR_OFFSET)
|
||||
#define LM_I2CS_DR(n) (LM_I2CS_BASE(n) + LM_I2CS_DR_OFFSET)
|
||||
#define LM_I2CS_IMR(n) (LM_I2CS_BASE(n) + LM_I2CS_IMR_OFFSET)
|
||||
#define LM_I2CS_RIS(n) (LM_I2CS_BASE(n) + LM_I2CS_RIS_OFFSET)
|
||||
#define LM_I2CS_MIS(n) (LM_I2CS_BASE(n) + LM_I2CS_MIS_OFFSET)
|
||||
#define LM_I2CS_ICR(n) (LM_I2CS_BASE(n) + LM_I2CS_ICR_OFFSET)
|
||||
#define TIVA_I2CS_BASE(n) (TIVA_I2CS0_BASE + (n)*0x1000)
|
||||
#define TIVA_I2CS_OAR(n) (TIVA_I2CS_BASE(n) + TIVA_I2CS_OAR_OFFSET)
|
||||
#define TIVA_I2CS_CSR(n) (TIVA_I2CS_BASE(n) + TIVA_I2CS_CSR_OFFSET)
|
||||
#define TIVA_I2CS_DR(n) (TIVA_I2CS_BASE(n) + TIVA_I2CS_DR_OFFSET)
|
||||
#define TIVA_I2CS_IMR(n) (TIVA_I2CS_BASE(n) + TIVA_I2CS_IMR_OFFSET)
|
||||
#define TIVA_I2CS_RIS(n) (TIVA_I2CS_BASE(n) + TIVA_I2CS_RIS_OFFSET)
|
||||
#define TIVA_I2CS_MIS(n) (TIVA_I2CS_BASE(n) + TIVA_I2CS_MIS_OFFSET)
|
||||
#define TIVA_I2CS_ICR(n) (TIVA_I2CS_BASE(n) + TIVA_I2CS_ICR_OFFSET)
|
||||
|
||||
/* I2C0 Master */
|
||||
|
||||
#define LM_I2CM0_SA (LM_I2CM0_BASE + LM_I2CM_SA_OFFSET)
|
||||
#define LM_I2CM0_CS (LM_I2CM0_BASE + LM_I2CM_CS_OFFSET)
|
||||
#define LM_I2CM0_DR (LM_I2CM0_BASE + LM_I2CM_DR_OFFSET)
|
||||
#define LM_I2CM0_TPR (LM_I2CM0_BASE + LM_I2CM_TPR_OFFSET)
|
||||
#define LM_I2CM0_IMR (LM_I2CM0_BASE + LM_I2CM_IMR_OFFSET)
|
||||
#define LM_I2CM0_RIS (LM_I2CM0_BASE + LM_I2CM_RIS_OFFSET)
|
||||
#define LM_I2CM0_MIS (LM_I2CM0_BASE + LM_I2CM_MIS_OFFSET)
|
||||
#define LM_I2CM0_ICR (LM_I2CM0_BASE + LM_I2CM_ICR_OFFSET)
|
||||
#define LM_I2CM0_CR (LM_I2CM0_BASE + LM_I2CM_CR_OFFSET)
|
||||
#define TIVA_I2CM0_SA (TIVA_I2CM0_BASE + TIVA_I2CM_SA_OFFSET)
|
||||
#define TIVA_I2CM0_CS (TIVA_I2CM0_BASE + TIVA_I2CM_CS_OFFSET)
|
||||
#define TIVA_I2CM0_DR (TIVA_I2CM0_BASE + TIVA_I2CM_DR_OFFSET)
|
||||
#define TIVA_I2CM0_TPR (TIVA_I2CM0_BASE + TIVA_I2CM_TPR_OFFSET)
|
||||
#define TIVA_I2CM0_IMR (TIVA_I2CM0_BASE + TIVA_I2CM_IMR_OFFSET)
|
||||
#define TIVA_I2CM0_RIS (TIVA_I2CM0_BASE + TIVA_I2CM_RIS_OFFSET)
|
||||
#define TIVA_I2CM0_MIS (TIVA_I2CM0_BASE + TIVA_I2CM_MIS_OFFSET)
|
||||
#define TIVA_I2CM0_ICR (TIVA_I2CM0_BASE + TIVA_I2CM_ICR_OFFSET)
|
||||
#define TIVA_I2CM0_CR (TIVA_I2CM0_BASE + TIVA_I2CM_CR_OFFSET)
|
||||
|
||||
/* I2C0 Slave */
|
||||
|
||||
#define LM_I2CS0_OAR (LM_I2CS0_BASE + LM_I2CS_OAR_OFFSET)
|
||||
#define LM_I2CS0_CSR (LM_I2CS0_BASE + LM_I2CS_CSR_OFFSET)
|
||||
#define LM_I2CS0_DR (LM_I2CS0_BASE + LM_I2CS_DR_OFFSET)
|
||||
#define LM_I2CS0_IMR (LM_I2CS0_BASE + LM_I2CS_IMR_OFFSET)
|
||||
#define LM_I2CS0_RIS (LM_I2CS0_BASE + LM_I2CS_RIS_OFFSET)
|
||||
#define LM_I2CS0_MIS (LM_I2CS0_BASE + LM_I2CS_MIS_OFFSET)
|
||||
#define LM_I2CS0_ICR (LM_I2CS0_BASE + LM_I2CS_ICR_OFFSET)
|
||||
#define TIVA_I2CS0_OAR (TIVA_I2CS0_BASE + TIVA_I2CS_OAR_OFFSET)
|
||||
#define TIVA_I2CS0_CSR (TIVA_I2CS0_BASE + TIVA_I2CS_CSR_OFFSET)
|
||||
#define TIVA_I2CS0_DR (TIVA_I2CS0_BASE + TIVA_I2CS_DR_OFFSET)
|
||||
#define TIVA_I2CS0_IMR (TIVA_I2CS0_BASE + TIVA_I2CS_IMR_OFFSET)
|
||||
#define TIVA_I2CS0_RIS (TIVA_I2CS0_BASE + TIVA_I2CS_RIS_OFFSET)
|
||||
#define TIVA_I2CS0_MIS (TIVA_I2CS0_BASE + TIVA_I2CS_MIS_OFFSET)
|
||||
#define TIVA_I2CS0_ICR (TIVA_I2CS0_BASE + TIVA_I2CS_ICR_OFFSET)
|
||||
|
||||
#if LM_NI2C > 1
|
||||
#if TIVA_NI2C > 1
|
||||
|
||||
/* I2C1 Master */
|
||||
|
||||
#define LM_I2CM1_SA (LM_I2CM1_BASE + LM_I2CM_SA_OFFSET)
|
||||
#define LM_I2CM1_CS (LM_I2CM1_BASE + LM_I2CM_CS_OFFSET)
|
||||
#define LM_I2CM1_DR (LM_I2CM1_BASE + LM_I2CM_DR_OFFSET)
|
||||
#define LM_I2CM1_TPR (LM_I2CM1_BASE + LM_I2CM_TPR_OFFSET)
|
||||
#define LM_I2CM1_IMR (LM_I2CM1_BASE + LM_I2CM_IMR_OFFSET)
|
||||
#define LM_I2CM1_RIS (LM_I2CM1_BASE + LM_I2CM_RIS_OFFSET)
|
||||
#define LM_I2CM1_MIS (LM_I2CM1_BASE + LM_I2CM_MIS_OFFSET)
|
||||
#define LM_I2CM1_ICR (LM_I2CM1_BASE + LM_I2CM_ICR_OFFSET)
|
||||
#define LM_I2CM1_CR (LM_I2CM1_BASE + LM_I2CM_CR_OFFSET)
|
||||
#define TIVA_I2CM1_SA (TIVA_I2CM1_BASE + TIVA_I2CM_SA_OFFSET)
|
||||
#define TIVA_I2CM1_CS (TIVA_I2CM1_BASE + TIVA_I2CM_CS_OFFSET)
|
||||
#define TIVA_I2CM1_DR (TIVA_I2CM1_BASE + TIVA_I2CM_DR_OFFSET)
|
||||
#define TIVA_I2CM1_TPR (TIVA_I2CM1_BASE + TIVA_I2CM_TPR_OFFSET)
|
||||
#define TIVA_I2CM1_IMR (TIVA_I2CM1_BASE + TIVA_I2CM_IMR_OFFSET)
|
||||
#define TIVA_I2CM1_RIS (TIVA_I2CM1_BASE + TIVA_I2CM_RIS_OFFSET)
|
||||
#define TIVA_I2CM1_MIS (TIVA_I2CM1_BASE + TIVA_I2CM_MIS_OFFSET)
|
||||
#define TIVA_I2CM1_ICR (TIVA_I2CM1_BASE + TIVA_I2CM_ICR_OFFSET)
|
||||
#define TIVA_I2CM1_CR (TIVA_I2CM1_BASE + TIVA_I2CM_CR_OFFSET)
|
||||
|
||||
/* I2C1 Slave */
|
||||
|
||||
#define LM_I2CS1_OAR (LM_I2CS1_BASE + LM_I2CS_OAR_OFFSET)
|
||||
#define LM_I2CS1_CSR (LM_I2CS1_BASE + LM_I2CS_CSR_OFFSET)
|
||||
#define LM_I2CS1_DR (LM_I2CS1_BASE + LM_I2CS_DR_OFFSET)
|
||||
#define LM_I2CS1_IMR (LM_I2CS1_BASE + LM_I2CS_IMR_OFFSET)
|
||||
#define LM_I2CS1_RIS (LM_I2CS1_BASE + LM_I2CS_RIS_OFFSET)
|
||||
#define LM_I2CS1_MIS (LM_I2CS1_BASE + LM_I2CS_MIS_OFFSET)
|
||||
#define LM_I2CS1_ICR (LM_I2CS1_BASE + LM_I2CS_ICR_OFFSET)
|
||||
#define TIVA_I2CS1_OAR (TIVA_I2CS1_BASE + TIVA_I2CS_OAR_OFFSET)
|
||||
#define TIVA_I2CS1_CSR (TIVA_I2CS1_BASE + TIVA_I2CS_CSR_OFFSET)
|
||||
#define TIVA_I2CS1_DR (TIVA_I2CS1_BASE + TIVA_I2CS_DR_OFFSET)
|
||||
#define TIVA_I2CS1_IMR (TIVA_I2CS1_BASE + TIVA_I2CS_IMR_OFFSET)
|
||||
#define TIVA_I2CS1_RIS (TIVA_I2CS1_BASE + TIVA_I2CS_RIS_OFFSET)
|
||||
#define TIVA_I2CS1_MIS (TIVA_I2CS1_BASE + TIVA_I2CS_MIS_OFFSET)
|
||||
#define TIVA_I2CS1_ICR (TIVA_I2CS1_BASE + TIVA_I2CS_ICR_OFFSET)
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
+128
-128
@@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#if LM_NSSI > 0
|
||||
#if TIVA_NSSI > 0
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
@@ -51,173 +51,173 @@
|
||||
|
||||
/* SSI register offsets *************************************************************/
|
||||
|
||||
#define LM_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */
|
||||
#define LM_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */
|
||||
#define LM_SSI_DR_OFFSET 0x008 /* SSI Data */
|
||||
#define LM_SSI_SR_OFFSET 0x00c /* SSI Status */
|
||||
#define LM_SSI_CPSR_OFFSET 0x010 /* SSI Clock Prescale */
|
||||
#define LM_SSI_IM_OFFSET 0x014 /* SSI Interrupt Mask */
|
||||
#define LM_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */
|
||||
#define LM_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */
|
||||
#define LM_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */
|
||||
#define LM_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */
|
||||
#define LM_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */
|
||||
#define LM_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */
|
||||
#define LM_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */
|
||||
#define LM_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */
|
||||
#define LM_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */
|
||||
#define LM_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */
|
||||
#define LM_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */
|
||||
#define LM_SSI_PCELLID0_OFFSET 0xff0 /* SSI PrimeCell Identification 0 */
|
||||
#define LM_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */
|
||||
#define LM_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */
|
||||
#define LM_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */
|
||||
#define TIVA_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */
|
||||
#define TIVA_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */
|
||||
#define TIVA_SSI_DR_OFFSET 0x008 /* SSI Data */
|
||||
#define TIVA_SSI_SR_OFFSET 0x00c /* SSI Status */
|
||||
#define TIVA_SSI_CPSR_OFFSET 0x010 /* SSI Clock Prescale */
|
||||
#define TIVA_SSI_IM_OFFSET 0x014 /* SSI Interrupt Mask */
|
||||
#define TIVA_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */
|
||||
#define TIVA_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */
|
||||
#define TIVA_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */
|
||||
#define TIVA_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */
|
||||
#define TIVA_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */
|
||||
#define TIVA_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */
|
||||
#define TIVA_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */
|
||||
#define TIVA_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */
|
||||
#define TIVA_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */
|
||||
#define TIVA_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */
|
||||
#define TIVA_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */
|
||||
#define TIVA_SSI_PCELLID0_OFFSET 0xff0 /* SSI PrimeCell Identification 0 */
|
||||
#define TIVA_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */
|
||||
#define TIVA_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */
|
||||
#define TIVA_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */
|
||||
|
||||
/* SSI register addresses ***********************************************************/
|
||||
|
||||
#define LM_SSI0_CR0 (LM_SSI0_BASE + LM_SSI_CR0_OFFSET)
|
||||
#define LM_SSI0_CR1 (LM_SSI0_BASE + LM_SSI_CR1_OFFSET)
|
||||
#define LM_SSI0_DR (LM_SSI0_BASE + LM_SSI_DR_OFFSET)
|
||||
#define LM_SSI0_SR (LM_SSI0_BASE + LM_SSI_SR_OFFSET)
|
||||
#define LM_SSI0_CPSR (LM_SSI0_BASE + LM_SSI_CPSR_OFFSET)
|
||||
#define LM_SSI0_IM (LM_SSI0_BASE + LM_SSI_IM_OFFSET)
|
||||
#define LM_SSI0_RIS (LM_SSI0_BASE + LM_SSI_RIS_OFFSET)
|
||||
#define LM_SSI0_MIS (LM_SSI0_BASE + LM_SSI_MIS_OFFSET)
|
||||
#define LM_SSI0_ICR (LM_SSI0_BASE + LM_SSI_ICR_OFFSET)
|
||||
#define LM_SSI0_PERIPHID4 (LM_SSI0_BASE + LM_SSI_PERIPHID4_OFFSET)
|
||||
#define LM_SSI0_PERIPHID5 (LM_SSI0_BASE + LM_SSI_PERIPHID5_OFFSET)
|
||||
#define LM_SSI0_PERIPHID6 (LM_SSI0_BASE + LM_SSI_PERIPHID6_OFFSET)
|
||||
#define LM_SSI0_PERIPHID7 (LM_SSI0_BASE + LM_SSI_PERIPHID7_OFFSET)
|
||||
#define LM_SSI0_PERIPHID0 (LM_SSI0_BASE + LM_SSI_PERIPHID0_OFFSET)
|
||||
#define LM_SSI0_PERIPHID1 (LM_SSI0_BASE + LM_SSI_PERIPHID1_OFFSET)
|
||||
#define LM_SSI0_PERIPHID2 (LM_SSI0_BASE + LM_SSI_PERIPHID2_OFFSET)
|
||||
#define LM_SSI0_PERIPHID3 (LM_SSI0_BASE + LM_SSI_PERIPHID3_OFFSET)
|
||||
#define LM_SSI0_PCELLID0 (LM_SSI0_BASE + LM_SSI_PCELLID0_OFFSET)
|
||||
#define LM_SSI0_PCELLID1 (LM_SSI0_BASE + LM_SSI_PCELLID1_OFFSET)
|
||||
#define LM_SSI0_PCELLID2 (LM_SSI0_BASE + LM_SSI_PCELLID2_OFFSET)
|
||||
#define LM_SSI0_PCELLID3 (LM_SSI0_BASE + LM_SSI_PCELLID3_OFFSET)
|
||||
#define TIVA_SSI0_CR0 (TIVA_SSI0_BASE + TIVA_SSI_CR0_OFFSET)
|
||||
#define TIVA_SSI0_CR1 (TIVA_SSI0_BASE + TIVA_SSI_CR1_OFFSET)
|
||||
#define TIVA_SSI0_DR (TIVA_SSI0_BASE + TIVA_SSI_DR_OFFSET)
|
||||
#define TIVA_SSI0_SR (TIVA_SSI0_BASE + TIVA_SSI_SR_OFFSET)
|
||||
#define TIVA_SSI0_CPSR (TIVA_SSI0_BASE + TIVA_SSI_CPSR_OFFSET)
|
||||
#define TIVA_SSI0_IM (TIVA_SSI0_BASE + TIVA_SSI_IM_OFFSET)
|
||||
#define TIVA_SSI0_RIS (TIVA_SSI0_BASE + TIVA_SSI_RIS_OFFSET)
|
||||
#define TIVA_SSI0_MIS (TIVA_SSI0_BASE + TIVA_SSI_MIS_OFFSET)
|
||||
#define TIVA_SSI0_ICR (TIVA_SSI0_BASE + TIVA_SSI_ICR_OFFSET)
|
||||
#define TIVA_SSI0_PERIPHID4 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID4_OFFSET)
|
||||
#define TIVA_SSI0_PERIPHID5 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID5_OFFSET)
|
||||
#define TIVA_SSI0_PERIPHID6 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID6_OFFSET)
|
||||
#define TIVA_SSI0_PERIPHID7 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID7_OFFSET)
|
||||
#define TIVA_SSI0_PERIPHID0 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID0_OFFSET)
|
||||
#define TIVA_SSI0_PERIPHID1 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID1_OFFSET)
|
||||
#define TIVA_SSI0_PERIPHID2 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID2_OFFSET)
|
||||
#define TIVA_SSI0_PERIPHID3 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID3_OFFSET)
|
||||
#define TIVA_SSI0_PCELLID0 (TIVA_SSI0_BASE + TIVA_SSI_PCELLID0_OFFSET)
|
||||
#define TIVA_SSI0_PCELLID1 (TIVA_SSI0_BASE + TIVA_SSI_PCELLID1_OFFSET)
|
||||
#define TIVA_SSI0_PCELLID2 (TIVA_SSI0_BASE + TIVA_SSI_PCELLID2_OFFSET)
|
||||
#define TIVA_SSI0_PCELLID3 (TIVA_SSI0_BASE + TIVA_SSI_PCELLID3_OFFSET)
|
||||
|
||||
#if LM_NSSI > 1
|
||||
#define LM_SSI1_CR0 (LM_SSI1_BASE + LM_SSI_CR0_OFFSET)
|
||||
#define LM_SSI1_CR1 (LM_SSI1_BASE + LM_SSI_CR1_OFFSET)
|
||||
#define LM_SSI1_DR (LM_SSI1_BASE + LM_SSI_DR_OFFSET)
|
||||
#define LM_SSI1_SR (LM_SSI1_BASE + LM_SSI_SR_OFFSET)
|
||||
#define LM_SSI1_CPSR (LM_SSI1_BASE + LM_SSI_CPSR_OFFSET)
|
||||
#define LM_SSI1_IM (LM_SSI1_BASE + LM_SSI_IM_OFFSET)
|
||||
#define LM_SSI1_RIS (LM_SSI1_BASE + LM_SSI_RIS_OFFSET)
|
||||
#define LM_SSI1_MIS (LM_SSI1_BASE + LM_SSI_MIS_OFFSET)
|
||||
#define LM_SSI1_ICR (LM_SSI1_BASE + LM_SSI_ICR_OFFSET)
|
||||
#define LM_SSI1_PERIPHID4 (LM_SSI1_BASE + LM_SSI_PERIPHID4_OFFSET)
|
||||
#define LM_SSI1_PERIPHID5 (LM_SSI1_BASE + LM_SSI_PERIPHID5_OFFSET)
|
||||
#define LM_SSI1_PERIPHID6 (LM_SSI1_BASE + LM_SSI_PERIPHID6_OFFSET)
|
||||
#define LM_SSI1_PERIPHID7 (LM_SSI1_BASE + LM_SSI_PERIPHID7_OFFSET)
|
||||
#define LM_SSI1_PERIPHID0 (LM_SSI1_BASE + LM_SSI_PERIPHID0_OFFSET)
|
||||
#define LM_SSI1_PERIPHID1 (LM_SSI1_BASE + LM_SSI_PERIPHID1_OFFSET)
|
||||
#define LM_SSI1_PERIPHID2 (LM_SSI1_BASE + LM_SSI_PERIPHID2_OFFSET)
|
||||
#define LM_SSI1_PERIPHID3 (LM_SSI1_BASE + LM_SSI_PERIPHID3_OFFSET)
|
||||
#define LM_SSI1_PCELLID0 (LM_SSI1_BASE + LM_SSI_PCELLID0_OFFSET)
|
||||
#define LM_SSI1_PCELLID1 (LM_SSI1_BASE + LM_SSI_PCELLID1_OFFSET)
|
||||
#define LM_SSI1_PCELLID2 (LM_SSI1_BASE + LM_SSI_PCELLID2_OFFSET)
|
||||
#define LM_SSI1_PCELLID3 (LM_SSI1_BASE + LM_SSI_PCELLID3_OFFSET)
|
||||
#if TIVA_NSSI > 1
|
||||
#define TIVA_SSI1_CR0 (TIVA_SSI1_BASE + TIVA_SSI_CR0_OFFSET)
|
||||
#define TIVA_SSI1_CR1 (TIVA_SSI1_BASE + TIVA_SSI_CR1_OFFSET)
|
||||
#define TIVA_SSI1_DR (TIVA_SSI1_BASE + TIVA_SSI_DR_OFFSET)
|
||||
#define TIVA_SSI1_SR (TIVA_SSI1_BASE + TIVA_SSI_SR_OFFSET)
|
||||
#define TIVA_SSI1_CPSR (TIVA_SSI1_BASE + TIVA_SSI_CPSR_OFFSET)
|
||||
#define TIVA_SSI1_IM (TIVA_SSI1_BASE + TIVA_SSI_IM_OFFSET)
|
||||
#define TIVA_SSI1_RIS (TIVA_SSI1_BASE + TIVA_SSI_RIS_OFFSET)
|
||||
#define TIVA_SSI1_MIS (TIVA_SSI1_BASE + TIVA_SSI_MIS_OFFSET)
|
||||
#define TIVA_SSI1_ICR (TIVA_SSI1_BASE + TIVA_SSI_ICR_OFFSET)
|
||||
#define TIVA_SSI1_PERIPHID4 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID4_OFFSET)
|
||||
#define TIVA_SSI1_PERIPHID5 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID5_OFFSET)
|
||||
#define TIVA_SSI1_PERIPHID6 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID6_OFFSET)
|
||||
#define TIVA_SSI1_PERIPHID7 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID7_OFFSET)
|
||||
#define TIVA_SSI1_PERIPHID0 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID0_OFFSET)
|
||||
#define TIVA_SSI1_PERIPHID1 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID1_OFFSET)
|
||||
#define TIVA_SSI1_PERIPHID2 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID2_OFFSET)
|
||||
#define TIVA_SSI1_PERIPHID3 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID3_OFFSET)
|
||||
#define TIVA_SSI1_PCELLID0 (TIVA_SSI1_BASE + TIVA_SSI_PCELLID0_OFFSET)
|
||||
#define TIVA_SSI1_PCELLID1 (TIVA_SSI1_BASE + TIVA_SSI_PCELLID1_OFFSET)
|
||||
#define TIVA_SSI1_PCELLID2 (TIVA_SSI1_BASE + TIVA_SSI_PCELLID2_OFFSET)
|
||||
#define TIVA_SSI1_PCELLID3 (TIVA_SSI1_BASE + TIVA_SSI_PCELLID3_OFFSET)
|
||||
|
||||
#define LM_SSI_BASE(n) (LM_SSI0_BASE + (n)*0x01000)
|
||||
#define TIVA_SSI_BASE(n) (TIVA_SSI0_BASE + (n)*0x01000)
|
||||
|
||||
#define LM_SSI_CR0(n) (LM_SSI_BASE(n) + LM_SSI_CR0_OFFSET)
|
||||
#define LM_SSI_CR1(n) (LM_SSI_BASE(n) + LM_SSI_CR1_OFFSET)
|
||||
#define LM_SSI_DR(n) (LM_SSI_BASE(n) + LM_SSI_DR_OFFSET)
|
||||
#define LM_SSI_SR(n) (LM_SSI_BASE(n) + LM_SSI_SR_OFFSET)
|
||||
#define LM_SSI_CPSR(n) (LM_SSI_BASE(n) + LM_SSI_CPSR_OFFSET)
|
||||
#define LM_SSI_IM(n) (LM_SSI_BASE(n) + LM_SSI_IM_OFFSET)
|
||||
#define LM_SSI_RIS(n) (LM_SSI_BASE(n) + LM_SSI_RIS_OFFSET)
|
||||
#define LM_SSI_MIS(n) (LM_SSI_BASE(n) + LM_SSI_MIS_OFFSET)
|
||||
#define LM_SSI_ICR(n) (LM_SSI_BASE(n) + LM_SSI_ICR_OFFSET)
|
||||
#define LM_SSI_PERIPHID4(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID4_OFFSET)
|
||||
#define LM_SSI_PERIPHID5(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID5_OFFSET)
|
||||
#define LM_SSI_PERIPHID6(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID6_OFFSET)
|
||||
#define LM_SSI_PERIPHID7(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID7_OFFSET)
|
||||
#define LM_SSI_PERIPHID0(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID0_OFFSET)
|
||||
#define LM_SSI_PERIPHID1(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID1_OFFSET)
|
||||
#define LM_SSI_PERIPHID2(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID2_OFFSET)
|
||||
#define LM_SSI_PERIPHID3(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID3_OFFSET)
|
||||
#define LM_SSI_PCELLID0(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID0_OFFSET)
|
||||
#define LM_SSI_PCELLID1(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID1_OFFSET)
|
||||
#define LM_SSI_PCELLID2(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID2_OFFSET)
|
||||
#define LM_SSI_PCELLID3(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID3_OFFSET)
|
||||
#endif /* LM_NSSI > 1 */
|
||||
#define TIVA_SSI_CR0(n) (TIVA_SSI_BASE(n) + TIVA_SSI_CR0_OFFSET)
|
||||
#define TIVA_SSI_CR1(n) (TIVA_SSI_BASE(n) + TIVA_SSI_CR1_OFFSET)
|
||||
#define TIVA_SSI_DR(n) (TIVA_SSI_BASE(n) + TIVA_SSI_DR_OFFSET)
|
||||
#define TIVA_SSI_SR(n) (TIVA_SSI_BASE(n) + TIVA_SSI_SR_OFFSET)
|
||||
#define TIVA_SSI_CPSR(n) (TIVA_SSI_BASE(n) + TIVA_SSI_CPSR_OFFSET)
|
||||
#define TIVA_SSI_IM(n) (TIVA_SSI_BASE(n) + TIVA_SSI_IM_OFFSET)
|
||||
#define TIVA_SSI_RIS(n) (TIVA_SSI_BASE(n) + TIVA_SSI_RIS_OFFSET)
|
||||
#define TIVA_SSI_MIS(n) (TIVA_SSI_BASE(n) + TIVA_SSI_MIS_OFFSET)
|
||||
#define TIVA_SSI_ICR(n) (TIVA_SSI_BASE(n) + TIVA_SSI_ICR_OFFSET)
|
||||
#define TIVA_SSI_PERIPHID4(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID4_OFFSET)
|
||||
#define TIVA_SSI_PERIPHID5(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID5_OFFSET)
|
||||
#define TIVA_SSI_PERIPHID6(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID6_OFFSET)
|
||||
#define TIVA_SSI_PERIPHID7(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID7_OFFSET)
|
||||
#define TIVA_SSI_PERIPHID0(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID0_OFFSET)
|
||||
#define TIVA_SSI_PERIPHID1(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID1_OFFSET)
|
||||
#define TIVA_SSI_PERIPHID2(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID2_OFFSET)
|
||||
#define TIVA_SSI_PERIPHID3(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID3_OFFSET)
|
||||
#define TIVA_SSI_PCELLID0(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PCELLID0_OFFSET)
|
||||
#define TIVA_SSI_PCELLID1(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PCELLID1_OFFSET)
|
||||
#define TIVA_SSI_PCELLID2(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PCELLID2_OFFSET)
|
||||
#define TIVA_SSI_PCELLID3(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PCELLID3_OFFSET)
|
||||
#endif /* TIVA_NSSI > 1 */
|
||||
|
||||
/* SSI register bit defitiions ******************************************************/
|
||||
|
||||
/* SSI Control 0 (SSICR0), offset 0x000 */
|
||||
|
||||
#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */
|
||||
#define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT)
|
||||
#define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */
|
||||
#define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */
|
||||
#define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT)
|
||||
#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */
|
||||
#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */
|
||||
#define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */
|
||||
#define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */
|
||||
#define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */
|
||||
#define SSI_CR0_SCR_SHIFT 8 /* Bits 15-8: SSI Serial Clock Rate */
|
||||
#define SSI_CR0_SCR_MASK (0xff << SSI_CR0_SCR_SHIFT)
|
||||
#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */
|
||||
#define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT)
|
||||
#define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */
|
||||
#define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */
|
||||
#define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT)
|
||||
#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */
|
||||
#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */
|
||||
#define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */
|
||||
#define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */
|
||||
#define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */
|
||||
#define SSI_CR0_SCR_SHIFT 8 /* Bits 15-8: SSI Serial Clock Rate */
|
||||
#define SSI_CR0_SCR_MASK (0xff << SSI_CR0_SCR_SHIFT)
|
||||
|
||||
/* SSI Control 1 (SSICR1), offset 0x004 */
|
||||
|
||||
#define SSI_CR1_LBM (1 << 0) /* Bit 0: SSI Loopback Mode */
|
||||
#define SSI_CR1_SSE (1 << 1) /* Bit 1: SSI Synchronous Serial Port Enable */
|
||||
#define SSI_CR1_MS (1 << 2) /* Bit 2: SSI Master/Slave Select slave */
|
||||
#define SSI_CR1_SOD (1 << 3) /* Bit 3: SSI Slave Mode Output Disable */
|
||||
#define SSI_CR1_LBM (1 << 0) /* Bit 0: SSI Loopback Mode */
|
||||
#define SSI_CR1_SSE (1 << 1) /* Bit 1: SSI Synchronous Serial Port Enable */
|
||||
#define SSI_CR1_MS (1 << 2) /* Bit 2: SSI Master/Slave Select slave */
|
||||
#define SSI_CR1_SOD (1 << 3) /* Bit 3: SSI Slave Mode Output Disable */
|
||||
|
||||
/* SSI Data (SSIDR), offset 0x008 */
|
||||
|
||||
#define SSI_DR_MASK 0xffff /* Bits 15-0: SSI data */
|
||||
#define SSI_DR_MASK 0xffff /* Bits 15-0: SSI data */
|
||||
|
||||
/* SSI Status (SSISR), offset 0x00c */
|
||||
|
||||
#define SSI_SR_TFE (1 << 0) /* Bit 0: SSI Transmit FIFO Empty */
|
||||
#define SSI_SR_TNF (1 << 1) /* Bit 1: SSI Transmit FIFO Not Full */
|
||||
#define SSI_SR_RNE (1 << 2) /* Bit 2: SSI Receive FIFO Not Empty */
|
||||
#define SSI_SR_RFF (1 << 3) /* Bit 3: SSI Receive FIFO Full */
|
||||
#define SSI_SR_BSY (1 << 4) /* Bit 4: SSI Busy Bit */
|
||||
#define SSI_SR_TFE (1 << 0) /* Bit 0: SSI Transmit FIFO Empty */
|
||||
#define SSI_SR_TNF (1 << 1) /* Bit 1: SSI Transmit FIFO Not Full */
|
||||
#define SSI_SR_RNE (1 << 2) /* Bit 2: SSI Receive FIFO Not Empty */
|
||||
#define SSI_SR_RFF (1 << 3) /* Bit 3: SSI Receive FIFO Full */
|
||||
#define SSI_SR_BSY (1 << 4) /* Bit 4: SSI Busy Bit */
|
||||
|
||||
/* SSI Clock Prescale (SSICPSR), offset 0x010 */
|
||||
|
||||
#define SSI_CPSR_DIV_MASK 0xff /* Bits 7-0: SSI Clock Prescale Divisor */
|
||||
#define SSI_CPSR_DIV_MASK 0xff /* Bits 7-0: SSI Clock Prescale Divisor */
|
||||
|
||||
/* SSI Interrupt Mask (SSIIM), offset 0x014 */
|
||||
|
||||
#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */
|
||||
#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */
|
||||
#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */
|
||||
#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */
|
||||
#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */
|
||||
#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */
|
||||
#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */
|
||||
#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */
|
||||
|
||||
/* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */
|
||||
|
||||
#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */
|
||||
#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */
|
||||
#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */
|
||||
#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */
|
||||
#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */
|
||||
#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */
|
||||
#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */
|
||||
#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */
|
||||
|
||||
/* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */
|
||||
|
||||
#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */
|
||||
#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */
|
||||
#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */
|
||||
#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */
|
||||
#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */
|
||||
#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */
|
||||
#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */
|
||||
#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */
|
||||
|
||||
/* SSI Interrupt Clear (SSIICR), offset 0x020 */
|
||||
|
||||
#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */
|
||||
#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */
|
||||
#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */
|
||||
#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */
|
||||
|
||||
/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */
|
||||
|
||||
#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */
|
||||
#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */
|
||||
|
||||
/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */
|
||||
|
||||
#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */
|
||||
#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
@@ -231,5 +231,5 @@
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* LM_NSSI > 0 */
|
||||
#endif /* TIVA_NSSI > 0 */
|
||||
#endif /* __ARCH_ARM_SRC_TIVA_CHIP_TIVA_SSI_H */
|
||||
|
||||
@@ -46,29 +46,29 @@
|
||||
|
||||
/* Timer register offsets ***********************************************************/
|
||||
|
||||
#define LM_TIMER_GPTMCFG_OFFSET 0x000
|
||||
#define LM_TIMER_GPTMTAMR_OFFSET 0x004
|
||||
#define LM_TIMER_GPTMCTL_OFFSET 0x00c
|
||||
#define LM_TIMER_GPTMIMR_OFFSET 0x018
|
||||
#define LM_TIMER_GPTMRIS_OFFSET 0x01c
|
||||
#define LM_TIMER_GPTMICR_OFFSET 0x024
|
||||
#define LM_TIMER_GPTMTAILR_OFFSET 0x028
|
||||
#define LM_TIMER_GPTMTAR_OFFSET 0x048
|
||||
#define TIVA_TIMER_GPTMCFG_OFFSET 0x000
|
||||
#define TIVA_TIMER_GPTMTAMR_OFFSET 0x004
|
||||
#define TIVA_TIMER_GPTMCTL_OFFSET 0x00c
|
||||
#define TIVA_TIMER_GPTMIMR_OFFSET 0x018
|
||||
#define TIVA_TIMER_GPTMRIS_OFFSET 0x01c
|
||||
#define TIVA_TIMER_GPTMICR_OFFSET 0x024
|
||||
#define TIVA_TIMER_GPTMTAILR_OFFSET 0x028
|
||||
#define TIVA_TIMER_GPTMTAR_OFFSET 0x048
|
||||
|
||||
/* SSI register addresses ***********************************************************/
|
||||
|
||||
#define LM_TIMER_BASE(n) (LM_TIMER0_BASE + (n)*0x01000)
|
||||
#define TIVA_TIMER_BASE(n) (TIVA_TIMER0_BASE + (n)*0x01000)
|
||||
|
||||
#define LM_TIMER_GPTMCFG(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMCFG_OFFSET)
|
||||
#define LM_TIMER_GPTMTAMR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAMR_OFFSET)
|
||||
#define LM_TIMER_GPTMCTL(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMCTL_OFFSET)
|
||||
#define LM_TIMER_GPTMIMR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMIMR_OFFSET)
|
||||
#define LM_TIMER_GPTMRIS(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMRIS_OFFSET)
|
||||
#define LM_TIMER_GPTMICR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMICR_OFFSET)
|
||||
#define LM_TIMER_GPTMTAILR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAILR_OFFSET)
|
||||
#define LM_TIMER_GPTMTAR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAR_OFFSET)
|
||||
#define TIVA_TIMER_GPTMCFG(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMCFG_OFFSET)
|
||||
#define TIVA_TIMER_GPTMTAMR(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMTAMR_OFFSET)
|
||||
#define TIVA_TIMER_GPTMCTL(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMCTL_OFFSET)
|
||||
#define TIVA_TIMER_GPTMIMR(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMIMR_OFFSET)
|
||||
#define TIVA_TIMER_GPTMRIS(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMRIS_OFFSET)
|
||||
#define TIVA_TIMER_GPTMICR(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMICR_OFFSET)
|
||||
#define TIVA_TIMER_GPTMTAILR(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMTAILR_OFFSET)
|
||||
#define TIVA_TIMER_GPTMTAR(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMTAR_OFFSET)
|
||||
|
||||
/* SSI register bit defitiions ******************************************************/
|
||||
/* SSI register bit definitions *****************************************************/
|
||||
|
||||
/* GPTM Configuration (GPTMCFG), offset 0x000 */
|
||||
|
||||
|
||||
+105
-105
@@ -48,117 +48,117 @@
|
||||
|
||||
/* UART register offsets ************************************************************/
|
||||
|
||||
#define LM_UART_DR_OFFSET 0x000 /* UART Data */
|
||||
#define LM_UART_RSR_OFFSET 0x004 /* UART Receive Status */
|
||||
#define LM_UART_ECR_OFFSET 0x004 /* UART Error Clear */
|
||||
#define LM_UART_FR_OFFSET 0x018 /* UART Flag */
|
||||
#define LM_UART_ILPR_OFFSET 0x020 /* UART IrDA Low-Power Register */
|
||||
#define LM_UART_IBRD_OFFSET 0x024 /* UART Integer Baud-Rate Divisor*/
|
||||
#define LM_UART_FBRD_OFFSET 0x028 /* UART Fractional Baud-Rate Divisor */
|
||||
#define LM_UART_LCRH_OFFSET 0x02c /* UART Line Control */
|
||||
#define LM_UART_CTL_OFFSET 0x030 /* UART Control */
|
||||
#define LM_UART_IFLS_OFFSET 0x034 /* UART Interrupt FIFO Level Select */
|
||||
#define LM_UART_IM_OFFSET 0x038 /* UART Interrupt Mask */
|
||||
#define LM_UART_RIS_OFFSET 0x03c /* UART Raw Interrupt Status */
|
||||
#define LM_UART_MIS_OFFSET 0x040 /* UART Masked Interrupt Status */
|
||||
#define LM_UART_ICR_OFFSET 0x044 /* UART Interrupt Clear */
|
||||
#define LM_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */
|
||||
#define LM_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */
|
||||
#define LM_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */
|
||||
#define LM_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */
|
||||
#define LM_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */
|
||||
#define LM_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */
|
||||
#define LM_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */
|
||||
#define LM_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */
|
||||
#define LM_UART_PCELLID0_OFFSET 0xff0 /* UART PrimeCell Identification 0 */
|
||||
#define LM_UART_PCELLID1_OFFSET 0xff4 /* UART PrimeCell Identification 1 */
|
||||
#define LM_UART_PCELLID2_OFFSET 0xff8 /* UART PrimeCell Identification 2 */
|
||||
#define LM_UART_PCELLID3_OFFSET 0xffc /* UART PrimeCell Identification 3 */
|
||||
#define TIVA_UART_DR_OFFSET 0x000 /* UART Data */
|
||||
#define TIVA_UART_RSR_OFFSET 0x004 /* UART Receive Status */
|
||||
#define TIVA_UART_ECR_OFFSET 0x004 /* UART Error Clear */
|
||||
#define TIVA_UART_FR_OFFSET 0x018 /* UART Flag */
|
||||
#define TIVA_UART_ILPR_OFFSET 0x020 /* UART IrDA Low-Power Register */
|
||||
#define TIVA_UART_IBRD_OFFSET 0x024 /* UART Integer Baud-Rate Divisor*/
|
||||
#define TIVA_UART_FBRD_OFFSET 0x028 /* UART Fractional Baud-Rate Divisor */
|
||||
#define TIVA_UART_LCRH_OFFSET 0x02c /* UART Line Control */
|
||||
#define TIVA_UART_CTL_OFFSET 0x030 /* UART Control */
|
||||
#define TIVA_UART_IFLS_OFFSET 0x034 /* UART Interrupt FIFO Level Select */
|
||||
#define TIVA_UART_IM_OFFSET 0x038 /* UART Interrupt Mask */
|
||||
#define TIVA_UART_RIS_OFFSET 0x03c /* UART Raw Interrupt Status */
|
||||
#define TIVA_UART_MIS_OFFSET 0x040 /* UART Masked Interrupt Status */
|
||||
#define TIVA_UART_ICR_OFFSET 0x044 /* UART Interrupt Clear */
|
||||
#define TIVA_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */
|
||||
#define TIVA_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */
|
||||
#define TIVA_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */
|
||||
#define TIVA_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */
|
||||
#define TIVA_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */
|
||||
#define TIVA_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */
|
||||
#define TIVA_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */
|
||||
#define TIVA_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */
|
||||
#define TIVA_UART_PCELLID0_OFFSET 0xff0 /* UART PrimeCell Identification 0 */
|
||||
#define TIVA_UART_PCELLID1_OFFSET 0xff4 /* UART PrimeCell Identification 1 */
|
||||
#define TIVA_UART_PCELLID2_OFFSET 0xff8 /* UART PrimeCell Identification 2 */
|
||||
#define TIVA_UART_PCELLID3_OFFSET 0xffc /* UART PrimeCell Identification 3 */
|
||||
|
||||
/* UART register addresses **********************************************************/
|
||||
|
||||
#define LM_UART_BASE(n) (LM_UART0_BASE + (n)*0x01000)
|
||||
#define TIVA_UART_BASE(n) (TIVA_UART0_BASE + (n)*0x01000)
|
||||
|
||||
#define LM_UART_DR(n) (LM_UART_BASE(n) + LM_UART_DR_OFFSET)
|
||||
#define LM_UART_RSR(n) (LM_UART_BASE(n) + LM_UART_RSR_OFFSET)
|
||||
#define LM_UART_ECR(n) (LM_UART_BASE(n) + LM_UART_ECR_OFFSET)
|
||||
#define LM_UART_FR(n) (LM_UART_BASE(n) + LM_UART_FR_OFFSET)
|
||||
#define LM_UART_ILPR(n) (LM_UART_BASE(n) + LM_UART_ILPR_OFFSET)
|
||||
#define LM_UART_IBRD(n) (LM_UART_BASE(n) + LM_UART_IBRD_OFFSET)
|
||||
#define LM_UART_FBRD(n) (LM_UART_BASE(n) + LM_UART_FBRD_OFFSET)
|
||||
#define LM_UART_LCRH(n) (LM_UART_BASE(n) + LM_UART_LCRH_OFFSET)
|
||||
#define LM_UART_CTL(n) (LM_UART_BASE(n) + LM_UART_CTL_OFFSET)
|
||||
#define LM_UART_IFLS(n) (LM_UART_BASE(n) + LM_UART_IFLS_OFFSET)
|
||||
#define LM_UART_IM(n) (LM_UART_BASE(n) + LM_UART_IM_OFFSET)
|
||||
#define LM_UART_RIS(n) (LM_UART_BASE(n) + LM_UART_RIS_OFFSET)
|
||||
#define LM_UART_MIS(n) (LM_UART_BASE(n) + LM_UART_MIS_OFFSET)
|
||||
#define LM_UART_ICR(n) (LM_UART_BASE(n) + LM_UART_ICR_OFFSET)
|
||||
#define LM_UART_PERIPHID4(n) (LM_UART_BASE(n) + LM_UART_PERIPHID4_OFFSET)
|
||||
#define LM_UART_PERIPHID5(n) (LM_UART_BASE(n) + LM_UART_PERIPHID5_OFFSET)
|
||||
#define LM_UART_PERIPHID6(n) (LM_UART_BASE(n) + LM_UART_PERIPHID6_OFFSET)
|
||||
#define LM_UART_PERIPHID7(n) (LM_UART_BASE(n) + LM_UART_PERIPHID7_OFFSET)
|
||||
#define LM_UART_PERIPHID0(n) (LM_UART_BASE(n) + LM_UART_PERIPHID0_OFFSET)
|
||||
#define LM_UART_PERIPHID1(n) (LM_UART_BASE(n) + LM_UART_PERIPHID1_OFFSET)
|
||||
#define LM_UART_PERIPHID2(n) (LM_UART_BASE(n) + LM_UART_PERIPHID2_OFFSET)
|
||||
#define LM_UART_PERIPHID3(n) (LM_UART_BASE(n) + LM_UART_PERIPHID3_OFFSET)
|
||||
#define LM_UART_PCELLID0(n) (LM_UART_BASE(n) + LM_UART_PCELLID0_OFFSET)
|
||||
#define LM_UART_PCELLID1(n) (LM_UART_BASE(n) + LM_UART_PCELLID1_OFFSET)
|
||||
#define LM_UART_PCELLID2(n) (LM_UART_BASE(n) + LM_UART_PCELLID2_OFFSET)
|
||||
#define LM_UART_PCELLID3(n) (LM_UART_BASE(n) + LM_UART_PCELLID3_OFFSET)
|
||||
#define TIVA_UART_DR(n) (TIVA_UART_BASE(n) + TIVA_UART_DR_OFFSET)
|
||||
#define TIVA_UART_RSR(n) (TIVA_UART_BASE(n) + TIVA_UART_RSR_OFFSET)
|
||||
#define TIVA_UART_ECR(n) (TIVA_UART_BASE(n) + TIVA_UART_ECR_OFFSET)
|
||||
#define TIVA_UART_FR(n) (TIVA_UART_BASE(n) + TIVA_UART_FR_OFFSET)
|
||||
#define TIVA_UART_ILPR(n) (TIVA_UART_BASE(n) + TIVA_UART_ILPR_OFFSET)
|
||||
#define TIVA_UART_IBRD(n) (TIVA_UART_BASE(n) + TIVA_UART_IBRD_OFFSET)
|
||||
#define TIVA_UART_FBRD(n) (TIVA_UART_BASE(n) + TIVA_UART_FBRD_OFFSET)
|
||||
#define TIVA_UART_LCRH(n) (TIVA_UART_BASE(n) + TIVA_UART_LCRH_OFFSET)
|
||||
#define TIVA_UART_CTL(n) (TIVA_UART_BASE(n) + TIVA_UART_CTL_OFFSET)
|
||||
#define TIVA_UART_IFLS(n) (TIVA_UART_BASE(n) + TIVA_UART_IFLS_OFFSET)
|
||||
#define TIVA_UART_IM(n) (TIVA_UART_BASE(n) + TIVA_UART_IM_OFFSET)
|
||||
#define TIVA_UART_RIS(n) (TIVA_UART_BASE(n) + TIVA_UART_RIS_OFFSET)
|
||||
#define TIVA_UART_MIS(n) (TIVA_UART_BASE(n) + TIVA_UART_MIS_OFFSET)
|
||||
#define TIVA_UART_ICR(n) (TIVA_UART_BASE(n) + TIVA_UART_ICR_OFFSET)
|
||||
#define TIVA_UART_PERIPHID4(n) (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID4_OFFSET)
|
||||
#define TIVA_UART_PERIPHID5(n) (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID5_OFFSET)
|
||||
#define TIVA_UART_PERIPHID6(n) (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID6_OFFSET)
|
||||
#define TIVA_UART_PERIPHID7(n) (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID7_OFFSET)
|
||||
#define TIVA_UART_PERIPHID0(n) (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID0_OFFSET)
|
||||
#define TIVA_UART_PERIPHID1(n) (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID1_OFFSET)
|
||||
#define TIVA_UART_PERIPHID2(n) (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID2_OFFSET)
|
||||
#define TIVA_UART_PERIPHID3(n) (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID3_OFFSET)
|
||||
#define TIVA_UART_PCELLID0(n) (TIVA_UART_BASE(n) + TIVA_UART_PCELLID0_OFFSET)
|
||||
#define TIVA_UART_PCELLID1(n) (TIVA_UART_BASE(n) + TIVA_UART_PCELLID1_OFFSET)
|
||||
#define TIVA_UART_PCELLID2(n) (TIVA_UART_BASE(n) + TIVA_UART_PCELLID2_OFFSET)
|
||||
#define TIVA_UART_PCELLID3(n) (TIVA_UART_BASE(n) + TIVA_UART_PCELLID3_OFFSET)
|
||||
|
||||
#define LM_UART0_DR (LM_UART0_BASE + LM_UART_TDR_OFFSET)
|
||||
#define LM_UART0_RSR (LM_UART0_BASE + LM_UART_RSR_OFFSET)
|
||||
#define LM_UART0_ECR (LM_UART0_BASE + LM_UART_ECR_OFFSET)
|
||||
#define LM_UART0_FR (LM_UART0_BASE + LM_UART_FR_OFFSET)
|
||||
#define LM_UART0_ILPR (LM_UART0_BASE + LM_UART_ILPR_OFFSET)
|
||||
#define LM_UART0_IBRD (LM_UART0_BASE + LM_UART_IBRD_OFFSET)
|
||||
#define LM_UART0_FBRD (LM_UART0_BASE + LM_UART_FBRD_OFFSET)
|
||||
#define LM_UART0_LCRH (LM_UART0_BASE + LM_UART_LCRH_OFFSET)
|
||||
#define LM_UART0_CTL (LM_UART0_BASE + LM_UART_CTL_OFFSET)
|
||||
#define LM_UART0_IFLS (LM_UART0_BASE + LM_UART_IFLS_OFFSET)
|
||||
#define LM_UART0_IM (LM_UART0_BASE + LM_UART_IM_OFFSET)
|
||||
#define LM_UART0_RIS (LM_UART0_BASE + LM_UART_RIS_OFFSET)
|
||||
#define LM_UART0_MIS (LM_UART0_BASE + LM_UART_MIS_OFFSET)
|
||||
#define LM_UART0_ICR (LM_UART0_BASE + LM_UART_ICR_OFFSET)
|
||||
#define LM_UART0_PERIPHID4 (LM_UART0_BASE + LM_UART_PERIPHID4_OFFSET)
|
||||
#define LM_UART0_PERIPHID5 (LM_UART0_BASE + LM_UART_PERIPHID5_OFFSET)
|
||||
#define LM_UART0_PERIPHID6 (LM_UART0_BASE + LM_UART_PERIPHID6_OFFSET)
|
||||
#define LM_UART0_PERIPHID7 (LM_UART0_BASE + LM_UART_PERIPHID7_OFFSET)
|
||||
#define LM_UART0_PERIPHID0 (LM_UART0_BASE + LM_UART_PERIPHID0_OFFSET)
|
||||
#define LM_UART0_PERIPHID1 (LM_UART0_BASE + LM_UART_PERIPHID1_OFFSET)
|
||||
#define LM_UART0_PERIPHID2 (LM_UART0_BASE + LM_UART_PERIPHID2_OFFSET)
|
||||
#define LM_UART0_PERIPHID3 (LM_UART0_BASE + LM_UART_PERIPHID3_OFFSET)
|
||||
#define LM_UART0_PCELLID0 (LM_UART0_BASE + LM_UART_PCELLID0_OFFSET)
|
||||
#define LM_UART0_PCELLID1 (LM_UART0_BASE + LM_UART_PCELLID1_OFFSET)
|
||||
#define LM_UART0_PCELLID2 (LM_UART0_BASE + LM_UART_PCELLID2_OFFSET)
|
||||
#define LM_UART0_PCELLID3 (LM_UART0_BASE + LM_UART_PCELLID3_OFFSET)
|
||||
#define TIVA_UART0_DR (TIVA_UART0_BASE + TIVA_UART_TDR_OFFSET)
|
||||
#define TIVA_UART0_RSR (TIVA_UART0_BASE + TIVA_UART_RSR_OFFSET)
|
||||
#define TIVA_UART0_ECR (TIVA_UART0_BASE + TIVA_UART_ECR_OFFSET)
|
||||
#define TIVA_UART0_FR (TIVA_UART0_BASE + TIVA_UART_FR_OFFSET)
|
||||
#define TIVA_UART0_ILPR (TIVA_UART0_BASE + TIVA_UART_ILPR_OFFSET)
|
||||
#define TIVA_UART0_IBRD (TIVA_UART0_BASE + TIVA_UART_IBRD_OFFSET)
|
||||
#define TIVA_UART0_FBRD (TIVA_UART0_BASE + TIVA_UART_FBRD_OFFSET)
|
||||
#define TIVA_UART0_LCRH (TIVA_UART0_BASE + TIVA_UART_LCRH_OFFSET)
|
||||
#define TIVA_UART0_CTL (TIVA_UART0_BASE + TIVA_UART_CTL_OFFSET)
|
||||
#define TIVA_UART0_IFLS (TIVA_UART0_BASE + TIVA_UART_IFLS_OFFSET)
|
||||
#define TIVA_UART0_IM (TIVA_UART0_BASE + TIVA_UART_IM_OFFSET)
|
||||
#define TIVA_UART0_RIS (TIVA_UART0_BASE + TIVA_UART_RIS_OFFSET)
|
||||
#define TIVA_UART0_MIS (TIVA_UART0_BASE + TIVA_UART_MIS_OFFSET)
|
||||
#define TIVA_UART0_ICR (TIVA_UART0_BASE + TIVA_UART_ICR_OFFSET)
|
||||
#define TIVA_UART0_PERIPHID4 (TIVA_UART0_BASE + TIVA_UART_PERIPHID4_OFFSET)
|
||||
#define TIVA_UART0_PERIPHID5 (TIVA_UART0_BASE + TIVA_UART_PERIPHID5_OFFSET)
|
||||
#define TIVA_UART0_PERIPHID6 (TIVA_UART0_BASE + TIVA_UART_PERIPHID6_OFFSET)
|
||||
#define TIVA_UART0_PERIPHID7 (TIVA_UART0_BASE + TIVA_UART_PERIPHID7_OFFSET)
|
||||
#define TIVA_UART0_PERIPHID0 (TIVA_UART0_BASE + TIVA_UART_PERIPHID0_OFFSET)
|
||||
#define TIVA_UART0_PERIPHID1 (TIVA_UART0_BASE + TIVA_UART_PERIPHID1_OFFSET)
|
||||
#define TIVA_UART0_PERIPHID2 (TIVA_UART0_BASE + TIVA_UART_PERIPHID2_OFFSET)
|
||||
#define TIVA_UART0_PERIPHID3 (TIVA_UART0_BASE + TIVA_UART_PERIPHID3_OFFSET)
|
||||
#define TIVA_UART0_PCELLID0 (TIVA_UART0_BASE + TIVA_UART_PCELLID0_OFFSET)
|
||||
#define TIVA_UART0_PCELLID1 (TIVA_UART0_BASE + TIVA_UART_PCELLID1_OFFSET)
|
||||
#define TIVA_UART0_PCELLID2 (TIVA_UART0_BASE + TIVA_UART_PCELLID2_OFFSET)
|
||||
#define TIVA_UART0_PCELLID3 (TIVA_UART0_BASE + TIVA_UART_PCELLID3_OFFSET)
|
||||
|
||||
#define LM_UART1_DR (LM_UART1_BASE + LM_UART_DR_OFFSET)
|
||||
#define LM_UART1_RSR (LM_UART1_BASE + LM_UART_RSR_OFFSET)
|
||||
#define LM_UART1_ECR (LM_UART1_BASE + LM_UART_ECR_OFFSET)
|
||||
#define LM_UART1_FR (LM_UART1_BASE + LM_UART_FR_OFFSET)
|
||||
#define LM_UART1_ILPR (LM_UART1_BASE + LM_UART_ILPR_OFFSET)
|
||||
#define LM_UART1_IBRD (LM_UART1_BASE + LM_UART_IBRD_OFFSET)
|
||||
#define LM_UART1_FBRD (LM_UART1_BASE + LM_UART_FBRD_OFFSET)
|
||||
#define LM_UART1_LCRH (LM_UART1_BASE + LM_UART_LCRH_OFFSET)
|
||||
#define LM_UART1_CTL (LM_UART1_BASE + LM_UART_CTL_OFFSET)
|
||||
#define LM_UART1_IFLS (LM_UART1_BASE + LM_UART_IFLS_OFFSET)
|
||||
#define LM_UART1_IM (LM_UART1_BASE + LM_UART_IM_OFFSET)
|
||||
#define LM_UART1_RIS (LM_UART1_BASE + LM_UART_RIS_OFFSET)
|
||||
#define LM_UART1_MIS (LM_UART1_BASE + LM_UART_MIS_OFFSET)
|
||||
#define LM_UART1_ICR (LM_UART1_BASE + LM_UART_ICR_OFFSET)
|
||||
#define LM_UART1_PERIPHID4 (LM_UART1_BASE + LM_UART_PERIPHID4_OFFSET)
|
||||
#define LM_UART1_PERIPHID5 (LM_UART1_BASE + LM_UART_PERIPHID5_OFFSET)
|
||||
#define LM_UART1_PERIPHID6 (LM_UART1_BASE + LM_UART_PERIPHID6_OFFSET)
|
||||
#define LM_UART1_PERIPHID7 (LM_UART1_BASE + LM_UART_PERIPHID7_OFFSET)
|
||||
#define LM_UART1_PERIPHID0 (LM_UART1_BASE + LM_UART_PERIPHID0_OFFSET)
|
||||
#define LM_UART1_PERIPHID1 (LM_UART1_BASE + LM_UART_PERIPHID1_OFFSET)
|
||||
#define LM_UART1_PERIPHID2 (LM_UART1_BASE + LM_UART_PERIPHID2_OFFSET)
|
||||
#define LM_UART1_PERIPHID3 (LM_UART1_BASE + LM_UART_PERIPHID3_OFFSET)
|
||||
#define LM_UART1_PCELLID0 (LM_UART1_BASE + LM_UART_PCELLID0_OFFSET)
|
||||
#define LM_UART1_PCELLID1 (LM_UART1_BASE + LM_UART_PCELLID1_OFFSET)
|
||||
#define LM_UART1_PCELLID2 (LM_UART1_BASE + LM_UART_PCELLID2_OFFSET)
|
||||
#define LM_UART1_PCELLID3 (LM_UART1_BASE + LM_UART_PCELLID3_OFFSET)
|
||||
#define TIVA_UART1_DR (TIVA_UART1_BASE + TIVA_UART_DR_OFFSET)
|
||||
#define TIVA_UART1_RSR (TIVA_UART1_BASE + TIVA_UART_RSR_OFFSET)
|
||||
#define TIVA_UART1_ECR (TIVA_UART1_BASE + TIVA_UART_ECR_OFFSET)
|
||||
#define TIVA_UART1_FR (TIVA_UART1_BASE + TIVA_UART_FR_OFFSET)
|
||||
#define TIVA_UART1_ILPR (TIVA_UART1_BASE + TIVA_UART_ILPR_OFFSET)
|
||||
#define TIVA_UART1_IBRD (TIVA_UART1_BASE + TIVA_UART_IBRD_OFFSET)
|
||||
#define TIVA_UART1_FBRD (TIVA_UART1_BASE + TIVA_UART_FBRD_OFFSET)
|
||||
#define TIVA_UART1_LCRH (TIVA_UART1_BASE + TIVA_UART_LCRH_OFFSET)
|
||||
#define TIVA_UART1_CTL (TIVA_UART1_BASE + TIVA_UART_CTL_OFFSET)
|
||||
#define TIVA_UART1_IFLS (TIVA_UART1_BASE + TIVA_UART_IFLS_OFFSET)
|
||||
#define TIVA_UART1_IM (TIVA_UART1_BASE + TIVA_UART_IM_OFFSET)
|
||||
#define TIVA_UART1_RIS (TIVA_UART1_BASE + TIVA_UART_RIS_OFFSET)
|
||||
#define TIVA_UART1_MIS (TIVA_UART1_BASE + TIVA_UART_MIS_OFFSET)
|
||||
#define TIVA_UART1_ICR (TIVA_UART1_BASE + TIVA_UART_ICR_OFFSET)
|
||||
#define TIVA_UART1_PERIPHID4 (TIVA_UART1_BASE + TIVA_UART_PERIPHID4_OFFSET)
|
||||
#define TIVA_UART1_PERIPHID5 (TIVA_UART1_BASE + TIVA_UART_PERIPHID5_OFFSET)
|
||||
#define TIVA_UART1_PERIPHID6 (TIVA_UART1_BASE + TIVA_UART_PERIPHID6_OFFSET)
|
||||
#define TIVA_UART1_PERIPHID7 (TIVA_UART1_BASE + TIVA_UART_PERIPHID7_OFFSET)
|
||||
#define TIVA_UART1_PERIPHID0 (TIVA_UART1_BASE + TIVA_UART_PERIPHID0_OFFSET)
|
||||
#define TIVA_UART1_PERIPHID1 (TIVA_UART1_BASE + TIVA_UART_PERIPHID1_OFFSET)
|
||||
#define TIVA_UART1_PERIPHID2 (TIVA_UART1_BASE + TIVA_UART_PERIPHID2_OFFSET)
|
||||
#define TIVA_UART1_PERIPHID3 (TIVA_UART1_BASE + TIVA_UART_PERIPHID3_OFFSET)
|
||||
#define TIVA_UART1_PCELLID0 (TIVA_UART1_BASE + TIVA_UART_PCELLID0_OFFSET)
|
||||
#define TIVA_UART1_PCELLID1 (TIVA_UART1_BASE + TIVA_UART_PCELLID1_OFFSET)
|
||||
#define TIVA_UART1_PCELLID2 (TIVA_UART1_BASE + TIVA_UART_PCELLID2_OFFSET)
|
||||
#define TIVA_UART1_PCELLID3 (TIVA_UART1_BASE + TIVA_UART_PCELLID3_OFFSET)
|
||||
|
||||
/* UART register bit settings *******************************************************/
|
||||
|
||||
|
||||
@@ -60,64 +60,64 @@
|
||||
|
||||
/* NOTE: this is duplicated in tiva_gpio.c */
|
||||
|
||||
static const uintptr_t g_gpiobase[LM_NPORTS] =
|
||||
static const uintptr_t g_gpiobase[TIVA_NPORTS] =
|
||||
{
|
||||
#if LM_NPORTS > 0
|
||||
LM_GPIOA_BASE
|
||||
#if TIVA_NPORTS > 0
|
||||
TIVA_GPIOA_BASE
|
||||
#endif
|
||||
#if LM_NPORTS > 1
|
||||
, LM_GPIOB_BASE
|
||||
#if TIVA_NPORTS > 1
|
||||
, TIVA_GPIOB_BASE
|
||||
#endif
|
||||
#if LM_NPORTS > 2
|
||||
, LM_GPIOC_BASE
|
||||
#if TIVA_NPORTS > 2
|
||||
, TIVA_GPIOC_BASE
|
||||
#endif
|
||||
#if LM_NPORTS > 3
|
||||
, LM_GPIOD_BASE
|
||||
#if TIVA_NPORTS > 3
|
||||
, TIVA_GPIOD_BASE
|
||||
#endif
|
||||
#if LM_NPORTS > 4
|
||||
, LM_GPIOE_BASE
|
||||
#if TIVA_NPORTS > 4
|
||||
, TIVA_GPIOE_BASE
|
||||
#endif
|
||||
#if LM_NPORTS > 5
|
||||
, LM_GPIOF_BASE
|
||||
#if TIVA_NPORTS > 5
|
||||
, TIVA_GPIOF_BASE
|
||||
#endif
|
||||
#if LM_NPORTS > 6
|
||||
, LM_GPIOG_BASE
|
||||
#if TIVA_NPORTS > 6
|
||||
, TIVA_GPIOG_BASE
|
||||
#endif
|
||||
#if LM_NPORTS > 7
|
||||
, LM_GPIOH_BASE
|
||||
#if TIVA_NPORTS > 7
|
||||
, TIVA_GPIOH_BASE
|
||||
#endif
|
||||
#if LM_NPORTS > 8
|
||||
, LM_GPIOJ_BASE
|
||||
#if TIVA_NPORTS > 8
|
||||
, TIVA_GPIOJ_BASE
|
||||
#endif
|
||||
};
|
||||
|
||||
static const char g_portchar[LM_NPORTS] =
|
||||
static const char g_portchar[TIVA_NPORTS] =
|
||||
{
|
||||
#if LM_NPORTS > 0
|
||||
#if TIVA_NPORTS > 0
|
||||
'A'
|
||||
#endif
|
||||
#if LM_NPORTS > 1
|
||||
#if TIVA_NPORTS > 1
|
||||
, 'B'
|
||||
#endif
|
||||
#if LM_NPORTS > 2
|
||||
#if TIVA_NPORTS > 2
|
||||
, 'C'
|
||||
#endif
|
||||
#if LM_NPORTS > 3
|
||||
#if TIVA_NPORTS > 3
|
||||
, 'D'
|
||||
#endif
|
||||
#if LM_NPORTS > 4
|
||||
#if TIVA_NPORTS > 4
|
||||
, 'E'
|
||||
#endif
|
||||
#if LM_NPORTS > 5
|
||||
#if TIVA_NPORTS > 5
|
||||
, 'F'
|
||||
#endif
|
||||
#if LM_NPORTS > 6
|
||||
#if TIVA_NPORTS > 6
|
||||
, 'G'
|
||||
#endif
|
||||
#if LM_NPORTS > 7
|
||||
#if TIVA_NPORTS > 7
|
||||
, 'H'
|
||||
#endif
|
||||
#if LM_NPORTS > 8
|
||||
#if TIVA_NPORTS > 8
|
||||
, 'J'
|
||||
#endif
|
||||
};
|
||||
@@ -137,7 +137,7 @@ static const char g_portchar[LM_NPORTS] =
|
||||
|
||||
static inline uintptr_t tiva_gpiobaseaddress(int port)
|
||||
{
|
||||
return port < LM_NPORTS ? g_gpiobase[port] : 0;
|
||||
return port < TIVA_NPORTS ? g_gpiobase[port] : 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -151,7 +151,7 @@ static inline uintptr_t tiva_gpiobaseaddress(int port)
|
||||
|
||||
static inline uint8_t tiva_gpioport(int port)
|
||||
{
|
||||
return port < LM_NPORTS ? g_portchar[port] : '?';
|
||||
return port < TIVA_NPORTS ? g_portchar[port] : '?';
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -182,7 +182,7 @@ int tiva_dumpgpio(uint32_t pinset, const char *msg)
|
||||
/* The following requires exclusive access to the GPIO registers */
|
||||
|
||||
flags = irqsave();
|
||||
rcgc2 = getreg32(LM_SYSCON_RCGC2);
|
||||
rcgc2 = getreg32(TIVA_SYSCON_RCGC2);
|
||||
enabled = ((rcgc2 & SYSCON_RCGC2_GPIO(port)) != 0);
|
||||
|
||||
lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
|
||||
@@ -195,16 +195,16 @@ int tiva_dumpgpio(uint32_t pinset, const char *msg)
|
||||
if (enabled)
|
||||
{
|
||||
lldbg(" AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n",
|
||||
getreg32(base + LM_GPIO_AFSEL_OFFSET), getreg32(base + LM_GPIO_DEN_OFFSET),
|
||||
getreg32(base + LM_GPIO_DIR_OFFSET), getreg32(base + LM_GPIO_DATA_OFFSET + 0x3fc));
|
||||
getreg32(base + TIVA_GPIO_AFSEL_OFFSET), getreg32(base + TIVA_GPIO_DEN_OFFSET),
|
||||
getreg32(base + TIVA_GPIO_DIR_OFFSET), getreg32(base + TIVA_GPIO_DATA_OFFSET + 0x3fc));
|
||||
lldbg(" IS: %02x IBE: %02x IEV: %02x IM: %02x RIS: %08x MIS: %08x\n",
|
||||
getreg32(base + LM_GPIO_IEV_OFFSET), getreg32(base + LM_GPIO_IM_OFFSET),
|
||||
getreg32(base + LM_GPIO_RIS_OFFSET), getreg32(base + LM_GPIO_MIS_OFFSET));
|
||||
getreg32(base + TIVA_GPIO_IEV_OFFSET), getreg32(base + TIVA_GPIO_IM_OFFSET),
|
||||
getreg32(base + TIVA_GPIO_RIS_OFFSET), getreg32(base + TIVA_GPIO_MIS_OFFSET));
|
||||
lldbg(" 2MA: %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n",
|
||||
getreg32(base + LM_GPIO_DR2R_OFFSET), getreg32(base + LM_GPIO_DR4R_OFFSET),
|
||||
getreg32(base + LM_GPIO_DR8R_OFFSET), getreg32(base + LM_GPIO_ODR_OFFSET),
|
||||
getreg32(base + LM_GPIO_PUR_OFFSET), getreg32(base + LM_GPIO_PDR_OFFSET),
|
||||
getreg32(base + LM_GPIO_SLR_OFFSET));
|
||||
getreg32(base + TIVA_GPIO_DR2R_OFFSET), getreg32(base + TIVA_GPIO_DR4R_OFFSET),
|
||||
getreg32(base + TIVA_GPIO_DR8R_OFFSET), getreg32(base + TIVA_GPIO_ODR_OFFSET),
|
||||
getreg32(base + TIVA_GPIO_PUR_OFFSET), getreg32(base + TIVA_GPIO_PDR_OFFSET),
|
||||
getreg32(base + TIVA_GPIO_SLR_OFFSET));
|
||||
}
|
||||
irqrestore(flags);
|
||||
return OK;
|
||||
|
||||
+148
-149
File diff suppressed because it is too large
Load Diff
@@ -44,7 +44,7 @@
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#if LM_NETHCONTROLLERS > 1
|
||||
#if TIVA_NETHCONTROLLERS > 1
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@@ -99,5 +99,5 @@ int tiva_ethinitialize(int intf);
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* LM_NETHCONTROLLERS > 1 */
|
||||
#endif /* TIVA_NETHCONTROLLERS > 1 */
|
||||
#endif /* __ARCH_ARM_SRC_TIVA_TIVA_ETHERNET_H */
|
||||
|
||||
@@ -62,9 +62,9 @@
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define LM_VIRTUAL_NPAGES (LM_FLASH_NPAGES - CONFIG_LM_FLASH_STARTPAGE)
|
||||
#define LM_VIRTUAL_BASE (LM_FLASH_BASE \
|
||||
+ CONFIG_LM_FLASH_STARTPAGE * LM_FLASH_PAGESIZE)
|
||||
#define TIVA_VIRTUAL_NPAGES (TIVA_FLASH_NPAGES - CONFIG_TIVA_FLASH_STARTPAGE)
|
||||
#define TIVA_VIRTUAL_BASE (TIVA_FLASH_BASE \
|
||||
+ CONFIG_TIVA_FLASH_STARTPAGE * TIVA_FLASH_PAGESIZE)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
@@ -140,26 +140,26 @@ static int tiva_erase(FAR struct mtd_dev_s *dev, off_t startblock,
|
||||
int curpage;
|
||||
uint32_t pageaddr;
|
||||
|
||||
DEBUGASSERT(nblocks <= LM_VIRTUAL_NPAGES);
|
||||
DEBUGASSERT(nblocks <= TIVA_VIRTUAL_NPAGES);
|
||||
|
||||
for (curpage = startblock; curpage < nblocks; curpage++)
|
||||
{
|
||||
pageaddr = LM_VIRTUAL_BASE + curpage * LM_FLASH_PAGESIZE;
|
||||
pageaddr = TIVA_VIRTUAL_BASE + curpage * TIVA_FLASH_PAGESIZE;
|
||||
|
||||
fvdbg("Erase page at %08x\n", pageaddr);
|
||||
|
||||
/* set page address */
|
||||
|
||||
putreg32((pageaddr << FLASH_FMA_OFFSET_SHIFT) & FLASH_FMA_OFFSET_MASK,
|
||||
LM_FLASH_FMA);
|
||||
TIVA_FLASH_FMA);
|
||||
|
||||
/* set flash write key and erase bit */
|
||||
|
||||
putreg32(FLASH_FMC_WRKEY | FLASH_FMC_ERASE, LM_FLASH_FMC);
|
||||
putreg32(FLASH_FMC_WRKEY | FLASH_FMC_ERASE, TIVA_FLASH_FMC);
|
||||
|
||||
/* wait until erase has finished */
|
||||
|
||||
while (getreg32(LM_FLASH_FMC) & FLASH_FMC_ERASE);
|
||||
while (getreg32(TIVA_FLASH_FMC) & FLASH_FMC_ERASE);
|
||||
}
|
||||
|
||||
return OK;
|
||||
@@ -176,10 +176,10 @@ static int tiva_erase(FAR struct mtd_dev_s *dev, off_t startblock,
|
||||
static ssize_t tiva_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks,
|
||||
FAR uint8_t *buf)
|
||||
{
|
||||
DEBUGASSERT(startblock + nblocks <= LM_VIRTUAL_NPAGES);
|
||||
DEBUGASSERT(startblock + nblocks <= TIVA_VIRTUAL_NPAGES);
|
||||
|
||||
memcpy(buf, (void*)(LM_VIRTUAL_BASE + startblock * LM_FLASH_PAGESIZE),
|
||||
nblocks * LM_FLASH_PAGESIZE);
|
||||
memcpy(buf, (void*)(TIVA_VIRTUAL_BASE + startblock * TIVA_FLASH_PAGESIZE),
|
||||
nblocks * TIVA_FLASH_PAGESIZE);
|
||||
|
||||
return nblocks;
|
||||
}
|
||||
@@ -196,28 +196,28 @@ static ssize_t tiva_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t n
|
||||
FAR const uint8_t *buf)
|
||||
{
|
||||
FAR uint32_t *src = (uint32_t*)buf;
|
||||
FAR uint32_t *dst = (uint32_t*)(LM_VIRTUAL_BASE + startblock * LM_FLASH_PAGESIZE);
|
||||
FAR uint32_t *dst = (uint32_t*)(TIVA_VIRTUAL_BASE + startblock * TIVA_FLASH_PAGESIZE);
|
||||
int i;
|
||||
|
||||
DEBUGASSERT(nblocks <= LM_VIRTUAL_NPAGES);
|
||||
DEBUGASSERT(nblocks <= TIVA_VIRTUAL_NPAGES);
|
||||
|
||||
for (i = 0; i < (nblocks * LM_FLASH_PAGESIZE) >> 2; i++)
|
||||
for (i = 0; i < (nblocks * TIVA_FLASH_PAGESIZE) >> 2; i++)
|
||||
{
|
||||
/* set data to write */
|
||||
|
||||
putreg32(*src++, LM_FLASH_FMD);
|
||||
putreg32(*src++, TIVA_FLASH_FMD);
|
||||
|
||||
/* set destination address */
|
||||
|
||||
putreg32((uint32_t)dst++, LM_FLASH_FMA);
|
||||
putreg32((uint32_t)dst++, TIVA_FLASH_FMA);
|
||||
|
||||
/* start write */
|
||||
|
||||
putreg32(FLASH_FMC_WRKEY | FLASH_FMC_WRITE, LM_FLASH_FMC);
|
||||
putreg32(FLASH_FMC_WRKEY | FLASH_FMC_WRITE, TIVA_FLASH_FMC);
|
||||
|
||||
/* wait until write has finished */
|
||||
|
||||
while(getreg32(LM_FLASH_FMC) & FLASH_FMC_WRITE);
|
||||
while(getreg32(TIVA_FLASH_FMC) & FLASH_FMC_WRITE);
|
||||
}
|
||||
|
||||
return nblocks;
|
||||
@@ -234,9 +234,9 @@ static ssize_t tiva_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t n
|
||||
static ssize_t tiva_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
|
||||
FAR uint8_t *buf)
|
||||
{
|
||||
DEBUGASSERT(offset + nbytes < LM_VIRTUAL_NPAGES * LM_FLASH_PAGESIZE);
|
||||
DEBUGASSERT(offset + nbytes < TIVA_VIRTUAL_NPAGES * TIVA_FLASH_PAGESIZE);
|
||||
|
||||
memcpy(buf, (void*)(LM_VIRTUAL_BASE + offset), nbytes);
|
||||
memcpy(buf, (void*)(TIVA_VIRTUAL_BASE + offset), nbytes);
|
||||
|
||||
return nbytes;
|
||||
}
|
||||
@@ -282,9 +282,9 @@ static int tiva_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
|
||||
* appear so.
|
||||
*/
|
||||
|
||||
geo->blocksize = LM_FLASH_PAGESIZE; /* Size of one read/write block */
|
||||
geo->erasesize = LM_FLASH_PAGESIZE; /* Size of one erase block */
|
||||
geo->neraseblocks = LM_VIRTUAL_NPAGES;
|
||||
geo->blocksize = TIVA_FLASH_PAGESIZE; /* Size of one read/write block */
|
||||
geo->erasesize = TIVA_FLASH_PAGESIZE; /* Size of one erase block */
|
||||
geo->neraseblocks = TIVA_VIRTUAL_NPAGES;
|
||||
ret = OK;
|
||||
}
|
||||
}
|
||||
@@ -301,7 +301,7 @@ static int tiva_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
|
||||
* this case altogether and simply return -ENOTTY.
|
||||
*/
|
||||
|
||||
*ppv = (void*)LM_VIRTUAL_BASE;
|
||||
*ppv = (void*)TIVA_VIRTUAL_BASE;
|
||||
ret = OK;
|
||||
}
|
||||
}
|
||||
@@ -311,7 +311,7 @@ static int tiva_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
|
||||
{
|
||||
/* Erase the entire device */
|
||||
|
||||
tiva_erase(dev, 0, LM_VIRTUAL_NPAGES);
|
||||
tiva_erase(dev, 0, TIVA_VIRTUAL_NPAGES);
|
||||
|
||||
ret = OK;
|
||||
}
|
||||
|
||||
@@ -146,34 +146,34 @@ static const struct gpio_func_s g_funcbits[] =
|
||||
|
||||
/* NOTE: this is duplicated in tiva_dumpgpio.c */
|
||||
|
||||
static const uintptr_t g_gpiobase[LM_NPORTS] =
|
||||
static const uintptr_t g_gpiobase[TIVA_NPORTS] =
|
||||
{
|
||||
#if LM_NPORTS > 0
|
||||
LM_GPIOA_BASE
|
||||
#if TIVA_NPORTS > 0
|
||||
TIVA_GPIOA_BASE
|
||||
#endif
|
||||
#if LM_NPORTS > 1
|
||||
, LM_GPIOB_BASE
|
||||
#if TIVA_NPORTS > 1
|
||||
, TIVA_GPIOB_BASE
|
||||
#endif
|
||||
#if LM_NPORTS > 2
|
||||
, LM_GPIOC_BASE
|
||||
#if TIVA_NPORTS > 2
|
||||
, TIVA_GPIOC_BASE
|
||||
#endif
|
||||
#if LM_NPORTS > 3
|
||||
, LM_GPIOD_BASE
|
||||
#if TIVA_NPORTS > 3
|
||||
, TIVA_GPIOD_BASE
|
||||
#endif
|
||||
#if LM_NPORTS > 4
|
||||
, LM_GPIOE_BASE
|
||||
#if TIVA_NPORTS > 4
|
||||
, TIVA_GPIOE_BASE
|
||||
#endif
|
||||
#if LM_NPORTS > 5
|
||||
, LM_GPIOF_BASE
|
||||
#if TIVA_NPORTS > 5
|
||||
, TIVA_GPIOF_BASE
|
||||
#endif
|
||||
#if LM_NPORTS > 6
|
||||
, LM_GPIOG_BASE
|
||||
#if TIVA_NPORTS > 6
|
||||
, TIVA_GPIOG_BASE
|
||||
#endif
|
||||
#if LM_NPORTS > 7
|
||||
, LM_GPIOH_BASE
|
||||
#if TIVA_NPORTS > 7
|
||||
, TIVA_GPIOH_BASE
|
||||
#endif
|
||||
#if LM_NPORTS > 8
|
||||
, LM_GPIOJ_BASE
|
||||
#if TIVA_NPORTS > 8
|
||||
, TIVA_GPIOJ_BASE
|
||||
#endif
|
||||
};
|
||||
|
||||
@@ -197,7 +197,7 @@ static const uintptr_t g_gpiobase[LM_NPORTS] =
|
||||
static uintptr_t tiva_gpiobaseaddress(unsigned int port)
|
||||
{
|
||||
uintptr_t gpiobase = 0;
|
||||
if (port < LM_NPORTS)
|
||||
if (port < TIVA_NPORTS)
|
||||
{
|
||||
gpiobase = g_gpiobase[port];
|
||||
}
|
||||
@@ -234,10 +234,10 @@ static void tiva_gpiofunc(uint32_t base, uint32_t pinno,
|
||||
setbit = (((uint32_t)func->setbits >> ODR_SHIFT) & 1) << pinno;
|
||||
clrbit = (((uint32_t)func->clrbits >> ODR_SHIFT) & 1) << pinno;
|
||||
|
||||
regval = getreg32(base + LM_GPIO_ODR_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_ODR_OFFSET);
|
||||
regval &= ~clrbit;
|
||||
regval |= setbit;
|
||||
putreg32(regval, base + LM_GPIO_ODR_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_ODR_OFFSET);
|
||||
|
||||
/* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control
|
||||
* register. When a bit is set to 1, it enables a weak pull-up resistor on the
|
||||
@@ -250,10 +250,10 @@ static void tiva_gpiofunc(uint32_t base, uint32_t pinno,
|
||||
|
||||
if (setbit || clrbit)
|
||||
{
|
||||
regval = getreg32(base + LM_GPIO_PUR_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_PUR_OFFSET);
|
||||
regval &= ~clrbit;
|
||||
regval |= setbit;
|
||||
putreg32(regval, base + LM_GPIO_PUR_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_PUR_OFFSET);
|
||||
}
|
||||
|
||||
/* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control
|
||||
@@ -267,10 +267,10 @@ static void tiva_gpiofunc(uint32_t base, uint32_t pinno,
|
||||
|
||||
if (setbit || clrbit)
|
||||
{
|
||||
regval = getreg32(base + LM_GPIO_PDR_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_PDR_OFFSET);
|
||||
regval &= ~clrbit;
|
||||
regval |= setbit;
|
||||
putreg32(regval, base + LM_GPIO_PDR_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_PDR_OFFSET);
|
||||
}
|
||||
|
||||
/* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable
|
||||
@@ -285,10 +285,10 @@ static void tiva_gpiofunc(uint32_t base, uint32_t pinno,
|
||||
setbit = (((uint32_t)func->setbits >> DEN_SHIFT) & 1) << pinno;
|
||||
clrbit = (((uint32_t)func->clrbits >> DEN_SHIFT) & 1) << pinno;
|
||||
|
||||
regval = getreg32(base + LM_GPIO_DEN_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_DEN_OFFSET);
|
||||
regval &= ~clrbit;
|
||||
regval |= setbit;
|
||||
putreg32(regval, base + LM_GPIO_DEN_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_DEN_OFFSET);
|
||||
|
||||
/* Set/clear/ignore the GPIO DIR bit. "The GPIODIR register is the data
|
||||
* direction register. Bits set to 1 in the GPIODIR register configure
|
||||
@@ -300,10 +300,10 @@ static void tiva_gpiofunc(uint32_t base, uint32_t pinno,
|
||||
setbit = (((uint32_t)func->setbits >> DIR_SHIFT) & 1) << pinno;
|
||||
clrbit = (((uint32_t)func->clrbits >> DIR_SHIFT) & 1) << pinno;
|
||||
|
||||
regval = getreg32(base + LM_GPIO_DIR_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_DIR_OFFSET);
|
||||
regval &= ~clrbit;
|
||||
regval |= setbit;
|
||||
putreg32(regval, base + LM_GPIO_DIR_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_DIR_OFFSET);
|
||||
|
||||
/* Set/clear/ignore the GPIO AFSEL bit. "The GPIOAFSEL register is the mode
|
||||
* control select register. Writing a 1 to any bit in this register selects
|
||||
@@ -317,10 +317,10 @@ static void tiva_gpiofunc(uint32_t base, uint32_t pinno,
|
||||
setbit = (((uint32_t)func->setbits >> AFSEL_SHIFT) & 1) << pinno;
|
||||
clrbit = (((uint32_t)func->clrbits >> AFSEL_SHIFT) & 1) << pinno;
|
||||
|
||||
regval = getreg32(base + LM_GPIO_AFSEL_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_AFSEL_OFFSET);
|
||||
regval &= ~clrbit;
|
||||
regval |= setbit;
|
||||
putreg32(regval, base + LM_GPIO_AFSEL_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_AFSEL_OFFSET);
|
||||
|
||||
/* Set/clear/ignore the GPIO AMSEL bit. "The GPIOAMSEL register controls
|
||||
* isolation circuits to the analog side of a unified I/O pad. Because
|
||||
@@ -334,10 +334,10 @@ static void tiva_gpiofunc(uint32_t base, uint32_t pinno,
|
||||
setbit = (((uint32_t)func->setbits >> AMSEL_SHIFT) & 1) << pinno;
|
||||
clrbit = (((uint32_t)func->clrbits >> AMSEL_SHIFT) & 1) << pinno;
|
||||
|
||||
regval = getreg32(base + LM_GPIO_AMSEL_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_AMSEL_OFFSET);
|
||||
regval &= ~clrbit;
|
||||
regval |= setbit;
|
||||
putreg32(regval, base + LM_GPIO_AMSEL_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_AMSEL_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -374,7 +374,7 @@ static inline void tiva_gpiopadstrength(uint32_t base, uint32_t pin,
|
||||
* DRV8 bit in the GPIODR8R register are automatically cleared by hardware."
|
||||
*/
|
||||
|
||||
regoffset = LM_GPIO_DR2R_OFFSET;
|
||||
regoffset = TIVA_GPIO_DR2R_OFFSET;
|
||||
}
|
||||
break;
|
||||
|
||||
@@ -387,7 +387,7 @@ static inline void tiva_gpiopadstrength(uint32_t base, uint32_t pin,
|
||||
* in the GPIO DR8R register are automatically cleared by hardware."
|
||||
*/
|
||||
|
||||
regoffset = LM_GPIO_DR4R_OFFSET;
|
||||
regoffset = TIVA_GPIO_DR4R_OFFSET;
|
||||
}
|
||||
break;
|
||||
|
||||
@@ -412,7 +412,7 @@ static inline void tiva_gpiopadstrength(uint32_t base, uint32_t pin,
|
||||
* DRV4 bit in the GPIO DR4R register are automatically cleared by hardware."
|
||||
*/
|
||||
|
||||
regoffset = LM_GPIO_DR8R_OFFSET;
|
||||
regoffset = TIVA_GPIO_DR8R_OFFSET;
|
||||
}
|
||||
break;
|
||||
}
|
||||
@@ -423,10 +423,10 @@ static inline void tiva_gpiopadstrength(uint32_t base, uint32_t pin,
|
||||
regval |= pin;
|
||||
putreg32(regval, base + regoffset);
|
||||
|
||||
regval = getreg32(base + LM_GPIO_SLR_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_SLR_OFFSET);
|
||||
regval &= slrclr;
|
||||
regval |= slrset;
|
||||
putreg32(regval, base + LM_GPIO_SLR_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_SLR_OFFSET);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -542,10 +542,10 @@ static inline void tiva_gpiopadtype(uint32_t base, uint32_t pin,
|
||||
*/
|
||||
|
||||
#if 0 /* always overwritten by tiva_gpiofunc */
|
||||
regval = getreg32(base + LM_GPIO_ODR_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_ODR_OFFSET);
|
||||
regval &= ~odrclr;
|
||||
regval |= odrset;
|
||||
putreg32(regval, base + LM_GPIO_ODR_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_ODR_OFFSET);
|
||||
#endif
|
||||
|
||||
/* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control
|
||||
@@ -554,10 +554,10 @@ static inline void tiva_gpiopadtype(uint32_t base, uint32_t pin,
|
||||
* corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..."
|
||||
*/
|
||||
|
||||
regval = getreg32(base + LM_GPIO_PUR_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_PUR_OFFSET);
|
||||
regval &= ~purclr;
|
||||
regval |= purset;
|
||||
putreg32(regval, base + LM_GPIO_PUR_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_PUR_OFFSET);
|
||||
|
||||
/* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control
|
||||
* register. When a bit is set to 1, it enables a weak pull-down resistor on the
|
||||
@@ -565,10 +565,10 @@ static inline void tiva_gpiopadtype(uint32_t base, uint32_t pin,
|
||||
* the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..."
|
||||
*/
|
||||
|
||||
regval = getreg32(base + LM_GPIO_PDR_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_PDR_OFFSET);
|
||||
regval &= ~pdrclr;
|
||||
regval |= pdrset;
|
||||
putreg32(regval, base + LM_GPIO_PDR_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_PDR_OFFSET);
|
||||
|
||||
/* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable
|
||||
* register. By default, with the exception of the GPIO signals used for JTAG/SWD
|
||||
@@ -580,10 +580,10 @@ static inline void tiva_gpiopadtype(uint32_t base, uint32_t pin,
|
||||
*/
|
||||
|
||||
#if 0 /* always overwritten by tiva_gpiofunc */
|
||||
regval = getreg32(base + LM_GPIO_DEN_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_DEN_OFFSET);
|
||||
regval &= ~denclr;
|
||||
regval |= denset;
|
||||
putreg32(regval, base + LM_GPIO_DEN_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_DEN_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -628,18 +628,18 @@ static inline void tiva_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
|
||||
* on that pin. All bits are cleared by a reset."
|
||||
*/
|
||||
|
||||
regval = getreg32(base + LM_GPIO_IM_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_IM_OFFSET);
|
||||
regval &= ~pin;
|
||||
putreg32(regval, base + LM_GPIO_IM_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_IM_OFFSET);
|
||||
|
||||
/* "The GPIOICR register is the interrupt clear register. Writing a 1 to a bit
|
||||
* in this register clears the corresponding interrupt edge detection logic
|
||||
* register. Writing a 0 has no effect."
|
||||
*/
|
||||
|
||||
regval = getreg32(base + LM_GPIO_ICR_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_ICR_OFFSET);
|
||||
regval |= pin;
|
||||
putreg32(regval, base + LM_GPIO_ICR_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_ICR_OFFSET);
|
||||
|
||||
/* Assume rising edge */
|
||||
|
||||
@@ -695,10 +695,10 @@ static inline void tiva_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
|
||||
* by a reset.
|
||||
*/
|
||||
|
||||
regval = getreg32(base + LM_GPIO_IS_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_IS_OFFSET);
|
||||
regval &= isclr;
|
||||
regval |= isset;
|
||||
putreg32(regval, base + LM_GPIO_IS_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_IS_OFFSET);
|
||||
|
||||
/* "The GPIO IBE register is the interrupt both-edges register. When the
|
||||
* corresponding bit in the GPIO Interrupt Sense (GPIO IS) register ... is
|
||||
@@ -709,10 +709,10 @@ static inline void tiva_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
|
||||
* are cleared by a reset.
|
||||
*/
|
||||
|
||||
regval = getreg32(base + LM_GPIO_IBE_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_IBE_OFFSET);
|
||||
regval &= ibeclr;
|
||||
regval |= ibeset;
|
||||
putreg32(regval, base + LM_GPIO_IBE_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_IBE_OFFSET);
|
||||
|
||||
/* "The GPIOIEV register is the interrupt event register. Bits set to
|
||||
* High in GPIO IEV configure the corresponding pin to detect rising edges
|
||||
@@ -722,10 +722,10 @@ static inline void tiva_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
|
||||
* value in GPIOIS. All bits are cleared by a reset.
|
||||
*/
|
||||
|
||||
regval = getreg32(base + LM_GPIO_IEV_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_IEV_OFFSET);
|
||||
regval &= iveclr;
|
||||
regval |= iveset;
|
||||
putreg32(regval, base + LM_GPIO_IEV_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_IEV_OFFSET);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -758,11 +758,11 @@ static inline void tiva_portcontrol(uint32_t base, uint32_t pinno,
|
||||
|
||||
/* Set the alternate function in the port control register */
|
||||
|
||||
regval = getreg32(base + LM_GPIO_PCTL_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_PCTL_OFFSET);
|
||||
mask = GPIO_PCTL_PMC_MASK(pinno);
|
||||
regval &= ~mask;
|
||||
regval |= (alt << GPIO_PCTL_PMC_SHIFT(pinno)) & mask;
|
||||
putreg32(regval, base + LM_GPIO_PCTL_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_PCTL_OFFSET);
|
||||
}
|
||||
#else
|
||||
# define tiva_portcontrol(b,p,c,f)
|
||||
@@ -813,9 +813,9 @@ int tiva_configgpio(uint32_t cfgset)
|
||||
* in the RCGC2 register."
|
||||
*/
|
||||
|
||||
regval = getreg32(LM_SYSCON_RCGC2);
|
||||
regval = getreg32(TIVA_SYSCON_RCGC2);
|
||||
regval |= SYSCON_RCGC2_GPIO(port);
|
||||
putreg32(regval, LM_SYSCON_RCGC2);
|
||||
putreg32(regval, TIVA_SYSCON_RCGC2);
|
||||
|
||||
/* First, set the port to digital input. This is the safest state in which
|
||||
* to perform reconfiguration.
|
||||
@@ -890,7 +890,7 @@ void tiva_gpiowrite(uint32_t pinset, bool value)
|
||||
* "... All bits are cleared by a reset."
|
||||
*/
|
||||
|
||||
putreg32((uint32_t)value << pinno, base + LM_GPIO_DATA_OFFSET + (1 << (pinno + 2)));
|
||||
putreg32((uint32_t)value << pinno, base + TIVA_GPIO_DATA_OFFSET + (1 << (pinno + 2)));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -929,6 +929,5 @@ bool tiva_gpioread(uint32_t pinset, bool value)
|
||||
* are cleared by a reset."
|
||||
*/
|
||||
|
||||
return (getreg32(base + LM_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0);
|
||||
return (getreg32(base + TIVA_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0);
|
||||
}
|
||||
|
||||
|
||||
@@ -71,34 +71,34 @@ static FAR xcpt_t g_gpioirqvector[NR_GPIO_IRQS];
|
||||
|
||||
static const uintptr_t g_gpiobase[] =
|
||||
{
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
|
||||
LM_GPIOA_BASE
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOA_IRQS
|
||||
TIVA_GPIOA_BASE
|
||||
#else
|
||||
0
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
|
||||
, LM_GPIOB_BASE
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOB_IRQS
|
||||
, TIVA_GPIOB_BASE
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
|
||||
, LM_GPIOC_BASE
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOC_IRQS
|
||||
, TIVA_GPIOC_BASE
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
|
||||
, LM_GPIOD_BASE
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOD_IRQS
|
||||
, TIVA_GPIOD_BASE
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
|
||||
, LM_GPIOE_BASE
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOE_IRQS
|
||||
, TIVA_GPIOE_BASE
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
|
||||
, LM_GPIOF_BASE
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOF_IRQS
|
||||
, TIVA_GPIOF_BASE
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
|
||||
, LM_GPIOG_BASE
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOG_IRQS
|
||||
, TIVA_GPIOG_BASE
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
|
||||
, LM_GPIOH_BASE
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOH_IRQS
|
||||
, TIVA_GPIOH_BASE
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
|
||||
, LM_GPIOJ_BASE
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOJ_IRQS
|
||||
, TIVA_GPIOJ_BASE
|
||||
#endif
|
||||
};
|
||||
|
||||
@@ -156,7 +156,7 @@ static int tiva_gpiohandler(uint32_t regbase, int irqbase, void *context)
|
||||
* either no interrupt has been generated, or the interrupt is masked."
|
||||
*/
|
||||
|
||||
mis = getreg32(regbase + LM_GPIO_MIS_OFFSET) & 0xff;
|
||||
mis = getreg32(regbase + TIVA_GPIO_MIS_OFFSET) & 0xff;
|
||||
|
||||
/* Clear all GPIO interrupts that we are going to process. "The GPIO ICR
|
||||
* register is the interrupt clear register. Writing a 1 to a bit in this
|
||||
@@ -164,7 +164,7 @@ static int tiva_gpiohandler(uint32_t regbase, int irqbase, void *context)
|
||||
* Writing a 0 has no effect."
|
||||
*/
|
||||
|
||||
putreg32(mis, regbase + LM_GPIO_ICR_OFFSET);
|
||||
putreg32(mis, regbase + TIVA_GPIO_ICR_OFFSET);
|
||||
|
||||
/* Now process each IRQ pending in the MIS */
|
||||
|
||||
@@ -179,66 +179,66 @@ static int tiva_gpiohandler(uint32_t regbase, int irqbase, void *context)
|
||||
return OK;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOA_IRQS
|
||||
static int tiva_gpioahandler(int irq, FAR void *context)
|
||||
{
|
||||
return tiva_gpiohandler(LM_GPIOA_BASE, LM_IRQ_GPIOA_0, context);
|
||||
return tiva_gpiohandler(TIVA_GPIOA_BASE, TIVA_IRQ_GPIOA_0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOB_IRQS
|
||||
static int tiva_gpiobhandler(int irq, FAR void *context)
|
||||
{
|
||||
return tiva_gpiohandler(LM_GPIOB_BASE, LM_IRQ_GPIOB_0, context);
|
||||
return tiva_gpiohandler(TIVA_GPIOB_BASE, TIVA_IRQ_GPIOB_0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOC_IRQS
|
||||
static int tiva_gpiochandler(int irq, FAR void *context)
|
||||
{
|
||||
return tiva_gpiohandler(LM_GPIOC_BASE, LM_IRQ_GPIOC_0, context);
|
||||
return tiva_gpiohandler(TIVA_GPIOC_BASE, TIVA_IRQ_GPIOC_0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOD_IRQS
|
||||
static int tiva_gpiodhandler(int irq, FAR void *context)
|
||||
{
|
||||
return tiva_gpiohandler(LM_GPIOD_BASE, LM_IRQ_GPIOD_0, context);
|
||||
return tiva_gpiohandler(TIVA_GPIOD_BASE, TIVA_IRQ_GPIOD_0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOE_IRQS
|
||||
static int tiva_gpioehandler(int irq, FAR void *context)
|
||||
{
|
||||
return tiva_gpiohandler(LM_GPIOE_BASE, LM_IRQ_GPIOE_0, context);
|
||||
return tiva_gpiohandler(TIVA_GPIOE_BASE, TIVA_IRQ_GPIOE_0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOF_IRQS
|
||||
static int tiva_gpiofhandler(int irq, FAR void *context)
|
||||
{
|
||||
return tiva_gpiohandler(LM_GPIOF_BASE, LM_IRQ_GPIOF_0, context);
|
||||
return tiva_gpiohandler(TIVA_GPIOF_BASE, TIVA_IRQ_GPIOF_0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOG_IRQS
|
||||
static int tiva_gpioghandler(int irq, FAR void *context)
|
||||
{
|
||||
return tiva_gpiohandler(LM_GPIOG_BASE, LM_IRQ_GPIOG_0, context);
|
||||
return tiva_gpiohandler(TIVA_GPIOG_BASE, TIVA_IRQ_GPIOG_0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOH_IRQS
|
||||
static int tiva_gpiohhandler(int irq, FAR void *context)
|
||||
{
|
||||
return tiva_gpiohandler(LM_GPIOH_BASE, LM_IRQ_GPIOH_0, context);
|
||||
return tiva_gpiohandler(TIVA_GPIOH_BASE, TIVA_IRQ_GPIOH_0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOJ_IRQS
|
||||
static int tiva_gpiojhandler(int irq, FAR void *context)
|
||||
{
|
||||
return tiva_gpiohandler(LM_GPIOJ_BASE, LM_IRQ_GPIOJ_0, context);
|
||||
return tiva_gpiohandler(TIVA_GPIOJ_BASE, TIVA_IRQ_GPIOJ_0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -269,41 +269,41 @@ int gpio_irqinitialize(void)
|
||||
* interrupts
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
|
||||
irq_attach(LM_IRQ_GPIOA, tiva_gpioahandler);
|
||||
up_enable_irq(LM_IRQ_GPIOA);
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOA_IRQS
|
||||
irq_attach(TIVA_IRQ_GPIOA, tiva_gpioahandler);
|
||||
up_enable_irq(TIVA_IRQ_GPIOA);
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
|
||||
irq_attach(LM_IRQ_GPIOB, tiva_gpiobhandler);
|
||||
up_enable_irq(LM_IRQ_GPIOB);
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOB_IRQS
|
||||
irq_attach(TIVA_IRQ_GPIOB, tiva_gpiobhandler);
|
||||
up_enable_irq(TIVA_IRQ_GPIOB);
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
|
||||
irq_attach(LM_IRQ_GPIOC, tiva_gpiochandler);
|
||||
up_enable_irq(LM_IRQ_GPIOC);
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOC_IRQS
|
||||
irq_attach(TIVA_IRQ_GPIOC, tiva_gpiochandler);
|
||||
up_enable_irq(TIVA_IRQ_GPIOC);
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
|
||||
irq_attach(LM_IRQ_GPIOD, tiva_gpiodhandler);
|
||||
up_enable_irq(LM_IRQ_GPIOD);
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOD_IRQS
|
||||
irq_attach(TIVA_IRQ_GPIOD, tiva_gpiodhandler);
|
||||
up_enable_irq(TIVA_IRQ_GPIOD);
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
|
||||
irq_attach(LM_IRQ_GPIOE, tiva_gpioehandler);
|
||||
up_enable_irq(LM_IRQ_GPIOE);
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOE_IRQS
|
||||
irq_attach(TIVA_IRQ_GPIOE, tiva_gpioehandler);
|
||||
up_enable_irq(TIVA_IRQ_GPIOE);
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
|
||||
irq_attach(LM_IRQ_GPIOF, tiva_gpiofhandler);
|
||||
up_enable_irq(LM_IRQ_GPIOF);
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOF_IRQS
|
||||
irq_attach(TIVA_IRQ_GPIOF, tiva_gpiofhandler);
|
||||
up_enable_irq(TIVA_IRQ_GPIOF);
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
|
||||
irq_attach(LM_IRQ_GPIOG, tiva_gpioghandler);
|
||||
up_enable_irq(LM_IRQ_GPIOG);
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOG_IRQS
|
||||
irq_attach(TIVA_IRQ_GPIOG, tiva_gpioghandler);
|
||||
up_enable_irq(TIVA_IRQ_GPIOG);
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
|
||||
irq_attach(LM_IRQ_GPIOH, tiva_gpiohhandler);
|
||||
up_enable_irq(LM_IRQ_GPIOH);
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOH_IRQS
|
||||
irq_attach(TIVA_IRQ_GPIOH, tiva_gpiohhandler);
|
||||
up_enable_irq(TIVA_IRQ_GPIOH);
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
|
||||
irq_attach(LM_IRQ_GPIOJ, tiva_gpiojhandler);
|
||||
up_enable_irq(LM_IRQ_GPIOJ);
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIOJ_IRQS
|
||||
irq_attach(TIVA_IRQ_GPIOJ, tiva_gpiojhandler);
|
||||
up_enable_irq(TIVA_IRQ_GPIOJ);
|
||||
#endif
|
||||
|
||||
return OK;
|
||||
@@ -381,9 +381,9 @@ void gpio_irqenable(int irq)
|
||||
*/
|
||||
|
||||
flags = irqsave();
|
||||
regval = getreg32(base + LM_GPIO_IM_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_IM_OFFSET);
|
||||
regval |= pin;
|
||||
putreg32(regval, base + LM_GPIO_IM_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_IM_OFFSET);
|
||||
irqrestore(flags);
|
||||
}
|
||||
}
|
||||
@@ -420,9 +420,9 @@ void gpio_irqdisable(int irq)
|
||||
*/
|
||||
|
||||
flags = irqsave();
|
||||
regval = getreg32(base + LM_GPIO_IM_OFFSET);
|
||||
regval = getreg32(base + TIVA_GPIO_IM_OFFSET);
|
||||
regval &= ~pin;
|
||||
putreg32(regval, base + LM_GPIO_IM_OFFSET);
|
||||
putreg32(regval, base + TIVA_GPIO_IM_OFFSET);
|
||||
irqrestore(flags);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -226,21 +226,21 @@ static inline void tiva_prioritize_syscall(int priority)
|
||||
static int tiva_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
|
||||
uintptr_t offset)
|
||||
{
|
||||
DEBUGASSERT(irq >= LM_IRQ_NMI && irq < NR_IRQS);
|
||||
DEBUGASSERT(irq >= TIVA_IRQ_NMI && irq < NR_IRQS);
|
||||
|
||||
/* Check for external interrupt */
|
||||
|
||||
if (irq >= LM_IRQ_INTERRUPTS)
|
||||
if (irq >= TIVA_IRQ_INTERRUPTS)
|
||||
{
|
||||
if (irq < LM_IRQ_INTERRUPTS + 32)
|
||||
if (irq < TIVA_IRQ_INTERRUPTS + 32)
|
||||
{
|
||||
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
|
||||
*bit = 1 << (irq - LM_IRQ_INTERRUPTS);
|
||||
*bit = 1 << (irq - TIVA_IRQ_INTERRUPTS);
|
||||
}
|
||||
else if (irq < NR_IRQS)
|
||||
{
|
||||
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
|
||||
*bit = 1 << (irq - LM_IRQ_INTERRUPTS - 32);
|
||||
*bit = 1 << (irq - TIVA_IRQ_INTERRUPTS - 32);
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -253,19 +253,19 @@ static int tiva_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
|
||||
else
|
||||
{
|
||||
*regaddr = NVIC_SYSHCON;
|
||||
if (irq == LM_IRQ_MEMFAULT)
|
||||
if (irq == TIVA_IRQ_MEMFAULT)
|
||||
{
|
||||
*bit = NVIC_SYSHCON_MEMFAULTENA;
|
||||
}
|
||||
else if (irq == LM_IRQ_BUSFAULT)
|
||||
else if (irq == TIVA_IRQ_BUSFAULT)
|
||||
{
|
||||
*bit = NVIC_SYSHCON_BUSFAULTENA;
|
||||
}
|
||||
else if (irq == LM_IRQ_USAGEFAULT)
|
||||
else if (irq == TIVA_IRQ_USAGEFAULT)
|
||||
{
|
||||
*bit = NVIC_SYSHCON_USGFAULTENA;
|
||||
}
|
||||
else if (irq == LM_IRQ_SYSTICK)
|
||||
else if (irq == TIVA_IRQ_SYSTICK)
|
||||
{
|
||||
*regaddr = NVIC_SYSTICK_CTRL;
|
||||
*bit = NVIC_SYSTICK_CTRL_ENABLE;
|
||||
@@ -327,7 +327,7 @@ void up_irqinitialize(void)
|
||||
|
||||
/* Initialize support for GPIO interrupts if included in this build */
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIO_IRQS
|
||||
#ifndef CONFIG_TIVA_DISABLE_GPIO_IRQS
|
||||
#ifdef CONFIG_HAVE_WEAKFUNCTIONS
|
||||
if (gpio_irqinitialize != NULL)
|
||||
#endif
|
||||
@@ -342,13 +342,13 @@ void up_irqinitialize(void)
|
||||
* under certain conditions.
|
||||
*/
|
||||
|
||||
irq_attach(LM_IRQ_SVCALL, up_svcall);
|
||||
irq_attach(LM_IRQ_HARDFAULT, up_hardfault);
|
||||
irq_attach(TIVA_IRQ_SVCALL, up_svcall);
|
||||
irq_attach(TIVA_IRQ_HARDFAULT, up_hardfault);
|
||||
|
||||
/* Set the priority of the SVCall interrupt */
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
/* up_prioritize_irq(LM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
|
||||
/* up_prioritize_irq(TIVA_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
|
||||
#endif
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
tiva_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
|
||||
@@ -359,22 +359,22 @@ void up_irqinitialize(void)
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARMV7M_MPU
|
||||
irq_attach(LM_IRQ_MEMFAULT, up_memfault);
|
||||
up_enable_irq(LM_IRQ_MEMFAULT);
|
||||
irq_attach(TIVA_IRQ_MEMFAULT, up_memfault);
|
||||
up_enable_irq(TIVA_IRQ_MEMFAULT);
|
||||
#endif
|
||||
|
||||
/* Attach all other processor exceptions (except reset and sys tick) */
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
irq_attach(LM_IRQ_NMI, tiva_nmi);
|
||||
irq_attach(TIVA_IRQ_NMI, tiva_nmi);
|
||||
#ifndef CONFIG_ARMV7M_MPU
|
||||
irq_attach(LM_IRQ_MEMFAULT, up_memfault);
|
||||
irq_attach(TIVA_IRQ_MEMFAULT, up_memfault);
|
||||
#endif
|
||||
irq_attach(LM_IRQ_BUSFAULT, tiva_busfault);
|
||||
irq_attach(LM_IRQ_USAGEFAULT, tiva_usagefault);
|
||||
irq_attach(LM_IRQ_PENDSV, tiva_pendsv);
|
||||
irq_attach(LM_IRQ_DBGMONITOR, tiva_dbgmonitor);
|
||||
irq_attach(LM_IRQ_RESERVED, tiva_reserved);
|
||||
irq_attach(TIVA_IRQ_BUSFAULT, tiva_busfault);
|
||||
irq_attach(TIVA_IRQ_USAGEFAULT, tiva_usagefault);
|
||||
irq_attach(TIVA_IRQ_PENDSV, tiva_pendsv);
|
||||
irq_attach(TIVA_IRQ_DBGMONITOR, tiva_dbgmonitor);
|
||||
irq_attach(TIVA_IRQ_RESERVED, tiva_reserved);
|
||||
#endif
|
||||
|
||||
tiva_dumpnvic("initial", NR_IRQS);
|
||||
@@ -409,7 +409,7 @@ void up_disable_irq(int irq)
|
||||
* clear the bit in the System Handler Control and State Register.
|
||||
*/
|
||||
|
||||
if (irq >= LM_IRQ_INTERRUPTS)
|
||||
if (irq >= TIVA_IRQ_INTERRUPTS)
|
||||
{
|
||||
putreg32(bit, regaddr);
|
||||
}
|
||||
@@ -446,7 +446,7 @@ void up_enable_irq(int irq)
|
||||
* set the bit in the System Handler Control and State Register.
|
||||
*/
|
||||
|
||||
if (irq >= LM_IRQ_INTERRUPTS)
|
||||
if (irq >= TIVA_IRQ_INTERRUPTS)
|
||||
{
|
||||
putreg32(bit, regaddr);
|
||||
}
|
||||
@@ -491,10 +491,10 @@ int up_prioritize_irq(int irq, int priority)
|
||||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
DEBUGASSERT(irq >= LM_IRQ_MEMFAULT && irq < NR_IRQS &&
|
||||
DEBUGASSERT(irq >= TIVA_IRQ_MEMFAULT && irq < NR_IRQS &&
|
||||
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
|
||||
if (irq < LM_IRQ_INTERRUPTS)
|
||||
if (irq < TIVA_IRQ_INTERRUPTS)
|
||||
{
|
||||
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
|
||||
* registers (0-3 are invalid)
|
||||
@@ -507,7 +507,7 @@ int up_prioritize_irq(int irq, int priority)
|
||||
{
|
||||
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
|
||||
|
||||
irq -= LM_IRQ_INTERRUPTS;
|
||||
irq -= TIVA_IRQ_INTERRUPTS;
|
||||
regaddr = NVIC_IRQ_PRIORITY(irq);
|
||||
}
|
||||
|
||||
|
||||
@@ -59,82 +59,82 @@
|
||||
/* Select UART parameters for the selected console */
|
||||
|
||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
|
||||
# define LM_CONSOLE_BASE LM_UART0_BASE
|
||||
# define LM_CONSOLE_BAUD CONFIG_UART0_BAUD
|
||||
# define LM_CONSOLE_BITS CONFIG_UART0_BITS
|
||||
# define LM_CONSOLE_PARITY CONFIG_UART0_PARITY
|
||||
# define LM_CONSOLE_2STOP CONFIG_UART0_2STOP
|
||||
# define TIVA_CONSOLE_BASE TIVA_UART0_BASE
|
||||
# define TIVA_CONSOLE_BAUD CONFIG_UART0_BAUD
|
||||
# define TIVA_CONSOLE_BITS CONFIG_UART0_BITS
|
||||
# define TIVA_CONSOLE_PARITY CONFIG_UART0_PARITY
|
||||
# define TIVA_CONSOLE_2STOP CONFIG_UART0_2STOP
|
||||
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
|
||||
# define LM_CONSOLE_BASE LM_UART1_BASE
|
||||
# define LM_CONSOLE_BAUD CONFIG_UART1_BAUD
|
||||
# define LM_CONSOLE_BITS CONFIG_UART1_BITS
|
||||
# define LM_CONSOLE_PARITY CONFIG_UART1_PARITY
|
||||
# define LM_CONSOLE_2STOP CONFIG_UART1_2STOP
|
||||
# define TIVA_CONSOLE_BASE TIVA_UART1_BASE
|
||||
# define TIVA_CONSOLE_BAUD CONFIG_UART1_BAUD
|
||||
# define TIVA_CONSOLE_BITS CONFIG_UART1_BITS
|
||||
# define TIVA_CONSOLE_PARITY CONFIG_UART1_PARITY
|
||||
# define TIVA_CONSOLE_2STOP CONFIG_UART1_2STOP
|
||||
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
|
||||
# define LM_CONSOLE_BASE LM_UART2_BASE
|
||||
# define LM_CONSOLE_BAUD CONFIG_UART2_BAUD
|
||||
# define LM_CONSOLE_BITS CONFIG_UART2_BITS
|
||||
# define LM_CONSOLE_PARITY CONFIG_UART2_PARITY
|
||||
# define LM_CONSOLE_2STOP CONFIG_UART2_2STOP
|
||||
# define TIVA_CONSOLE_BASE TIVA_UART2_BASE
|
||||
# define TIVA_CONSOLE_BAUD CONFIG_UART2_BAUD
|
||||
# define TIVA_CONSOLE_BITS CONFIG_UART2_BITS
|
||||
# define TIVA_CONSOLE_PARITY CONFIG_UART2_PARITY
|
||||
# define TIVA_CONSOLE_2STOP CONFIG_UART2_2STOP
|
||||
#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
|
||||
# define LM_CONSOLE_BASE LM_UART3_BASE
|
||||
# define LM_CONSOLE_BAUD CONFIG_UART3_BAUD
|
||||
# define LM_CONSOLE_BITS CONFIG_UART3_BITS
|
||||
# define LM_CONSOLE_PARITY CONFIG_UART3_PARITY
|
||||
# define LM_CONSOLE_2STOP CONFIG_UART3_2STOP
|
||||
# define TIVA_CONSOLE_BASE TIVA_UART3_BASE
|
||||
# define TIVA_CONSOLE_BAUD CONFIG_UART3_BAUD
|
||||
# define TIVA_CONSOLE_BITS CONFIG_UART3_BITS
|
||||
# define TIVA_CONSOLE_PARITY CONFIG_UART3_PARITY
|
||||
# define TIVA_CONSOLE_2STOP CONFIG_UART3_2STOP
|
||||
#elif defined(CONFIG_UART4_SERIAL_CONSOLE)
|
||||
# define LM_CONSOLE_BASE LM_UART4_BASE
|
||||
# define LM_CONSOLE_BAUD CONFIG_UART4_BAUD
|
||||
# define LM_CONSOLE_BITS CONFIG_UART4_BITS
|
||||
# define LM_CONSOLE_PARITY CONFIG_UART4_PARITY
|
||||
# define LM_CONSOLE_2STOP CONFIG_UART4_2STOP
|
||||
# define TIVA_CONSOLE_BASE TIVA_UART4_BASE
|
||||
# define TIVA_CONSOLE_BAUD CONFIG_UART4_BAUD
|
||||
# define TIVA_CONSOLE_BITS CONFIG_UART4_BITS
|
||||
# define TIVA_CONSOLE_PARITY CONFIG_UART4_PARITY
|
||||
# define TIVA_CONSOLE_2STOP CONFIG_UART4_2STOP
|
||||
#elif defined(CONFIG_UART5_SERIAL_CONSOLE)
|
||||
# define LM_CONSOLE_BASE LM_UART5_BASE
|
||||
# define LM_CONSOLE_BAUD CONFIG_UART5_BAUD
|
||||
# define LM_CONSOLE_BITS CONFIG_UART5_BITS
|
||||
# define LM_CONSOLE_PARITY CONFIG_UART5_PARITY
|
||||
# define LM_CONSOLE_2STOP CONFIG_UART5_2STOP
|
||||
# define TIVA_CONSOLE_BASE TIVA_UART5_BASE
|
||||
# define TIVA_CONSOLE_BAUD CONFIG_UART5_BAUD
|
||||
# define TIVA_CONSOLE_BITS CONFIG_UART5_BITS
|
||||
# define TIVA_CONSOLE_PARITY CONFIG_UART5_PARITY
|
||||
# define TIVA_CONSOLE_2STOP CONFIG_UART5_2STOP
|
||||
#elif defined(CONFIG_UART6_SERIAL_CONSOLE)
|
||||
# define LM_CONSOLE_BASE LM_UART6_BASE
|
||||
# define LM_CONSOLE_BAUD CONFIG_UART6_BAUD
|
||||
# define LM_CONSOLE_BITS CONFIG_UART6_BITS
|
||||
# define LM_CONSOLE_PARITY CONFIG_UART6_PARITY
|
||||
# define LM_CONSOLE_2STOP CONFIG_UART6_2STOP
|
||||
# define TIVA_CONSOLE_BASE TIVA_UART6_BASE
|
||||
# define TIVA_CONSOLE_BAUD CONFIG_UART6_BAUD
|
||||
# define TIVA_CONSOLE_BITS CONFIG_UART6_BITS
|
||||
# define TIVA_CONSOLE_PARITY CONFIG_UART6_PARITY
|
||||
# define TIVA_CONSOLE_2STOP CONFIG_UART6_2STOP
|
||||
#elif defined(CONFIG_UART7_SERIAL_CONSOLE)
|
||||
# define LM_CONSOLE_BASE LM_UART7_BASE
|
||||
# define LM_CONSOLE_BAUD CONFIG_UART7_BAUD
|
||||
# define LM_CONSOLE_BITS CONFIG_UART7_BITS
|
||||
# define LM_CONSOLE_PARITY CONFIG_UART7_PARITY
|
||||
# define LM_CONSOLE_2STOP CONFIG_UART7_2STOP
|
||||
# define TIVA_CONSOLE_BASE TIVA_UART7_BASE
|
||||
# define TIVA_CONSOLE_BAUD CONFIG_UART7_BAUD
|
||||
# define TIVA_CONSOLE_BITS CONFIG_UART7_BITS
|
||||
# define TIVA_CONSOLE_PARITY CONFIG_UART7_PARITY
|
||||
# define TIVA_CONSOLE_2STOP CONFIG_UART7_2STOP
|
||||
#else
|
||||
# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
|
||||
#endif
|
||||
|
||||
/* Get LCRH settings */
|
||||
|
||||
#if LM_CONSOLE_BITS == 5
|
||||
#if TIVA_CONSOLE_BITS == 5
|
||||
# define UART_LCRH_NBITS UART_LCRH_WLEN_5BITS
|
||||
#elif LM_CONSOLE_BITS == 6
|
||||
#elif TIVA_CONSOLE_BITS == 6
|
||||
# define UART_LCRH_NBITS UART_LCRH_WLEN_6BITS
|
||||
#elif LM_CONSOLE_BITS == 7
|
||||
#elif TIVA_CONSOLE_BITS == 7
|
||||
# define UART_LCRH_NBITS UART_LCRH_WLEN_7BITS
|
||||
#elif LM_CONSOLE_BITS == 8
|
||||
#elif TIVA_CONSOLE_BITS == 8
|
||||
# define UART_LCRH_NBITS UART_LCRH_WLEN_8BITS
|
||||
#else
|
||||
# error "Number of bits not supported"
|
||||
#endif
|
||||
|
||||
#if LM_CONSOLE_PARITY == 0
|
||||
#if TIVA_CONSOLE_PARITY == 0
|
||||
# define UART_LCRH_PARITY (0)
|
||||
#elif LM_CONSOLE_PARITY == 1
|
||||
#elif TIVA_CONSOLE_PARITY == 1
|
||||
# define UART_LCRH_PARITY UART_LCRH_PEN
|
||||
#elif LM_CONSOLE_PARITY == 2
|
||||
#elif TIVA_CONSOLE_PARITY == 2
|
||||
# define UART_LCRH_PARITY (UART_LCRH_PEN|UART_LCRH_EPS)
|
||||
#else
|
||||
# error "Invalid parity selection"
|
||||
#endif
|
||||
|
||||
#if LM_CONSOLE_2STOP != 0
|
||||
#if TIVA_CONSOLE_2STOP != 0
|
||||
# define UART_LCRH_NSTOP UART_LCRH_STP2
|
||||
#else
|
||||
# define UART_LCRH_NSTOP (0)
|
||||
@@ -174,17 +174,17 @@
|
||||
* divisor must be followed by a write to the UARTLCRH register for the changes to take effect. ..."
|
||||
*/
|
||||
|
||||
#define LM_BRDDEN (16 * LM_CONSOLE_BAUD)
|
||||
#define LM_BRDI (SYSCLK_FREQUENCY / LM_BRDDEN)
|
||||
#define LM_REMAINDER (SYSCLK_FREQUENCY - LM_BRDDEN * LM_BRDI)
|
||||
#define LM_DIVFRAC ((LM_REMAINDER * 64 + (LM_BRDDEN/2)) / LM_BRDDEN)
|
||||
#define TIVA_BRDDEN (16 * TIVA_CONSOLE_BAUD)
|
||||
#define TIVA_BRDI (SYSCLK_FREQUENCY / TIVA_BRDDEN)
|
||||
#define TIVA_REMAINDER (SYSCLK_FREQUENCY - TIVA_BRDDEN * TIVA_BRDI)
|
||||
#define TIVA_DIVFRAC ((TIVA_REMAINDER * 64 + (TIVA_BRDDEN/2)) / TIVA_BRDDEN)
|
||||
|
||||
/* For example: LM_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000:
|
||||
/* For example: TIVA_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000:
|
||||
*
|
||||
* LM_BRDDEN = (16 * 115,200) = 1,843,200
|
||||
* LM_BRDI = 50,000,000 / 1,843,200 = 27
|
||||
* LM_REMAINDER = 50,000,000 - 1,843,200 * 27 = 233,600
|
||||
* LM_DIVFRAC = (233,600 * 64 + 921,600) / 1,843,200 = 8
|
||||
* TIVA_BRDDEN = (16 * 115,200) = 1,843,200
|
||||
* TIVA_BRDI = 50,000,000 / 1,843,200 = 27
|
||||
* TIVA_REMAINDER = 50,000,000 - 1,843,200 * 27 = 233,600
|
||||
* TIVA_DIVFRAC = (233,600 * 64 + 921,600) / 1,843,200 = 8
|
||||
*
|
||||
* Which should yied BAUD = 50,000,000 / (16 * (27 + 8/64)) = 115207.37
|
||||
*/
|
||||
@@ -226,11 +226,11 @@ void up_lowputc(char ch)
|
||||
#ifdef HAVE_SERIAL_CONSOLE
|
||||
/* Wait until the TX FIFO is not full */
|
||||
|
||||
while ((getreg32(LM_CONSOLE_BASE+LM_UART_FR_OFFSET) & UART_FR_TXFF) != 0);
|
||||
while ((getreg32(TIVA_CONSOLE_BASE+TIVA_UART_FR_OFFSET) & UART_FR_TXFF) != 0);
|
||||
|
||||
/* Then send the character */
|
||||
|
||||
putreg32((uint32_t)ch, LM_CONSOLE_BASE+LM_UART_DR_OFFSET);
|
||||
putreg32((uint32_t)ch, TIVA_CONSOLE_BASE+TIVA_UART_DR_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -256,73 +256,73 @@ void up_lowsetup(void)
|
||||
* this pin configuration -- whether or not a serial console is selected.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_LM_UART0
|
||||
regval = getreg32(LM_SYSCON_RCGC1);
|
||||
#ifdef CONFIG_TIVA_UART0
|
||||
regval = getreg32(TIVA_SYSCON_RCGC1);
|
||||
regval |= SYSCON_RCGC1_UART0;
|
||||
putreg32(regval, LM_SYSCON_RCGC1);
|
||||
putreg32(regval, TIVA_SYSCON_RCGC1);
|
||||
|
||||
tiva_configgpio(GPIO_UART0_RX);
|
||||
tiva_configgpio(GPIO_UART0_TX);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LM_UART1
|
||||
regval = getreg32(LM_SYSCON_RCGC1);
|
||||
#ifdef CONFIG_TIVA_UART1
|
||||
regval = getreg32(TIVA_SYSCON_RCGC1);
|
||||
regval |= SYSCON_RCGC1_UART1;
|
||||
putreg32(regval, LM_SYSCON_RCGC1);
|
||||
putreg32(regval, TIVA_SYSCON_RCGC1);
|
||||
|
||||
tiva_configgpio(GPIO_UART1_RX);
|
||||
tiva_configgpio(GPIO_UART1_TX);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LM_UART2
|
||||
regval = getreg32(LM_SYSCON_RCGC1);
|
||||
#ifdef CONFIG_TIVA_UART2
|
||||
regval = getreg32(TIVA_SYSCON_RCGC1);
|
||||
regval |= SYSCON_RCGC1_UART2;
|
||||
putreg32(regval, LM_SYSCON_RCGC1);
|
||||
putreg32(regval, TIVA_SYSCON_RCGC1);
|
||||
|
||||
tiva_configgpio(GPIO_UART2_RX);
|
||||
tiva_configgpio(GPIO_UART2_TX);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LM_UART3
|
||||
regval = getreg32(LM_SYSCON_RCGCUART);
|
||||
#ifdef CONFIG_TIVA_UART3
|
||||
regval = getreg32(TIVA_SYSCON_RCGCUART);
|
||||
regval |= SYSCON_RCGCUART_R3;
|
||||
putreg32(regval, LM_SYSCON_RCGCUART);
|
||||
putreg32(regval, TIVA_SYSCON_RCGCUART);
|
||||
|
||||
tiva_configgpio(GPIO_UART3_RX);
|
||||
tiva_configgpio(GPIO_UART3_TX);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LM_UART4
|
||||
regval = getreg32(LM_SYSCON_RCGCUART);
|
||||
#ifdef CONFIG_TIVA_UART4
|
||||
regval = getreg32(TIVA_SYSCON_RCGCUART);
|
||||
regval |= SYSCON_RCGCUART_R4;
|
||||
putreg32(regval, LM_SYSCON_RCGCUART);
|
||||
putreg32(regval, TIVA_SYSCON_RCGCUART);
|
||||
|
||||
tiva_configgpio(GPIO_UART4_RX);
|
||||
tiva_configgpio(GPIO_UART4_TX);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LM_UART5
|
||||
regval = getreg32(LM_SYSCON_RCGCUART);
|
||||
#ifdef CONFIG_TIVA_UART5
|
||||
regval = getreg32(TIVA_SYSCON_RCGCUART);
|
||||
regval |= SYSCON_RCGCUART_R5;
|
||||
putreg32(regval, LM_SYSCON_RCGCUART);
|
||||
putreg32(regval, TIVA_SYSCON_RCGCUART);
|
||||
|
||||
tiva_configgpio(GPIO_UART5_RX);
|
||||
tiva_configgpio(GPIO_UART5_TX);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LM_UART6
|
||||
regval = getreg32(LM_SYSCON_RCGCUART);
|
||||
#ifdef CONFIG_TIVA_UART6
|
||||
regval = getreg32(TIVA_SYSCON_RCGCUART);
|
||||
regval |= SYSCON_RCGCUART_R6;
|
||||
putreg32(regval, LM_SYSCON_RCGCUART);
|
||||
putreg32(regval, TIVA_SYSCON_RCGCUART);
|
||||
|
||||
tiva_configgpio(GPIO_UART6_RX);
|
||||
tiva_configgpio(GPIO_UART6_TX);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LM_UART7
|
||||
regval = getreg32(LM_SYSCON_RCGCUART);
|
||||
#ifdef CONFIG_TIVA_UART7
|
||||
regval = getreg32(TIVA_SYSCON_RCGCUART);
|
||||
regval |= SYSCON_RCGCUART_R7;
|
||||
putreg32(regval, LM_SYSCON_RCGCUART);
|
||||
putreg32(regval, TIVA_SYSCON_RCGCUART);
|
||||
|
||||
tiva_configgpio(GPIO_UART7_RX);
|
||||
tiva_configgpio(GPIO_UART7_TX);
|
||||
@@ -333,25 +333,25 @@ void up_lowsetup(void)
|
||||
#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
/* Disable the UART by clearing the UARTEN bit in the UART CTL register */
|
||||
|
||||
ctl = getreg32(LM_CONSOLE_BASE+LM_UART_CTL_OFFSET);
|
||||
ctl = getreg32(TIVA_CONSOLE_BASE+TIVA_UART_CTL_OFFSET);
|
||||
ctl &= ~UART_CTL_UARTEN;
|
||||
putreg32(ctl, LM_CONSOLE_BASE+LM_UART_CTL_OFFSET);
|
||||
putreg32(ctl, TIVA_CONSOLE_BASE+TIVA_UART_CTL_OFFSET);
|
||||
|
||||
/* Write the integer portion of the BRD to the UART IBRD register */
|
||||
|
||||
putreg32(LM_BRDI, LM_CONSOLE_BASE+LM_UART_IBRD_OFFSET);
|
||||
putreg32(TIVA_BRDI, TIVA_CONSOLE_BASE+TIVA_UART_IBRD_OFFSET);
|
||||
|
||||
/* Write the fractional portion of the BRD to the UART FBRD register */
|
||||
|
||||
putreg32(LM_DIVFRAC, LM_CONSOLE_BASE+LM_UART_FBRD_OFFSET);
|
||||
putreg32(TIVA_DIVFRAC, TIVA_CONSOLE_BASE+TIVA_UART_FBRD_OFFSET);
|
||||
|
||||
/* Write the desired serial parameters to the UART LCRH register */
|
||||
|
||||
putreg32(UART_LCRH_VALUE, LM_CONSOLE_BASE+LM_UART_LCRH_OFFSET);
|
||||
putreg32(UART_LCRH_VALUE, TIVA_CONSOLE_BASE+TIVA_UART_LCRH_OFFSET);
|
||||
|
||||
/* Enable the UART by setting the UARTEN bit in the UART CTL register */
|
||||
|
||||
ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
|
||||
putreg32(ctl, LM_CONSOLE_BASE+LM_UART_CTL_OFFSET);
|
||||
putreg32(ctl, TIVA_CONSOLE_BASE+TIVA_UART_CTL_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -47,26 +47,26 @@
|
||||
************************************************************************************/
|
||||
/* Configuration *******************************************************************/
|
||||
|
||||
#if LM_NUARTS < 8
|
||||
# undef CONFIG_LM_UART7
|
||||
#if TIVA_NUARTS < 8
|
||||
# undef CONFIG_TIVA_UART7
|
||||
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||
# if LM_NUARTS < 7
|
||||
# undef CONFIG_LM_UART6
|
||||
# if TIVA_NUARTS < 7
|
||||
# undef CONFIG_TIVA_UART6
|
||||
# undef CONFIG_UART6_SERIAL_CONSOLE
|
||||
# if LM_NUARTS < 6
|
||||
# undef CONFIG_LM_UART5
|
||||
# if TIVA_NUARTS < 6
|
||||
# undef CONFIG_TIVA_UART5
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# if LM_NUARTS < 5
|
||||
# undef CONFIG_LM_UART4
|
||||
# if TIVA_NUARTS < 5
|
||||
# undef CONFIG_TIVA_UART4
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# if LM_NUARTS < 4
|
||||
# undef CONFIG_LM_UART3
|
||||
# if TIVA_NUARTS < 4
|
||||
# undef CONFIG_TIVA_UART3
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# if LM_NUARTS < 3
|
||||
# undef CONFIG_LM_UART2
|
||||
# if TIVA_NUARTS < 3
|
||||
# undef CONFIG_TIVA_UART2
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# if LM_NUARTS < 2
|
||||
# undef CONFIG_LM_UART1
|
||||
# if TIVA_NUARTS < 2
|
||||
# undef CONFIG_TIVA_UART1
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# endif
|
||||
# endif
|
||||
@@ -78,7 +78,7 @@
|
||||
|
||||
/* Is there a serial console? */
|
||||
|
||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM_UART0)
|
||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_TIVA_UART0)
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
@@ -87,7 +87,7 @@
|
||||
# undef CONFIG_UART6_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM_UART1)
|
||||
#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_TIVA_UART1)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
@@ -96,7 +96,7 @@
|
||||
# undef CONFIG_UART6_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM_UART2)
|
||||
#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_TIVA_UART2)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
@@ -105,7 +105,7 @@
|
||||
# undef CONFIG_UART6_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_LM_UART2)
|
||||
#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_TIVA_UART2)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
@@ -114,7 +114,7 @@
|
||||
# undef CONFIG_UART6_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_LM_UART2)
|
||||
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_TIVA_UART2)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
@@ -123,7 +123,7 @@
|
||||
# undef CONFIG_UART6_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_LM_UART2)
|
||||
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_TIVA_UART2)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
@@ -132,7 +132,7 @@
|
||||
# undef CONFIG_UART6_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
#elif defined(CONFIG_UART6_SERIAL_CONSOLE) && defined(CONFIG_LM_UART2)
|
||||
#elif defined(CONFIG_UART6_SERIAL_CONSOLE) && defined(CONFIG_TIVA_UART2)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
@@ -141,7 +141,7 @@
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_LM_UART2)
|
||||
#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_TIVA_UART2)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
|
||||
+113
-113
File diff suppressed because it is too large
Load Diff
@@ -83,12 +83,12 @@
|
||||
* such case, the following must be expanded).
|
||||
*/
|
||||
|
||||
#if LM_NSSI == 0
|
||||
#if TIVA_NSSI == 0
|
||||
# undef CONFIG_SSI0_DISABLE
|
||||
# define CONFIG_SSI0_DISABLE 1
|
||||
# undef CONFIG_SSI1_DISABLE
|
||||
# define CONFIG_SSI1_DISABLE 1
|
||||
#elif LM_NSSI == 1
|
||||
#elif TIVA_NSSI == 1
|
||||
# undef CONFIG_SSI1_DISABLE
|
||||
# define CONFIG_SSI1_DISABLE 1
|
||||
#endif
|
||||
@@ -102,15 +102,15 @@
|
||||
# define NSSI_ENABLED 2 /* Two SSI interfaces: SSI0 & SSI1 */
|
||||
# else
|
||||
# define NSSI_ENABLED 1 /* One SSI interface: SSI0 */
|
||||
# define SSI_BASE LM_SSI0_BASE
|
||||
# define SSI_IRQ LM_IRQ_SSI0
|
||||
# define SSI_BASE TIVA_SSI0_BASE
|
||||
# define SSI_IRQ TIVA_IRQ_SSI0
|
||||
# endif
|
||||
#else
|
||||
# ifndef CONFIG_SSI1_DISABLE
|
||||
# define SSI1_NDX 0 /* Index to SSI1 in g_ssidev[] */
|
||||
# define NSSI_ENABLED 1 /* One SSI interface: SSI1 */
|
||||
# define SSI_BASE LM_SSI1_BASE
|
||||
# define SSI_IRQ LM_IRQ_SSI1
|
||||
# define SSI_BASE TIVA_SSI1_BASE
|
||||
# define SSI_IRQ TIVA_IRQ_SSI1
|
||||
# else
|
||||
# define NSSI_ENABLED 0 /* No SSI interfaces */
|
||||
# endif
|
||||
@@ -124,19 +124,19 @@
|
||||
|
||||
/* The number of (16-bit) words that will fit in the Tx FIFO */
|
||||
|
||||
#define LM_TXFIFO_WORDS 8
|
||||
#define TIVA_TXFIFO_WORDS 8
|
||||
|
||||
/* Configuration settings */
|
||||
|
||||
#ifndef CONFIG_SSI_TXLIMIT
|
||||
# define CONFIG_SSI_TXLIMIT (LM_TXFIFO_WORDS/2)
|
||||
# define CONFIG_SSI_TXLIMIT (TIVA_TXFIFO_WORDS/2)
|
||||
#endif
|
||||
|
||||
#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM_TXFIFO_WORDS
|
||||
#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > TIVA_TXFIFO_WORDS
|
||||
# error "Invalid range for CONFIG_SSI_TXLIMIT"
|
||||
#endif
|
||||
|
||||
#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM_TXFIFO_WORDS/2)
|
||||
#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (TIVA_TXFIFO_WORDS/2)
|
||||
# error "CONFIG_SSI_TXLIMIT must be at least half the TX FIFO size"
|
||||
#endif
|
||||
|
||||
@@ -304,10 +304,10 @@ static struct tiva_ssidev_s g_ssidev[] =
|
||||
{
|
||||
.ops = &g_spiops,
|
||||
#if NSSI_ENABLED > 1
|
||||
.base = LM_SSI0_BASE,
|
||||
.base = TIVA_SSI0_BASE,
|
||||
#endif
|
||||
#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
|
||||
.irq = LM_IRQ_SSI0,
|
||||
.irq = TIVA_IRQ_SSI0,
|
||||
#endif
|
||||
},
|
||||
#endif
|
||||
@@ -315,10 +315,10 @@ static struct tiva_ssidev_s g_ssidev[] =
|
||||
{
|
||||
.ops = &g_spiops,
|
||||
#if NSSI_ENABLED > 1
|
||||
.base = LM_SSI1_BASE,
|
||||
.base = TIVA_SSI1_BASE,
|
||||
#endif
|
||||
#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
|
||||
.irq = LM_IRQ_SSI1,
|
||||
.irq = TIVA_IRQ_SSI1,
|
||||
#endif
|
||||
},
|
||||
#endif
|
||||
@@ -406,9 +406,9 @@ static uint32_t ssi_disable(struct tiva_ssidev_s *priv)
|
||||
uint32_t retval;
|
||||
uint32_t regval;
|
||||
|
||||
retval = ssi_getreg(priv, LM_SSI_CR1_OFFSET);
|
||||
retval = ssi_getreg(priv, TIVA_SSI_CR1_OFFSET);
|
||||
regval = (retval & ~SSI_CR1_SSE);
|
||||
ssi_putreg(priv, LM_SSI_CR1_OFFSET, regval);
|
||||
ssi_putreg(priv, TIVA_SSI_CR1_OFFSET, regval);
|
||||
ssivdbg("CR1: %08x\n", regval);
|
||||
return retval;
|
||||
}
|
||||
@@ -432,10 +432,10 @@ static uint32_t ssi_disable(struct tiva_ssidev_s *priv)
|
||||
|
||||
static void ssi_enable(struct tiva_ssidev_s *priv, uint32_t enable)
|
||||
{
|
||||
uint32_t regval = ssi_getreg(priv, LM_SSI_CR1_OFFSET);
|
||||
uint32_t regval = ssi_getreg(priv, TIVA_SSI_CR1_OFFSET);
|
||||
regval &= ~SSI_CR1_SSE;
|
||||
regval |= (enable & SSI_CR1_SSE);
|
||||
ssi_putreg(priv, LM_SSI_CR1_OFFSET, regval);
|
||||
ssi_putreg(priv, TIVA_SSI_CR1_OFFSET, regval);
|
||||
ssivdbg("CR1: %08x\n", regval);
|
||||
}
|
||||
|
||||
@@ -486,14 +486,14 @@ static void ssi_semtake(sem_t *sem)
|
||||
static void ssi_txnull(struct tiva_ssidev_s *priv)
|
||||
{
|
||||
ssivdbg("TX: ->0xffff\n");
|
||||
ssi_putreg(priv, LM_SSI_DR_OFFSET, 0xffff);
|
||||
ssi_putreg(priv, TIVA_SSI_DR_OFFSET, 0xffff);
|
||||
}
|
||||
|
||||
static void ssi_txuint16(struct tiva_ssidev_s *priv)
|
||||
{
|
||||
uint16_t *ptr = (uint16_t*)priv->txbuffer;
|
||||
ssivdbg("TX: %p->%04x\n", ptr, *ptr);
|
||||
ssi_putreg(priv, LM_SSI_DR_OFFSET, (uint32_t)(*ptr++));
|
||||
ssi_putreg(priv, TIVA_SSI_DR_OFFSET, (uint32_t)(*ptr++));
|
||||
priv->txbuffer = (void*)ptr;
|
||||
}
|
||||
|
||||
@@ -501,7 +501,7 @@ static void ssi_txuint8(struct tiva_ssidev_s *priv)
|
||||
{
|
||||
uint8_t *ptr = (uint8_t*)priv->txbuffer;
|
||||
ssivdbg("TX: %p->%02x\n", ptr, *ptr);
|
||||
ssi_putreg(priv, LM_SSI_DR_OFFSET, (uint32_t)(*ptr++));
|
||||
ssi_putreg(priv, TIVA_SSI_DR_OFFSET, (uint32_t)(*ptr++));
|
||||
priv->txbuffer = (void*)ptr;
|
||||
}
|
||||
|
||||
@@ -525,17 +525,17 @@ static void ssi_txuint8(struct tiva_ssidev_s *priv)
|
||||
static void ssi_rxnull(struct tiva_ssidev_s *priv)
|
||||
{
|
||||
#if defined(SSI_DEBUG) && defined(CONFIG_DEBUG_VERBOSE)
|
||||
uint32_t regval = ssi_getreg(priv, LM_SSI_DR_OFFSET);
|
||||
uint32_t regval = ssi_getreg(priv, TIVA_SSI_DR_OFFSET);
|
||||
ssivdbg("RX: discard %04x\n", regval);
|
||||
#else
|
||||
(void)ssi_getreg(priv, LM_SSI_DR_OFFSET);
|
||||
(void)ssi_getreg(priv, TIVA_SSI_DR_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void ssi_rxuint16(struct tiva_ssidev_s *priv)
|
||||
{
|
||||
uint16_t *ptr = (uint16_t*)priv->rxbuffer;
|
||||
*ptr = (uint16_t)ssi_getreg(priv, LM_SSI_DR_OFFSET);
|
||||
*ptr = (uint16_t)ssi_getreg(priv, TIVA_SSI_DR_OFFSET);
|
||||
ssivdbg("RX: %p<-%04x\n", ptr, *ptr);
|
||||
priv->rxbuffer = (void*)(++ptr);
|
||||
}
|
||||
@@ -543,7 +543,7 @@ static void ssi_rxuint16(struct tiva_ssidev_s *priv)
|
||||
static void ssi_rxuint8(struct tiva_ssidev_s *priv)
|
||||
{
|
||||
uint8_t *ptr = (uint8_t*)priv->rxbuffer;
|
||||
*ptr = (uint8_t)ssi_getreg(priv, LM_SSI_DR_OFFSET);
|
||||
*ptr = (uint8_t)ssi_getreg(priv, TIVA_SSI_DR_OFFSET);
|
||||
ssivdbg("RX: %p<-%02x\n", ptr, *ptr);
|
||||
priv->rxbuffer = (void*)(++ptr);
|
||||
}
|
||||
@@ -564,7 +564,7 @@ static void ssi_rxuint8(struct tiva_ssidev_s *priv)
|
||||
|
||||
static inline bool ssi_txfifofull(struct tiva_ssidev_s *priv)
|
||||
{
|
||||
return (ssi_getreg(priv, LM_SSI_SR_OFFSET) & SSI_SR_TNF) == 0;
|
||||
return (ssi_getreg(priv, TIVA_SSI_SR_OFFSET) & SSI_SR_TNF) == 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -583,7 +583,7 @@ static inline bool ssi_txfifofull(struct tiva_ssidev_s *priv)
|
||||
|
||||
static inline bool ssi_rxfifoempty(struct tiva_ssidev_s *priv)
|
||||
{
|
||||
return (ssi_getreg(priv, LM_SSI_SR_OFFSET) & SSI_SR_RNE) == 0;
|
||||
return (ssi_getreg(priv, TIVA_SSI_SR_OFFSET) & SSI_SR_RNE) == 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -659,7 +659,7 @@ static int ssi_performtx(struct tiva_ssidev_s *priv)
|
||||
/* Check again... Now have all of the Tx words been sent? */
|
||||
|
||||
#ifndef CONFIG_SSI_POLLWAIT
|
||||
regval = ssi_getreg(priv, LM_SSI_IM_OFFSET);
|
||||
regval = ssi_getreg(priv, TIVA_SSI_IM_OFFSET);
|
||||
if (priv->ntxwords > 0)
|
||||
{
|
||||
/* No.. Enable the Tx FIFO interrupt. This interrupt occurs
|
||||
@@ -680,7 +680,7 @@ static int ssi_performtx(struct tiva_ssidev_s *priv)
|
||||
|
||||
regval &= ~(SSI_IM_TX|SSI_RIS_ROR);
|
||||
}
|
||||
ssi_putreg(priv, LM_SSI_IM_OFFSET, regval);
|
||||
ssi_putreg(priv, TIVA_SSI_IM_OFFSET, regval);
|
||||
#endif /* CONFIG_SSI_POLLWAIT */
|
||||
}
|
||||
return ntxd;
|
||||
@@ -730,7 +730,7 @@ static inline void ssi_performrx(struct tiva_ssidev_s *priv)
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_SSI_POLLWAIT
|
||||
regval = ssi_getreg(priv, LM_SSI_IM_OFFSET);
|
||||
regval = ssi_getreg(priv, TIVA_SSI_IM_OFFSET);
|
||||
if (priv->ntxwords == 0 && priv->nrxwords < priv->nwords)
|
||||
{
|
||||
/* There are no more outgoing words to send, but there are
|
||||
@@ -753,7 +753,7 @@ static inline void ssi_performrx(struct tiva_ssidev_s *priv)
|
||||
|
||||
regval &= ~(SSI_IM_RX|SSI_IM_RT);
|
||||
}
|
||||
ssi_putreg(priv, LM_SSI_IM_OFFSET, regval);
|
||||
ssi_putreg(priv, TIVA_SSI_IM_OFFSET, regval);
|
||||
#endif /* CONFIG_SSI_POLLWAIT */
|
||||
}
|
||||
|
||||
@@ -831,7 +831,7 @@ static int ssi_transfer(struct tiva_ssidev_s *priv, const void *txbuffer,
|
||||
flags = irqsave();
|
||||
ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
|
||||
priv->ntxwords, priv->nrxwords, priv->nwords,
|
||||
ssi_getreg(priv, LM_SSI_SR_OFFSET));
|
||||
ssi_getreg(priv, TIVA_SSI_SR_OFFSET));
|
||||
|
||||
ntxd = ssi_performtx(priv);
|
||||
|
||||
@@ -844,8 +844,8 @@ static int ssi_transfer(struct tiva_ssidev_s *priv, const void *txbuffer,
|
||||
|
||||
ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
|
||||
priv->ntxwords, priv->nrxwords, priv->nwords,
|
||||
ssi_getreg(priv, LM_SSI_SR_OFFSET),
|
||||
ssi_getreg(priv, LM_SSI_IM_OFFSET));
|
||||
ssi_getreg(priv, TIVA_SSI_SR_OFFSET),
|
||||
ssi_getreg(priv, TIVA_SSI_IM_OFFSET));
|
||||
|
||||
/* Wait for the transfer to complete. Since there is no handshake
|
||||
* with SPI, the following should complete even if there are problems
|
||||
@@ -910,11 +910,11 @@ static inline struct tiva_ssidev_s *ssi_mapirq(int irq)
|
||||
switch (irq)
|
||||
{
|
||||
#ifndef CONFIG_SSI0_DISABLE
|
||||
case LM_IRQ_SSI0:
|
||||
case TIVA_IRQ_SSI0:
|
||||
return &g_ssidev[SSI0_NDX];
|
||||
#endif
|
||||
#ifndef CONFIG_SSI1_DISABLE
|
||||
case LM_IRQ_SSI1:
|
||||
case TIVA_IRQ_SSI1:
|
||||
return &g_ssidev[SSI1_NDX];
|
||||
#endif
|
||||
default:
|
||||
@@ -954,8 +954,8 @@ static int ssi_interrupt(int irq, void *context)
|
||||
|
||||
/* Clear pending interrupts */
|
||||
|
||||
regval = ssi_getreg(priv, LM_SSI_RIS_OFFSET);
|
||||
ssi_putreg(priv, LM_SSI_ICR_OFFSET, regval);
|
||||
regval = ssi_getreg(priv, TIVA_SSI_RIS_OFFSET);
|
||||
ssi_putreg(priv, TIVA_SSI_ICR_OFFSET, regval);
|
||||
|
||||
/* Check for Rx FIFO overruns */
|
||||
|
||||
@@ -968,7 +968,7 @@ static int ssi_interrupt(int irq, void *context)
|
||||
|
||||
ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
|
||||
priv->ntxwords, priv->nrxwords, priv->nwords,
|
||||
ssi_getreg(priv, LM_SSI_SR_OFFSET));
|
||||
ssi_getreg(priv, TIVA_SSI_SR_OFFSET));
|
||||
|
||||
/* Handle outgoing Tx FIFO transfers */
|
||||
|
||||
@@ -980,8 +980,8 @@ static int ssi_interrupt(int irq, void *context)
|
||||
|
||||
ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
|
||||
priv->ntxwords, priv->nrxwords, priv->nwords,
|
||||
ssi_getreg(priv, LM_SSI_SR_OFFSET),
|
||||
ssi_getreg(priv, LM_SSI_IM_OFFSET));
|
||||
ssi_getreg(priv, TIVA_SSI_SR_OFFSET),
|
||||
ssi_getreg(priv, TIVA_SSI_IM_OFFSET));
|
||||
|
||||
/* Check if the transfer is complete */
|
||||
|
||||
@@ -989,7 +989,7 @@ static int ssi_interrupt(int irq, void *context)
|
||||
{
|
||||
/* Yes.. Disable all SSI interrupt sources */
|
||||
|
||||
ssi_putreg(priv, LM_SSI_IM_OFFSET, 0);
|
||||
ssi_putreg(priv, TIVA_SSI_IM_OFFSET, 0);
|
||||
|
||||
/* Wake up the waiting thread */
|
||||
|
||||
@@ -1138,14 +1138,14 @@ static uint32_t ssi_setfrequencyinternal(struct tiva_ssidev_s *priv,
|
||||
/* Set CPDVSR */
|
||||
|
||||
DEBUGASSERT(cpsdvsr < 255);
|
||||
ssi_putreg(priv, LM_SSI_CPSR_OFFSET, cpsdvsr);
|
||||
ssi_putreg(priv, TIVA_SSI_CPSR_OFFSET, cpsdvsr);
|
||||
|
||||
/* Set SCR */
|
||||
|
||||
regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET);
|
||||
regval = ssi_getreg(priv, TIVA_SSI_CR0_OFFSET);
|
||||
regval &= ~SSI_CR0_SCR_MASK;
|
||||
regval |= (scr << SSI_CR0_SCR_SHIFT);
|
||||
ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval);
|
||||
ssi_putreg(priv, TIVA_SSI_CR0_OFFSET, regval);
|
||||
ssivdbg("CR0: %08x CPSR: %08x\n", regval, cpsdvsr);
|
||||
|
||||
/* Calcluate the actual frequency */
|
||||
@@ -1238,10 +1238,10 @@ static void ssi_setmodeinternal(struct tiva_ssidev_s *priv, enum spi_mode_e mode
|
||||
|
||||
/* Then set the selected mode: Freescale SPI format, mode0-3 */
|
||||
|
||||
regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET);
|
||||
regval = ssi_getreg(priv, TIVA_SSI_CR0_OFFSET);
|
||||
regval &= ~(SSI_CR0_FRF_MASK|SSI_CR0_SPH|SSI_CR0_SPO);
|
||||
regval |= modebits;
|
||||
ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval);
|
||||
ssi_putreg(priv, TIVA_SSI_CR0_OFFSET, regval);
|
||||
ssivdbg("CR0: %08x\n", regval);
|
||||
|
||||
/* Save the mode so that subsequent re-configuratins will be faster */
|
||||
@@ -1290,10 +1290,10 @@ static void ssi_setbitsinternal(struct tiva_ssidev_s *priv, int nbits)
|
||||
DEBUGASSERT(priv);
|
||||
if (nbits != priv->nbits && nbits >=4 && nbits <= 16)
|
||||
{
|
||||
regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET);
|
||||
regval = ssi_getreg(priv, TIVA_SSI_CR0_OFFSET);
|
||||
regval &= ~SSI_CR0_DSS_MASK;
|
||||
regval |= ((nbits - 1) << SSI_CR0_DSS_SHIFT);
|
||||
ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval);
|
||||
ssi_putreg(priv, TIVA_SSI_CR0_OFFSET, regval);
|
||||
ssivdbg("CR0: %08x\n", regval);
|
||||
|
||||
priv->nbits = nbits;
|
||||
@@ -1469,9 +1469,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
|
||||
|
||||
/* Enable the SSI0 peripheral */
|
||||
|
||||
regval = getreg32(LM_SYSCON_RCGC1);
|
||||
regval = getreg32(TIVA_SYSCON_RCGC1);
|
||||
regval |= SYSCON_RCGC1_SSI0;
|
||||
putreg32(regval, LM_SYSCON_RCGC1);
|
||||
putreg32(regval, TIVA_SYSCON_RCGC1);
|
||||
ssivdbg("RCGC1: %08x\n", regval);
|
||||
|
||||
/* Configure SSI0 GPIOs (NOTE that SS is not initialized here, the
|
||||
@@ -1493,9 +1493,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
|
||||
|
||||
/* Enable the SSI1 peripheral */
|
||||
|
||||
regval = getreg32(LM_SYSCON_RCGC1);
|
||||
regval = getreg32(TIVA_SYSCON_RCGC1);
|
||||
regval |= SYSCON_RCGC1_SSI1;
|
||||
putreg32(regval, LM_SYSCON_RCGC1);
|
||||
putreg32(regval, TIVA_SYSCON_RCGC1);
|
||||
ssivdbg("RCGC1: %08x\n", regval);
|
||||
|
||||
/* Configure SSI1 GPIOs */
|
||||
@@ -1523,11 +1523,11 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
|
||||
|
||||
/* Set all CR1 fields to reset state. This will be master mode. */
|
||||
|
||||
ssi_putreg(priv, LM_SSI_CR1_OFFSET, 0);
|
||||
ssi_putreg(priv, TIVA_SSI_CR1_OFFSET, 0);
|
||||
|
||||
/* Set all CR0 fields to the reset state. This will also select Freescale SPI mode. */
|
||||
|
||||
ssi_putreg(priv, LM_SSI_CR0_OFFSET, 0);
|
||||
ssi_putreg(priv, TIVA_SSI_CR0_OFFSET, 0);
|
||||
|
||||
/* Set the initial mode to mode 0. The application may override
|
||||
* this initial setting using the setmode() method.
|
||||
@@ -1552,7 +1552,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
|
||||
* while there is an SSI transfer in progress.
|
||||
*/
|
||||
|
||||
ssi_putreg(priv, LM_SSI_IM_OFFSET, 0);
|
||||
ssi_putreg(priv, TIVA_SSI_IM_OFFSET, 0);
|
||||
|
||||
/* Attach the interrupt */
|
||||
|
||||
|
||||
@@ -174,7 +174,7 @@ static inline void tiva_plllock(void)
|
||||
{
|
||||
/* Check if the PLL is locked on */
|
||||
|
||||
if ((getreg32(LM_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0)
|
||||
if ((getreg32(TIVA_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0)
|
||||
{
|
||||
/* Yes.. return now */
|
||||
|
||||
@@ -206,17 +206,17 @@ void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
|
||||
|
||||
/* Get the current values of the RCC and RCC2 registers */
|
||||
|
||||
rcc = getreg32(LM_SYSCON_RCC);
|
||||
rcc2 = getreg32(LM_SYSCON_RCC2);
|
||||
rcc = getreg32(TIVA_SYSCON_RCC);
|
||||
rcc2 = getreg32(TIVA_SYSCON_RCC2);
|
||||
|
||||
/* Temporarily bypass the PLL and system clock dividers */
|
||||
|
||||
rcc |= SYSCON_RCC_BYPASS;
|
||||
rcc &= ~(SYSCON_RCC_USESYSDIV);
|
||||
putreg32(rcc, LM_SYSCON_RCC);
|
||||
putreg32(rcc, TIVA_SYSCON_RCC);
|
||||
|
||||
rcc2 |= SYSCON_RCC2_BYPASS2;
|
||||
putreg32(rcc2, LM_SYSCON_RCC2);
|
||||
putreg32(rcc2, TIVA_SYSCON_RCC2);
|
||||
|
||||
/* We are probably using the main oscillator. The main oscillator is disabled on
|
||||
* reset and so probably must be enabled here. The internal oscillator is enabled
|
||||
@@ -233,7 +233,7 @@ void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
|
||||
/* Enable any selected osciallators (but don't disable any yet) */
|
||||
|
||||
rcc &= (~RCC_OSCMASK | (newrcc & RCC_OSCMASK));
|
||||
putreg32(rcc, LM_SYSCON_RCC);
|
||||
putreg32(rcc, TIVA_SYSCON_RCC);
|
||||
|
||||
/* Wait for the newly selected oscillator(s) to settle. This is tricky because
|
||||
* the time that we wait can be significant and is determined by the previous
|
||||
@@ -253,7 +253,7 @@ void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
|
||||
|
||||
/* Clear the PLL lock interrupt */
|
||||
|
||||
putreg32(SYSCON_MISC_PLLLMIS, LM_SYSCON_MISC);
|
||||
putreg32(SYSCON_MISC_PLLLMIS, TIVA_SYSCON_MISC);
|
||||
|
||||
/* Write the new RCC/RCC2 values.
|
||||
*
|
||||
@@ -269,14 +269,14 @@ void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
|
||||
#ifndef LM4F
|
||||
if ((rcc2 & SYSCON_RCC2_USERCC2) != 0)
|
||||
{
|
||||
putreg32(rcc2, LM_SYSCON_RCC2);
|
||||
putreg32(rcc, LM_SYSCON_RCC);
|
||||
putreg32(rcc2, TIVA_SYSCON_RCC2);
|
||||
putreg32(rcc, TIVA_SYSCON_RCC);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
putreg32(rcc, LM_SYSCON_RCC);
|
||||
putreg32(rcc2, LM_SYSCON_RCC2);
|
||||
putreg32(rcc, TIVA_SYSCON_RCC);
|
||||
putreg32(rcc2, TIVA_SYSCON_RCC2);
|
||||
}
|
||||
|
||||
/* Wait for the new crystal value and oscillator source to take effect */
|
||||
@@ -313,11 +313,11 @@ void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
|
||||
* before writing the RCC2 register.
|
||||
*/
|
||||
|
||||
putreg32(rcc, LM_SYSCON_RCC);
|
||||
putreg32(rcc, TIVA_SYSCON_RCC);
|
||||
#ifdef LM4F
|
||||
rcc = getreg32(LM_SYSCON_RCC);
|
||||
rcc = getreg32(TIVA_SYSCON_RCC);
|
||||
#endif
|
||||
putreg32(rcc2, LM_SYSCON_RCC2);
|
||||
putreg32(rcc2, TIVA_SYSCON_RCC2);
|
||||
|
||||
/* Wait for the system divider to be effective */
|
||||
|
||||
@@ -336,16 +336,16 @@ void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
|
||||
void up_clockconfig(void)
|
||||
{
|
||||
#ifdef CONFIG_LM_REVA2
|
||||
/* Some early silicon returned an increase LDO voltage or 2.75V to work
|
||||
/* Some early LM3 silicon returned an increase LDO voltage or 2.75V to work
|
||||
* around a PLL bug
|
||||
*/
|
||||
|
||||
putreg32(SYSCON_LPDOPCTL_2750MV, LM_SYSCON_LDOPCTL);
|
||||
putreg32(SYSCON_LPDOPCTL_2750MV, TIVA_SYSCON_LDOPCTL);
|
||||
#endif
|
||||
|
||||
/* Set the clocking to run with the default settings provided in the board.h
|
||||
* header file
|
||||
*/
|
||||
|
||||
tiva_clockconfig(LM_RCC_VALUE, LM_RCC2_VALUE);
|
||||
tiva_clockconfig(TIVA_RCC_VALUE, TIVA_RCC2_VALUE);
|
||||
}
|
||||
|
||||
@@ -130,7 +130,7 @@ void up_timerinit(void)
|
||||
|
||||
/* Attach the timer interrupt vector */
|
||||
|
||||
(void)irq_attach(LM_IRQ_SYSTICK, (xcpt_t)up_timerisr);
|
||||
(void)irq_attach(TIVA_IRQ_SYSTICK, (xcpt_t)up_timerisr);
|
||||
|
||||
/* Enable SysTick interrupts */
|
||||
|
||||
@@ -138,5 +138,5 @@ void up_timerinit(void)
|
||||
|
||||
/* And enable the timer interrupt */
|
||||
|
||||
up_enable_irq(LM_IRQ_SYSTICK);
|
||||
up_enable_irq(TIVA_IRQ_SYSTICK);
|
||||
}
|
||||
|
||||
@@ -33,8 +33,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_TIVA_LM_USERSPACE_H
|
||||
#define __ARCH_ARM_SRC_TIVA_LM_USERSPACE_H
|
||||
#ifndef __ARCH_ARM_SRC_TIVA_TIVA_USERSPACE_H
|
||||
#define __ARCH_ARM_SRC_TIVA_TIVA_USERSPACE_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@@ -73,4 +73,4 @@
|
||||
void tiva_userspace(void);
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_TIVA_LM_USERSPACE_H */
|
||||
#endif /* __ARCH_ARM_SRC_TIVA_TIVA_USERSPACE_H */
|
||||
|
||||
@@ -180,16 +180,16 @@ _vectors:
|
||||
.type handlers, function
|
||||
.thumb_func
|
||||
handlers:
|
||||
HANDLER tiva_reserved, LM_IRQ_RESERVED /* Unexpected/reserved vector */
|
||||
HANDLER tiva_nmi, LM_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */
|
||||
HANDLER tiva_hardfault, LM_IRQ_HARDFAULT /* Vector 3: Hard fault */
|
||||
HANDLER tiva_mpu, LM_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */
|
||||
HANDLER tiva_busfault, LM_IRQ_BUSFAULT /* Vector 5: Bus fault */
|
||||
HANDLER tiva_usagefault, LM_IRQ_USAGEFAULT /* Vector 6: Usage fault */
|
||||
HANDLER tiva_svcall, LM_IRQ_SVCALL /* Vector 11: SVC call */
|
||||
HANDLER tiva_dbgmonitor, LM_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */
|
||||
HANDLER tiva_pendsv, LM_IRQ_PENDSV /* Vector 14: Penable system service request */
|
||||
HANDLER tiva_systick, LM_IRQ_SYSTICK /* Vector 15: System tick */
|
||||
HANDLER tiva_reserved, TIVA_IRQ_RESERVED /* Unexpected/reserved vector */
|
||||
HANDLER tiva_nmi, TIVA_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */
|
||||
HANDLER tiva_hardfault, TIVA_IRQ_HARDFAULT /* Vector 3: Hard fault */
|
||||
HANDLER tiva_mpu, TIVA_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */
|
||||
HANDLER tiva_busfault, TIVA_IRQ_BUSFAULT /* Vector 5: Bus fault */
|
||||
HANDLER tiva_usagefault, TIVA_IRQ_USAGEFAULT /* Vector 6: Usage fault */
|
||||
HANDLER tiva_svcall, TIVA_IRQ_SVCALL /* Vector 11: SVC call */
|
||||
HANDLER tiva_dbgmonitor, TIVA_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */
|
||||
HANDLER tiva_pendsv, TIVA_IRQ_PENDSV /* Vector 14: Penable system service request */
|
||||
HANDLER tiva_systick, TIVA_IRQ_SYSTICK /* Vector 15: System tick */
|
||||
|
||||
#undef VECTOR
|
||||
#define VECTOR(l,i) HANDLER l, i
|
||||
|
||||
Reference in New Issue
Block a user