Added more granular Kconfig options for STM32G0 line. Added CRS and HSI48 defines to get Nuttx to compile.

Minor formatting change

Change G0CX to G0C1 in Kconfig

Change HAVE_DAC to HAVE_DAC1

arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h

@@ -74,6 +74,7 @@
 #define STM32_USART4_BASE    0x40004c00     /* 0x40004c00-0x40004fff USART4 */
 #define STM32_I2C1_BASE      0x40005400     /* 0x40005400-0x400057ff I2C1 */
 #define STM32_I2C2_BASE      0x40005800     /* 0x40005800-0x40005bff I2C2 */
+#define STM32_CRS_BASE       0x40006C00     /* 0x40006C00-0x40006fff CRS */
 #define STM32_PWR_BASE       0x40007000     /* 0x40007000-0x400073ff PWR */
 #define STM32_DAC1_BASE      0x40007400     /* 0x40007400-0x400077ff DAC 1 */
 #define STM32_CEC_BASE       0x40007800     /* 0x40007800-0x40007bff HDMI CEC */

arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h

@@ -93,7 +93,9 @@
 #define RCC_CR_HSEBYP               (1 << 18) /* Bit 18: External high speed clock bypass */
 
 #define RCC_CR_CSSON                (1 << 19) /* Bit 19: Clock security system enable */
-                                              /* Bits 20-23: Reserved */
+                                              /* Bits 20-21: Reserved */
+#define RCC_CR_HSI48ON              (1 << 22) /* Bit 22: HSI48 On */
+#define RCC_CR_HSI48RDY             (1 << 23) /* Bit 23: HSI48 Ready */
 #define RCC_CR_PLLON                (1 << 24) /* Bit 24: PLL enable */
 #define RCC_CR_PLLRDY               (1 << 25) /* Bit 25: PLL clock ready flag */
                                               /* Bits 26-27: Reserved */

arch/arm/src/stm32f0l0g0/stm32_hsi48.c

@@ -45,6 +45,10 @@
 #  define STM32_HSI48_REG STM32_RCC_CRRCR
 #  define STM32_HSI48ON   RCC_CRRCR_HSI48ON
 #  define STM32_HSI48RDY  RCC_CRRCR_HSI48RDY
+#elif defined(CONFIG_ARCH_CHIP_STM32G0)
+#  define STM32_HSI48_REG STM32_RCC_CR
+#  define STM32_HSI48ON   RCC_CR_HSI48ON
+#  define STM32_HSI48RDY  RCC_CR_HSI48RDY
 #else
 #  error "Unsupported STM32F0/L0 HSI48"
 #endif