mirror of
https://github.com/apache/nuttx.git
synced 2026-05-23 14:58:13 +08:00
configs/metro-m4: Fix RxD PAD selection. Add a configuration option to use OSCULP32K instead of XOSC32K.
This commit is contained in:
Gregory Nutt
@@ -50,167 +50,167 @@
|
||||
|
||||
/* External interrupts (vectors >= 16) */
|
||||
|
||||
#define SAM_IRQ_PM (SAM_IRQ_EXTINT+0) /* 0 Power Manager: SLEEPRDY */
|
||||
#define SAM_IRQ_MCLK (SAM_IRQ_EXTINT+1) /* 1 Main clock: CKRDY */
|
||||
#define SAM_IRQ_XOSC0 (SAM_IRQ_EXTINT+2) /* 2 XOSC0: Fail/Ready */
|
||||
#define SAM_IRQ_XOSC1 (SAM_IRQ_EXTINT+3) /* 3 XOSC1: Fail/Ready */
|
||||
#define SAM_IRQ_DFLL (SAM_IRQ_EXTINT+4) /* 4 OSCCTRLD: FLLLOCKC, DFLLLOCKF,
|
||||
* DFLLOOB, DFLLRCS, DFLLRDY */
|
||||
#define SAM_IRQ_DPLL0 (SAM_IRQ_EXTINT+5) /* 5 DPLL0: DPLLLCKF, DPLLLCKR,
|
||||
* DPLLLDRTO, DPLLLTO */
|
||||
#define SAM_IRQ_DPLL1 (SAM_IRQ_EXTINT+6) /* 6 DPLL1: DPLLLCKF, DPLLLCKR,
|
||||
* DPLLLDRTO, DPLLLTO */
|
||||
#define SAM_IRQ_OSC32K (SAM_IRQ_EXTINT+7) /* 7 OSC32KCTRL: OSC32KRDY,
|
||||
* XOSC32KFAIL, XOSC32KRDY */
|
||||
#define SAM_IRQ_SUPCRDY (SAM_IRQ_EXTINT+8) /* 8 Supply Controller: BOD12RDY,
|
||||
* BOD33RDY, B12SRDY, B33SRDY,
|
||||
* VCORERDY, VREGRDY */
|
||||
#define SAM_IRQ_SUPCDET (SAM_IRQ_EXTINT+9) /* 9 Supply Controller: BOD12DET,
|
||||
* BOD33DET */
|
||||
#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+10) /* 10 WDT: EW */
|
||||
#define SAM_IRQ_RTC (SAM_IRQ_EXTINT+11) /* 11 RTC, CMPA0-3, PERA0-7, TAMPERA */
|
||||
#define SAM_IRQ_EXTINT0 (SAM_IRQ_EXTINT+12) /* 12 EIC: EXTINT0 */
|
||||
#define SAM_IRQ_EXTINT1 (SAM_IRQ_EXTINT+13) /* 13 EIC: EXTINT1 */
|
||||
#define SAM_IRQ_EXTINT2 (SAM_IRQ_EXTINT+14) /* 14 EIC: EXTINT2 */
|
||||
#define SAM_IRQ_EXTINT3 (SAM_IRQ_EXTINT+15) /* 15 EIC: EXTINT3 */
|
||||
#define SAM_IRQ_EXTINT4 (SAM_IRQ_EXTINT+16) /* 16 EIC: EXTINT4 */
|
||||
#define SAM_IRQ_EXTINT5 (SAM_IRQ_EXTINT+17) /* 17 EIC: EXTINT5 */
|
||||
#define SAM_IRQ_EXTINT6 (SAM_IRQ_EXTINT+18) /* 18 EIC: EXTINT6 */
|
||||
#define SAM_IRQ_EXTINT7 (SAM_IRQ_EXTINT+19) /* 19 EIC: EXTINT7 */
|
||||
#define SAM_IRQ_EXTINT8 (SAM_IRQ_EXTINT+20) /* 20 EIC: EXTINT8 */
|
||||
#define SAM_IRQ_EXTINT9 (SAM_IRQ_EXTINT+21) /* 21 EIC: EXTINT9 */
|
||||
#define SAM_IRQ_EXTINT10 (SAM_IRQ_EXTINT+22) /* 22 EIC: EXTINT10 */
|
||||
#define SAM_IRQ_EXTINT11 (SAM_IRQ_EXTINT+23) /* 23 EIC: EXTINT11 */
|
||||
#define SAM_IRQ_EXTINT12 (SAM_IRQ_EXTINT+24) /* 24 EIC: EXTINT12 */
|
||||
#define SAM_IRQ_EXTINT13 (SAM_IRQ_EXTINT+25) /* 25 EIC: EXTINT13 */
|
||||
#define SAM_IRQ_EXTINT14 (SAM_IRQ_EXTINT+26) /* 26 EIC: EXTINT14 */
|
||||
#define SAM_IRQ_EXTINT15 (SAM_IRQ_EXTINT+27) /* 27 EIC: EXTINT15 */
|
||||
#define SAM_IRQ_FREQM (SAM_IRQ_EXTINT+28) /* 28 FREQM: Done */
|
||||
#define SAM_IRQ_NVMCTRL0 (SAM_IRQ_EXTINT+29) /* 29 NVMCTRL: 0-7 */
|
||||
#define SAM_IRQ_NVMCTRL1 (SAM_IRQ_EXTINT+30) /* 30 NVMCTRL: 8-10 */
|
||||
#define SAM_IRQ_DMACH0 (SAM_IRQ_EXTINT+31) /* 31 DMA Channel 0: SUSP, TCMPL, TERR */
|
||||
#define SAM_IRQ_DMACH1 (SAM_IRQ_EXTINT+32) /* 32 DMA Channel 1: SUSP, TCMPL, TERR */
|
||||
#define SAM_IRQ_DMACH2 (SAM_IRQ_EXTINT+33) /* 33 DMA Channel 2: SUSP, TCMPL, TERR */
|
||||
#define SAM_IRQ_DMACH3 (SAM_IRQ_EXTINT+34) /* 34 DMA Channel 3: SUSP, TCMPL, TERR */
|
||||
#define SAM_IRQ_DMACH4_31 (SAM_IRQ_EXTINT+35) /* 35 DMA Channels 4-31: SUSP, TCMPL, TERR */
|
||||
#define SAM_IRQ_EVSYS0 (SAM_IRQ_EXTINT+36) /* 36 EVSYS Channel 0: EVD, OVR */
|
||||
#define SAM_IRQ_EVSYS1 (SAM_IRQ_EXTINT+37) /* 37 EVSYS Channel 1: EVD, OVR */
|
||||
#define SAM_IRQ_EVSYS2 (SAM_IRQ_EXTINT+38) /* 38 EVSYS Channel 2: EVD, OVR */
|
||||
#define SAM_IRQ_EVSYS3 (SAM_IRQ_EXTINT+39) /* 39 EVSYS Channel 3: EVD, OVR */
|
||||
#define SAM_IRQ_EVSYS4_11 (SAM_IRQ_EXTINT+40) /* 40 EVSYS Channels 4-11: EVD, OVR */
|
||||
#define SAM_IRQ_PAC (SAM_IRQ_EXTINT+41) /* 41 PAC: ERR */
|
||||
#define SAM_IRQ_RAMECC (SAM_IRQ_EXTINT+45) /* 45 RAM ECC: 0-1 */
|
||||
#define SAM_IRQ_SERCOM0_0 (SAM_IRQ_EXTINT+46) /* 46 SERCOM0: 0 */
|
||||
#define SAM_IRQ_SERCOM0_1 (SAM_IRQ_EXTINT+47) /* 47 SERCOM0: 1 */
|
||||
#define SAM_IRQ_SERCOM0_2 (SAM_IRQ_EXTINT+48) /* 48 SERCOM0: 2 */
|
||||
#define SAM_IRQ_SERCOM0_46 (SAM_IRQ_EXTINT+49) /* 49 SERCOM0: 4-6 */
|
||||
#define SAM_IRQ_SERCOM1_0 (SAM_IRQ_EXTINT+50) /* 50 SERCOM1: 0 */
|
||||
#define SAM_IRQ_SERCOM1_1 (SAM_IRQ_EXTINT+51) /* 51 SERCOM1: 1 */
|
||||
#define SAM_IRQ_SERCOM1_2 (SAM_IRQ_EXTINT+52) /* 52 SERCOM1: 2 */
|
||||
#define SAM_IRQ_SERCOM1_46 (SAM_IRQ_EXTINT+53) /* 53 SERCOM1: 4-6 */
|
||||
#define SAM_IRQ_SERCOM2_0 (SAM_IRQ_EXTINT+54) /* 54 SERCOM2: 0 */
|
||||
#define SAM_IRQ_SERCOM2_1 (SAM_IRQ_EXTINT+55) /* 55 SERCOM2: 1 */
|
||||
#define SAM_IRQ_SERCOM2_2 (SAM_IRQ_EXTINT+56) /* 56 SERCOM2: 2 */
|
||||
#define SAM_IRQ_SERCOM2_46 (SAM_IRQ_EXTINT+57) /* 57 SERCOM2: 4-6 */
|
||||
#define SAM_IRQ_SERCOM3_0 (SAM_IRQ_EXTINT+58) /* 58 SERCOM3: 0 */
|
||||
#define SAM_IRQ_SERCOM3_1 (SAM_IRQ_EXTINT+59) /* 59 SERCOM3: 1 */
|
||||
#define SAM_IRQ_SERCOM3_2 (SAM_IRQ_EXTINT+60) /* 60 SERCOM3: 2 */
|
||||
#define SAM_IRQ_SERCOM3_46 (SAM_IRQ_EXTINT+61) /* 61 SERCOM3: 4-6 */
|
||||
#define SAM_IRQ_SERCOM4_0 (SAM_IRQ_EXTINT+62) /* 62 SERCOM4: 0 */
|
||||
#define SAM_IRQ_SERCOM4_1 (SAM_IRQ_EXTINT+63) /* 63 SERCOM4: 1 */
|
||||
#define SAM_IRQ_SERCOM4_2 (SAM_IRQ_EXTINT+64) /* 64 SERCOM4: 2 */
|
||||
#define SAM_IRQ_SERCOM4_46 (SAM_IRQ_EXTINT+65) /* 65 SERCOM4: 4-6 */
|
||||
#define SAM_IRQ_SERCOM5_0 (SAM_IRQ_EXTINT+66) /* 66 SERCOM5: 0 */
|
||||
#define SAM_IRQ_SERCOM5_1 (SAM_IRQ_EXTINT+67) /* 67 SERCOM5: 1 */
|
||||
#define SAM_IRQ_SERCOM5_2 (SAM_IRQ_EXTINT+68) /* 68 SERCOM5: 2 */
|
||||
#define SAM_IRQ_SERCOM5_46 (SAM_IRQ_EXTINT+69) /* 69 SERCOM5: 4-6 */
|
||||
#define SAM_IRQ_SERCOM6_0 (SAM_IRQ_EXTINT+70) /* 70 SERCOM6: 0 */
|
||||
#define SAM_IRQ_SERCOM6_1 (SAM_IRQ_EXTINT+71) /* 71 SERCOM6: 1 */
|
||||
#define SAM_IRQ_SERCOM6_2 (SAM_IRQ_EXTINT+72) /* 72 SERCOM6: 2 */
|
||||
#define SAM_IRQ_SERCOM6_46 (SAM_IRQ_EXTINT+73) /* 73 SERCOM6: 4-6 */
|
||||
#define SAM_IRQ_SERCOM7_0 (SAM_IRQ_EXTINT+74) /* 74 SERCOM7: 0 */
|
||||
#define SAM_IRQ_SERCOM7_1 (SAM_IRQ_EXTINT+75) /* 75 SERCOM7: 1 */
|
||||
#define SAM_IRQ_SERCOM7_2 (SAM_IRQ_EXTINT+76) /* 76 SERCOM7: 2 */
|
||||
#define SAM_IRQ_SERCOM7_46 (SAM_IRQ_EXTINT+77) /* 77 SERCOM7: 4-6 */
|
||||
#define SAM_IRQ_CAN0 (SAM_IRQ_EXTINT+78) /* 78 CAN0: Line0, Line1 */
|
||||
#define SAM_IRQ_CAN1 (SAM_IRQ_EXTINT+79) /* 79 CAN1: Line0, Line1 */
|
||||
#define SAM_IRQ_USB (SAM_IRQ_EXTINT+80) /* 80 USB: EORSM, DNRSM, EORST RST,
|
||||
* LPM DCONN, LPMSUSP DDISC, MSOF,
|
||||
* RAMACER, RXSTP TXSTP 0-7, STALL0
|
||||
* STALL 0-7, STALL1 0-7, SUSPEND,
|
||||
* TRFAIL0 TRFAIL 097, TRFAIL1 PERR
|
||||
* 0..7, UPRSM, WAKEUP */
|
||||
#define SAM_IRQ_USBSOF (SAM_IRQ_EXTINT+81) /* 81 USB: SOF HSOF */
|
||||
#define SAM_IRQ_USBTRCPT0 (SAM_IRQ_EXTINT+82) /* 82 USB: TRCPT0 0..7 */
|
||||
#define SAM_IRQ_USBTRCPT1 (SAM_IRQ_EXTINT+83) /* 83 USB: TRCPT0 0..7 */
|
||||
#define SAM_IRQ_GMAL (SAM_IRQ_EXTINT+84) /* 84 GMAC: GMAC, WOL */
|
||||
#define SAM_IRQ_TCC0 (SAM_IRQ_EXTINT+85) /* 85 TCC0: CNT A, DFS A, ERR A, FAULTA
|
||||
* A, FAULTB A, FAULT0 A, FAULT1 A,
|
||||
* OVF, TRG, UFS A */
|
||||
#define SAM_IRQ_TCC0MC0 (SAM_IRQ_EXTINT+86) /* 86 TCC0: MC 0 */
|
||||
#define SAM_IRQ_TCC0MC1 (SAM_IRQ_EXTINT+87) /* 87 TCC0: MC 1 */
|
||||
#define SAM_IRQ_TCC0MC2 (SAM_IRQ_EXTINT+88) /* 88 TCC0: MC 2 */
|
||||
#define SAM_IRQ_TCC0MC3 (SAM_IRQ_EXTINT+89) /* 89 TCC0: MC 3 */
|
||||
#define SAM_IRQ_TCC0MC4 (SAM_IRQ_EXTINT+90) /* 90 TCC0: MC 4 */
|
||||
#define SAM_IRQ_TCC0MC5 (SAM_IRQ_EXTINT+91) /* 91 TCC0: MC 5 */
|
||||
#define SAM_IRQ_TCC1 (SAM_IRQ_EXTINT+92) /* 92 TCC1: CNT A, DFS A, ERR A, FAULTA
|
||||
* A, FAULTB A, FAULT0 A, FAULT1 A,
|
||||
* OVF, TRG, UFS A */
|
||||
#define SAM_IRQ_TCC1MC0 (SAM_IRQ_EXTINT+93) /* 93 TCC1: MC 0 */
|
||||
#define SAM_IRQ_TCC1MC1 (SAM_IRQ_EXTINT+94) /* 94 TCC1: MC 1 */
|
||||
#define SAM_IRQ_TCC1MC2 (SAM_IRQ_EXTINT+95) /* 95 TCC1: MC 2 */
|
||||
#define SAM_IRQ_TCC1MC3 (SAM_IRQ_EXTINT+96) /* 96 TCC1: MC 3 */
|
||||
#define SAM_IRQ_TCC2 (SAM_IRQ_EXTINT+97) /* 97 TCC2: CNT A, DFS A, ERR A, FAULTA
|
||||
* A, FAULTB A, FAULT0 A, FAULT1 A,
|
||||
* OVF, TRG, UFS A */
|
||||
#define SAM_IRQ_TCC2MC0 (SAM_IRQ_EXTINT+98) /* 98 TCC2: MC 0 */
|
||||
#define SAM_IRQ_TCC2MC1 (SAM_IRQ_EXTINT+99) /* 99 TCC2: MC 1 */
|
||||
#define SAM_IRQ_TCC2MC2 (SAM_IRQ_EXTINT+100) /* 100 TCC2: MC 2 */
|
||||
#define SAM_IRQ_TCC3 (SAM_IRQ_EXTINT+101) /* 101 TCC3: CNT A, DFS A, ERR A, FAULTA
|
||||
* A, FAULTB A, FAULT0 A, FAULT1 A,
|
||||
* OVF, TRG, UFS A */
|
||||
#define SAM_IRQ_TCC3MC0 (SAM_IRQ_EXTINT+102) /* 102 TCC3: MC 0 */
|
||||
#define SAM_IRQ_TCC3MC1 (SAM_IRQ_EXTINT+103) /* 103 TCC3: MC 1 */
|
||||
#define SAM_IRQ_TCC4 (SAM_IRQ_EXTINT+104) /* 104 TCC4: CNT A, DFS A, ERR A, FAULTA
|
||||
* A, FAULTB A, FAULT0 A, FAULT1 A,
|
||||
* OVF, TRG, UFS A */
|
||||
#define SAM_IRQ_TCC4MC0 (SAM_IRQ_EXTINT+105) /* 105 TCC4: MC 0 */
|
||||
#define SAM_IRQ_TCC4MC1 (SAM_IRQ_EXTINT+106) /* 106 TCC4: MC 1 */
|
||||
#define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+107) /* 107 TC0: ERR A, MC 0, MC 1, OVF */
|
||||
#define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+108) /* 108 TC1: ERR A, MC 0, MC 1, OVF */
|
||||
#define SAM_IRQ_TC2 (SAM_IRQ_EXTINT+109) /* 109 TC2: ERR A, MC 0, MC 1, OVF */
|
||||
#define SAM_IRQ_TC3 (SAM_IRQ_EXTINT+110) /* 110 TC3: ERR A, MC 0, MC 1, OVF */
|
||||
#define SAM_IRQ_TC4 (SAM_IRQ_EXTINT+111) /* 111 TC4: ERR A, MC 0, MC 1, OVF */
|
||||
#define SAM_IRQ_TC5 (SAM_IRQ_EXTINT+112) /* 112 TC5: ERR A, MC 0, MC 1, OVF */
|
||||
#define SAM_IRQ_TC6 (SAM_IRQ_EXTINT+113) /* 113 TC6: ERR A, MC 0, MC 1, OVF */
|
||||
#define SAM_IRQ_TC7 (SAM_IRQ_EXTINT+114) /* 114 TC7: ERR A, MC 0, MC 1, OVF */
|
||||
#define SAM_IRQ_PDEC (SAM_IRQ_EXTINT+115) /* 115 PDEC: DIR A, ERR A, OVF, VLC A */
|
||||
#define SAM_IRQ_PDECMC0 (SAM_IRQ_EXTINT+116) /* 116 PDEC: MC 0 */
|
||||
#define SAM_IRQ_PDECMC1 (SAM_IRQ_EXTINT+117) /* 117 PDEC: MC 1 */
|
||||
#define SAM_IRQ_ADC0 (SAM_IRQ_EXTINT+118) /* 118 ADC0: OVERRUN, WINMON */
|
||||
#define SAM_IRQ_ADC0RDY (SAM_IRQ_EXTINT+119) /* 119 ADC0: RESRDY */
|
||||
#define SAM_IRQ_ADC1 (SAM_IRQ_EXTINT+120) /* 120 ADC0: OVERRUN, WINMON */
|
||||
#define SAM_IRQ_ADC1RDY (SAM_IRQ_EXTINT+121) /* 121 ADC0: RESRDY */
|
||||
#define SAM_IRQ_AC (SAM_IRQ_EXTINT+122) /* 122 AC: COMP 0, COMP 1, WIN 0 */
|
||||
#define SAM_IRQ_DACERR (SAM_IRQ_EXTINT+123) /* 123 DAC: OVERRUN A 0, OVERRUN A 1,
|
||||
* UNDERRUN A 0, UNDERRUN A 1 */
|
||||
#define SAM_IRQ_DACEMPTY0 (SAM_IRQ_EXTINT+124) /* 124 DAC: EMPTY 0 */
|
||||
#define SAM_IRQ_DACEMPTY1 (SAM_IRQ_EXTINT+125) /* 125 DAC: EMPTY 1 */
|
||||
#define SAM_IRQ_DACRDY0 (SAM_IRQ_EXTINT+126) /* 126 DAC: RESRDY 0 */
|
||||
#define SAM_IRQ_DACRDY1 (SAM_IRQ_EXTINT+127) /* 127 DAC: RESRDY 1 */
|
||||
#define SAM_IRQ_I2S (SAM_IRQ_EXTINT+128) /* 128 I2S: RXOR 0, RXOR 1, RXRDY 0, RXRDY
|
||||
* 1, TXRDY 0, TXRDY 1, TXUR 0, TXUR 1 */
|
||||
#define SAM_IRQ_PCC (SAM_IRQ_EXTINT+129) /* 129 PCC: */
|
||||
#define SAM_IRQ_AES (SAM_IRQ_EXTINT+130) /* 130 AES: ENCCMP, GFMCMP */
|
||||
#define SAM_IRQ_TRNG (SAM_IRQ_EXTINT+131) /* 131 TRNG: IS0 */
|
||||
#define SAM_IRQ_ICM (SAM_IRQ_EXTINT+132) /* 132 ICM: */
|
||||
#define SAM_IRQ_PUKCC (SAM_IRQ_EXTINT+133) /* 133 PUKCC: */
|
||||
#define SAM_IRQ_QSPI (SAM_IRQ_EXTINT+134) /* 134 QSPI: */
|
||||
#define SAM_IRQ_SDHC0 (SAM_IRQ_EXTINT+135) /* 135 SDHC0: SDHC0, TIMER */
|
||||
#define SAM_IRQ_SDHC1 (SAM_IRQ_EXTINT+136) /* 136 SDHC1: SDHC1, TIMER */
|
||||
#define SAM_IRQ_PM (SAM_IRQ_EXTINT + 0) /* 0 Power Manager: SLEEPRDY */
|
||||
#define SAM_IRQ_MCLK (SAM_IRQ_EXTINT + 1) /* 1 Main clock: CKRDY */
|
||||
#define SAM_IRQ_XOSC0 (SAM_IRQ_EXTINT + 2) /* 2 XOSC0: Fail/Ready */
|
||||
#define SAM_IRQ_XOSC1 (SAM_IRQ_EXTINT + 3) /* 3 XOSC1: Fail/Ready */
|
||||
#define SAM_IRQ_DFLL (SAM_IRQ_EXTINT + 4) /* 4 OSCCTRLD: FLLLOCKC, DFLLLOCKF,
|
||||
* DFLLOOB, DFLLRCS, DFLLRDY */
|
||||
#define SAM_IRQ_DPLL0 (SAM_IRQ_EXTINT + 5) /* 5 DPLL0: DPLLLCKF, DPLLLCKR,
|
||||
* DPLLLDRTO, DPLLLTO */
|
||||
#define SAM_IRQ_DPLL1 (SAM_IRQ_EXTINT + 6) /* 6 DPLL1: DPLLLCKF, DPLLLCKR,
|
||||
* DPLLLDRTO, DPLLLTO */
|
||||
#define SAM_IRQ_OSC32K (SAM_IRQ_EXTINT + 7) /* 7 OSC32KCTRL: OSC32KRDY,
|
||||
* XOSC32KFAIL, XOSC32KRDY */
|
||||
#define SAM_IRQ_SUPCRDY (SAM_IRQ_EXTINT + 8) /* 8 Supply Controller: BOD12RDY,
|
||||
* BOD33RDY, B12SRDY, B33SRDY,
|
||||
* VCORERDY, VREGRDY */
|
||||
#define SAM_IRQ_SUPCDET (SAM_IRQ_EXTINT + 9) /* 9 Supply Controller: BOD12DET,
|
||||
* BOD33DET */
|
||||
#define SAM_IRQ_WDT (SAM_IRQ_EXTINT + 10) /* 10 WDT: EW */
|
||||
#define SAM_IRQ_RTC (SAM_IRQ_EXTINT + 11) /* 11 RTC, CMPA0-3, PERA0-7, TAMPERA */
|
||||
#define SAM_IRQ_EXTINT0 (SAM_IRQ_EXTINT + 12) /* 12 EIC: EXTINT0 */
|
||||
#define SAM_IRQ_EXTINT1 (SAM_IRQ_EXTINT + 13) /* 13 EIC: EXTINT1 */
|
||||
#define SAM_IRQ_EXTINT2 (SAM_IRQ_EXTINT + 14) /* 14 EIC: EXTINT2 */
|
||||
#define SAM_IRQ_EXTINT3 (SAM_IRQ_EXTINT + 15) /* 15 EIC: EXTINT3 */
|
||||
#define SAM_IRQ_EXTINT4 (SAM_IRQ_EXTINT + 16) /* 16 EIC: EXTINT4 */
|
||||
#define SAM_IRQ_EXTINT5 (SAM_IRQ_EXTINT + 17) /* 17 EIC: EXTINT5 */
|
||||
#define SAM_IRQ_EXTINT6 (SAM_IRQ_EXTINT + 18) /* 18 EIC: EXTINT6 */
|
||||
#define SAM_IRQ_EXTINT7 (SAM_IRQ_EXTINT + 19) /* 19 EIC: EXTINT7 */
|
||||
#define SAM_IRQ_EXTINT8 (SAM_IRQ_EXTINT + 20) /* 20 EIC: EXTINT8 */
|
||||
#define SAM_IRQ_EXTINT9 (SAM_IRQ_EXTINT + 21) /* 21 EIC: EXTINT9 */
|
||||
#define SAM_IRQ_EXTINT10 (SAM_IRQ_EXTINT + 22) /* 22 EIC: EXTINT10 */
|
||||
#define SAM_IRQ_EXTINT11 (SAM_IRQ_EXTINT + 23) /* 23 EIC: EXTINT11 */
|
||||
#define SAM_IRQ_EXTINT12 (SAM_IRQ_EXTINT + 24) /* 24 EIC: EXTINT12 */
|
||||
#define SAM_IRQ_EXTINT13 (SAM_IRQ_EXTINT + 25) /* 25 EIC: EXTINT13 */
|
||||
#define SAM_IRQ_EXTINT14 (SAM_IRQ_EXTINT + 26) /* 26 EIC: EXTINT14 */
|
||||
#define SAM_IRQ_EXTINT15 (SAM_IRQ_EXTINT + 27) /* 27 EIC: EXTINT15 */
|
||||
#define SAM_IRQ_FREQM (SAM_IRQ_EXTINT + 28) /* 28 FREQM: Done */
|
||||
#define SAM_IRQ_NVMCTRL0 (SAM_IRQ_EXTINT + 29) /* 29 NVMCTRL: 0-7 */
|
||||
#define SAM_IRQ_NVMCTRL1 (SAM_IRQ_EXTINT + 30) /* 30 NVMCTRL: 8-10 */
|
||||
#define SAM_IRQ_DMACH0 (SAM_IRQ_EXTINT + 31) /* 31 DMA Channel 0: SUSP, TCMPL, TERR */
|
||||
#define SAM_IRQ_DMACH1 (SAM_IRQ_EXTINT + 32) /* 32 DMA Channel 1: SUSP, TCMPL, TERR */
|
||||
#define SAM_IRQ_DMACH2 (SAM_IRQ_EXTINT + 33) /* 33 DMA Channel 2: SUSP, TCMPL, TERR */
|
||||
#define SAM_IRQ_DMACH3 (SAM_IRQ_EXTINT + 34) /* 34 DMA Channel 3: SUSP, TCMPL, TERR */
|
||||
#define SAM_IRQ_DMACH4_31 (SAM_IRQ_EXTINT + 35) /* 35 DMA Channels 4-31: SUSP, TCMPL, TERR */
|
||||
#define SAM_IRQ_EVSYS0 (SAM_IRQ_EXTINT + 36) /* 36 EVSYS Channel 0: EVD, OVR */
|
||||
#define SAM_IRQ_EVSYS1 (SAM_IRQ_EXTINT + 37) /* 37 EVSYS Channel 1: EVD, OVR */
|
||||
#define SAM_IRQ_EVSYS2 (SAM_IRQ_EXTINT + 38) /* 38 EVSYS Channel 2: EVD, OVR */
|
||||
#define SAM_IRQ_EVSYS3 (SAM_IRQ_EXTINT + 39) /* 39 EVSYS Channel 3: EVD, OVR */
|
||||
#define SAM_IRQ_EVSYS4_11 (SAM_IRQ_EXTINT + 40) /* 40 EVSYS Channels 4-11: EVD, OVR */
|
||||
#define SAM_IRQ_PAC (SAM_IRQ_EXTINT + 41) /* 41 PAC: ERR */
|
||||
#define SAM_IRQ_RAMECC (SAM_IRQ_EXTINT + 45) /* 45 RAM ECC: 0-1 */
|
||||
#define SAM_IRQ_SERCOM0_0 (SAM_IRQ_EXTINT + 46) /* 46 SERCOM0: 0 */
|
||||
#define SAM_IRQ_SERCOM0_1 (SAM_IRQ_EXTINT + 47) /* 47 SERCOM0: 1 */
|
||||
#define SAM_IRQ_SERCOM0_2 (SAM_IRQ_EXTINT + 48) /* 48 SERCOM0: 2 */
|
||||
#define SAM_IRQ_SERCOM0_46 (SAM_IRQ_EXTINT + 49) /* 49 SERCOM0: 4-6 */
|
||||
#define SAM_IRQ_SERCOM1_0 (SAM_IRQ_EXTINT + 50) /* 50 SERCOM1: 0 */
|
||||
#define SAM_IRQ_SERCOM1_1 (SAM_IRQ_EXTINT + 51) /* 51 SERCOM1: 1 */
|
||||
#define SAM_IRQ_SERCOM1_2 (SAM_IRQ_EXTINT + 52) /* 52 SERCOM1: 2 */
|
||||
#define SAM_IRQ_SERCOM1_46 (SAM_IRQ_EXTINT + 53) /* 53 SERCOM1: 4-6 */
|
||||
#define SAM_IRQ_SERCOM2_0 (SAM_IRQ_EXTINT + 54) /* 54 SERCOM2: 0 */
|
||||
#define SAM_IRQ_SERCOM2_1 (SAM_IRQ_EXTINT + 55) /* 55 SERCOM2: 1 */
|
||||
#define SAM_IRQ_SERCOM2_2 (SAM_IRQ_EXTINT + 56) /* 56 SERCOM2: 2 */
|
||||
#define SAM_IRQ_SERCOM2_46 (SAM_IRQ_EXTINT + 57) /* 57 SERCOM2: 4-6 */
|
||||
#define SAM_IRQ_SERCOM3_0 (SAM_IRQ_EXTINT + 58) /* 58 SERCOM3: 0 */
|
||||
#define SAM_IRQ_SERCOM3_1 (SAM_IRQ_EXTINT + 59) /* 59 SERCOM3: 1 */
|
||||
#define SAM_IRQ_SERCOM3_2 (SAM_IRQ_EXTINT + 60) /* 60 SERCOM3: 2 */
|
||||
#define SAM_IRQ_SERCOM3_46 (SAM_IRQ_EXTINT + 61) /* 61 SERCOM3: 4-6 */
|
||||
#define SAM_IRQ_SERCOM4_0 (SAM_IRQ_EXTINT + 62) /* 62 SERCOM4: 0 */
|
||||
#define SAM_IRQ_SERCOM4_1 (SAM_IRQ_EXTINT + 63) /* 63 SERCOM4: 1 */
|
||||
#define SAM_IRQ_SERCOM4_2 (SAM_IRQ_EXTINT + 64) /* 64 SERCOM4: 2 */
|
||||
#define SAM_IRQ_SERCOM4_46 (SAM_IRQ_EXTINT + 65) /* 65 SERCOM4: 4-6 */
|
||||
#define SAM_IRQ_SERCOM5_0 (SAM_IRQ_EXTINT + 66) /* 66 SERCOM5: 0 */
|
||||
#define SAM_IRQ_SERCOM5_1 (SAM_IRQ_EXTINT + 67) /* 67 SERCOM5: 1 */
|
||||
#define SAM_IRQ_SERCOM5_2 (SAM_IRQ_EXTINT + 68) /* 68 SERCOM5: 2 */
|
||||
#define SAM_IRQ_SERCOM5_46 (SAM_IRQ_EXTINT + 69) /* 69 SERCOM5: 4-6 */
|
||||
#define SAM_IRQ_SERCOM6_0 (SAM_IRQ_EXTINT + 70) /* 70 SERCOM6: 0 */
|
||||
#define SAM_IRQ_SERCOM6_1 (SAM_IRQ_EXTINT + 71) /* 71 SERCOM6: 1 */
|
||||
#define SAM_IRQ_SERCOM6_2 (SAM_IRQ_EXTINT + 72) /* 72 SERCOM6: 2 */
|
||||
#define SAM_IRQ_SERCOM6_46 (SAM_IRQ_EXTINT + 73) /* 73 SERCOM6: 4-6 */
|
||||
#define SAM_IRQ_SERCOM7_0 (SAM_IRQ_EXTINT + 74) /* 74 SERCOM7: 0 */
|
||||
#define SAM_IRQ_SERCOM7_1 (SAM_IRQ_EXTINT + 75) /* 75 SERCOM7: 1 */
|
||||
#define SAM_IRQ_SERCOM7_2 (SAM_IRQ_EXTINT + 76) /* 76 SERCOM7: 2 */
|
||||
#define SAM_IRQ_SERCOM7_46 (SAM_IRQ_EXTINT + 77) /* 77 SERCOM7: 4-6 */
|
||||
#define SAM_IRQ_CAN0 (SAM_IRQ_EXTINT + 78) /* 78 CAN0: Line0, Line1 */
|
||||
#define SAM_IRQ_CAN1 (SAM_IRQ_EXTINT + 79) /* 79 CAN1: Line0, Line1 */
|
||||
#define SAM_IRQ_USB (SAM_IRQ_EXTINT + 80) /* 80 USB: EORSM, DNRSM, EORST RST,
|
||||
* LPM DCONN, LPMSUSP DDISC, MSOF,
|
||||
* RAMACER, RXSTP TXSTP 0-7, STALL0
|
||||
* STALL 0-7, STALL1 0-7, SUSPEND,
|
||||
* TRFAIL0 TRFAIL 097, TRFAIL1 PERR
|
||||
* 0..7, UPRSM, WAKEUP */
|
||||
#define SAM_IRQ_USBSOF (SAM_IRQ_EXTINT + 81) /* 81 USB: SOF HSOF */
|
||||
#define SAM_IRQ_USBTRCPT0 (SAM_IRQ_EXTINT + 82) /* 82 USB: TRCPT0 0..7 */
|
||||
#define SAM_IRQ_USBTRCPT1 (SAM_IRQ_EXTINT + 83) /* 83 USB: TRCPT0 0..7 */
|
||||
#define SAM_IRQ_GMAL (SAM_IRQ_EXTINT + 84) /* 84 GMAC: GMAC, WOL */
|
||||
#define SAM_IRQ_TCC0 (SAM_IRQ_EXTINT + 85) /* 85 TCC0: CNT A, DFS A, ERR A, FAULTA
|
||||
* A, FAULTB A, FAULT0 A, FAULT1 A,
|
||||
* OVF, TRG, UFS A */
|
||||
#define SAM_IRQ_TCC0MC0 (SAM_IRQ_EXTINT + 86) /* 86 TCC0: MC 0 */
|
||||
#define SAM_IRQ_TCC0MC1 (SAM_IRQ_EXTINT + 87) /* 87 TCC0: MC 1 */
|
||||
#define SAM_IRQ_TCC0MC2 (SAM_IRQ_EXTINT + 88) /* 88 TCC0: MC 2 */
|
||||
#define SAM_IRQ_TCC0MC3 (SAM_IRQ_EXTINT + 89) /* 89 TCC0: MC 3 */
|
||||
#define SAM_IRQ_TCC0MC4 (SAM_IRQ_EXTINT + 90) /* 90 TCC0: MC 4 */
|
||||
#define SAM_IRQ_TCC0MC5 (SAM_IRQ_EXTINT + 91) /* 91 TCC0: MC 5 */
|
||||
#define SAM_IRQ_TCC1 (SAM_IRQ_EXTINT + 92) /* 92 TCC1: CNT A, DFS A, ERR A, FAULTA
|
||||
* A, FAULTB A, FAULT0 A, FAULT1 A,
|
||||
* OVF, TRG, UFS A */
|
||||
#define SAM_IRQ_TCC1MC0 (SAM_IRQ_EXTINT + 93) /* 93 TCC1: MC 0 */
|
||||
#define SAM_IRQ_TCC1MC1 (SAM_IRQ_EXTINT + 94) /* 94 TCC1: MC 1 */
|
||||
#define SAM_IRQ_TCC1MC2 (SAM_IRQ_EXTINT + 95) /* 95 TCC1: MC 2 */
|
||||
#define SAM_IRQ_TCC1MC3 (SAM_IRQ_EXTINT + 96) /* 96 TCC1: MC 3 */
|
||||
#define SAM_IRQ_TCC2 (SAM_IRQ_EXTINT + 97) /* 97 TCC2: CNT A, DFS A, ERR A, FAULTA
|
||||
* A, FAULTB A, FAULT0 A, FAULT1 A,
|
||||
* OVF, TRG, UFS A */
|
||||
#define SAM_IRQ_TCC2MC0 (SAM_IRQ_EXTINT + 98) /* 98 TCC2: MC 0 */
|
||||
#define SAM_IRQ_TCC2MC1 (SAM_IRQ_EXTINT + 99) /* 99 TCC2: MC 1 */
|
||||
#define SAM_IRQ_TCC2MC2 (SAM_IRQ_EXTINT + 100) /* 100 TCC2: MC 2 */
|
||||
#define SAM_IRQ_TCC3 (SAM_IRQ_EXTINT + 101) /* 101 TCC3: CNT A, DFS A, ERR A, FAULTA
|
||||
* A, FAULTB A, FAULT0 A, FAULT1 A,
|
||||
* OVF, TRG, UFS A */
|
||||
#define SAM_IRQ_TCC3MC0 (SAM_IRQ_EXTINT + 102) /* 102 TCC3: MC 0 */
|
||||
#define SAM_IRQ_TCC3MC1 (SAM_IRQ_EXTINT + 103) /* 103 TCC3: MC 1 */
|
||||
#define SAM_IRQ_TCC4 (SAM_IRQ_EXTINT + 104) /* 104 TCC4: CNT A, DFS A, ERR A, FAULTA
|
||||
* A, FAULTB A, FAULT0 A, FAULT1 A,
|
||||
* OVF, TRG, UFS A */
|
||||
#define SAM_IRQ_TCC4MC0 (SAM_IRQ_EXTINT + 105) /* 105 TCC4: MC 0 */
|
||||
#define SAM_IRQ_TCC4MC1 (SAM_IRQ_EXTINT + 106) /* 106 TCC4: MC 1 */
|
||||
#define SAM_IRQ_TC0 (SAM_IRQ_EXTINT + 107) /* 107 TC0: ERR A, MC 0, MC 1, OVF */
|
||||
#define SAM_IRQ_TC1 (SAM_IRQ_EXTINT + 108) /* 108 TC1: ERR A, MC 0, MC 1, OVF */
|
||||
#define SAM_IRQ_TC2 (SAM_IRQ_EXTINT + 109) /* 109 TC2: ERR A, MC 0, MC 1, OVF */
|
||||
#define SAM_IRQ_TC3 (SAM_IRQ_EXTINT + 110) /* 110 TC3: ERR A, MC 0, MC 1, OVF */
|
||||
#define SAM_IRQ_TC4 (SAM_IRQ_EXTINT + 111) /* 111 TC4: ERR A, MC 0, MC 1, OVF */
|
||||
#define SAM_IRQ_TC5 (SAM_IRQ_EXTINT + 112) /* 112 TC5: ERR A, MC 0, MC 1, OVF */
|
||||
#define SAM_IRQ_TC6 (SAM_IRQ_EXTINT + 113) /* 113 TC6: ERR A, MC 0, MC 1, OVF */
|
||||
#define SAM_IRQ_TC7 (SAM_IRQ_EXTINT + 114) /* 114 TC7: ERR A, MC 0, MC 1, OVF */
|
||||
#define SAM_IRQ_PDEC (SAM_IRQ_EXTINT + 115) /* 115 PDEC: DIR A, ERR A, OVF, VLC A */
|
||||
#define SAM_IRQ_PDECMC0 (SAM_IRQ_EXTINT + 116) /* 116 PDEC: MC 0 */
|
||||
#define SAM_IRQ_PDECMC1 (SAM_IRQ_EXTINT + 117) /* 117 PDEC: MC 1 */
|
||||
#define SAM_IRQ_ADC0 (SAM_IRQ_EXTINT + 118) /* 118 ADC0: OVERRUN, WINMON */
|
||||
#define SAM_IRQ_ADC0RDY (SAM_IRQ_EXTINT + 119) /* 119 ADC0: RESRDY */
|
||||
#define SAM_IRQ_ADC1 (SAM_IRQ_EXTINT + 120) /* 120 ADC0: OVERRUN, WINMON */
|
||||
#define SAM_IRQ_ADC1RDY (SAM_IRQ_EXTINT + 121) /* 121 ADC0: RESRDY */
|
||||
#define SAM_IRQ_AC (SAM_IRQ_EXTINT + 122) /* 122 AC: COMP 0, COMP 1, WIN 0 */
|
||||
#define SAM_IRQ_DACERR (SAM_IRQ_EXTINT + 123) /* 123 DAC: OVERRUN A 0, OVERRUN A 1,
|
||||
* UNDERRUN A 0, UNDERRUN A 1 */
|
||||
#define SAM_IRQ_DACEMPTY0 (SAM_IRQ_EXTINT + 124) /* 124 DAC: EMPTY 0 */
|
||||
#define SAM_IRQ_DACEMPTY1 (SAM_IRQ_EXTINT + 125) /* 125 DAC: EMPTY 1 */
|
||||
#define SAM_IRQ_DACRDY0 (SAM_IRQ_EXTINT + 126) /* 126 DAC: RESRDY 0 */
|
||||
#define SAM_IRQ_DACRDY1 (SAM_IRQ_EXTINT + 127) /* 127 DAC: RESRDY 1 */
|
||||
#define SAM_IRQ_I2S (SAM_IRQ_EXTINT + 128) /* 128 I2S: RXOR 0, RXOR 1, RXRDY 0, RXRDY
|
||||
* 1, TXRDY 0, TXRDY 1, TXUR 0, TXUR 1 */
|
||||
#define SAM_IRQ_PCC (SAM_IRQ_EXTINT + 129) /* 129 PCC: */
|
||||
#define SAM_IRQ_AES (SAM_IRQ_EXTINT + 130) /* 130 AES: ENCCMP, GFMCMP */
|
||||
#define SAM_IRQ_TRNG (SAM_IRQ_EXTINT + 131) /* 131 TRNG: IS0 */
|
||||
#define SAM_IRQ_ICM (SAM_IRQ_EXTINT + 132) /* 132 ICM: */
|
||||
#define SAM_IRQ_PUKCC (SAM_IRQ_EXTINT + 133) /* 133 PUKCC: */
|
||||
#define SAM_IRQ_QSPI (SAM_IRQ_EXTINT + 134) /* 134 QSPI: */
|
||||
#define SAM_IRQ_SDHC0 (SAM_IRQ_EXTINT + 135) /* 135 SDHC0: SDHC0, TIMER */
|
||||
#define SAM_IRQ_SDHC1 (SAM_IRQ_EXTINT + 136) /* 136 SDHC1: SDHC1, TIMER */
|
||||
|
||||
#define SAM_IRQ_NEXTINT 137 /* Total number of external interrupt numbers */
|
||||
#define NR_IRQS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT) /* The number of vectors */
|
||||
#define SAM_IRQ_NEXTINT 137 /* Total number of external interrupt numbers */
|
||||
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT) /* The number of vectors */
|
||||
|
||||
/************************************************************************************************
|
||||
* Public Types
|
||||
|
||||
@@ -225,10 +225,10 @@
|
||||
* Peripheral: .... .... .... .... .... ....
|
||||
*/
|
||||
|
||||
#define PORT_OUTVALUE_SHIFT (12) /* Bit 12: Initial value of output */
|
||||
#define PORT_OUTVALUE_MASK (1 << PORT_SYNCHRONIZER_SHIFT)
|
||||
# define PORT_OUTPUT_CLEAR (0 << PORT_SYNCHRONIZER_SHIFT)
|
||||
# define PORT_OUTPUT_SET (1 << PORT_SYNCHRONIZER_SHIFT)
|
||||
#define PORT_OUTVALUE_SHIFT (12) /* Bit 12: Initial value of output */
|
||||
#define PORT_OUTVALUE_MASK (1 << PORT_OUTVALUE_SHIFT)
|
||||
# define PORT_OUTPUT_CLEAR (0 << PORT_OUTVALUE_SHIFT)
|
||||
# define PORT_OUTPUT_SET (1 << PORT_OUTVALUE_SHIFT)
|
||||
|
||||
/* Selections for external interrupts:
|
||||
*
|
||||
|
||||
@@ -200,7 +200,7 @@
|
||||
# define PORT_SYNCHRONIZER_OFF (0 << PORT_SYNCHRONIZER_SHIFT)
|
||||
# define PORT_SYNCHRONIZER_ON (1 << PORT_SYNCHRONIZER_SHIFT)
|
||||
|
||||
/* Output and Input Buffer both enabled to let readback
|
||||
/* Output and Input Buffer both enabled to support readback of output pins.
|
||||
*
|
||||
* MODE BITFIELDS
|
||||
* ------------ -----------------------------
|
||||
@@ -217,7 +217,7 @@
|
||||
# define PORT_OUTREADBACK_DISABLE (0 << PORT_OUTREADBACK_SHIFT)
|
||||
# define PORT_OUTREADBACK_ENABLE (1 << PORT_OUTREADBACK_SHIFT)
|
||||
|
||||
/* If the pin is an PORT output, then this identifies the initial output value:
|
||||
/* If the pin is a PORT output, then this identifies the initial output value:
|
||||
*
|
||||
* MODE BITFIELDS
|
||||
* ------------ -----------------------------
|
||||
@@ -229,10 +229,10 @@
|
||||
* Peripheral: .... .... .... .... .... ....
|
||||
*/
|
||||
|
||||
#define PORT_OUTVALUE_SHIFT (12) /* Bit 12: Initial value of output */
|
||||
#define PORT_OUTVALUE_MASK (1 << PORT_SYNCHRONIZER_SHIFT)
|
||||
# define PORT_OUTPUT_CLEAR (0 << PORT_SYNCHRONIZER_SHIFT)
|
||||
# define PORT_OUTPUT_SET (1 << PORT_SYNCHRONIZER_SHIFT)
|
||||
#define PORT_OUTVALUE_SHIFT (12) /* Bit 12: Initial value of output */
|
||||
#define PORT_OUTVALUE_MASK (1 << PORT_OUTVALUE_SHIFT)
|
||||
# define PORT_OUTPUT_CLEAR (0 << PORT_OUTVALUE_SHIFT)
|
||||
# define PORT_OUTPUT_SET (1 << PORT_OUTVALUE_SHIFT)
|
||||
|
||||
/* Selections for external interrupts:
|
||||
*
|
||||
|
||||
@@ -676,7 +676,7 @@ static int sam_interrupt(int irq, void *context, FAR void *arg)
|
||||
|
||||
intflag = sam_serialin8(priv, SAM_USART_INTFLAG_OFFSET);
|
||||
inten = sam_serialin8(priv, SAM_USART_INTENCLR_OFFSET);
|
||||
pending = intflag & inten;
|
||||
pending = intflag & inten;
|
||||
|
||||
/* Handle an incoming, receive byte. The RXC flag is set when there is
|
||||
* unread data in DATA register. This flag is cleared by reading the DATA
|
||||
@@ -907,9 +907,9 @@ static void sam_rxint(struct uart_dev_s *dev, bool enable)
|
||||
|
||||
if (enable)
|
||||
{
|
||||
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
|
||||
/* Receive an interrupt when their is anything in the Rx data register */
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
|
||||
sam_serialout8(priv, SAM_USART_INTENSET_OFFSET, USART_INT_RXC);
|
||||
#endif
|
||||
}
|
||||
@@ -963,11 +963,11 @@ static void sam_txint(struct uart_dev_s *dev, bool enable)
|
||||
flags = enter_critical_section();
|
||||
if (enable)
|
||||
{
|
||||
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
|
||||
/* Set to receive an interrupt when the TX holding register register
|
||||
* is empty
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
|
||||
sam_serialout8(priv, SAM_USART_INTENSET_OFFSET, USART_INT_DRE);
|
||||
|
||||
/* Fake a TX interrupt here by just calling uart_xmitchars() with
|
||||
@@ -975,7 +975,6 @@ static void sam_txint(struct uart_dev_s *dev, bool enable)
|
||||
*/
|
||||
|
||||
uart_xmitchars(dev);
|
||||
|
||||
#endif
|
||||
}
|
||||
else
|
||||
|
||||
@@ -29,4 +29,21 @@ config METRO_M4_RUNFROMSRAM
|
||||
from SRAM.
|
||||
|
||||
endchoice # Execution memory
|
||||
|
||||
config METRO_M4_32KHZXTAL
|
||||
bool "32.768 KHz XTAL"
|
||||
default n
|
||||
---help---
|
||||
According to the schematic, a 32.768 KHz crystal is installed on
|
||||
board. However, I have been unable to use this crystal and thought
|
||||
perhaps it is missing or defective on my board (there is a metal
|
||||
package that could be a crystal on board, but I am not certain).
|
||||
Another, more likely option is that there is a coding error on my
|
||||
part that prevents the 32.768 KHz crystal from usable(?)
|
||||
|
||||
The configuration defaults to using the always-on OSCULP32 as the
|
||||
slow clock source. This option will select instead XOSC32 as the
|
||||
slow clock source.
|
||||
|
||||
|
||||
endif # ARCH_BOARD_METRO_M4
|
||||
|
||||
@@ -92,17 +92,23 @@ STATUS
|
||||
3. GCLK3 ->SERCOM slow clock channel.
|
||||
This hangs when I try to enable the peripheral clock.
|
||||
|
||||
2018-08-31: I found a workaround by substituting OSCULP32K for XOSC32
|
||||
as the source to GCLK3 (workaround *NOT* committed):
|
||||
2018-09-01: I found a workaround by substituting OSCULP32K for XOSC32
|
||||
as the source to GCLK3:
|
||||
|
||||
-#define BOARD_GCLK3_SOURCE 5 /* Select XOSC32K as GCLK3 source */
|
||||
+#define BOARD_GCLK3_SOURCE 4 /* Select OSCULP32K as GCLK3 source */
|
||||
|
||||
With that workaround, the port gets past all clock and USART
|
||||
configuration and, in fact, completely through OS initialization and
|
||||
aplication startup! The NSH shell runs and the NSH prompt is presented
|
||||
application startup! The NSH shell runs and the NSH prompt is presented
|
||||
on the serial console at the correct baud. Serial input, however, is
|
||||
not received so there is still more to be done.
|
||||
not received. There are no serial Rx interrupts! So there is still
|
||||
more to be done.
|
||||
|
||||
A new configuration option was added, CONFIG_METRO_M4_32KHZXTAL. By
|
||||
default this workaround is in place. But you can enabled
|
||||
CONFIG_METRO_M4_32KHZXTAL if you want to further study the XOSC32K
|
||||
problem.
|
||||
|
||||
Unlocking FLASH
|
||||
===============
|
||||
|
||||
@@ -57,10 +57,13 @@
|
||||
/* Clocking *************************************************************************/
|
||||
/* Overview
|
||||
*
|
||||
* The Adafruit Metro M4 Pro has one on-board crystal:
|
||||
* Per the schematic Adafruit Metro M4 Pro has one on-board crystal:
|
||||
*
|
||||
* X4 32.768KHz XOSC32
|
||||
*
|
||||
* However, I have been unsuccessful using it and have fallen back to using OSCULP32K
|
||||
* (Unless CONFIG_METRO_M4_32KHZXTAL=y)
|
||||
*
|
||||
* Since there is no high speed crystal, we will run from the OSC16M clock source.
|
||||
*
|
||||
* OSC48M Output = 48Mhz
|
||||
@@ -78,6 +81,7 @@
|
||||
* CPU Input = 120MHz
|
||||
*/
|
||||
|
||||
#define BOARD_OSC32K_FREQUENCY 32768 /* OSCULP32K frequency 32.768 KHz (nominal) */
|
||||
#define BOARD_XOSC32K_FREQUENCY 32768 /* XOSC32K frequency 32.768 KHz */
|
||||
#define BOARD_DFLL_FREQUENCY 48000000 /* FDLL frequency 28MHz */
|
||||
#define BOARD_XOSC0_FREQUENCY 12000000 /* XOSC0 frequency 12MHz (disabled) */
|
||||
@@ -88,7 +92,11 @@
|
||||
#define BOARD_GCLK0_FREQUENCY BOARD_DPLL0_FREQUENCY
|
||||
#define BOARD_GCLK1_FREQUENCY BOARD_DFLL_FREQUENCY
|
||||
#define BOARD_GCLK2_FREQUENCY (BOARD_XOSC32K_FREQUENCY / 4) /* Disabled */
|
||||
#define BOARD_GCLK3_FREQUENCY BOARD_XOSC32K_FREQUENCY /* Disabled */
|
||||
#ifdef CONFIG_METRO_M4_32KHZXTAL
|
||||
# define BOARD_GCLK3_FREQUENCY BOARD_XOSC32K_FREQUENCY /* Enabled */
|
||||
#else
|
||||
# define BOARD_GCLK3_FREQUENCY BOARD_OSC32K_FREQUENCY /* Always-on */
|
||||
#endif
|
||||
#define BOARD_GCLK4_FREQUENCY BOARD_DPLL0_FREQUENCY
|
||||
#define BOARD_GCLK5_FREQUENCY (BOARD_DFLL_FREQUENCY / 24)
|
||||
#define BOARD_GCLK6_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
|
||||
@@ -101,8 +109,13 @@
|
||||
|
||||
/* XOSC32 */
|
||||
|
||||
#define BOARD_HAVE_XOSC32K 1 /* 32.768 KHz XOSC32 crystal installed */
|
||||
#define BOARD_XOSC32K_ENABLE TRUE /* Enable XOSC32 */
|
||||
#ifdef CONFIG_METRO_M4_32KHZXTAL
|
||||
# define BOARD_HAVE_XOSC32K 1 /* 32.768 KHz XOSC32 crystal installed */
|
||||
# define BOARD_XOSC32K_ENABLE TRUE /* Enable XOSC32 */
|
||||
#else
|
||||
# define BOARD_HAVE_XOSC32K 0 /* No 32.768 KHz XOSC32 crystal installed */
|
||||
# define BOARD_XOSC32K_ENABLE FALSE /* Disable XOSC32 */
|
||||
#endif
|
||||
#define BOARD_XOSC32K_XTALEN TRUE /* Crystal connected on XIN32 */
|
||||
#define BOARD_XOSC32K_EN32K FALSE /* No 32KHz output */
|
||||
#define BOARD_XOSC32K_EN1K FALSE /* No 1KHz output */
|
||||
@@ -166,14 +179,18 @@
|
||||
#define BOARD_GCLK2_OOV FALSE /* Clock output will be LOW */
|
||||
#define BOARD_GCLK2_OE FALSE /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK2_RUNSTDBY FALSE /* Don't run in standby */
|
||||
#define BOARD_GCLK2_SOURCE 5 /* Select XOSC32K as GCLK2 source */
|
||||
#define BOARD_GCLK2_SOURCE 1 /* Select XOSC1 as GCLK2 source */
|
||||
#define BOARD_GCLK2_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK3_ENABLE TRUE /* Enable GCLK3 */
|
||||
#define BOARD_GCLK3_OOV FALSE /* Clock output will be LOW */
|
||||
#define BOARD_GCLK3_OE FALSE /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK3_RUNSTDBY FALSE /* Don't run in standby */
|
||||
#define BOARD_GCLK3_SOURCE 5 /* Select XOSC32K as GCLK3 source */
|
||||
#ifdef CONFIG_METRO_M4_32KHZXTAL
|
||||
# define BOARD_GCLK3_SOURCE 5 /* Select XOSC32K as GCLK3 source */
|
||||
#else
|
||||
# define BOARD_GCLK3_SOURCE 4 /* Select OSCULP32K as GCLK3 source */
|
||||
#endif
|
||||
#define BOARD_GCLK3_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK4_ENABLE TRUE /* Enable GCLK4 */
|
||||
@@ -418,18 +435,18 @@
|
||||
* D1 PA22 SERCOM3 PAD0 TXD
|
||||
*
|
||||
* NOTES:
|
||||
* USART_CTRLA_TXPAD0_1: TxD=PAD0XCK=N/A RTS/TE=PAD2 CTS=PAD3
|
||||
* USART_CTRLA_RXPAD2: RxD=PAD1
|
||||
* USART_CTRLA_TXPAD0_2: TxD=PAD0 XCK=N/A RTS/TE=PAD2 CTS=PAD3
|
||||
* USART_CTRLA_RXPAD1: RxD=PAD1
|
||||
*/
|
||||
|
||||
#define BOARD_SERCOM3_MUXCONFIG (USART_CTRLA_TXPAD0_2 | USART_CTRLA_RXPAD2)
|
||||
#define BOARD_SERCOM3_PINMAP_PAD0 PORT_SERCOM3_PAD0_1 /* USART TX */
|
||||
#define BOARD_SERCOM3_PINMAP_PAD1 PORT_SERCOM3_PAD1_1 /* USART RX */
|
||||
#define BOARD_SERCOM3_PINMAP_PAD2 0 /* (not used) */
|
||||
#define BOARD_SERCOM3_PINMAP_PAD3 0 /* (not used) */
|
||||
#define BOARD_SERCOM3_MUXCONFIG (USART_CTRLA_TXPAD0_2 | USART_CTRLA_RXPAD1)
|
||||
#define BOARD_SERCOM3_PINMAP_PAD0 PORT_SERCOM3_PAD0_1 /* PAD0: USART TX */
|
||||
#define BOARD_SERCOM3_PINMAP_PAD1 PORT_SERCOM3_PAD1_1 /* PAD1: USART RX */
|
||||
#define BOARD_SERCOM3_PINMAP_PAD2 0 /* PAD2: (not used) */
|
||||
#define BOARD_SERCOM3_PINMAP_PAD3 0 /* PAD3: (not used) */
|
||||
|
||||
#define BOARD_TXIRQ_SERCOM3 SAM_IRQ_SERCOM3_0
|
||||
#define BOARD_RXIRQ_SERCOM3 SAM_IRQ_SERCOM3_1
|
||||
#define BOARD_TXIRQ_SERCOM3 SAM_IRQ_SERCOM3_0 /* PAD0 */
|
||||
#define BOARD_RXIRQ_SERCOM3 SAM_IRQ_SERCOM3_1 /* PAD1 */
|
||||
|
||||
#define BOARD_SERCOM3_COREGEN 1 /* 48MHz Core clock */
|
||||
#define BOARD_SERCOM3_CORELOCK FALSE /* Don't lock the CORECLOCK */
|
||||
|
||||
Reference in New Issue
Block a user