A10: Fix error in IRQ dispatch; vector table seems to be offset by 64 bytes?

arch/arm/src/a1x/a1x_boot.c

@@ -270,7 +270,7 @@ static void a1x_copyvectorblock(void)
 
   src  = (uint32_t*)&_vector_start;
   end  = (uint32_t*)&_vector_end;
-  dest = (uint32_t*)A1X_VECTOR_VSRAM;
+  dest = (uint32_t*)(A1X_VECTOR_VSRAM + VECTOR_TABLE_OFFSET);
 
   while (src < end)
     {

arch/arm/src/a1x/a1x_irq.c

@@ -304,7 +304,7 @@ uint32_t *arm_decodeirq(uint32_t *regs)
 
               else
                 {
-                  if ((pending & 0x00000001) == 0)
+                  if ((pending & 0x00000001) != 0)
                     {
                       /* Yes.. dispatch the interrupt */
 

arch/arm/src/a1x/chip/a10_memorymap.h

@@ -576,9 +576,13 @@
  *   A1X_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM
  *   A1X_VECTOR_VSRAM - Virtual address of vector table in SRAM
  *   A1X_VECTOR_VADDR - Virtual address of vector table (0x00000000 or 0xffff0000)
+ *
+ * NOTE: When using LOWVECTORS, the actual base of the vectors appears to be
+ * offset to address 0x0000:0040
  */
 
 #define VECTOR_TABLE_SIZE         0x00010000
+#define VECTOR_TABLE_OFFSET       0x00000040
 
 #ifdef CONFIG_ARCH_LOWVECTORS  /* Vectors located at 0x0000:0000  */
 

arch/arm/src/armv7-a/cache.h

@@ -896,7 +896,7 @@ extern "C" {
  * Description:
  *   Ensure that the I and D caches are coherent within specified region
  *   by cleaning the D cache (i.e., flushing the D cache contents to memory
- *   and invalidating the I cache. This is typically used when code has been
+ *   and invalidating the I cache). This is typically used when code has been
  *   written to a memory region, and will be executed.
  *
  * Input Parameters: