Merged in ziggurat29/nuttx/extended_clock_work (pull request #10)

support for HSE and MSI clock sources; prelude to USB

arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h

@@ -120,8 +120,8 @@
 
 /* Clock control register */
 
-#define RCC_CR_MSION                (1 << 0)  /* Bit 0: Internal Medium Speed clock enable */
-#define RCC_CR_MSIRDY               (1 << 1)  /* Bit 1: Internal Medium Speed clock ready flag */
+#define RCC_CR_MSION                (1 << 0)  /* Bit 0: Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY               (1 << 1)  /* Bit 1: Internal Multi Speed clock ready flag */
 #define RCC_CR_MSIPLLEN             (1 << 2)  /* Bit 2: MSI clock PLL enable */
 #define RCC_CR_MSIRGSEL             (1 << 3)  /* Bit 2: MSI clock range selection */
 #define RCC_CR_MSIRANGE_SHIFT       (4)       /* Bits 7-4: MSI clock range */
@@ -161,9 +161,9 @@
 #define RCC_CR_HSITRIM_MASK         (0x1f << RCC_CR_HSITRIM_SHIFT)
 #define RCC_CR_HSICAL_SHIFT         (16)      /* Bits 23-16: Internal High Speed clock Calibration */
 #define RCC_CR_HSICAL_MASK          (0xff << RCC_CR_HSICAL_SHIFT)
-#define RCC_CR_MSITRIM_SHIFT        (8)       /* Bits 15-8: Internal Medium Speed clock trimming */
+#define RCC_CR_MSITRIM_SHIFT        (8)       /* Bits 15-8: Internal Multi Speed clock trimming */
 #define RCC_CR_MSITRIM_MASK         (0xff << RCC_CR_MSITRIM_SHIFT)
-#define RCC_CR_MSICAL_SHIFT         (0)       /* Bits 7-0: Internal Menium Speed clock Calibration */
+#define RCC_CR_MSICAL_SHIFT         (0)       /* Bits 7-0: Internal Multi Speed clock Calibration */
 #define RCC_CR_MSICAL_MASK          (0xff << RCC_CR_MSICAL_SHIFT)
 
 /* Clock configuration register */

arch/arm/src/stm32l4/stm32l4x6xx_rcc.c

@@ -57,9 +57,10 @@
 
 #define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
 
-/* Same for HSI */
+/* Same for HSI and MSI */
 
 #define HSIRDY_TIMEOUT HSERDY_TIMEOUT
+#define MSIRDY_TIMEOUT HSERDY_TIMEOUT
 
 /* HSE divisor to yield ~1MHz RTC clock */
 
@@ -578,14 +579,38 @@ static void stm32l4_stdclockconfig(void)
 #elif defined(STM32L4_BOARD_USEMSI)
   /* Enable Internal Multi-Speed Clock (MSI) */
 
-#  error STM32L4_BOARD_USEMSI not yet implemented in arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
+  /* Wait until the MSI is either off or ready (or until a timeout elapsed) */
+
+  for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
+    {
+      if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION))
+        {
+          /* If so, then break-out with timeout > 0 */
+
+          break;
+        }
+    }
+
   /* setting MSIRANGE */
-  /* setting MSIPLLEN */
 
   regval  = getreg32(STM32L4_RCC_CR);
-  regval |= RCC_CR_MSION;           /* Enable MSI */
+  regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION);    /* Enable MSI and frequ */
   putreg32(regval, STM32L4_RCC_CR);
 
+  /* Wait until the MSI is ready (or until a timeout elapsed) */
+
+  for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
+    {
+      /* Check if the MSIRDY flag is the set in the CR */
+
+      if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0)
+        {
+          /* If so, then break-out with timeout > 0 */
+
+          break;
+        }
+    }
+
 #elif defined(STM32L4_BOARD_USEHSE)
   /* Enable External High-Speed Clock (HSE) */
 
@@ -696,6 +721,8 @@ static void stm32l4_stdclockconfig(void)
 
 #ifdef STM32L4_BOARD_USEHSI
       regval |= RCC_PLLCFG_PLLSRC_HSI;
+#elif defined(STM32L4_BOARD_USEMSI)
+      regval |= RCC_PLLCFG_PLLSRC_MSI;
 #else /* if STM32L4_BOARD_USEHSE */
       regval |= RCC_PLLCFG_PLLSRC_HSE;
 #endif
@@ -833,6 +860,14 @@ static void stm32l4_stdclockconfig(void)
        */
 
       stm32l4_rcc_enablelse();
+
+#  if defined(STM32L4_BOARD_USEMSI)
+      /* now that LSE is up, auto trim the MSI */
+
+      regval  = getreg32(STM32L4_RCC_CR);
+      regval |= RCC_CR_MSIPLLEN;
+      putreg32(regval, STM32L4_RCC_CR);
+#  endif
 #endif
 
 #if defined(STM32L4_USE_CLK48)