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arch/stm32: Fix nxstyle errors

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arch/arm/src/stm32/stm32_wdg.h:
arch/arm/src/stm32/stm32f40xxx_rtcc.c:
arch/arm/src/stm32/stm32l15xxx_alarm.h:

    * Fix nxstyle errors.
This commit is contained in:
Nathan Hartman
2020-11-27 16:11:54 -05:00
committed by Xiang Xiao
parent 4305718691
commit 675c1b8457
3 changed files with 24 additions and 14 deletions
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arch/arm/src/stm32/stm32_wdg.h
+3 -3
View File
@@ -63,7 +63,7 @@ extern "C"
#endif
/****************************************************************************
* Public Functions
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
@@ -92,8 +92,8 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq);
* Name: stm32_wwdginitialize
*
* Description:
* Initialize the WWDG watchdog time. The watchdog timer is initializeed and
* registers as 'devpath. The initial state of the watchdog time is
* Initialize the WWDG watchdog time. The watchdog timer is initializeed
* and registers as 'devpath. The initial state of the watchdog time is
* disabled.
*
* Input Parameters:
arch/arm/src/stm32/stm32f40xxx_rtcc.c
+19 -10
View File
@@ -247,8 +247,8 @@ static void rtc_wprunlock(void)
stm32_pwr_enablebkp(true);
/* The following steps are required to unlock the write protection on all the
* RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR).
/* The following steps are required to unlock the write protection on all
* the RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR):
*
* 1. Write 0xCA into the RTC_WPR register.
* 2. Write 0x53 into the RTC_WPR register.
@@ -867,16 +867,20 @@ static int stm32_rtc_getalarmdatetime(rtc_alarmreg_t reg, FAR struct tm *tp)
* ranges of values correspond between struct tm and the time register.
*/
tmp = (data & (RTC_ALRMR_SU_MASK | RTC_ALRMR_ST_MASK)) >> RTC_ALRMR_SU_SHIFT;
tmp = (data & (RTC_ALRMR_SU_MASK | RTC_ALRMR_ST_MASK)) >>
RTC_ALRMR_SU_SHIFT;
tp->tm_sec = rtc_bcd2bin(tmp);
tmp = (data & (RTC_ALRMR_MNU_MASK | RTC_ALRMR_MNT_MASK)) >> RTC_ALRMR_MNU_SHIFT;
tmp = (data & (RTC_ALRMR_MNU_MASK | RTC_ALRMR_MNT_MASK)) >>
RTC_ALRMR_MNU_SHIFT;
tp->tm_min = rtc_bcd2bin(tmp);
tmp = (data & (RTC_ALRMR_HU_MASK | RTC_ALRMR_HT_MASK)) >> RTC_ALRMR_HU_SHIFT;
tmp = (data & (RTC_ALRMR_HU_MASK | RTC_ALRMR_HT_MASK)) >>
RTC_ALRMR_HU_SHIFT;
tp->tm_hour = rtc_bcd2bin(tmp);
tmp = (data & (RTC_ALRMR_DU_MASK | RTC_ALRMR_DT_MASK)) >> RTC_ALRMR_DU_SHIFT;
tmp = (data & (RTC_ALRMR_DU_MASK | RTC_ALRMR_DT_MASK)) >>
RTC_ALRMR_DU_SHIFT;
tp->tm_mday = rtc_bcd2bin(tmp);
return OK;
@@ -981,13 +985,16 @@ int up_rtc_initialize(void)
#if defined(CONFIG_STM32_RTC_HSECLOCK)
/* Change to the new clock as the input to the RTC block */
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_HSE);
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK,
RCC_XXX_RTCSEL_HSE);
#elif defined(CONFIG_STM32_RTC_LSICLOCK)
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSI);
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK,
RCC_XXX_RTCSEL_LSI);
#elif defined(CONFIG_STM32_RTC_LSECLOCK)
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSE);
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK,
RCC_XXX_RTCSEL_LSE);
#endif
putreg32(tr_bkp, STM32_RTC_TR);
@@ -997,7 +1004,9 @@ int up_rtc_initialize(void)
putreg32(RTC_MAGIC, RTC_MAGIC_REG);
/* Enable the RTC Clock by setting the RTCEN bit in the RCC register */
/* Enable the RTC Clock by setting the RTCEN bit in the RCC
* register
*/
modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_RTCEN);
}
arch/arm/src/stm32/stm32l15xxx_alarm.h
+2 -1
View File
@@ -152,7 +152,8 @@ int stm32_rtc_cancelalarm(enum alm_id_e alarmid);
*
****************************************************************************/
int stm32_rtc_setperiodic(FAR const struct timespec *period, wakeupcb_t callback);
int stm32_rtc_setperiodic(FAR const struct timespec *period,
wakeupcb_t callback);
/****************************************************************************
* Name: stm32_rtc_cancelperiodic