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Add STM32L15X memory map
This commit is contained in:
Gregory Nutt
@@ -4732,4 +4732,6 @@
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* arch/arm/include/stm32/stm32l15xxx_irq.h and arch/arm/src/stm32/chip/stm32l15xxx_vectors.h:
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Support for STM32L15X interrupt vectors (2013-5-18).
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* arch/arm/src/stm32/chip/stm32l15xxx_gpio.h and related STM32 GPIO files:
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Add GPIO support for the STM32L215X
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Add GPIO support for the STM32L215X (2013-5-18).
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* arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h: STM32L215X memory map
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(2013-5-18).
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@@ -43,7 +43,9 @@
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#include <nuttx/config.h>
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#include "chip.h"
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#if defined(CONFIG_STM32_STM32F10XX)
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#if defined(CONFIG_STM32_STM32L15XX)
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# include "chip/stm32l15xxx_memorymap.h"
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#elif defined(CONFIG_STM32_STM32F10XX)
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# include "chip/stm32f10xxx_memorymap.h"
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#elif defined(CONFIG_STM32_STM32F20XX)
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# include "chip/stm32f20xxx_memorymap.h"
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@@ -0,0 +1,142 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h
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* For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based 32-bit MCUs
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_MEMORYMAP_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_MEMORYMAP_H
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* STM32F40XXX Address Blocks *******************************************************/
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#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
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#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
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#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
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/* 0x60000000-0xdfffffff: Reserved */
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#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
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#define STM32_REGION_MASK 0xf0000000
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#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
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/* Code Base Addresses **************************************************************/
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#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x07ffffff: Aliased boot memory */
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#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x0801ffff: FLASH memory */
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/* 0x08020000-0x807fffff: Reserved */
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#define STM32_EEPROM_BASE 0x08080000 /* 0x10000000-0x1000ffff: 64Kb CCM data RAM */
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/* 0x10010000-0x1ffeffff: Reserved */
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#define STM32_SYSMEM_BASE 0x1ff00000 /* 0x1ff00000-0x1ff00fff: System memory */
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/* 0x1ff01000-0x1fff7fff: Reserved */
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#define STM32_OPTION_BASE 0x1ff80000 /* 0x1fffc000-0x1ff8001f: Option bytes */
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/* 0x1ff80020-0x1fffffff: Reserved */
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/* Peripheral Base Addresses ********************************************************/
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#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40007c03: APB1 */
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/* 0x40007c04-0x4000ffff: Reserved */
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#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40013bff: APB2 */
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/* 0x40013c00-0x4001ffff: Reserved */
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#define STM32_AHB_BASE 0x40020000 /* 0x40020000-0xa0000fff: AHB */
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/* 0xa0001000-0x4fffffff: Reserved */
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/* APB1 Base Addresses **************************************************************/
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#define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff TIM2 */
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#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */
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#define STM32_TIM4_BASE 0x40000800 /* 0x40000800-0x40000bff TIM4 */
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#define STM32_TIM5_BASE 0x40000800 /* 0x40000c00-0x40000fff TIM5 */
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#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */
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#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */
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#define STM32_LCD_BASE 0x40002400 /* 0x40002400-0x400027ff LCD */
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#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
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#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
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#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
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#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2 */
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#define STM32_SPI3_BASE 0x40003c00 /* 0x40003c00-0x40003fff SPI3 */
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#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */
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#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff USART3 */
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#define STM32_USART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff USART4 */
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#define STM32_USART5_BASE 0x40005000 /* 0x40005000-0x400053ff USART5 */
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#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */
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#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */
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#define STM32_USB_BASE 0x40005c00 /* 0x40005c00-0x40005fff USB device FS */
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#define STM32_USBRAM_BASE 0x40006000 /* 0x40006000-0x400063ff USB SRAM 512B */
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#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */
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#define STM32_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff DAC (dual) */
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#define STM32_DAC_COMP 0x40007c00 /* 0x40007c00-0x40007c03 COMP */
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#define STM32_DAC_RI 0x40007c04 /* 0x40007c04-0x40007c5b RI */
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#define STM32_DAC_OPAMP 0x40007c5c /* 0x40007c5c-0x40007fff OPAMP */
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/* APB2 Base Addresses **************************************************************/
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#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103FF SYSCFG */
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#define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107FF EXTI */
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#define STM32_TIM9_BASE 0x40010800 /* 0x40010800-0x40010bff TIM9 */
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#define STM32_TIM10_BASE 0x40010c00 /* 0x40010c00-0x40010fff TIM10 */
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#define STM32_ADC_BASE 0x40012400 /* 0x40012400-0x400127ff ADC */
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#define STM32_SDIO_BASE 0x40012c00 /* 0x40012c00-0x40012fff SDIO */
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#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */
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#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */
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/* AHB Base Addresses ***************************************************************/
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#define STM32_GPIOA_BASE 0x40020000 /* 0x40020000-0x400203ff GPIO Port A */
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#define STM32_GPIOB_BASE 0x40020400 /* 0x40020400-0x400207ff GPIO Port B */
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#define STM32_GPIOC_BASE 0x40020800 /* 0x40020800-0x40020bff GPIO Port C */
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#define STM32_GPIOD_BASE 0x40020c00 /* 0x40020c00-0x40020fff GPIO Port D */
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#define STM32_GPIOE_BASE 0x40021000 /* 0x40021000-0x400213ff GPIO Port E */
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#define STM32_GPIOH_BASE 0x40021400 /* 0x40021400-0x400217ff GPIO Port H */
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#define STM32_GPIOF_BASE 0x40021800 /* 0x40021800-0x40021bff GPIO Port F */
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#define STM32_GPIOG_BASE 0x40021c00 /* 0x40021c00-0x40021fff GPIO Port G */
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#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff CRC */
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#define STM32_RCC_BASE 0x40023800 /* 0x40023800-0x40023bff RCC */
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#define STM32_FLASHIF_BASE 0x40023c00 /* 0x40023c00-0x40023fff Flash memory interface */
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#define STM32_DMA1_BASE 0x40026000 /* 0x40026000-0x400263ff DMA1 */
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#define STM32_DMA2_BASE 0x40026400 /* 0x40026400-0x400267ff DMA2 */
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#define STM32_AES_BASE 0x50060000 /* 0x50060000-0x500603ff AES */
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#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xa0000fff FSMC */
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/* Cortex-M4 Base Addresses *********************************************************/
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/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this
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* address range
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*/
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#define STM32_SCS_BASE 0xe000e000
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#define STM32_DEBUGMCU_BASE 0xe0042000
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_MEMORYMAP_H */
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