Merge branch 'master' into can

2026-05-21 21:34:07 +08:00 · 2016-05-19 21:49:31 +02:00
parent 8aae953f67 34c0c7b54c
commit 6642898ee4
169 changed files with 10053 additions and 2174 deletions
@@ -11718,3 +11718,35 @@
 	* Several Makefiles: Add .PHONY definitions to prevent 'clean up to date'
 	  message weirdness when 'make clean' is done with no .config or Make.defs
 	  file (2016-05-10).
+	* include/nuttx/can.h and drivers/can.c:  Improve CAN error reporting.
+	  From Frank Benkert (2016-05-11).
+	* fs/Kconfig:  Allow CONFIG_FS_WRITABLE to be manually selectable
+	  (2016-05-11).
+	* Various file:  Search for places where a stray semicolon following an
+	  if condition cause the if body to be executed unconditionally.  Fixes
+	  in all SAM DMA logic, unionfs, OS signalling logic,
+	* configs/nucleo-144: Basic port for the Nucleo-144 board with the
+	  STM32F746ZG MCU.  From Kconstantin Berezenko (2015-05-12).
+	* arch/arm-src/armv7-a:  Complete re-design of logic to initialize each
+	  CPUn, n > 0, when CONFIG_SMP=y (2016-05-13).
+	* arch/arm/src/imx6 and configs/sabre-6quad:  The basic i.MX6 port is
+	  complete.  This is a very minimal port at present and probably still
+	  has some as-of-yet-undiscovered issues (2016-05-17).
+	* arch/*/Makefile: Add definitions that can be overrided to use GCC
+	  instead of LD in the final link.  From Paul Alexander Patience
+	  (2016-05-18) .
+	* arch/arm/src/stm32, stm32l4, and stm32f7 serial:  Add support for
+	  compliant BSD-style breaks. From David Sidrane (2016-05-18).
+	* enter/leave_critical_section() may attempt to access task lists before
+	  they have been initialized in the SMP configuration (2016-05-18).
+	* configs/stm32f103-minimum: Add support for this minimual STM32F103CBT6
+	  "blue" board.  From Alan Carvalho de Assis (2016-05-18).
+	* arch/arm/src/sam* Watchdogs:  Rename up_wdginitialize() to something
+	  more appropriate for an internal, MCU-specific function (2016-05-18).
+	* configs/*/src/*_watchdog.c:  Remove all implementations of
+	  up_wdginitialize() which was only used by apps/examples/watchdog.
+	  That internal OS function is no longer called from application code.
+	  If you want to use the watchdog example, you will need to configure
+	  the watchdog driver by calling the appropriate, MCU-specific driver
+	  configuration function from your board initialization logic
+	  (2016-05-18).
@@ -12,7 +12,7 @@
      <h1><big><font color="#3c34ec">
        <i>NuttX RTOS Porting Guide</i>
      </font></big></h1>
-      <p>Last Updated: March 28, 2016</p>
+      <p>Last Updated: May 12, 2016</p>
    </td>
  </tr>
 </table>
@@ -154,9 +154,8 @@
      <a href="#uptestset">4.7.1 <code>up_testset()</code></a><br>
      <a href="#upcpuindex">4.7.2 <code>up_cpu_index()</code></a><br>
      <a href="#upcpustart">4.7.3 <code>up_cpu_start()</code></a><br>
-      <a href="#upcpuinitialize">4.7.4 <code>up_cpu_initialize()</code></a><br>
-      <a href="#upcpupause">4.7.5 <code>up_cpu_pause()</code></a><br>
-      <a href="#upcpuresume">4.7.6 <code>up_cpu_resume()</code></a>
+      <a href="#upcpupause">4.7.4 <code>up_cpu_pause()</code></a><br>
+      <a href="#upcpuresume">4.7.5 <code>up_cpu_resume()</code></a>
    </ul>
    <a href="#exports">4.8 APIs Exported by NuttX to Architecture-Specific Logic</a>
    <ul>
@@ -3722,34 +3721,7 @@ int up_cpu_start(int cpu);
  </p>
 </ul>

-<h3><a name="upcpuinitialize">4.7.4 <code>up_cpu_initialize()</code></a></h3>
-<p><b>Function Prototype</b>:<p>
-<ul><pre>
-#include &lt;nuttx/arch.h&gt;
-#ifdef CONFIG_SMP
-int up_cpu_initialize(void);
-#endif
-</pre></ul>
-
-<p><b>Description</b>:</p>
-<ul>
-  <p>
-    After the CPU has been started (via <code>up_cpu_start()</code>) the system will call back into the architecture-specific code with this function on the thread of execution of the newly started CPU.
-    This gives the architecture-specific a chance to perform ny initial, CPU-specific initialize on that thread.
-  </p>
-</ul>
-<p><b>Input Parameters</b>:</p>
-<ul>
-  None
-</ul>
-<p><b>Returned Value</b>:</p>
-<ul>
-  <p>
-    Zero (<code>OK</code>) is returned on success; a negated <code>errno</code> value on failure.
-  </p>
-</ul>
-
-<h3><a name="upcpupause">4.7.5 <code>up_cpu_pause()</code></a></h3>
+<h3><a name="upcpupause">4.7.4 <code>up_cpu_pause()</code></a></h3>
 <p><b>Function Prototype</b>:<p>
 <ul><pre>
 #include &lt;nuttx/arch.h&gt;
@@ -3781,7 +3753,7 @@ int up_cpu_pause(int cpu);
  </p>
 </ul>

-<h3><a name="upcpuresume">4.7.6 <code>up_cpu_resume()</code></a></h3>
+<h3><a name="upcpuresume">4.7.5 <code>up_cpu_resume()</code></a></h3>
 <p><b>Function Prototype</b>:<p>
 <ul><pre>
 #include &lt;nuttx/arch.h&gt;
@@ -8,7 +8,7 @@
  <tr align="center" bgcolor="#e4e4e4">
    <td>
      <h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
-      <p>Last Updated:  April 12, 2016</p>
+      <p>Last Updated:  May 18, 2016</p>
    </td>
  </tr>
 </table>
@@ -157,6 +157,8 @@ nuttx/
 |   |- ntosd-dm320/
 |   |   |- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/ntosd-dm320/doc/README.txt" target="_blank">doc/README.txt</a>
 |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/ntosd-dm320/README.txt" target="_blank"><b><i>README.txt</i></b></a>
+ |   |- nucleo-144/
+ |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/nucleo-144/README.txt" target="_blank"><b><i>README.txt</i></b></a>
 |   |- nucleo-f4x1re/
 |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/nucleo-f4x1re/README.txt" target="_blank"><b><i>README.txt</i></b></a>
 |   |- nutiny-nuc120/
@@ -249,6 +251,8 @@ nuttx/
 |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm3240g-eval/README.txt" target="_blank"><b><i>README.txt</i></b></a>
 |   |- stm32_tiny/
 |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32_tiny/README.txt" target="_blank"><b><i>README.txt</i></b></a>
+ |   |- stm32f103-minumum/
+ |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32f103-minumum/README.txt" target="_blank"><b><i>README.txt</i></b></a>
 |   |- stm32f3discovery/
 |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32f3discovery/README.txt" target="_blank"><b><i>README.txt</i></b></a>
 |   |- stm32f4discovery/
@@ -1332,6 +1332,8 @@ nuttx/
 |   |- ntosd-dm320/
 |   |   |- doc/README.txt
 |   |   `- README.txt
+ |   |- nucleo-144/
+ |   |   `- README.txt
 |   |- nucleo-f4x1re/
 |   |   `- README.txt
 |   |- nutiny-nuc120/
@@ -1424,6 +1426,8 @@ nuttx/
 |   |   `- README.txt
 |   |- stm32_tiny/
 |   |   `- README.txt
+ |   |- stm32f103-minumum/
+ |   |   `- README.txt
 |   |- stm32f3discovery/
 |   |   `- README.txt
 |   |- stm32f4discovery/
@@ -1,7 +1,7 @@
 ############################################################################
 # arch/arm/src/Makefile
 #
-#   Copyright (C) 2007-2009, 2011-2012, 2014-2015 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2007-2009, 2011-2012, 2014-2016 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -127,6 +127,11 @@ BIN  = libarch$(LIBEXT)

 LDFLAGS += $(ARCHSCRIPT)

+# Override in Make.defs if linker is not 'ld'
+
+LDSTARTGROUP ?= --start-group
+LDENDGROUP ?= --end-group
+
 EXTRA_LIBS ?=
 EXTRA_LIBPATHS ?=
 LINKLIBS ?=
@@ -198,7 +203,7 @@ nuttx$(EXEEXT): $(HEAD_OBJ) board$(DELIM)libboard$(LIBEXT)
 	$(Q) echo "LD: nuttx"
 	$(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \
 		-o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \
-		--start-group $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) --end-group
+		$(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) $(LDENDGROUP)
 ifneq ($(CONFIG_WINDOWS_NATIVE),y)
 	$(Q) $(NM) $(NUTTX) | \
 	grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
@@ -289,7 +289,7 @@ static void a1x_copyvectorblock(void)
 ****************************************************************************/

 /****************************************************************************
- * Name: up_boot
+ * Name: arm_boot
 *
 * Description:
 *   Complete boot operations started in arm_head.S
@@ -305,7 +305,7 @@ static void a1x_copyvectorblock(void)
 *
 ****************************************************************************/

-void up_boot(void)
+void arm_boot(void)
 {
 #ifndef CONFIG_ARCH_ROMPGTABLE
  /* __start provided the basic MMU mappings for SRAM.  Now provide mappings
@@ -609,7 +609,7 @@ __start:

 	/* Perform early C-level, platform-specific initialization */

-	bl		up_boot
+	bl		arm_boot

 #ifdef CONFIG_STACK_COLORATION
 	/* Write a known value to the IDLE thread stack to support stack
@@ -88,7 +88,7 @@ void up_pginitialize(void)
 {
  /* None needed at present.  This file is just retained in case the need
   * arises in the future.  Nothing calls up_pginitialize() now.  If needed,
-   * if should be called early in up_boot.c to assure that all paging is
+   * if should be called early in arm_boot.c to assure that all paging is
   * ready.
   */
 }
@@ -0,0 +1,492 @@
+/****************************************************************************
+ * arch/arm/src/armv7-a/arm_cpuhead.S
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/board/board.h>
+
+#include "arm.h"
+#include "cp15.h"
+#include "sctlr.h"
+#include "mmu.h"
+#include "smp.h"
+
+#include "chip.h"
+#include "up_internal.h"
+
+	.file	"arm_cpuhead.S"
+
+/**********************************************************************************
+ * Configuration
+ **********************************************************************************/
+
+/* Hard-coded options */
+
+#undef CPU_ALIGNMENT_TRAP
+#undef CPU_CACHE_ROUND_ROBIN
+#undef CPU_DCACHE_DISABLE
+#undef CPU_ICACHE_DISABLE
+#undef CPU_AFE_ENABLE
+
+/* Check for the identity mapping:  For this configuration, this would be
+ * the case where the virtual beginning of RAM is the same as the physical
+ * beginning of RAM.
+ */
+
+#if !defined(CONFIG_RAM_START) || !defined(CONFIG_RAM_VSTART)
+#  error "CONFIG_RAM_START or CONFIG_RAM_VSTART is not defined"
+#endif
+
+#if CONFIG_RAM_START == CONFIG_RAM_VSTART
+#  define CONFIG_IDENTITY_TEXTMAP 1
+#endif
+
+/****************************************************************************
+ * .text
+ ****************************************************************************/
+
+	.text
+
+/****************************************************************************
+ * Name: __cpu[n]_start
+ *
+ * Description:
+ *   Boot functions for each CPU (other than CPU0).  These functions set up
+ *   the ARM operating mode, the initial stack, and configure co-processor
+ *   registers.  At the end of the boot, arm_cpu_boot() is called.
+ *
+ *   These functions are provided by the common ARMv7-A logic.
+ *
+ * Input parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Do not return.
+ *
+ ****************************************************************************/
+
+#if CONFIG_SMP_NCPUS > 1
+	.global	__cpu1_start
+	.type	__cpu1_start, #function
+
+__cpu1_start:
+	/* Set up the stack pointer and the CPU index */
+
+	ldr		sp, .Lcpu1_stackpointer
+	mov		r5, #1
+
+	/* Then branch to the common startup logic (PC-relative) */
+
+	b		.Lcpu_start
+
+.Lcpu1_stackpointer:
+	.long	.Lcpu1_stacktop
+	.size	__cpu1_start, .-__cpu1_start
+
+#if CONFIG_SMP_NCPUS > 2
+	.global	__cpu2_start
+	.type	__cpu2_start, #function
+
+__cpu2_start:
+	/* Set up the stack pointer and the CPU index */
+
+	ldr		sp, .Lcpu2_stackpointer
+	mov		r5, #2
+
+	/* Then branch to the common startup logic (PC-relative) */
+
+	b		.Lcpu_start
+
+.Lcpu2_stackpointer:
+	.long	.Lcpu2_stacktop
+	.size	__cpu2_start, .-__cpu2_start
+
+#if CONFIG_SMP_NCPUS > 3
+	.global	__cpu3_start
+	.type	__cpu3_start, #function
+
+__cpu3_start:
+	/* Set up the stack pointer and the CPU index */
+
+	ldr		sp, .Lcpu3_stackpointer
+	mov		r5, #3
+
+	/* Then branch to the common startup logic (PC-relative) */
+
+	b		.Lcpu_start
+
+.Lcpu3_stackpointer:
+	.long	.Lcpu3_stacktop
+	.size	__cpu3_start, .-__cpu3_start
+
+#if CONFIG_SMP_NCPUS > 4
+#  error This logic needs to extended for CONFIG_SMP_NCPUS > 4
+
+#endif /* CONFIG_SMP_NCPUS > 4 */
+#endif /* CONFIG_SMP_NCPUS > 3 */
+#endif /* CONFIG_SMP_NCPUS > 2 */
+#endif /* CONFIG_SMP_NCPUS > 1 */
+
+/****************************************************************************
+ * Name: .Lcpu_start
+ *
+ * Description:
+ *   Common CPUn startup logic (n > 0)
+ *
+ * On input:
+ *   SP = Set to top of CPU IDLE stack (virtual)
+ *   R5 = CPU number
+ *
+ ****************************************************************************/
+
+	.type	.Lcpu_start, #function
+
+.Lcpu_start:
+	/* Make sure that we are in SVC mode with IRQs and FIQs disabled */
+
+	mov		r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+	msr		cpsr_c, r0
+
+	/* The MMU and caches should be disabled */
+
+	mrc		CP15_SCTLR(r0)
+	bic		r0, r0, #(SCTLR_M | SCTLR_C)
+	bic		r0, r0, #(SCTLR_I)
+	mcr		CP15_SCTLR(r0)
+
+	/* Invalidate caches and TLBs.
+	 *
+	 *   NOTE: "The ARMv7 Virtual Memory System Architecture (VMSA) does not
+	 *   support a CP15 operation to invalidate the entire data cache. ...
+	 *   In normal usage the only time the entire data cache has to be
+	 *   invalidated is on reset."
+	 *
+	 * The instruction cache is virtually indexed and physically tagged but
+	 * the data cache is physically indexed and physically tagged.  So it
+	 * should not be an issue if the system comes up with a dirty Dcache;
+	 * the ICache, however, must be invalidated.
+	 */
+
+	mov		r0, #0
+	mcr		CP15_TLBIALL(r0,c7)	/* Invalidate the entire unified TLB */
+	mcr		CP15_TLBIALL(r0,c6)
+	mcr		CP15_TLBIALL(r0,c5)
+	mcr		CP15_BPIALL(r0)		/* Invalidate entire branch prediction array */
+	mcr		CP15_ICIALLU(r0)	/* Invalidate I-cache */
+
+	/* Load the page table address.
+	 *
+	 * NOTES:
+	 * - Here we assume that the page table address is aligned to at least
+	 *   least a 16KB boundary (bits 0-13 are zero).  No masking is provided
+	 *   to protect against an unaligned page table address.
+	 * - The ARMv7-A has two page table address registers, TTBR0 and 1.
+	 *   Only TTBR0 is used in this implementation but both are initialized.
+	 */
+
+	ldr		r1, .LCppgtable		/* r1=phys. page table */
+	orr		r1, r1, #(TTBR0_RGN_WBWA | TTBR0_IRGN0)	/* Select cache properties */
+	mcr		CP15_TTBR0(r1)
+	mcr		CP15_TTBR1(r1)
+
+	/* Set the TTB control register (TTBCR) to indicate that we are using
+	 * TTBR0.  r0 still holds the value of zero.
+	 *
+	 *   N   : 0=Selects TTBR0 and 16KB page table size indexed by VA[31:20]
+	 *   PD0 : 0=Perform translation table walks using TTBR0
+	 *   PD1 : 0=Perform translation table walks using TTBR1 (but it is disabled)
+	 *   EAE : 0=Use 32-bit translation system
+	 */
+
+	mcr		CP15_TTBCR(r0)
+
+	/* Enable the MMU and caches
+	 * lr = Resume at .Lcpu_vstart with the MMU enabled
+	 */
+
+	ldr		lr, .LCcpu_vstart		/* Abs. virtual address */
+
+	/* Configure the domain access register (see mmu.h).  Only domain 0 is
+	 * supported and it uses the permissions in the TLB.
+	 */
+
+	mov		r0, #DACR_CLIENT(0)
+	mcr		CP15_DACR(r0)			/* Set domain access register */
+
+	/* Configure the system control register (see sctrl.h) */
+
+	mrc		CP15_SCTLR(r0)			/* Get control register */
+
+	/* Clear bits to reset values.  This is only necessary in situations like, for
+	 * example, we get here via a bootloader and the control register is in some
+	 * unknown state.
+	 *
+	 *   SCTLR_M    Bit 0:  Enable the MMU
+	 *   SCTLR_A    Bit 1:  Strict alignment disabled (reset value)
+	 *   SCTLR_C    Bit 2:  DCache disabled (reset value)
+	 *
+	 *   SCTLR_SW   Bit 10: SWP/SWPB not enabled (reset value)
+	 *   SCTLR_I    Bit 12: ICache disabled (reset value)
+	 *   SCTLR_V    Bit 13: Assume low vectors (reset value)
+	 *   SCTLR_RR   Bit 14: The Cortex-A5 processor only supports a fixed random
+	 *                      replacement strategy.
+	 *   SCTLR_HA   Bit 17: Not supported by A5
+	 *
+	 *   SCTLR_EE   Bit 25: 0=Little endian (reset value).
+	 *   SCTLR_TRE  Bit 28: No memory region remapping (reset value)
+	 *   SCTLR_AFE  Bit 29: Full, legacy access permissions behavior (reset value).
+	 *   SCTLR_TE   Bit 30: All exceptions handled in ARM state (reset value).
+	 */
+
+	bic		r0, r0, #(SCTLR_A  | SCTLR_C)
+	bic		r0, r0, #(SCTLR_SW | SCTLR_I   | SCTLR_V   | SCTLR_RR | SCTLR_HA)
+	bic		r0, r0, #(SCTLR_EE | SCTLR_TRE | SCTLR_AFE | SCTLR_TE)
+
+	/* Set bits to enable the MMU
+	 *
+	 *   SCTLR_M     Bit 0:  Enable the MMU
+	 *   SCTLR_Z     Bit 11: Program flow prediction control always enabled on A5
+	 */
+
+	orr		r0, r0, #(SCTLR_M)
+#ifndef CONFIG_ARCH_CORTEXA5
+	orr		r0, r0, #(SCTLR_Z)
+#endif
+
+#ifndef CONFIG_ARCH_LOWVECTORS
+	/* Position vectors to 0xffff0000 if so configured.
+	 *
+	 *   SCTLR_V    Bit 13: High vectors
+	 */
+
+	orr		r0, r0, #(SCTLR_V)
+#endif
+
+#if defined(CPU_CACHE_ROUND_ROBIN) && !defined(CONFIG_ARCH_CORTEXA5)
+	/* Round Robin cache replacement
+	 *
+	 *   SCTLR_RR   Bit 14: The Cortex-A5 processor only supports a fixed random
+	 *                      replacement strategy.
+	 */
+
+	orr		r0, r0, #(SCTLR_RR)
+#endif
+
+#ifndef CPU_DCACHE_DISABLE
+	/* Dcache enable
+	 *
+	 *   SCTLR_C    Bit 2:  DCache enable
+	 */
+
+	orr		r0, r0, #(SCTLR_C)
+#endif
+
+#ifndef CPU_ICACHE_DISABLE
+	/* Icache enable
+	 *
+	 *   SCTLR_I    Bit 12: ICache enable
+	 */
+
+	orr		r0, r0, #(SCTLR_I)
+#endif
+
+#ifdef CPU_ALIGNMENT_TRAP
+	/* Alignment abort enable
+	 *
+	 *   SCTLR_A    Bit 1:  Strict alignment enabled
+	 */
+
+	orr		r0, r0, #(SCTLR_A)
+#endif
+
+#ifdef CONFIG_ENDIAN_BIG
+	/* Big endian mode
+	 *
+	 *   SCTLR_EE       Bit 25: 1=Big endian.
+	 */
+
+	orr		r0, r0, #(SCTLR_EE)
+#endif
+
+#ifdef CPU_AFE_ENABLE
+	/* AP[0:2] Permissions model
+	 *
+	 *   SCTLR_AFE  Bit 29: Full, legacy access permissions behavior (reset value).
+	 *
+	 * When AFE=1, the page table AP[0] is used as an access flag and AP[2:1]
+	 * control.  When AFE=0, AP[2:0] control access permissions.
+	 */
+
+	orr		r0, r0, #(SCTLR_AFE)
+#endif
+
+	/* Then write the configured control register */
+
+	mcr		CP15_SCTLR(r0)			/* Write control reg */
+	.rept	12						/* Cortex A8 wants lots of NOPs here */
+	nop
+	.endr
+
+	/* And "jump" to .Lcpu_vstart in the newly mapped virtual address space */
+
+	mov		pc, lr
+
+/****************************************************************************
+ * PC_Relative Data
+ ****************************************************************************/
+
+	/* The physical base address of the page table */
+
+	.type	.LCppgtable, %object
+.LCppgtable:
+	.long	PGTABLE_BASE_PADDR		/* Physical start of page table */
+	.size	.LCppgtable, . -.LCppgtable
+
+	/* The virtual start address of the second phase boot logic */
+
+	.type	.LCcpu_vstart, %object
+.LCcpu_vstart:
+	.long	.Lcpu_vstart
+	.size	.LCcpu_vstart, . -.LCcpu_vstart
+
+	.size	.Lcpu_start, .-.Lcpu_start
+
+/****************************************************************************
+ * Name: .Lcpu_vstart
+ *
+ * Description:
+ *   Continue initialization after the MMU has been enabled.
+ *
+ *   The following is executed after the MMU has been enabled. This uses
+ *   absolute addresses; this is not position independent.
+ *
+ * On input:
+ *   SP = Set to top of CPU IDLE stack (virtual)
+ *   R5 = CPU number
+ *
+ ****************************************************************************/
+
+	.align	8
+	.globl	arm_cpu_boot
+	.type	.Lcpu_vstart, %function
+
+.Lcpu_vstart:
+
+#ifdef CONFIG_STACK_COLORATION
+	/* Write a known value to the IDLE thread stack to support stack
+	 * monitoring logic
+	 */
+
+	adr		r3, .Lstkinit
+	ldmia	r3, {r0, r1, r2}	/* R0 = start of IDLE stack; R1 = Size of stack; R2 = coloration */
+
+1:								/* Top of the loop */
+	sub		r1, r1, #1			/* R1 = Number of words remaining */
+	cmp		r1, #0				/* Check (nwords == 0) */
+	str		r2, [r0], #4		/* Save stack color word, increment stack address */
+	bne		1b					/* Bottom of the loop */
+#endif
+
+	/* Branch to continue C level CPU initialization */
+
+	mov		fp, #0				/* Clear framepointer */
+	mov		lr, #0				/* LR = return address (none) */
+	mov		r0, r5				/* Input parameter = CPU index */
+	b		arm_cpu_boot		/* Branch to C level CPU initialization */
+	.size	.Lcpu_vstart, .-.Lcpu_vstart
+
+/***************************************************************************
+ * Text-section constants
+ ***************************************************************************/
+
+	/* Text-section constants: */
+
+#ifdef CONFIG_STACK_COLORATION
+	.type	.Lstkinit, %object
+.Lstkinit:
+	.long	SMP_STACK_WORDS
+	.long	STACK_COLOR				/* Stack coloration word */
+	.size	.Lstkinit, . -.Lstkinit
+#endif
+
+/***************************************************************************
+ * .noinit section data
+ ***************************************************************************/
+
+	.section	.noinit, "aw"
+
+#if CONFIG_SMP_NCPUS > 1
+	.align	8
+	.globl	g_cpu1_idlestack
+	.type	g_cpu1_idlestack, object
+
+g_cpu1_idlestack:
+	.space	SMP_STACK_SIZE
+.Lcpu1_stacktop:
+	.size	g_cpu1_idlestack, .Lcpu1_stacktop-g_cpu1_idlestack
+
+#if CONFIG_SMP_NCPUS > 2
+	.align	8
+	.globl	g_cpu2_idlestack
+	.type	g_cpu2_idlestack, object
+
+g_cpu2_idlestack:
+	.space	SMP_STACK_SIZE
+.Lcpu2_stacktop:
+	.size	g_cpu2_idlestack, .Lcpu2_stacktop-g_cpu2_idlestack
+
+#if CONFIG_SMP_NCPUS > 3
+	.align	8
+	.globl	g_cpu3_idlestack
+	.type	g_cpu3_idlestack, object
+
+g_cpu3_idlestack:
+	.space	SMP_STACK_SIZE
+.Lcpu3_stacktop:
+	.size	g_cpu3_idlestack, .Lcpu3_stacktop-g_cpu3_idlestack
+
+#if CONFIG_SMP_NCPUS > 4
+#  error This logic needs to extended for CONFIG_SMP_NCPUS > 4
+
+#endif /* CONFIG_SMP_NCPUS > 4 */
+#endif /* CONFIG_SMP_NCPUS > 3 */
+#endif /* CONFIG_SMP_NCPUS > 2 */
+#endif /* CONFIG_SMP_NCPUS > 1 */
+
+	.end
@@ -0,0 +1,149 @@
+/****************************************************************************
+ * arch/arm/src/armv7-a/arm_cpuidlestack.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/sched.h>
+
+#include "smp.h"
+#include "up_internal.h"
+
+#ifdef CONFIG_SMP
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Stack alignment macros */
+
+#define STACK_ISALIGNED(a) ((uintptr_t)(a) & ~SMP_STACK_MASK)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#if CONFIG_SMP_NCPUS > 1
+static FAR const uint32_t *g_cpu_stackalloc[CONFIG_SMP_NCPUS] =
+{
+    0
+  , g_cpu1_idlestack
+#if CONFIG_SMP_NCPUS > 2
+  , g_cpu2_idlestack
+#if CONFIG_SMP_NCPUS > 3
+  , g_cpu3_idlestack
+#endif /* CONFIG_SMP_NCPUS > 3 */
+#endif /* CONFIG_SMP_NCPUS > 2 */
+};
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_cpu_idlestack
+ *
+ * Description:
+ *   Allocate a stack for the CPU[n] IDLE task (n > 0) if appropriate and
+ *   setup up stack-related information in the IDLE task's TCB.  This
+ *   function is always called before up_cpu_start().  This function is
+ *   only called for the CPU's initial IDLE task; up_create_task is used for
+ *   all normal tasks, pthreads, and kernel threads for all CPUs.
+ *
+ *   The initial IDLE task is a special case because the CPUs can be started
+ *   in different wans in different environments:
+ *
+ *   1. The CPU may already have been started and waiting in a low power
+ *      state for up_cpu_start().  In this case, the IDLE thread's stack
+ *      has already been allocated and is already in use.  Here
+ *      up_cpu_idlestack() only has to provide information about the
+ *      already allocated stack.
+ *
+ *   2. The CPU may be disabled but started when up_cpu_start() is called.
+ *      In this case, a new stack will need to be created for the IDLE
+ *      thread and this function is then equivalent to:
+ *
+ *      return up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL);
+ *
+ *   The following TCB fields must be initialized by this function:
+ *
+ *   - adj_stack_size: Stack size after adjustment for hardware, processor,
+ *     etc.  This value is retained only for debug purposes.
+ *   - stack_alloc_ptr: Pointer to allocated stack
+ *   - adj_stack_ptr: Adjusted stack_alloc_ptr for HW.  The initial value of
+ *     the stack pointer.
+ *
+ * Inputs:
+ *   - cpu:         CPU index that indicates which CPU the IDLE task is
+ *                  being created for.
+ *   - tcb:         The TCB of new CPU IDLE task
+ *   - stack_size:  The requested stack size for the IDLE task.  At least
+ *                  this much must be allocated.  This should be
+ *                  CONFIG_SMP_STACK_SIZE.
+ *
+ ****************************************************************************/
+
+int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size)
+{
+#if CONFIG_SMP_NCPUS > 1
+  uintptr_t stack_alloc;
+  uintptr_t top_of_stack;
+
+  DEBUGASSERT(cpu > 0 && cpu < CONFIG_SMP_NCPUS && tcb != NULL &&
+              stack_size <= SMP_STACK_SIZE);
+
+  /* Get the top of the stack */
+
+
+  stack_alloc          = (uintptr_t)g_cpu_stackalloc[cpu];
+  DEBUGASSERT(stack_alloc != 0 && STACK_ISALIGNED(stack_alloc));
+  top_of_stack         = stack_alloc + SMP_STACK_TOP;
+
+  tcb->adj_stack_size  = SMP_STACK_SIZE;
+  tcb->stack_alloc_ptr = (FAR uint32_t *)stack_alloc;
+  tcb->adj_stack_ptr   = (FAR uint32_t *)top_of_stack;
+#endif
+
+  return OK;
+}
+
+#endif /* CONFIG_SMP */
@@ -211,7 +211,16 @@ void arm_gic_initialize(void)

 #endif

-#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_TRUSTZONE_BOTH)
+#if defined(CONFIG_ARCH_TRUSTZONE_SECURE)
+  /* Set FIQn=1 if secure interrupts are to signal using nfiq_c.
+   *
+   * NOTE:  Only for processors that operate in secure state.
+   * REVISIT: Do I need to do this?
+   */
+
+  //iccicr |= GIC_ICCICRS_FIQEN;
+
+#elif defined(CONFIG_ARCH_TRUSTZONE_BOTH)
  /* Set FIQn=1 if secure interrupts are to signal using nfiq_c.
   *
   * NOTE:  Only for processors that operate in secure state.
@@ -221,25 +230,35 @@ void arm_gic_initialize(void)
  iccicr |= GIC_ICCICRS_FIQEN;
 #endif

-#if defined(ONFIG_ARCH_TRUSTZONE_BOTH)
+#if defined(CONFIG_ARCH_TRUSTZONE_SECURE)
  /* Program the AckCtl bit to select the required interrupt acknowledge
   * behavior.
   *
   * NOTE: Only for processors that operate in both secure and non-secure
   * state.
-   * REVISIT: I don't yet fully understand this setting.
+   * REVISIT: This is here only for superstituous reasons.  I don't think
+   * I need this setting in this configuration.
   */

-  // iccicr |= GIC_ICCICRS_ACKTCTL;
+   iccicr |= GIC_ICCICRS_ACKTCTL;
+
+#elif defined(CONFIG_ARCH_TRUSTZONE_BOTH)
+  /* Program the AckCtl bit to select the required interrupt acknowledge
+   * behavior.
+   *
+   * NOTE: Only for processors that operate in both secure and non-secure
+   * state.
+   */
+
+   iccicr |= GIC_ICCICRS_ACKTCTL;

  /* Program the SBPR bit to select the required binary pointer behavior.
   *
   * NOTE: Only for processors that operate in both secure and non-secure
   * state.
-   * REVISIT: I don't yet fully understand this setting.
   */

-  // iccicr |= GIC_ICCICRS_CBPR;
+   iccicr |= GIC_ICCICRS_CBPR;
 #endif

 #if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_TRUSTZONE_BOTH)
@@ -291,9 +310,15 @@ void arm_gic_initialize(void)
   * bypass.
   */

+#if 0 /* REVISIT -- I don't know why this needs to be like this */
  iccicr |= (GIC_ICCICRS_ENABLEGRP0 | GIC_ICCICRS_FIQBYPDISGRP0 |
             GIC_ICCICRS_IRQBYPDISGRP0 | GIC_ICCICRS_FIQBYPDISGRP1 |
             GIC_ICCICRS_IRQBYPDISGRP1);
+#else
+  iccicr |= (GIC_ICCICRS_ENABLEGRP0 | GIC_ICCICRS_ENABLEGRP1 |
+             GIC_ICCICRS_FIQBYPDISGRP0 | GIC_ICCICRS_IRQBYPDISGRP0 |
+             GIC_ICCICRS_FIQBYPDISGRP1 | GIC_ICCICRS_IRQBYPDISGRP1);
+#endif
  icddcr  = GIC_ICDDCR_ENABLEGRP0;

 #elif defined(CONFIG_ARCH_TRUSTZONE_BOTH)
@@ -498,4 +523,56 @@ int up_prioritize_irq(int irq, int priority)
  return -EINVAL;
 }

+/****************************************************************************
+ * Name: arm_gic_irq_trigger
+ *
+ * Description:
+ *   Set the trigger type for the specificd IRQ source and the current CPU.
+ *
+ *   Since this API is not supported on all architectures, it should be
+ *   avoided in common implementations where possible.
+ *
+ * Input Paramters:
+ *   irq - The interrupt request to modify.
+ *   edge - False: Active HIGH level sensitive, True: Rising edge sensitive
+ *
+ * Returned Value:
+ *   Zero (OK) on success; a negated errno value is returned on any failure.
+ *
+ ****************************************************************************/
+
+int arm_gic_irq_trigger(int irq, bool edge)
+{
+  uintptr_t regaddr;
+  uint32_t regval;
+  uint32_t intcfg;
+
+  if (irq > GIC_IRQ_SGI15 && irq < NR_IRQS)
+    {
+      /* Get the address of the Interrupt Configuration Register for this
+       * irq.
+       */
+
+      regaddr = GIC_ICDICFR(irq);
+
+      /* Get the new Interrupt configuration bit setting */
+
+      intcfg = (edge ? (INT_ICDICFR_EDGE | INT_ICDICFR_1N) : INT_ICDICFR_1N);
+
+      /* Write the correct interrupt trigger to the Interrupt Configuration
+       * Register.
+       */
+
+      regval  = getreg32(regaddr);
+      regval &= ~GIC_ICDICFR_ID_MASK(irq);
+      regval |= GIC_ICDICFR_ID(irq, intcfg);
+      putreg32(regval, regaddr);
+
+      return OK;
+    }
+
+  return -EINVAL;
+}
+
+
 #endif /* CONFIG_ARMV7A_HAVE_GICv2 */
@@ -630,18 +630,18 @@ __start:
 #ifndef CONFIG_BOOT_SDRAM_DATA
 	/* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is
 	 * ready to use.  Other memory, such as SDRAM, must be initialized before
-	 * it can be used.  up_boot() will perform that memory initialization and
-	 * .bss and .data can be initialized after up_boot() returns.
+	 * it can be used.  arm_boot() will perform that memory initialization and
+	 * .bss and .data can be initialized after arm_boot() returns.
 	 */

 	bl		arm_data_initialize
 #endif

 	/* Perform early C-level, platform-specific initialization.  Logic
-	 * within up_boot() must configure SDRAM and call arm_ram_initailize.
+	 * within arm_boot() must configure SDRAM and call arm_ram_initailize.
 	 */

-	bl		up_boot
+	bl		arm_boot

 #ifdef CONFIG_STACK_COLORATION
 	/* Write a known value to the IDLE thread stack to support stack
@@ -650,8 +650,8 @@ __start:

 	/* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is
 	 * ready to use.  Other memory, such as SDRAM, must be initialized before
-	 * it can be used.  up_boot() will perform that memory initialization and
-	 * .bss and .data can be initialized after up_boot() returns.
+	 * it can be used.  arm_boot() will perform that memory initialization and
+	 * .bss and .data can be initialized after arm_boot() returns.
 	 */

 	/* Set up the stack pointer and clear the frame pointer */
@@ -662,18 +662,18 @@ __start:
 #ifndef CONFIG_BOOT_SDRAM_DATA
 	/* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is
 	 * ready to use.  Other memory, such as SDRAM, must be initialized before
-	 * it can be used.  up_boot() will perform that memory initialization and
-	 * .bss and .data can be initialized after up_boot() returns.
+	 * it can be used.  arm_boot() will perform that memory initialization and
+	 * .bss and .data can be initialized after arm_boot() returns.
 	 */

 	bl		arm_data_initialize
 #endif

 	/* Perform early C-level, platform-specific initialization.  Logic
-	 * within up_boot() must configure SDRAM and call arm_ram_initailize.
+	 * within arm_boot() must configure SDRAM and call arm_ram_initailize.
 	 */

-	bl		up_boot
+	bl		arm_boot

 #ifdef CONFIG_STACK_COLORATION
 	/* Write a known value to the IDLE thread stack to support stack
@@ -88,7 +88,7 @@ void up_pginitialize(void)
 {
  /* None needed at present.  This file is just retained in case the need
   * arises in the future.  Nothing calls up_pginitialize() now.  If needed,
-   * if should be called early in up_boot.c to assure that all paging is
+   * if should be called early in arm_boot.c to assure that all paging is
   * ready.
   */
 }
@@ -495,7 +495,7 @@
 #define INT_ICDICFR_EDGE           2         /* Bit n+2: 1=Edge sensitive */

 #define GIC_ICDICFR_ID_SHIFT(n)    GIC_SHIFT16(n)
-#define GIC_ICDICFR_ID_MASK(n)     GIC_MASK16(n
+#define GIC_ICDICFR_ID_MASK(n)     GIC_MASK16(n)
 #  define GIC_ICDICFR_ID(n,c)      ((uint32_t)(c) << GIC_SHIFT16(n))

 /* PPI Status Register */
@@ -720,6 +720,26 @@ void arm_gic0_initialize(void);

 void arm_gic_initialize(void);

+/****************************************************************************
+ * Name: arm_gic_irq_trigger
+ *
+ * Description:
+ *   Set the trigger type for the specificd IRQ source and the current CPU.
+ *
+ *   Since this API is not supported on all architectures, it should be
+ *   avoided in common implementations where possible.
+ *
+ * Input Paramters:
+ *   irq - The interrupt request to modify.
+ *   edge - False: Active HIGH level sensitive, True: Rising edge sensitive
+ *
+ * Returned Value:
+ *   Zero (OK) on success; a negated errno value is returned on any failure.
+ *
+ ****************************************************************************/
+
+int arm_gic_irq_trigger(int irq, bool edge);
+
 /****************************************************************************
 * Name: arm_decodeirq
 *
@@ -0,0 +1,145 @@
+/****************************************************************************
+ * arch/arm/src/armv7-a/smp.h
+ * Common ARM support for SMP on multi-core CPUs.
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_ARMV7_A_SMP_H
+#define __ARCH_ARM_SRC_ARMV7_A_SMP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifdef CONFIG_SMP
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* ARM requires at least a 4-byte stack alignment.  For use with EABI and
+ * floating point, the stack must be aligned to 8-byte addresses.  We will
+ * always use the EABI stack alignment
+ */
+
+#define SMP_STACK_ALIGNMENT  8
+#define SMP_STACK_MASK       7
+#define SMP_STACK_SIZE       ((CONFIG_SMP_IDLETHREAD_STACKSIZE + 7) & ~7)
+#define SMP_STACK_WORDS      (SMP_STACK_SIZE >> 2)
+#define SMP_STACK_TOP        (SMP_STACK_SIZE - 8)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#if CONFIG_SMP_NCPUS > 1
+extern uint32_t g_cpu1_idlestack[SMP_STACK_WORDS];
+#if CONFIG_SMP_NCPUS > 2
+extern uint32_t g_cpu2_idlestack[SMP_STACK_WORDS];
+#if CONFIG_SMP_NCPUS > 3
+extern uint32_t g_cpu3_idlestack[SMP_STACK_WORDS];
+#if CONFIG_SMP_NCPUS > 4
+#  error This logic needs to extended for CONFIG_SMP_NCPUS > 4
+#endif /* CONFIG_SMP_NCPUS > 4 */
+#endif /* CONFIG_SMP_NCPUS > 3 */
+#endif /* CONFIG_SMP_NCPUS > 2 */
+#endif /* CONFIG_SMP_NCPUS > 1 */
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: __cpu[n]_start
+ *
+ * Description:
+ *   Boot functions for each CPU (other than CPU0).  These functions set up
+ *   the ARM operating mode, the initial stack, and configure co-processor
+ *   registers.  At the end of the boot, arm_cpu_boot() is called.
+ *
+ *   These functions are provided by the common ARMv7-A logic.
+ *
+ * Input parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Do not return.
+ *
+ ****************************************************************************/
+
+#if CONFIG_SMP_NCPUS > 1
+void __cpu1_start(void);
+#endif
+
+#if CONFIG_SMP_NCPUS > 2
+void __cpu2_start(void);
+#endif
+
+#if CONFIG_SMP_NCPUS > 3
+void __cpu3_start(void);
+#endif
+
+#if CONFIG_SMP_NCPUS > 4
+#  error This logic needs to extended for CONFIG_SMP_NCPUS > 4
+#endif
+
+/****************************************************************************
+ * Name: arm_cpu_boot
+ *
+ * Description:
+ *   Continues the C-level initialization started by the assembly language
+ *   __cpu[n]_start function.  At a minimum, this function needs to initialize
+ *   interrupt handling and, perhaps, wait on WFI for arm_cpu_start() to
+ *   issue an SGI.
+ *
+ *   This function must be provided by the each ARMv7-A MCU and implement
+ *   MCU-specific initialization logic.
+ *
+ * Input parameters:
+ *   cpu - The CPU index.  This is the same value that would be obtained by
+ *      calling up_cpu_index();
+ *
+ * Returned Value:
+ *   Does not return.
+ *
+ ****************************************************************************/
+
+void arm_cpu_boot(int cpu);
+
+#endif  /* __ASSEMBLY__ */
+#endif  /* CONFIG_SMP */
+#endif  /* __ARCH_ARM_SRC_ARMV7_A_SMP_H */
@@ -331,7 +331,7 @@ EXTERN uint32_t _eramfuncs;       /* Copy destination end address in RAM */

 /* Low level initialization provided by board-level logic ******************/

-void up_boot(void);
+void arm_boot(void);

 /* Context switching */

@@ -202,7 +202,7 @@ static void up_copyvectorblock(void)
 * Public Functions
 ************************************************************************************/

-void up_boot(void)
+void arm_boot(void)
 {
  /* __start provided the basic MMU mappings for SDRAM.  Now provide mappings for all
   * IO regions (Including the vector region).
@@ -195,7 +195,7 @@ static void up_copyvectorblock(void)
 * Public Functions
 ************************************************************************************/

-void up_boot(void)
+void arm_boot(void)
 {
  /* __start provided the basic MMU mappings for SDRAM.  Now provide mappings for all
   * IO regions (Including the vector region).
@@ -49,6 +49,9 @@ ifeq ($(CONFIG_PAGING),y)
 CMN_ASRCS  = arm_pghead.S
 else
 CMN_ASRCS  = arm_head.S
+ifeq ($(CONFIG_SMP),y)
+CMN_ASRCS += arm_cpuhead.S
+endif
 endif

 # Common assembly language files
@@ -77,7 +80,7 @@ CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c
 CMN_CSRCS += arm_unblocktask.c arm_undefinedinsn.c

 ifeq ($(CONFIG_SMP),y)
-CMN_CSRCS += arm_cpuindex.c arm_cpustart.c arm_cpupause.c
+CMN_CSRCS += arm_cpuindex.c arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c
 endif

 ifeq ($(CONFIG_DEBUG_IRQ),y)
@@ -145,5 +148,5 @@ CHIP_CSRCS += imx_timerisr.c imx_gpio.c imx_iomuxc.c
 CHIP_CSRCS += imx_serial.c imx_lowputc.c

 ifeq ($(CONFIG_SMP),y)
-CHIP_CSRCS += imx_cpuinit.c
+CHIP_CSRCS += imx_cpuboot.c
 endif
@@ -0,0 +1,212 @@
+/****************************************************************************************************
+ * arch/arm/src/imx6/imx_src.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Reference:
+ *   "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number
+ *   IMX6DQRM, Rev. 3, 07/2015, FreeScale.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMX6_CHIP_IMX_SRC_H
+#define __ARCH_ARM_SRC_IMX6_CHIP_IMX_SRC_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include <chip/imx_memorymap.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* SRC Register Offsets *****************************************************************************/
+
+#define IMX_SRC_SCR_OFFSET         0x0000 /* SRC Control Register */
+#define IMX_SRC_SBMR1_OFFSET       0x0004 /* SRC Boot Mode Register 1 */
+#define IMX_SRC_SRSR_OFFSET        0x0008 /* SRC Reset Status Register */
+#define IMX_SRC_SISR_OFFSET        0x0014 /* SRC Interrupt Status Register */
+#define IMX_SRC_SIMR_OFFSET        0x0018 /* SRC Interrupt Mask Register */
+#define IMX_SRC_SBMR2_OFFSET       0x001c /* SRC Boot Mode Register 2 */
+#define IMX_SRC_GPR1_OFFSET        0x0020 /* SRC General Purpose Register 1 */
+#define IMX_SRC_GPR2_OFFSET        0x0024 /* SRC General Purpose Register 2 */
+#define IMX_SRC_GPR3_OFFSET        0x0028 /* SRC General Purpose Register 3 */
+#define IMX_SRC_GPR4_OFFSET        0x002c /* SRC General Purpose Register 4 */
+#define IMX_SRC_GPR5_OFFSET        0x0030 /* SRC General Purpose Register 5 */
+#define IMX_SRC_GPR6_OFFSET        0x0034 /* SRC General Purpose Register 6 */
+#define IMX_SRC_GPR7_OFFSET        0x0038 /* SRC General Purpose Register 7 */
+#define IMX_SRC_GPR8_OFFSET        0x003c /* SRC General Purpose Register 8 */
+#define IMX_SRC_GPR9_OFFSET        0x0040 /* SRC General Purpose Register 9 */
+#define IMX_SRC_GPR10_OFFSET       0x0044 /* SRC General Purpose Register 10 */
+
+/* SRC Register Addresses ***************************************************************************/
+
+#define IMX_SRC_SCR                (IMX_SRC_VBASE+IMX_SRC_SCR_OFFSET)
+#define IMX_SRC_SBMR1              (IMX_SRC_VBASE+IMX_SRC_SBMR1_OFFSET)
+#define IMX_SRC_SRSR               (IMX_SRC_VBASE+IMX_SRC_SRSR_OFFSET)
+#define IMX_SRC_SISR               (IMX_SRC_VBASE+IMX_SRC_SISR_OFFSET)
+#define IMX_SRC_SIMR               (IMX_SRC_VBASE+IMX_SRC_SIMR_OFFSET)
+#define IMX_SRC_SBMR2              (IMX_SRC_VBASE+IMX_SRC_SBMR2_OFFSET)
+#define IMX_SRC_GPR1               (IMX_SRC_VBASE+IMX_SRC_GPR1_OFFSET)
+#define IMX_SRC_GPR2               (IMX_SRC_VBASE+IMX_SRC_GPR2_OFFSET)
+#define IMX_SRC_GPR3               (IMX_SRC_VBASE+IMX_SRC_GPR3_OFFSET)
+#define IMX_SRC_GPR4               (IMX_SRC_VBASE+IMX_SRC_GPR4_OFFSET)
+#define IMX_SRC_GPR5               (IMX_SRC_VBASE+IMX_SRC_GPR5_OFFSET)
+#define IMX_SRC_GPR6               (IMX_SRC_VBASE+IMX_SRC_GPR6_OFFSET)
+#define IMX_SRC_GPR7               (IMX_SRC_VBASE+IMX_SRC_GPR7_OFFSET)
+#define IMX_SRC_GPR8               (IMX_SRC_VBASE+IMX_SRC_GPR8_OFFSET)
+#define IMX_SRC_GPR9               (IMX_SRC_VBASE+IMX_SRC_GPR9_OFFSET)
+#define IMX_SRC_GPR10              (IMX_SRC_VBASE+IMX_SRC_GPR10_OFFSET)
+
+/* SRC Register Bit Definitions *********************************************************************/
+
+/* SRC Control Register: Reset value 0x00000521 */
+
+#define SRC_SCR_WARM_RESET_ENABLE  (1 << 0)  /* Bit 0:  WARM reset enable bit */
+#define SRC_SCR_SW_GPU_RST         (1 << 1)  /* Bit 1:  Software reset for GPU */
+#define SRC_SCR_SW_VPU_RST         (1 << 2)  /* Bit 2:  Software reset for VPU */
+#define SRC_SCR_SW_IPU1_RST        (1 << 3)  /* Bit 3:  Software reset for IPU1 */
+#define SRC_SCR_SW_OPEN_VG_RST     (1 << 4)  /* Bit 4:  Software reset for open_vg */
+#define SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT  (5) /* Bits 5-6: XTALI cycles before bypassing the MMDC ack */
+#define SRC_SCR_WARM_RST_BYPASS_COUNT_MASK   (3 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT)
+#  define SRC_SCR_WARM_RST_BYPASS_COUNT_NONE (0 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT) /* Counter not used */
+#  define SRC_SCR_WARM_RST_BYPASS_COUNT_16   (1 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT) /* 16 XTALI cycles before WARM to COLD reset */
+#  define SRC_SCR_WARM_RST_BYPASS_COUNT_32   (2 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT) /* 32 XTALI cycles before WARM to COLD reset */
+#  define SRC_SCR_WARM_RST_BYPASS_COUNT_64   (3 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT) /* 64 XTALI cycles before WARM to COLD reset */
+#define SRC_SCR_MASK_WDOG_RST_SHIFT          (7) /* Bits 7-10: Mask wdog_rst_b source */
+#define SRC_SCR_MASK_WDOG_RST_MASK           (15 << SRC_SCR_MASK_WDOG_RST_SHIFT)
+#  define SRC_SCR_MASK_WDOG_RST_MASKED       (15 << SRC_SCR_MASK_WDOG_RST_SHIFT) /* wdog_rst_b is masked */
+#  define SRC_SCR_MASK_WDOG_RST_UNMASKED     (15 << SRC_SCR_MASK_WDOG_RST_SHIFT) /* wdog_rst_b is not masked */
+#define SRC_SCR_EIM_RST            (1 << 11) /* Bit 11: EIM reset is needed in order to reconfigure the eim chip select */
+#define SRC_SCR_SW_IPU2_RST        (1 << 12) /* Bit 12: Software reset for ipu2 */
+#define SRC_SCR_CORE0_RST          (1 << 13) /* Bit 13: Software reset for core0 */
+#define SRC_SCR_CORE1_RST          (1 << 14) /* Bit 14: Software reset for core1 */
+#define SRC_SCR_CORE2_RST          (1 << 15) /* Bit 15: Software reset for core2 */
+#define SRC_SCR_CORE3_RST          (1 << 16) /* Bit 16: Software reset for core3 */
+#define SRC_SCR_CORE0_DBG_RST      (1 << 17) /* Bit 17: Software reset for core0 debug */
+#define SRC_SCR_CORE1_DBG_RST      (1 << 18) /* Bit 18: Software reset for core1 debug */
+#define SRC_SCR_CORE2_DBG_RST      (1 << 19) /* Bit 19: Software reset for core2 debug */
+#define SRC_SCR_CORE3_DBG_RST      (1 << 20) /* Bit 20: Software reset for core3 debug */
+#define SRC_SCR_CORES_DBG_RST      (1 << 21) /* Bit 21: Software reset for debug of arm platform */
+#define SRC_SCR_CORE1_ENABLE       (1 << 22) /* Bit 22: core1 enable */
+#define SRC_SCR_CORE2_ENABLE       (1 << 23) /* Bit 23: core2 enable */
+#define SRC_SCR_CORE3_ENABLE       (1 << 24) /* Bit 24: core3 enable */
+#define SRC_SCR_DBG_RST_MSK_PG     (1 << 25) /* Bit 25: No debug resets after core power gating event */
+                                             /* Bits 26-31: Reserved */
+
+/* SRC Boot Mode Register 1 */
+
+#define SRC_SBMR1_BOOT_CFG1_SHIFT  (0)       /* Bits 0-7: Refer to fusemap */
+#define SRC_SBMR1_BOOT_CFG1_MASK   (0xff << SRC_SBMR1_BOOT_CFG1_SHIFT)
+#  define SRC_SBMR1_BOOT_CFG1(n)   ((uint32_t)(n) << SRC_SBMR1_BOOT_CFG1_SHIFT)
+#define SRC_SBMR1_BOOT_CFG2_SHIFT  (8)       /* Bits 8-15: Refer to fusemap */
+#define SRC_SBMR1_BOOT_CFG2_MASK   (0xff << SRC_SBMR1_BOOT_CFG2_SHIFT)
+#  define SRC_SBMR1_BOOT_CFG2(n)   ((uint32_t)(n) << SRC_SBMR1_BOOT_CFG2_SHIFT)
+#define SRC_SBMR1_BOOT_CFG3_SHIFT  (16)      /* Bits 16-23: Refer to fusemap */
+#define SRC_SBMR1_BOOT_CFG3_MASK   (0xff << SRC_SBMR1_BOOT_CFG3_SHIFT)
+#  define SRC_SBMR1_BOOT_CFG3(n)   ((uint32_t)(n) << SRC_SBMR1_BOOT_CFG3_SHIFT)
+#define SRC_SBMR1_BOOT_CFG4_SHIFT  (24)      /* Bits 24-31: Refer to fusemap */
+#define SRC_SBMR1_BOOT_CFG4_MASK   (0xff << SRC_SBMR1_BOOT_CFG4_SHIFT)
+#  define SRC_SBMR1_BOOT_CFG4(n)   ((uint32_t)(n) << SRC_SBMR1_BOOT_CFG4_SHIFT)
+
+/* SRC Reset Status Register */
+
+#define SRC_SRSR_IPP_RESET         (1 << 0)  /* Bit 0:  Reset result of ipp_reset_b pin (Power-up sequence) */
+                                             /* Bit 1:  Reserved */
+#define SRC_SRSR_CSU_RESET         (1 << 2)  /* Bit 2:  Reset result of the csu_reset_b input */
+#define SRC_SRSR_IPP_USER_RESET    (1 << 3)  /* Bit 3:  Reset result of ipp_user_reset_b qualified reset */
+#define SRC_SRSR_WDOG_RST          (1 << 4)  /* Bit 4:  IC Watchdog Time-out reset */
+#define SRC_SRSR_JTAG_RST          (1 << 5)  /* Bit 5:  HIGH - Z JTAG reset */
+#define SRC_SRSR_JTAG_SW_RST       (1 << 6)  /* Bit 6:  JTAG software reset */
+                                             /* Bits 7-15: Reserved */
+#define SRC_SRSR_WARM_BOOT         (1 << 16) /* Bit 16: WARM boot indication shows that WARM boot was initiated by software */
+                                             /* Bits 17-31: Reserved */
+
+/* SRC Interrupt Status Register */
+
+#define SRC_SISR_GPU_PASSED_RESET      (1 << 0)  /* Bit 0:  GPU passed software reset and is ready */
+#define SRC_SISR_VPU_PASSED_RESET      (1 << 1)  /* Bit 1:  VPU passed software reset and is ready */
+#define SRC_SISR_IPU1_PASSED_RESET     (1 << 2)  /* Bit 2:  ipu passed software reset and is ready */
+#define SRC_SISR_OPEN_VG_PASSED_RESET  (1 << 3)  /* Bit 3:  open_vg passed software reset and is ready */
+#define SRC_SISR_IPU2_PASSED_RESET     (1 << 4)  /* Bit 4:  ipu2 passed software reset and is ready */
+#define SRC_SISR_CORE0_WDOG_RST_REQ    (1 << 5)  /* Bit 5:  WDOG reset request from core0 */
+#define SRC_SISR_CORE1_WDOG_RST_REQ    (1 << 6)  /* Bit 6:  WDOG reset request from core1 */
+#define SRC_SISR_CORE2_WDOG_RST_REQ    (1 << 7)  /* Bit 7:  WDOG reset request from core2 */
+#define SRC_SISR_CORE3_WDOG_RST_REQ    (1 << 8)  /* Bit 8:  WDOG reset request from core3 */
+                                                 /* Bits 9-31: Reserved */
+
+/* SRC Interrupt Mask Register */
+#define SRC_SIMR_
+
+#define SRC_SIMR_GPU_PASSED_RESET      (1 << 0)  /* Bit 0:  Mask GPU passed software reset interrupt */
+#define SRC_SIMR_VPU_PASSED_RESET      (1 << 1)  /* Bit 1:  Mask VPU passed software reset interrupt */
+#define SRC_SIMR_IPU1_PASSED_RESET     (1 << 2)  /* Bit 2:  Mask ipu passed software reset interrupt */
+#define SRC_SIMR_OPEN_VG_PASSED_RESET  (1 << 3)  /* Bit 3:  Mask open_vg passed software reset interrupt */
+#define SRC_SIMR_IPU2_PASSED_RESET     (1 << 4)  /* Bit 4:  Mask ipu2 passed software reset interrupt */
+                                                 /* Bits 5-31: Reserved */
+
+/* SRC Boot Mode Register 2 */
+
+#define SRC_SBMR2_SEC_CONFIG_SHIFT (0)       /* Bits 0-1: State of the SECONFIG fuses */
+                                             /* Bit 2: Reserved */
+#define SRC_SBMR2_DIR_BT_DIS       (1 << 3)  /* Bit 3:  State of the DIR_BT_DIS fuse */
+#define SRC_SBMR2_BT_FUSE_SEL      (1 << 4)  /* Bit 4: State of the BT_FUSE_SEL fuse */
+                                             /* Bits 5-23: Reserved */
+#define SRC_SBMR2_BMOD_SHIFT       (24)      /* Bits 24-25: Latched state of the BOOT_MODE1 and BOOT_MODE0 */
+#define SRC_SBMR2_BMOD_MASK        (3 << SRC_SBMR2_BMOD_SHIFT)
+                                             /* Bits 26-31: Reserved */
+
+/* SRC General Purpose Register 1:  32-bit PERSISTENT_ENTRY0: core0 entry function for waking-up from low power mode */
+/* SRC General Purpose Register 2:  32-bit PERSISTENT_ARG0:  core0 entry function argument */
+/* SRC General Purpose Register 3:  32-bit PERSISTENT_ENTRY1: core1 entry function for waking-up from low power mode */
+/* SRC General Purpose Register 4:  32-bit PERSISTENT_ARG1:  core1 entry function argument */
+/* SRC General Purpose Register 5:  32-bit PERSISTENT_ENTRY2: core2 entry function for waking-up from low power mode */
+/* SRC General Purpose Register 6:  32-bit PERSISTENT_ARG2:  core1 entry function argument */
+/* SRC General Purpose Register 7:  32-bit PERSISTENT_ENTRY3: core3 entry function for waking-up from low power mode */
+/* SRC General Purpose Register 8:  32-bit PERSISTENT_ARG3:  core3 entry function argument */
+/* SRC General Purpose Register 9:  Reserved */
+
+/* SRC General Purpose Register 10 */
+
+#define SRC_GPR10_RW1_SHIFT          (0)       /* Bits 0-24: General purpose R/W bits */
+#define SRC_GPR10_RW1_MASK           (0x01ffffff << SRC_GPR10_RW1_SHIFT)
+#  define SRC_GPR10_RW1(n)           ((uint32_t)(n) << SRC_GPR10_RW1_SHIFT)
+#define SRC_GPR10_CORE1_ERROR_STATUS (1 << 25) /* Bit 25: core1 error status bit */
+#define SRC_GPR10_CORE2_ERROR_STATUS (1 << 26) /* Bit 26: core2 error status bit */
+#define SRC_GPR10_CORE3_ERROR_STATUS (1 << 27) /* Bit 27: core3 error status bit */
+#define SRC_GPR10_RW2_SHIFT          (28)      /* Bits 28-31: General purpose R/W bits */
+#define SRC_GPR10_RW2_MASK           (15 << SRC_GPR10_RW2_SHIFT)
+#  define SRC_GPR10_RW2(n)           ((uint32_t)(n) << SRC_GPR10_RW2_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_IMX6_CHIP_IMX_SRC_H */
@@ -195,10 +195,10 @@
 #define UART_UCR1_RRDYEN       (1 << 9)  /* Bit 9: Receiver ready interrupt enable */
 #define UART_UCR1_ICD_SHIFT    10        /* Bit 10-11: Idle condition detect */
 #define UART_UCR1_ICD_MASK     (3 << UART_UCR1_ICD_SHIFT)
-# define UART_UCR1_ICD_4FRMS   (0 << UART_UCR1_ICD_SHIFT) /* Idle for more than 4 frames */
-# define UART_UCR1_ICD_8FRMS   (1 << UART_UCR1_ICD_SHIFT) /* Idle for more than 8 frames */
-# define UART_UCR1_ICD_16FRMS  (2 << UART_UCR1_ICD_SHIFT) /* Idle for more than 16 frames */
-# define UART_UCR1_ICD_32FRMS  (3 << UART_UCR1_ICD_SHIFT) /* Idle for more than 32 frames */
+#  define UART_UCR1_ICD_4FRMS  (0 << UART_UCR1_ICD_SHIFT) /* Idle for more than 4 frames */
+#  define UART_UCR1_ICD_8FRMS  (1 << UART_UCR1_ICD_SHIFT) /* Idle for more than 8 frames */
+#  define UART_UCR1_ICD_16FRMS (2 << UART_UCR1_ICD_SHIFT) /* Idle for more than 16 frames */
+#  define UART_UCR1_ICD_32FRMS (3 << UART_UCR1_ICD_SHIFT) /* Idle for more than 32 frames */
 #define UART_UCR1_IDEN         (1 << 12) /* Bit 12: Idle condition detected interrupt enable */
 #define UART_UCR1_TRDYEN       (1 << 13) /* Bit 13: Transmitter ready interrupt enable */
 #define UART_UCR1_ADBR         (1 << 14) /* Bit 14: Automatic detection of baud rate */
@@ -309,7 +309,7 @@ static void imx_copyvectorblock(void)
 #ifndef CONFIG_IMX6_WDT
 static inline void imx_wdtdisable(void)
 {
-#  warning REVISIT WDT initialization
+  /* REVISIT: WDT initialization */
 }
 #else
 #  define imx_wdtdisable()
@@ -320,7 +320,7 @@ static inline void imx_wdtdisable(void)
 ****************************************************************************/

 /****************************************************************************
- * Name: up_boot
+ * Name: arm_boot
 *
 * Description:
 *   Complete boot operations started in arm_head.S
@@ -386,7 +386,7 @@ static inline void imx_wdtdisable(void)
 *
 ****************************************************************************/

-void up_boot(void)
+void arm_boot(void)
 {
 #ifdef CONFIG_ARCH_RAMFUNCS
  const uint32_t *src;
@@ -400,6 +400,13 @@ void up_boot(void)
  imx_setupmappings();
  imx_lowputc('A');

+  /* Make sure that all other CPUs are in the disabled state.  This is a
+   * formality because the other CPUs are actually running then we have
+   * probably already crashed.
+   */
+
+  imx_cpu_disable();
+
  /* Provide a special mapping for the OCRAM interrupt vector positioned in
   * high memory.
   */
@@ -498,5 +505,13 @@ void up_boot(void)
  imx_earlyserialinit();
  imx_lowputc('M');
 #endif
+
+  /* Now we can enable all other CPUs.  The enabled CPUs will start execution
+   * at __cpuN_start and, after very low-level CPU initialzation has been
+   * performed, will branch to arm_cpu_boot() (see arch/arm/src/armv7-a/smp.h)
+   */
+
+  imx_cpu_enable();
+  imx_lowputc('N');
  imx_lowputc('\n');
 }
@@ -51,23 +51,11 @@
 #include "chip.h"

 /****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Inline Functions
+ * Public Function Prototypes
 ****************************************************************************/

 #ifndef __ASSEMBLY__

-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
 #undef EXTERN
 #if defined(__cplusplus)
 #define EXTERN extern "C"
@@ -78,9 +66,50 @@ extern "C"
 #endif

 /****************************************************************************
- * Public Function Prototypes
+ * Name: imx_cpu_disable
+ *
+ * Description:
+ *   Called from CPU0 to make sure that all other CPUs are in the disabled
+ *   state.  This is a formality because the other CPUs are actually running
+ *   then we have probably already crashed.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
 ****************************************************************************/

+#ifdef CONFIG_SMP
+void imx_cpu_disable(void);
+#else
+#  define imx_cpu_disable()
+#endif
+
+/****************************************************************************
+ * Name: imx_cpu_enable
+ *
+ * Description:
+ *   Called from CPU0 to enable all other CPUs.  The enabled CPUs will start
+ *   execution at __cpuN_start and, after very low-level CPU initialzation
+ *   has been performed, will branch to arm_cpu_boot()
+ *   (see arch/arm/src/armv7-a/smp.h)
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+void imx_cpu_enable(void);
+#else
+#  define imx_cpu_enable()
+#endif
+
 /****************************************************************************
 * Name: imx_board_initialize
 *
@@ -0,0 +1,302 @@
+/****************************************************************************
+ * arch/arm/src/imx6/imx_cpuboot.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "chip/imx_src.h"
+#include "sctlr.h"
+#include "smp.h"
+#include "gic.h"
+
+#ifdef CONFIG_SMP
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+typedef CODE void (*cpu_start_t)(void);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#if 0 /* Not used */
+static const uint32_t g_cpu_reset[CONFIG_SMP_NCPUS] =
+{
+  0,
+#if CONFIG_SMP_NCPUS > 1
+  SRC_SCR_CORE1_RST,
+#endif
+#if CONFIG_SMP_NCPUS > 2
+  SRC_SCR_CORE2_RST,
+#endif
+#if CONFIG_SMP_NCPUS > 3
+  SRC_SCR_CORE3_RST
+#endif
+};
+#endif
+
+static const uint32_t g_cpu_ctrl[CONFIG_SMP_NCPUS] =
+{
+  0,
+#if CONFIG_SMP_NCPUS > 1
+  SRC_SCR_CORE1_ENABLE,
+#endif
+#if CONFIG_SMP_NCPUS > 2
+  SRC_SCR_CORE2_ENABLE,
+#endif
+#if CONFIG_SMP_NCPUS > 3
+  SRC_SCR_CORE3_ENABLE
+#endif
+};
+
+static const uintptr_t g_cpu_gpr[CONFIG_SMP_NCPUS] =
+{
+  0,
+#if CONFIG_SMP_NCPUS > 1
+  IMX_SRC_GPR3,
+#endif
+#if CONFIG_SMP_NCPUS > 2
+  IMX_SRC_GPR5,
+#endif
+#if CONFIG_SMP_NCPUS > 3
+  IMX_SRC_GPR7
+#endif
+};
+
+static const cpu_start_t g_cpu_boot[CONFIG_SMP_NCPUS] =
+{
+  0,
+#if CONFIG_SMP_NCPUS > 1
+  __cpu1_start,
+#endif
+#if CONFIG_SMP_NCPUS > 2
+  __cpu2_start,
+#endif
+#if CONFIG_SMP_NCPUS > 3
+  __cpu3_start
+#endif
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* Symbols defined via the linker script */
+
+extern uint32_t _vector_start; /* Beginning of vector block */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imx_cpu_reset
+ *
+ * Description:
+ *   CPUn software reset
+ *
+ ****************************************************************************/
+
+#if 0 /* Not used */
+static void imx_cpu_reset(int cpu)
+{
+  uint32_t regval;
+
+  regval  = getreg32(IMX_SRC_SCR);
+  regval |= g_cpu_reset[cpu];
+  putreg32(regval, IMX_SRC_SCR);
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imx_cpu_disable
+ *
+ * Description:
+ *   Called from CPU0 to make sure that all other CPUs are in the disabled
+ *   state.  This is a formality because the other CPUs are actually running
+ *   then we have probably already crashed.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void imx_cpu_disable(void)
+{
+  uint32_t regval;
+  uint32_t cpumask;
+
+  cpumask  = 0;
+#if CONFIG_SMP_NCPUS > 1
+  cpumask |= SRC_SCR_CORE1_ENABLE;
+#endif
+#if CONFIG_SMP_NCPUS > 2
+  cpumask |= SRC_SCR_CORE2_ENABLE;
+#endif
+#if CONFIG_SMP_NCPUS > 3
+  cpumask |= SRC_SCR_CORE3_ENABLE;
+#endif
+
+  regval  = getreg32(IMX_SRC_SCR);
+  regval &= ~cpumask;
+  putreg32(regval, IMX_SRC_SCR);
+}
+
+/****************************************************************************
+ * Name: imx_cpu_enable
+ *
+ * Description:
+ *   Called from CPU0 to enable all other CPUs.  The enabled CPUs will start
+ *   execution at __cpuN_start and, after very low-level CPU initialzation
+ *   has been performed, will branch to arm_cpu_boot()
+ *   (see arch/arm/src/armv7-a/smp.h)
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void imx_cpu_enable(void)
+{
+  cpu_start_t bootaddr;
+  uintptr_t regaddr;
+  uint32_t regval;
+  int cpu;
+
+  for (cpu = 1; cpu < CONFIG_SMP_NCPUS; cpu++)
+    {
+      /* Set the start up address */
+
+      regaddr  = g_cpu_gpr[cpu];
+      bootaddr = g_cpu_boot[cpu];
+      putreg32((uint32_t)bootaddr, regaddr);
+
+      /* Then enable the CPU */
+
+      regval   = getreg32(IMX_SRC_SCR);
+      regval  |= g_cpu_ctrl[cpu];
+      putreg32(regval, IMX_SRC_SCR);
+    }
+}
+
+/****************************************************************************
+ * Name: arm_cpu_boot
+ *
+ * Description:
+ *   Continues the C-level initialization started by the assembly language
+ *   __cpu[n]_start function.  At a minimum, this function needs to initialize
+ *   interrupt handling and, perhaps, wait on WFI for arm_cpu_start() to
+ *   issue an SGI.
+ *
+ *   This function must be provided by the each ARMv7-A MCU and implement
+ *   MCU-specific initialization logic.
+ *
+ * Input parameters:
+ *   cpu - The CPU index.  This is the same value that would be obtained by
+ *      calling up_cpu_index();
+ *
+ * Returned Value:
+ *   Does not return.
+ *
+ ****************************************************************************/
+
+void arm_cpu_boot(int cpu)
+{
+  /* Initialize the Generic Interrupt Controller (GIC) for CPUn (n != 0) */
+
+  arm_gic_initialize();
+
+#ifdef CONFIG_ARCH_LOWVECTORS
+  /* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the
+   * beginning of the .text region must appear at address at the address
+   * specified in the VBAR.  There are two ways to accomplish this:
+   *
+   *   1. By explicitly mapping the beginning of .text region with a page
+   *      table entry so that the virtual address zero maps to the beginning
+   *      of the .text region.  VBAR == 0x0000:0000.
+   *
+   *   2. Set the Cortex-A5 VBAR register so that the vector table address
+   *      is moved to a location other than 0x0000:0000.
+   *
+   *  The second method is used by this logic.
+   */
+
+  /* Set the VBAR register to the address of the vector table */
+
+  DEBUGASSERT((((uintptr_t)&_vector_start) & ~VBAR_MASK) == 0);
+  cp15_wrvbar((uint32_t)&_vector_start);
+#endif /* CONFIG_ARCH_LOWVECTORS */
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+  /* And finally, enable interrupts */
+
+  (void)up_irq_enable();
+#endif
+
+  /* The next thing that we expect to happen is for logic running on CPU0
+   * to call up_cpu_start() which generate an SGI and a context switch to
+   * the configured NuttX IDLE task.
+   */
+
+  for (; ; )
+    {
+      asm("WFI");
+    }
+}
+#endif /* CONFIG_SMP */
@@ -50,6 +50,7 @@

 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
+#include <nuttx/init.h>
 #include <nuttx/serial/serial.h>
 #include <arch/serial.h>

@@ -57,6 +58,7 @@
 #include "up_arch.h"
 #include "up_internal.h"

+#include "gic.h"
 #include "chip/imx_uart.h"
 #include "imx_config.h"
 #include "imx_lowputc.h"
@@ -258,6 +260,12 @@ static bool imx_txempty(struct uart_dev_s *dev);
 * Private Data
 ****************************************************************************/

+/* Used to assure mutually exclusive access up_putc() */
+
+static sem_t g_putc_lock = SEM_INITIALIZER(1);
+
+/* Serial driver UART operations */
+
 static const struct uart_ops_s g_uart_ops =
 {
  .setup          = imx_setup,
@@ -613,6 +621,10 @@ static int imx_attach(struct uart_dev_s *dev)
  ret = irq_attach(priv->irq, priv->handler);
  if (ret == OK)
    {
+      /* Configure as a (high) level interrupt */
+
+      (void)arm_gic_irq_trigger(priv->irq, false);
+
      /* Enable the interrupt (RX and TX interrupts are still disabled
       * in the UART
       */
@@ -1001,6 +1013,27 @@ int up_putc(int ch)
 {
  struct imx_uart_s *priv = (struct imx_uart_s *)CONSOLE_DEV.priv;
  uint32_t ier;
+  bool locked;
+  int ret;
+
+  /* Only one thread may enter up_putc at a time. */
+
+  locked = false;
+
+  if (!up_interrupt_context() && g_os_initstate >= OSINIT_HARDWARE)
+    {
+      ret = sem_wait(&g_putc_lock);
+      if (ret < 0)
+        {
+          return ERROR;
+        }
+
+      locked = true;
+    }
+
+  /* Disable UART interrupts and wait until the hardware is ready to send
+   * a byte.
+   */

  imx_disableuartint(priv, &ier);
  imx_waittxready(priv);
@@ -1018,6 +1051,12 @@ int up_putc(int ch)
  imx_serialout(priv, UART_TXD_OFFSET, (uint32_t)ch);
  imx_waittxready(priv);
  imx_restoreuartint(priv, ier);
+
+  if (locked)
+    {
+      sem_post(&g_putc_lock);
+    }
+
  return ch;
 }

@@ -46,6 +46,7 @@
 #include <arch/irq.h>

 #include "up_arch.h"
+#include "gic.h"
 #include "chip/imx_ccm.h"
 #include "chip/imx_gpt.h"

@@ -76,10 +77,25 @@
 * We should be able to use a prescaler of 1.
 */

-#define GPT_PR_VALUE      1
-#define GPT_OCR3_VALUE   ((GPT_CLOCK + ((1*CLK_TCK) >> 1)) / (1*CLK_TCK))
-#define GPT_OCR2_VALUE   ((GPT_CLOCK + ((2*CLK_TCK) >> 1)) / (2*CLK_TCK))
-#define GPT_OCR1_VALUE   ((GPT_CLOCK + ((3*CLK_TCK) >> 1)) / (3*CLK_TCK))
+#define GPT_PR_VALUE     1
+
+/* Timer counter comparison settings:
+ *
+ * - OCR3 will interrupt at CLK_TCK ticks/second after the timer counter
+ *   has been reset.
+ * - OCR2 will interrupt at 2*CLK_TCK ticks/second after the timer counter
+ *   has been reset.
+ * - OCR2 will interrupt at 3*CLK_TCK ticks/second after the timer counter
+ *   has been reset and then will reset the timer, starting the 3 interrupt
+ *   sequence again.
+ *
+ * Using three comparisons virtually eliminates the possibility of timer
+ * interrupt overrun.
+ */
+
+#define GPT_OCR3_VALUE   ((1 * GPT_CLOCK + (CLK_TCK >> 1)) / CLK_TCK)
+#define GPT_OCR2_VALUE   ((2 * GPT_CLOCK + (CLK_TCK >> 1)) / CLK_TCK)
+#define GPT_OCR1_VALUE   ((3 * GPT_CLOCK + (CLK_TCK >> 1)) / CLK_TCK)

 /****************************************************************************
 * Private Functions
@@ -164,7 +180,7 @@ void up_timer_initialize(void)

  /* Disable GPT by setting EN=0 in GPT_CR register */

-  cr = getreg32(IMX_GPT_CR);
+  cr  = getreg32(IMX_GPT_CR);
  cr &= ~GPT_CR_EN;
  putreg32(cr, IMX_GPT_CR);

@@ -220,7 +236,7 @@ void up_timer_initialize(void)
   */

  cr &= ~GPT_CR_FFR;
-  putreg32(cr | GPT_CR_SWR, IMX_GPT_CR);
+  putreg32(cr, IMX_GPT_CR);

  /* Set ENMOD=1 in GPT_CR register, to bring GPT counter to 0x00000000.  If
   * the ENMOD bit is 1, then the Main Counter and Prescaler Counter values
@@ -235,6 +251,10 @@ void up_timer_initialize(void)
  cr |= GPT_CR_EN;
  putreg32(cr, IMX_GPT_CR);

+  /* Configure as a (rising) edge-triggered interrupt */
+
+  (void)arm_gic_irq_trigger(IMX_IRQ_GPT, true);
+
  /* Attach the timer interrupt vector */

  (void)irq_attach(IMX_IRQ_GPT, (xcpt_t)up_timerisr);
@@ -154,7 +154,7 @@ static inline void gpio_outputhigh(uint32_t ioconfig, uint32_t bit)
 * Name: lpc31_lowsetup
 *
 * Description:
- *   Called early in up_boot.  Performs chip-common low level initialization.
+ *   Called early in arm_boot.  Performs chip-common low level initialization.
 *
 ************************************************************************************/

@@ -333,14 +333,14 @@ static void up_copyvectorblock(void)
 ************************************************************************************/

 /************************************************************************************
- * Name: up_boot
+ * Name: arm_boot
 *
 * Description:
 *   Complete boot operations started in up_head.S
 *
 ************************************************************************************/

-void up_boot(void)
+void arm_boot(void)
 {
  /* __start provided the basic MMU mappings for SRAM.  Now provide mappings for all
   * IO regions (Including the vector region).
@@ -271,7 +271,7 @@ static inline void up_configbaud(void)
 * Name: lpc31_lowsetup
 *
 * Description:
- *   Called early in up_boot.  Performs chip-common low level initialization.
+ *   Called early in arm_boot.  Performs chip-common low level initialization.
 *
 ****************************************************************************/

@@ -338,7 +338,7 @@ static inline void sam_wdtdisable(void)
 ****************************************************************************/

 /****************************************************************************
- * Name: up_boot
+ * Name: arm_boot
 *
 * Description:
 *   Complete boot operations started in arm_head.S
@@ -407,7 +407,7 @@ static inline void sam_wdtdisable(void)
 *
 ****************************************************************************/

-void up_boot(void)
+void arm_boot(void)
 {
 #ifdef CONFIG_ARCH_RAMFUNCS
  const uint32_t *src;
@@ -648,7 +648,7 @@ static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
 ****************************************************************************/

 /****************************************************************************
- * Name: up_wdginitialize
+ * Name: sam_wdt_initialize
 *
 * Description:
 *   Initialize the WDT watchdog time.  The watchdog timer is initialized and
@@ -663,7 +663,7 @@ static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
 *
 ****************************************************************************/

-int up_wdginitialize(void)
+int sam_wdt_initialize(void)
 {
  FAR struct sam_lowerhalf_s *priv = &g_wdtdev;

@@ -1,7 +1,7 @@
 /****************************************************************************
 * arch/arm/src/sama5/sam_wdt.h
 *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@@ -66,6 +66,26 @@ extern "C"
 * Public Functions
 ****************************************************************************/

+/****************************************************************************
+ * Name: sam_wdt_initialize()
+ *
+ * Description:
+ *   Perform architecture-specific initialization of the Watchdog hardware.
+ *   This interface should be provided by all configurations using
+ *   to avoid exposed platform-dependent logic.
+ *
+ *   At a minimum, this function should call watchdog_register().
+ *
+ * Input parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int sam_wdt_initialize(void);
+
 #undef EXTERN
 #if defined(__cplusplus)
 }
@@ -26,7 +26,7 @@ config ARCH_CHIP_SAME70Q21
 	select ARCH_CHIP_SAME70Q

 config ARCH_CHIP_SAME70N19
-	bool "SAME70N10"
+	bool "SAME70N19"
 	select ARCH_CHIP_SAME70N

 config ARCH_CHIP_SAME70N20
@@ -648,7 +648,7 @@ static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
 ****************************************************************************/

 /****************************************************************************
- * Name: up_wdginitialize
+ * Name: sam_rswdt_initialize
 *
 * Description:
 *   Initialize the RSWDT watchdog time.  The watchdog timer is initialized and
@@ -663,7 +663,7 @@ static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
 *
 ****************************************************************************/

-int up_wdginitialize(void)
+int sam_rswdt_initialize(void)
 {
  FAR struct sam_lowerhalf_s *priv = &g_wdtdev;

@@ -648,7 +648,7 @@ static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
 ****************************************************************************/

 /****************************************************************************
- * Name: up_wdginitialize
+ * Name: sam_wdt_initialize
 *
 * Description:
 *   Initialize the WDT watchdog time.  The watchdog timer is initialized and
@@ -663,7 +663,7 @@ static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
 *
 ****************************************************************************/

-int up_wdginitialize(void)
+int sam_wdt_initialize(void)
 {
  FAR struct sam_lowerhalf_s *priv = &g_wdtdev;

@@ -66,6 +66,46 @@ extern "C"
 * Public Functions
 ****************************************************************************/

+/****************************************************************************
+ * Name: sam_wdt_initialize()
+ *
+ * Description:
+ *   Perform architecture-specific initialization of the WDT hardware.
+ *   This interface should be provided by all configurations using
+ *   to avoid exposed platform-dependent logic.
+ *
+ *   At a minimum, this function should call watchdog_register().
+ *
+ * Input parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int sam_wdt_initialize(void);
+
+/****************************************************************************
+ * Name: sam_rswdt_initialize()
+ *
+ * Description:
+ *   Perform architecture-specific initialization of the RSWDT hardware.
+ *   This interface should be provided by all configurations using
+ *   to avoid exposed platform-dependent logic.
+ *
+ *   At a minimum, this function should call watchdog_register().
+ *
+ * Input parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int sam_rswdt_initialize(void);
+
 #undef EXTERN
 #if defined(__cplusplus)
 }
@@ -5634,7 +5634,27 @@ config STM32_FLOWCONTROL_BROKEN
 		nRTS after every byte received)  Enable this setting workaround
 		this issue by useing software based management of RTS

-endmenu
+config STM32_USART_BREAKS
+	bool "Add TIOxSBRK to support sending Breaks"
+	depends on STM32_USART
+	default n
+	---help---
+		Add TIOCxBRK routines to send a line break per the STM32 manual, the
+		break will be a pulse based on the value M. This is not a BSD compatible
+		break.
+
+config STM32_SERIALBRK_BSDCOMPAT
+	bool "Use GPIO To send Break"
+	depends on STM32_USART && STM32_USART_BREAKS
+	default n
+	---help---
+		Enable using GPIO on the TX pin to send a BSD compatible break:
+		TIOCSBRK will start the break and TIOCCBRK will end the break.
+		The current STM32 U[S]ARTS have no way to leave the break (TX=LOW)
+		on because the SW starts the break and then the HW automatically clears
+		the break. This makes it is difficult to sent a long break.
+
+endmenu # U[S]ART Configuration

 config STM32_USART_SINGLEWIRE
 	bool "Single Wire Support"
@@ -255,6 +255,22 @@
 #  define PM_IDLE_DOMAIN             0 /* Revisit */
 #endif

+/* Keep track if a Break was set
+ *
+ * Note:
+ *
+ * 1) This value is set in the priv->ie but never written to the control
+ *    register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE
+ * 2) USART_CR3_EIE is also carried in the up_dev_s ie member.
+ *
+ * See up_restoreusartint where the masking is done.
+ */
+
+#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
+#  define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
+#  define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
+#endif
+
 #ifdef USE_SERIALDRIVER
 #ifdef HAVE_UART

@@ -1897,11 +1913,12 @@ static int up_interrupt_common(struct up_dev_s *priv)

 static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
 {
-#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT)
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \
+    || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT)
  struct inode      *inode = filep->f_inode;
  struct uart_dev_s *dev   = inode->i_private;
 #endif
-#ifdef CONFIG_SERIAL_TERMIOS
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT)
  struct up_dev_s   *priv  = (struct up_dev_s *)dev->priv;
 #endif
  int                ret    = OK;
@@ -2057,30 +2074,74 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
      break;
 #endif /* CONFIG_SERIAL_TERMIOS */

-#ifdef CONFIG_USART_BREAKS
+#ifdef CONFIG_STM32_USART_BREAKS
+#  ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
    case TIOCSBRK:  /* BSD compatibility: Turn break on, unconditionally */
      {
-        uint32_t cr2;
        irqstate_t flags;
+        uint32_t tx_break;

        flags = enter_critical_section();
-        cr2   = up_serialin(priv, STM32_USART_CR2_OFFSET);
-        up_serialout(priv, STM32_USART_CR2_OFFSET, cr2 | USART_CR2_LINEN);
+
+        /* Disable any further tx activity */
+
+        priv->ie |= USART_CR1_IE_BREAK_INPROGRESS;
+
+        up_txint(dev, false);
+
+        /* Configure TX as a GPIO output pin and Send a break signal*/
+
+        tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK|GPIO_OUTPUT_SET) & priv->tx_gpio);
+        stm32_configgpio(tx_break);
+
        leave_critical_section(flags);
      }
      break;

    case TIOCCBRK:  /* BSD compatibility: Turn break off, unconditionally */
      {
-        uint32_t cr2;
        irqstate_t flags;

        flags = enter_critical_section();
-        cr2   = up_serialin(priv, STM32_USART_CR2_OFFSET);
-        up_serialout(priv, STM32_USART_CR2_OFFSET, cr2 & ~USART_CR2_LINEN);
+
+        /* Configure TX back to U(S)ART */
+
+        stm32_configgpio(priv->tx_gpio);
+
+        priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS;
+
+        /* Enable further tx activity */
+
+        up_txint(dev, true);
+
        leave_critical_section(flags);
      }
      break;
+#  else
+    case TIOCSBRK:  /* No BSD compatibility: Turn break on for M bit times */
+      {
+        uint32_t cr1;
+        irqstate_t flags;
+
+        flags = enter_critical_section();
+        cr1   = up_serialin(priv, STM32_USART_CR1_OFFSET);
+        up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK);
+        leave_critical_section(flags);
+      }
+      break;
+
+    case TIOCCBRK:  /* No BSD compatibility: May turn off break too soon */
+      {
+        uint32_t cr1;
+        irqstate_t flags;
+
+        flags = enter_critical_section();
+        cr1   = up_serialin(priv, STM32_USART_CR1_OFFSET);
+        up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK);
+        leave_critical_section(flags);
+      }
+      break;
+#  endif
 #endif

    default:
@@ -2470,6 +2531,13 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
        }
 #  endif

+#  ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
+      if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
+        {
+          return;
+        }
+#  endif
+
      up_restoreusartint(priv, ie);

      /* Fake a TX interrupt here by just calling uart_xmitchars() with
@@ -435,6 +435,255 @@ config STM32F7_WWDG

 endmenu

+menu "U[S]ART Configuration"
+	depends on STM32F7_USART
+
+config USART1_RS485
+	bool "RS-485 on USART1"
+	default n
+	depends on STM32F7_USART1
+	---help---
+		Enable RS-485 interface on USART1. Your board config will have to
+		provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be
+		used with USART1_RXDMA.
+
+config USART1_RS485_DIR_POLARITY
+	int "USART1 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on USART1_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config USART1_RXDMA
+	bool "USART1 Rx DMA"
+	default n
+	depends on STM32F7_USART1 && STM32F7_DMA1
+	---help---
+		In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config USART2_RS485
+	bool "RS-485 on USART2"
+	default n
+	depends on STM32F7_USART2
+	---help---
+		Enable RS-485 interface on USART2. Your board config will have to
+		provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be
+		used with USART2_RXDMA.
+
+config USART2_RS485_DIR_POLARITY
+	int "USART2 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on USART2_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config USART2_RXDMA
+	bool "USART2 Rx DMA"
+	default n
+	depends on STM32F7_USART2 && STM32F7_DMA1
+	---help---
+		In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config USART3_RS485
+	bool "RS-485 on USART3"
+	default n
+	depends on STM32F7_USART3
+	---help---
+		Enable RS-485 interface on USART3. Your board config will have to
+		provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be
+		used with USART3_RXDMA.
+
+config USART3_RS485_DIR_POLARITY
+	int "USART3 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on USART3_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config USART3_RXDMA
+	bool "USART3 Rx DMA"
+	default n
+	depends on STM32F7_USART3 && STM32F7_DMA1
+	---help---
+		In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config UART4_RS485
+	bool "RS-485 on UART4"
+	default n
+	depends on STM32F7_UART4
+	---help---
+		Enable RS-485 interface on UART4. Your board config will have to
+		provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be
+		used with UART4_RXDMA.
+
+config UART4_RS485_DIR_POLARITY
+	int "UART4 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on UART4_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config UART4_RXDMA
+	bool "UART4 Rx DMA"
+	default n
+	depends on STM32F7_UART4 && STM32F7_DMA1
+	---help---
+		In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config UART5_RS485
+	bool "RS-485 on UART5"
+	default n
+	depends on STM32F7_UART5
+	---help---
+		Enable RS-485 interface on UART5. Your board config will have to
+		provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be
+		used with UART5_RXDMA.
+
+config UART5_RS485_DIR_POLARITY
+	int "UART5 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on UART5_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config UART5_RXDMA
+	bool "UART5 Rx DMA"
+	default n
+	depends on STM32F7_UART5 && STM32F7_DMA1
+	---help---
+		In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config USART6_RS485
+	bool "RS-485 on USART6"
+	default n
+	depends on STM32F7_USART6
+	---help---
+		Enable RS-485 interface on USART6. Your board config will have to
+		provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be
+		used with USART6_RXDMA.
+
+config USART6_RS485_DIR_POLARITY
+	int "USART6 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on USART6_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config USART6_RXDMA
+	bool "USART6 Rx DMA"
+	default n
+	depends on STM32F7_USART6 && STM32F7_DMA2
+	---help---
+		In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config UART7_RS485
+	bool "RS-485 on UART7"
+	default n
+	depends on STM32F7_UART7
+	---help---
+		Enable RS-485 interface on UART7. Your board config will have to
+		provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be
+		used with UART7_RXDMA.
+
+config UART7_RS485_DIR_POLARITY
+	int "UART7 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on UART7_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config UART7_RXDMA
+	bool "UART7 Rx DMA"
+	default n
+	depends on STM32F7_UART7 && STM32F7_DMA2
+	---help---
+		In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config UART8_RS485
+	bool "RS-485 on UART8"
+	default n
+	depends on STM32F7_UART8
+	---help---
+		Enable RS-485 interface on UART8. Your board config will have to
+		provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be
+		used with UART8_RXDMA.
+
+config UART8_RS485_DIR_POLARITY
+	int "UART8 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on UART8_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config UART8_RXDMA
+	bool "UART8 Rx DMA"
+	default n
+	depends on STM32F7_UART8 && STM32F7_DMA2
+	---help---
+		In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config SERIAL_DISABLE_REORDERING
+	bool "Disable reordering of ttySx devices."
+	depends on STM32F7_USART1 || STM32F7_USART2 || STM32F7_USART3 || STM32F7_UART4 || STM32F7_UART5 || STM32F7_USART6 || STM32F7_UART7 || STM32F7_UART8
+	default n
+	---help---
+		NuttX per default reorders the serial ports (/dev/ttySx) so that the
+		console is always on /dev/ttyS0. If more than one UART is in use this
+		can, however, have the side-effect that all port mappings
+		(hardware USART1 -> /dev/ttyS0) change if the console is moved to another
+		UART. This is in particular relevant if a project uses the USB console
+		in some configs and a serial console in other configs, but does not
+		want the side effect of having all serial port names change when just
+		the console is moved from serial to USB.
+
+config STM32F7_FLOWCONTROL_BROKEN
+	bool "Use Software UART RTS flow control"
+	depends on STM32F7_USART
+	default n
+	---help---
+		Enable UART RTS flow control using Software. Because STM
+		Current STM32 have broken HW based RTS behavior (they assert
+		nRTS after every byte received)  Enable this setting workaround
+		this issue by useing software based management of RTS
+
+config STM32F7_USART_BREAKS
+	bool "Add TIOxSBRK to support sending Breaks"
+	depends on STM32F7_USART
+	default n
+	---help---
+		Add TIOCxBRK routines to send a line break per the STM32 manual, the
+		break will be a pulse based on the value M. This is not a BSD compatible
+		break.
+
+config STM32F7_SERIALBRK_BSDCOMPAT
+	bool "Use GPIO To send Break"
+	depends on STM32F7_USART && STM32F7_USART_BREAKS
+	default n
+	---help---
+		Enable using GPIO on the TX pin to send a BSD compatible break:
+		TIOCSBRK will start the break and TIOCCBRK will end the break.
+		The current STM32 U[S]ARTS have no way to leave the break (TX=LOW)
+		on because the SW starts the break and then the HW automatically clears
+		the break. This makes it is difficult to sent a long break.
+
+endmenu # U[S]ART Configuration
+
 config STM32F7_CUSTOM_CLOCKCONFIG
        bool "Custom clock configuration"
 	default n
@@ -208,6 +208,22 @@
 #  define PM_IDLE_DOMAIN             0 /* Revisit */
 #endif

+/* Keep track if a Break was set
+ *
+ * Note:
+ *
+ * 1) This value is set in the priv->ie but never written to the control
+ *    register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE
+ * 2) USART_CR3_EIE is also carried in the up_dev_s ie member.
+ *
+ * See up_restoreusartint where the masking is done.
+ */
+
+#ifdef CONFIG_STM32F7_SERIALBRK_BSDCOMPAT
+#  define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
+#  define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
+#endif
+
 #ifdef USE_SERIALDRIVER
 #ifdef HAVE_UART

@@ -1817,11 +1833,12 @@ static int up_interrupt_common(struct up_dev_s *priv)

 static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
 {
-#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT)
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \
+    || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT)
  struct inode      *inode = filep->f_inode;
  struct uart_dev_s *dev   = inode->i_private;
 #endif
-#ifdef CONFIG_SERIAL_TERMIOS
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT)
  struct up_dev_s   *priv  = (struct up_dev_s *)dev->priv;
 #endif
  int                ret    = OK;
@@ -1964,30 +1981,74 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
      break;
 #endif /* CONFIG_SERIAL_TERMIOS */

-#ifdef CONFIG_USART_BREAKS
+#ifdef CONFIG_STM32F7_USART_BREAKS
+#  ifdef CONFIG_STM32F7_SERIALBRK_BSDCOMPAT
    case TIOCSBRK:  /* BSD compatibility: Turn break on, unconditionally */
      {
-        uint32_t cr2;
        irqstate_t flags;
+        uint32_t tx_break;

        flags = enter_critical_section();
-        cr2   = up_serialin(priv, STM32_USART_CR2_OFFSET);
-        up_serialout(priv, STM32_USART_CR2_OFFSET, cr2 | USART_CR2_LINEN);
+
+        /* Disable any further tx activity */
+
+        priv->ie |= USART_CR1_IE_BREAK_INPROGRESS;
+
+        up_txint(dev, false);
+
+        /* Configure TX as a GPIO output pin and Send a break signal*/
+
+        tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK|GPIO_OUTPUT_SET) & priv->tx_gpio);
+        stm32_configgpio(tx_break);
+
        leave_critical_section(flags);
      }
      break;

    case TIOCCBRK:  /* BSD compatibility: Turn break off, unconditionally */
      {
-        uint32_t cr2;
        irqstate_t flags;

        flags = enter_critical_section();
-        cr2   = up_serialin(priv, STM32_USART_CR2_OFFSET);
-        up_serialout(priv, STM32_USART_CR2_OFFSET, cr2 & ~USART_CR2_LINEN);
+
+        /* Configure TX back to U(S)ART */
+
+        stm32_configgpio(priv->tx_gpio);
+
+        priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS;
+
+        /* Enable further tx activity */
+
+        up_txint(dev, true);
+
        leave_critical_section(flags);
      }
      break;
+#  else
+    case TIOCSBRK:  /* No BSD compatibility: Turn break on for M bit times */
+      {
+        uint32_t cr1;
+        irqstate_t flags;
+
+        flags = enter_critical_section();
+        cr1   = up_serialin(priv, STM32_USART_CR1_OFFSET);
+        up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK);
+        leave_critical_section(flags);
+      }
+      break;
+
+    case TIOCCBRK:  /* No BSD compatibility: May turn off break too soon */
+      {
+        uint32_t cr1;
+        irqstate_t flags;
+
+        flags = enter_critical_section();
+        cr1   = up_serialin(priv, STM32_USART_CR1_OFFSET);
+        up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK);
+        leave_critical_section(flags);
+      }
+      break;
+#  endif
 #endif

    default:
@@ -2400,6 +2461,13 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
        }
 #  endif

+#  ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
+      if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
+        {
+          return;
+        }
+#  endif
+
      up_restoreusartint(priv, ie);

      /* Fake a TX interrupt here by just calling uart_xmitchars() with
@@ -782,7 +782,27 @@ config STM32L4_FLOWCONTROL_BROKEN
 		nRTS after every byte received)  Enable this setting workaround
 		this issue by useing software based management of RTS

-endmenu
+config STM32L4_USART_BREAKS
+	bool "Add TIOxSBRK to support sending Breaks"
+	depends on STM32_USART
+	default n
+	---help---
+		Add TIOCxBRK routines to send a line break per the STM32 manual, the
+		break will be a pulse based on the value M. This is not a BSD compatible
+		break.
+
+config STM32L4_SERIALBRK_BSDCOMPAT
+	bool "Use GPIO To send Break"
+	depends on STM32_USART && STM32_USART_BREAKS
+	default n
+	---help---
+		Enable using GPIO on the TX pin to send a BSD compatible break:
+		TIOCSBRK will start the break and TIOCCBRK will end the break.
+		The current STM32 U[S]ARTS have no way to leave the break (TX=LOW)
+		on because the SW starts the break and then the HW automatically clears
+		the break. This makes it is difficult to sent a long break.
+
+endmenu # U[S]ART Configuration

 menu "SPI Configuration"
 	depends on STM32L4_SPI
@@ -208,6 +208,22 @@
 #  define PM_IDLE_DOMAIN             0 /* Revisit */
 #endif

+/* Keep track if a Break was set
+ *
+ * Note:
+ *
+ * 1) This value is set in the priv->ie but never written to the control
+ *    register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE
+ * 2) USART_CR3_EIE is also carried in the up_dev_s ie member.
+ *
+ * See up_restoreusartint where the masking is done.
+ */
+
+#ifdef CONFIG_STM32L4_SERIALBRK_BSDCOMPAT
+#  define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
+#  define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
+#endif
+
 #ifdef USE_SERIALDRIVER
 #ifdef HAVE_UART

@@ -1560,11 +1576,12 @@ static int up_interrupt_common(struct up_dev_s *priv)

 static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
 {
-#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT)
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \
+    || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT)
  struct inode      *inode = filep->f_inode;
  struct uart_dev_s *dev   = inode->i_private;
 #endif
-#ifdef CONFIG_SERIAL_TERMIOS
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT)
  struct up_dev_s   *priv  = (struct up_dev_s *)dev->priv;
 #endif
  int                ret    = OK;
@@ -1720,30 +1737,74 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
      break;
 #endif /* CONFIG_SERIAL_TERMIOS */

-#ifdef CONFIG_USART_BREAKS
+#ifdef CONFIG_STM32L4_USART_BREAKS
+#  ifdef CONFIG_STM32L4_SERIALBRK_BSDCOMPAT
    case TIOCSBRK:  /* BSD compatibility: Turn break on, unconditionally */
      {
-        uint32_t cr2;
        irqstate_t flags;
+        uint32_t tx_break;

        flags = enter_critical_section();
-        cr2   = up_serialin(priv, STM32L4_USART_CR2_OFFSET);
-        up_serialout(priv, STM32L4_USART_CR2_OFFSET, cr2 | USART_CR2_LINEN);
+
+        /* Disable any further tx activity */
+
+        priv->ie |= USART_CR1_IE_BREAK_INPROGRESS;
+
+        up_txint(dev, false);
+
+        /* Configure TX as a GPIO output pin and Send a break signal*/
+
+        tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK|GPIO_OUTPUT_SET) & priv->tx_gpio);
+        stm32_configgpio(tx_break);
+
        leave_critical_section(flags);
      }
      break;

    case TIOCCBRK:  /* BSD compatibility: Turn break off, unconditionally */
      {
-        uint32_t cr2;
        irqstate_t flags;

        flags = enter_critical_section();
-        cr2   = up_serialin(priv, STM32L4_USART_CR2_OFFSET);
-        up_serialout(priv, STM32L4_USART_CR2_OFFSET, cr2 & ~USART_CR2_LINEN);
+
+        /* Configure TX back to U(S)ART */
+
+        stm32_configgpio(priv->tx_gpio);
+
+        priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS;
+
+        /* Enable further tx activity */
+
+        up_txint(dev, true);
+
        leave_critical_section(flags);
      }
      break;
+#  else
+    case TIOCSBRK:  /* No BSD compatibility: Turn break on for M bit times */
+      {
+        uint32_t cr1;
+        irqstate_t flags;
+
+        flags = enter_critical_section();
+        cr1   = up_serialin(priv, STM32_USART_CR1_OFFSET);
+        up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK);
+        leave_critical_section(flags);
+      }
+      break;
+
+    case TIOCCBRK:  /* No BSD compatibility: May turn off break too soon */
+      {
+        uint32_t cr1;
+        irqstate_t flags;
+
+        flags = enter_critical_section();
+        cr1   = up_serialin(priv, STM32_USART_CR1_OFFSET);
+        up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK);
+        leave_critical_section(flags);
+      }
+      break;
+#  endif
 #endif

    default:
@@ -2133,6 +2194,13 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
        }
 #  endif

+#  ifdef CONFIG_STM32L4_SERIALBRK_BSDCOMPAT
+      if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
+        {
+          return;
+        }
+#  endif
+
      up_restoreusartint(priv, ie);

      /* Fake a TX interrupt here by just calling uart_xmitchars() with
@@ -1,7 +1,7 @@
 ############################################################################
 # arch/avr/src/Makefile
 #
-#   Copyright (C) 2010-2012, 2014 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2010-2012, 2014, 2016 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -83,6 +83,11 @@ COBJS = $(CSRCS:.c=$(OBJEXT))
 SRCS = $(ASRCS) $(CSRCS)
 OBJS = $(AOBJS) $(COBJS)

+# Override in Make.defs if linker is not 'ld'
+
+LDSTARTGROUP ?= --start-group
+LDENDGROUP ?= --end-group
+
 LDFLAGS += $(ARCHSCRIPT)
 EXTRA_LIBS ?=
 LINKLIBS ?=
@@ -139,7 +144,7 @@ board/libboard$(LIBEXT):
 nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT)
 	@echo "LD: nuttx"
 	$(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) -o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \
-		--start-group $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) --end-group
+		$(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) $(LDENDGROUP)
 ifneq ($(CONFIG_WINDOWS_NATIVE),y)
 	$(Q) $(NM) $(NUTTX) | \
 	grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
@@ -134,7 +134,6 @@ extern uint32_t _ebss;            /* End+1 of .bss */

 /* Defined in files with the same name as the function */

-void up_boot(void);
 void up_irqinitialize(void);
 #ifdef CONFIG_ARCH_DMA
 void weak_function up_dmainitialize(void);
@@ -1,7 +1,7 @@
 ############################################################################
 # arch/hc/src/Makefile
 #
-#   Copyright (C) 2009, 2011-2012, 2014 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2009, 2011-2012, 2014, 2016 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -83,6 +83,11 @@ COBJS = $(CSRCS:.c=$(OBJEXT))
 SRCS = $(ASRCS) $(CSRCS)
 OBJS = $(AOBJS) $(COBJS)

+# Override in Make.defs if linker is not 'ld'
+
+LDSTARTGROUP ?= --start-group
+LDENDGROUP ?= --end-group
+
 LDFLAGS += $(ARCHSCRIPT)
 EXTRA_LIBS ?=
 LINKLIBS ?=
@@ -138,7 +143,7 @@ board/libboard$(LIBEXT):
 nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT)
 	$(Q) echo "LD: nuttx"
 	$(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) -o $(NUTTX)$(EXEEXT) $(HEAD_OBJ) \
-		--start-group $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) --end-group
+		$(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) $(LDENDGROUP)
 ifneq ($(CONFIG_WINDOWS_NATIVE),y)
 	$(Q) $(NM) $(NUTTX)$(EXEEXT) | \
 	grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
@@ -157,10 +157,6 @@ extern uint32_t g_intstackbase;
 * Public Functions
 ****************************************************************************/

-/* Start-up functions */
-
-void up_boot(void);
-
 /* Context switching functions */

 void up_copystate(uint8_t *dest, uint8_t *src);
@@ -1,7 +1,7 @@
 ############################################################################
 # arch/mips/src/Makefile
 #
-#   Copyright (C) 2011-2012, 2014 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2011-2012, 2014, 2016 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -80,6 +80,11 @@ COBJS = $(CSRCS:.c=$(OBJEXT))
 SRCS = $(ASRCS) $(CSRCS)
 OBJS = $(AOBJS) $(COBJS)

+# Override in Make.defs if linker is not 'ld'
+
+LDSTARTGROUP ?= --start-group
+LDENDGROUP ?= --end-group
+
 LDFLAGS += $(ARCHSCRIPT)
 EXTRA_LIBS ?=
 LINKLIBS ?=
@@ -136,7 +141,7 @@ board/libboard$(LIBEXT):
 nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT)
 	@echo "LD: nuttx"
 	$(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) -o $(NUTTX)$(EXEEXT) $(HEAD_OBJ) $(EXTRA_OBJS) \
-		--start-group $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) --end-group
+		$(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) $(LDENDGROUP)
 ifneq ($(CONFIG_WINDOWS_NATIVE),y)
 	$(Q) $(NM) $(NUTTX)$(EXEEXT) | \
 	grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
@@ -234,7 +234,7 @@ void pic32mx_uartconfigure(uintptr_t uart_base, uint32_t baudrate,
 *
 * Description:
 *   This function must be provided by the board-specific logic in the  directory
- *   configs/<board-name>/up_boot.c.
+ *   configs/<board-name>/pic32_boot.c.
 *
 ************************************************************************************/

@@ -1,7 +1,7 @@
 ############################################################################
 # arch/rgmp/src/Makefile
 #
-#   Copyright (C) 2011-2012, 2014 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2011-2012, 2014, 2016 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -39,25 +39,30 @@ include $(CONFIG_RGMP_SUBARCH)/Make.defs
 RGMP_ARCH_ASRCS := $(addprefix $(CONFIG_RGMP_SUBARCH)/,$(RGMP_ARCH_ASRCS))
 RGMP_ARCH_CSRCS := $(addprefix $(CONFIG_RGMP_SUBARCH)/,$(RGMP_ARCH_CSRCS))

-CPPFLAGS	+= -I$(TOPDIR)/sched -I$(TOPDIR)/fs $(EXTRADEFINES)
-CFLAGS		+= -I$(TOPDIR)/sched -I$(TOPDIR)/fs $(EXTRADEFINES)
-CXXFLAGS	+= -I$(TOPDIR)/sched -I$(TOPDIR)/fs $(EXTRADEFINES)
+CPPFLAGS += -I$(TOPDIR)/sched -I$(TOPDIR)/fs $(EXTRADEFINES)
+CFLAGS += -I$(TOPDIR)/sched -I$(TOPDIR)/fs $(EXTRADEFINES)
+CXXFLAGS += -I$(TOPDIR)/sched -I$(TOPDIR)/fs $(EXTRADEFINES)

-ASRCS		= $(RGMP_ARCH_ASRCS)
-CSRCS		= nuttx.c cxx.c $(RGMP_ARCH_CSRCS)
-AOBJS		= $(ASRCS:.S=$(OBJEXT))
-COBJS		= $(CSRCS:.c=$(OBJEXT))
+ASRCS = $(RGMP_ARCH_ASRCS)
+CSRCS = nuttx.c cxx.c $(RGMP_ARCH_CSRCS)
+AOBJS = $(ASRCS:.S=$(OBJEXT))
+COBJS = $(CSRCS:.c=$(OBJEXT))

-SRCS		= $(ASRCS) $(CSRCS)
-OBJS		= $(AOBJS) $(COBJS)
+SRCS = $(ASRCS) $(CSRCS)
+OBJS = $(AOBJS) $(COBJS)

-LINKSRCS    = rgmp.c bridge.c
-LINKOBJS    = $(LINKSRCS:.c=$(OBJEXT))
+LINKSRCS = rgmp.c bridge.c
+LINKOBJS = $(LINKSRCS:.c=$(OBJEXT))

-LDFLAGS		+= -T$(RGMPLKSCPT)
-LDLIBS		= $(patsubst %.a,%,$(patsubst lib%,-l%,$(LINKLIBS)))
-LIBPATHS		+= -L"$(TOPDIR)/lib" -L$(RGMPLIBDIR)
-LDLIBS		+= -lrgmp $(shell "$(CC)" -print-libgcc-file-name)
+# Override in Make.defs if linker is not 'ld'
+
+LDSTARTGROUP ?= --start-group
+LDENDGROUP ?= --end-group
+
+LDFLAGS += -T$(RGMPLKSCPT)
+LDLIBS = $(patsubst %.a,%,$(patsubst lib%,-l%,$(LINKLIBS)))
+LIBPATHS += -L"$(TOPDIR)/lib" -L$(RGMPLIBDIR)
+LDLIBS += -lrgmp $(shell "$(CC)" -print-libgcc-file-name)

 all: libarch$(LIBEXT)

@@ -79,7 +84,7 @@ libarch$(LIBEXT): $(OBJS)

 nuttx$(EXEEXT): $(LINKOBJS)
 	@echo "LD:  nuttx$(EXEEXT)"
-	@$(LD) $(LDFLAGS) $(LIBPATHS) $(LINKOBJS) --start-group $(LDLIBS) $(EXTRA_LIBS) --end-group -o $(TOPDIR)/$@
+	@$(LD) $(LDFLAGS) $(LIBPATHS) $(LINKOBJS) $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) -o $(TOPDIR)/$@
 	@$(OBJDUMP) -S $(TOPDIR)/$@ > $(TOPDIR)/nuttx.asm
 	@$(NM) -n $(TOPDIR)/$@ > $(TOPDIR)/nuttx.sym
 	@$(OBJCOPY) -S -O binary $(TOPDIR)/$@ nuttx.img
--- a/Show More
+++ b/Show More