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Merged in petekol/arch (pull request #30)

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This commit is contained in:
Gregory Nutt
2015-11-11 07:03:11 -06:00
parent 45549cb2e2 3e33d18cac
commit 657b4f7d71
10 changed files with 990 additions and 229 deletions
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arch/arm/include/lpc43xx/chip.h
+2 -2
View File
@@ -46,7 +46,7 @@
* Pre-processor Definitions
************************************************************************************/
/* Per the data sheet: LPC4350/30/20/10 Rev. 3.2 — 4 June 2012 */
/* Per the data sheet: LPC4350/30/20/10 Rev. 3.2 — 4 June 2012 */
/* Get customizations for each supported chip.
*
* SRAM Resources
@@ -74,7 +74,7 @@
* manager. This gives some symmetry to all of the members of the family.
*/
/* Per the user manual: UM10503, Rev. 1.2 — 8 June 2012 */
/* Per the user manual: UM10503, Rev. 1.2 — 8 June 2012 */
/* Get customizations for each supported chip.
*
* SRAM Resources
arch/arm/src/lpc43xx/Make.defs
+4 -2
View File
@@ -96,6 +96,8 @@ CHIP_CSRCS += lpc43_start.c lpc43_uart.c
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += lpc43_timerisr.c
else
CHIP_CSRCS += lpc43_tickless_rit.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
@@ -131,10 +133,10 @@ CHIP_CSRCS += lpc43_spifi.c
endif
ifeq ($(CONFIG_LPC43_SSP0),y)
CHIP_CSRCS += lpc43_ssp.c
CHIP_CSRCS += lpc43_ssp.c lpc43_spi.c
else
ifeq ($(CONFIG_LPC43_SSP1),y)
CHIP_CSRCS += lpc43_ssp.c
CHIP_CSRCS += lpc43_ssp.c lpc43_spi.c
endif
endif
arch/arm/src/lpc43xx/chip/lpc43_rit.h
-1
View File
@@ -42,7 +42,6 @@
************************************************************************************/
#include <nuttx/config.h>
#include "chip/lpc4310203050_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
arch/arm/src/lpc43xx/chip/lpc43_timer.h
+68 -68
View File
@@ -68,77 +68,77 @@
/* Register addresses ***************************************************************/
#define LPC43_TMR0_IR (LPC43_TMR0_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR0_TCR (LPC43_TMR0_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR0_TC (LPC43_TMR0_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR0_PR (LPC43_TMR0_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR0_PC (LPC43_TMR0_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR0_MCR (LPC43_TMR0_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR0_MR0 (LPC43_TMR0_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR0_MR1 (LPC43_TMR0_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR0_MR2 (LPC43_TMR0_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR0_MR3 (LPC43_TMR0_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR0_CCR (LPC43_TMR0_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR0_CR0 (LPC43_TMR0_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR0_CR1 (LPC43_TMR0_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR0_CR2 (LPC43_TMR0_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR0_CR3 (LPC43_TMR0_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR0_EMR (LPC43_TMR0_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR0_CTCR (LPC43_TMR0_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR0_IR (LPC43_TIMER0_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR0_TCR (LPC43_TIMER0_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR0_TC (LPC43_TIMER0_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR0_PR (LPC43_TIMER0_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR0_PC (LPC43_TIMER0_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR0_MCR (LPC43_TIMER0_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR0_MR0 (LPC43_TIMER0_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR0_MR1 (LPC43_TIMER0_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR0_MR2 (LPC43_TIMER0_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR0_MR3 (LPC43_TIMER0_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR0_CCR (LPC43_TIMER0_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR0_CR0 (LPC43_TIMER0_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR0_CR1 (LPC43_TIMER0_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR0_CR2 (LPC43_TIMER0_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR0_CR3 (LPC43_TIMER0_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR0_EMR (LPC43_TIMER0_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR0_CTCR (LPC43_TIMER0_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR1_IR (LPC43_TMR1_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR1_TCR (LPC43_TMR1_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR1_TC (LPC43_TMR1_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR1_PR (LPC43_TMR1_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR1_PC (LPC43_TMR1_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR1_MCR (LPC43_TMR1_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR1_MR0 (LPC43_TMR1_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR1_MR1 (LPC43_TMR1_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR1_MR2 (LPC43_TMR1_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR1_MR3 (LPC43_TMR1_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR1_CCR (LPC43_TMR1_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR1_CR0 (LPC43_TMR1_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR1_CR1 (LPC43_TMR1_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR1_CR2 (LPC43_TMR1_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR1_CR3 (LPC43_TMR1_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR1_EMR (LPC43_TMR1_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR1_CTCR (LPC43_TMR1_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR1_IR (LPC43_TIMER1_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR1_TCR (LPC43_TIMER1_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR1_TC (LPC43_TIMER1_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR1_PR (LPC43_TIMER1_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR1_PC (LPC43_TIMER1_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR1_MCR (LPC43_TIMER1_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR1_MR0 (LPC43_TIMER1_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR1_MR1 (LPC43_TIMER1_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR1_MR2 (LPC43_TIMER1_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR1_MR3 (LPC43_TIMER1_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR1_CCR (LPC43_TIMER1_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR1_CR0 (LPC43_TIMER1_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR1_CR1 (LPC43_TIMER1_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR1_CR2 (LPC43_TIMER1_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR1_CR3 (LPC43_TIMER1_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR1_EMR (LPC43_TIMER1_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR1_CTCR (LPC43_TIMER1_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR2_IR (LPC43_TMR2_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR2_TCR (LPC43_TMR2_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR2_TC (LPC43_TMR2_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR2_PR (LPC43_TMR2_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR2_PC (LPC43_TMR2_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR2_MCR (LPC43_TMR2_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR2_MR0 (LPC43_TMR2_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR2_MR1 (LPC43_TMR2_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR2_MR2 (LPC43_TMR2_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR2_MR3 (LPC43_TMR2_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR2_CCR (LPC43_TMR2_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR2_CR0 (LPC43_TMR2_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR2_CR1 (LPC43_TMR2_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR2_CR2 (LPC43_TMR2_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR2_CR3 (LPC43_TMR2_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR2_EMR (LPC43_TMR2_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR2_CTCR (LPC43_TMR2_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR2_IR (LPC43_TIMER2_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR2_TCR (LPC43_TIMER2_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR2_TC (LPC43_TIMER2_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR2_PR (LPC43_TIMER2_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR2_PC (LPC43_TIMER2_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR2_MCR (LPC43_TIMER2_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR2_MR0 (LPC43_TIMER2_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR2_MR1 (LPC43_TIMER2_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR2_MR2 (LPC43_TIMER2_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR2_MR3 (LPC43_TIMER2_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR2_CCR (LPC43_TIMER2_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR2_CR0 (LPC43_TIMER2_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR2_CR1 (LPC43_TIMER2_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR2_CR2 (LPC43_TIMER2_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR2_CR3 (LPC43_TIMER2_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR2_EMR (LPC43_TIMER2_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR2_CTCR (LPC43_TIMER2_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR3_IR (LPC43_TMR3_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR3_TCR (LPC43_TMR3_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR3_TC (LPC43_TMR3_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR3_PR (LPC43_TMR3_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR3_PC (LPC43_TMR3_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR3_MCR (LPC43_TMR3_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR3_MR0 (LPC43_TMR3_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR3_MR1 (LPC43_TMR3_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR3_MR2 (LPC43_TMR3_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR3_MR3 (LPC43_TMR3_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR3_CCR (LPC43_TMR3_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR3_CR0 (LPC43_TMR3_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR3_CR1 (LPC43_TMR3_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR3_CR2 (LPC43_TMR3_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR3_CR3 (LPC43_TMR3_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR3_EMR (LPC43_TMR3_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR3_CTCR (LPC43_TMR3_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR3_IR (LPC43_TIMER3_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR3_TCR (LPC43_TIMER3_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR3_TC (LPC43_TIMER3_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR3_PR (LPC43_TIMER3_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR3_PC (LPC43_TIMER3_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR3_MCR (LPC43_TIMER3_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR3_MR0 (LPC43_TIMER3_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR3_MR1 (LPC43_TIMER3_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR3_MR2 (LPC43_TIMER3_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR3_MR3 (LPC43_TIMER3_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR3_CCR (LPC43_TIMER3_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR3_CR0 (LPC43_TIMER3_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR3_CR1 (LPC43_TIMER3_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR3_CR2 (LPC43_TIMER3_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR3_CR3 (LPC43_TIMER3_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR3_EMR (LPC43_TIMER3_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR3_CTCR (LPC43_TIMER3_BASE+LPC43_TMR_CTCR_OFFSET)
/* Register bit definitions *********************************************************/
/* Registers holding 32-bit numeric values (no bit field definitions):
arch/arm/src/lpc43xx/lpc43_cgu.c
+1 -1
View File
@@ -461,7 +461,7 @@ void lpc43_pll0usbenable(void)
* operation and will make the lock signal high once it has regained
* lock on the input clock
*
* Wait for PLL1 to report that it is locked.
* Wait for PLL0 to report that it is locked.
*/
while ((getreg32(LPC43_PLL0USB_STAT) & PLL0USB_STAT_LOCK) == 0);
arch/arm/src/lpc43xx/lpc43_i2c.c
+5 -6
View File
@@ -206,8 +206,7 @@ static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits)
DEBUGASSERT(dev != NULL);
DEBUGASSERT(nbits == 7);
priv->msg.addr = addr << 1;
priv->msg.flags = 0 ;
priv->msg.addr = addr;
return OK;
}
@@ -231,7 +230,7 @@ static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer,
priv->wrcnt = 0;
priv->rdcnt = 0;
priv->msg.addr &= ~0x01;
priv->msg.flags = 0;
priv->msg.buffer = (uint8_t *)buffer;
priv->msg.length = buflen;
@@ -264,7 +263,7 @@ static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen)
priv->wrcnt = 0;
priv->rdcnt = 0;
priv->msg.addr |= 0x01;
priv->msg.flags = I2C_M_READ;
priv->msg.buffer = buffer;
priv->msg.length = buflen;
@@ -364,7 +363,7 @@ static int i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, i
priv->msgs = msgs;
priv->nmsg = count;
ret = count - i2c_start(priv);
ret = i2c_start(priv);
return ret;
}
@@ -428,7 +427,7 @@ static int i2c_interrupt(int irq, FAR void *context)
case 0x08: /* A START condition has been transmitted. */
case 0x10: /* A Repeated START condition has been transmitted. */
putreg32(msg->addr, priv->base + LPC43_I2C_DAT_OFFSET); /* set address */
putreg32(((I2C_M_READ & msg->flags) == I2C_M_READ)?I2C_READADDR8(msg->addr):I2C_WRITEADDR8(msg->addr), priv->base + LPC43_I2C_DAT_OFFSET); /* set address */
putreg32(I2C_CONCLR_STAC, priv->base + LPC43_I2C_CONCLR_OFFSET); /* clear start bit */
break;
arch/arm/src/lpc43xx/lpc43_spi.c
+37
View File
@@ -56,6 +56,7 @@
#include "chip.h"
#include "lpc43_pinconfig.h"
#include "lpc43_spi.h"
#include "lpc43_ssp.h"
#ifdef CONFIG_LPC43_SPI
@@ -583,3 +584,39 @@ FAR struct spi_dev_s *lpc43_spiinitialize(int port)
#endif /* CONFIG_LPC43_SPI */
/****************************************************************************
* Name: up_spiinitialize
*
* Description:
* Initialize the selected SPI port
* 0 - SPI
* 1 - SSP0
* 2 - SSP1
*
* Input Parameter:
* Port number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
* Valid SPI device structure reference on success; a NULL on failure
*
****************************************************************************/
FAR struct spi_dev_s *up_spiinitialize(int port)
{
if (port) {
#if ( defined(CONFIG_LPC43_SSP0) || defined(CONFIG_LPC43_SSP1) )
return lpc43_sspinitialize(port-1);
#else
return NULL;
#endif
} else {
#if defined(CONFIG_LPC43_SPI)
return lpc43_spiinitialize(port);
#else
return NULL;
#endif
}
}
arch/arm/src/lpc43xx/lpc43_ssp.c
+80 -114
View File
@@ -162,8 +162,12 @@ static const struct spi_ops_s g_spi0ops =
.cmddata = lpc43_ssp0cmddata, /* Provided externally */
#endif
.send = ssp_send,
#ifdef CONFIG_SPI_EXCHANGE
.exchange = ssp_exchange,
#else
.sndblock = ssp_sndblock,
.recvblock = ssp_recvblock,
#endif
#ifdef CONFIG_SPI_CALLBACK
.registercallback = lpc43_ssp0register, /* Provided externally */
#else
@@ -197,8 +201,12 @@ static const struct spi_ops_s g_spi1ops =
.cmddata = lpc43_ssp1cmddata, /* Provided externally */
#endif
.send = ssp_send,
#ifdef CONFIG_SPI_EXCHANGE
.exchange = ssp_exchange,
#else
.sndblock = ssp_sndblock,
.recvblock = ssp_recvblock,
#endif
#ifdef CONFIG_SPI_CALLBACK
.registercallback = lpc43_ssp1register, /* Provided externally */
#else
@@ -526,6 +534,76 @@ static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t wd)
return (uint16_t)regval;
}
static void ssp_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
FAR void *rxbuffer, size_t nwords) {
FAR struct lpc43_sspdev_s *priv = (FAR struct lpc43_sspdev_s *)dev;
union
{
FAR uint8_t *p8;
FAR uint16_t *p16;
FAR const void *pv;
} tx;
union
{
FAR uint8_t *p8;
FAR uint16_t *p16;
FAR const void *pv;
} rx;
uint32_t data;
uint32_t datadummy = (priv->nbits > 8)?0xffff:0xff;
uint32_t rxpending = 0;
/* While there is remaining to be sent (and no synchronization error has occurred) */
sspdbg("nwords: %d\n", nwords);
tx.pv = txbuffer;
rx.pv = rxbuffer;
while (nwords || rxpending)
{
/* Write data to the data register while (1) the TX FIFO is
* not full, (2) we have not exceeded the depth of the TX FIFO,
* and (3) there are more bytes to be sent.
*/
spivdbg("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
while ((ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_TNF) &&
(rxpending < LPC43_SSP_FIFOSZ) && nwords)
{
if (txbuffer && priv->nbits > 8)
{
data = (uint32_t)*tx.p16++;
}
else
{
data = (uint32_t)*tx.p8++;
}
ssp_putreg(priv, LPC43_SSP_DR_OFFSET, txbuffer?data:datadummy);
nwords--;
rxpending++;
}
/* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */
spivdbg("RX: rxpending: %d\n", rxpending);
while (ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_RNE)
{
data = ssp_getreg(priv, LPC43_SSP_DR_OFFSET);
if (rxbuffer && priv->nbits > 8)
{
*rx.p16++ = (uint16_t)data;
}
else
{
*rx.p8++ = (uint8_t)data;
}
rxpending--;
}
}
}
/****************************************************************************
* Name: ssp_sndblock
*
@@ -547,72 +625,7 @@ static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t wd)
static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
{
FAR struct lpc43_sspdev_s *priv = (FAR struct lpc43_sspdev_s *)dev;
union
{
FAR const uint8_t *p8;
FAR const uint16_t *p16;
FAR const void *pv;
} u;
uint32_t data;
uint32_t sr;
/* Loop while thre are bytes remaining to be sent */
sspdbg("nwords: %d\n", nwords);
u.pv = buffer;
while (nwords > 0)
{
/* While the TX FIFO is not full and there are bytes left to send */
while ((ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_TNF) && nwords)
{
/* Fetch the data to send */
if (priv->nbits > 8)
{
data = (uint32_t)*u.p16++;
}
else
{
data = (uint32_t)*u.p8++;
}
/* Send the data */
ssp_putreg(priv, LPC43_SSP_DR_OFFSET, data);
nwords--;
}
}
/* Then discard all card responses until the RX & TX FIFOs are emptied. */
sspdbg("discarding\n");
do
{
/* Is there anything in the RX fifo? */
sr = ssp_getreg(priv, LPC43_SSP_SR_OFFSET);
if ((sr & SSP_SR_RNE) != 0)
{
/* Yes.. Read and discard */
(void)ssp_getreg(priv, LPC43_SSP_DR_OFFSET);
}
/* There is a race condition where TFE may go true just before
* RNE goes true and this loop terminates prematurely. The nasty little
* delay in the following solves that (it could probably be tuned
* to improve performance).
*/
else if ((sr & SSP_SR_TFE) != 0)
{
up_udelay(100);
sr = ssp_getreg(priv, LPC43_SSP_SR_OFFSET);
}
}
while ((sr & SSP_SR_RNE) != 0 || (sr & SSP_SR_TFE) == 0);
return ssp_exchange(dev, buffer, NULL, nwords);
}
/****************************************************************************
@@ -636,54 +649,7 @@ static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
{
FAR struct lpc43_sspdev_s *priv = (FAR struct lpc43_sspdev_s *)dev;
union
{
FAR uint8_t *p8;
FAR uint16_t *p16;
FAR void *pv;
} u;
uint32_t data;
uint32_t rxpending = 0;
/* While there is remaining to be sent (and no synchronization error has occurred) */
sspdbg("nwords: %d\n", nwords);
u.pv = buffer;
while (nwords || rxpending)
{
/* Fill the transmit FIFO with 0xffff...
* Write 0xff to the data register while (1) the TX FIFO is
* not full, (2) we have not exceeded the depth of the TX FIFO,
* and (3) there are more bytes to be sent.
*/
spivdbg("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
while ((ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_TNF) &&
(rxpending < LPC43_SSP_FIFOSZ) && nwords)
{
ssp_putreg(priv, LPC43_SSP_DR_OFFSET, 0xffff);
nwords--;
rxpending++;
}
/* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */
spivdbg("RX: rxpending: %d\n", rxpending);
while (ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_RNE)
{
data = (uint8_t)ssp_getreg(priv, LPC43_SSP_DR_OFFSET);
if (priv->nbits > 8)
{
*u.p16++ = (uint16_t)data;
}
else
{
*u.p8++ = (uint8_t)data;
}
rxpending--;
}
}
return ssp_exchange(dev, NULL, buffer, nwords);
}
/****************************************************************************
arch/arm/src/lpc43xx/lpc43_tickless_rit.c
+773
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/lpc43xx/lpc43_usb0dev.c
+20 -35
View File
@@ -1079,9 +1079,8 @@ static void lpc43_usbreset(struct lpc43_usbdev_s *priv)
{
int epphy;
/* Disable all endpoints */
/* Disable all endpoints. Control endpoint 0 is always enabled */
lpc43_clrbits (USBDEV_ENDPTCTRL_RXE | USBDEV_ENDPTCTRL_TXE, LPC43_USBDEV_ENDPTCTRL0);
lpc43_clrbits (USBDEV_ENDPTCTRL_RXE | USBDEV_ENDPTCTRL_TXE, LPC43_USBDEV_ENDPTCTRL1);
lpc43_clrbits (USBDEV_ENDPTCTRL_RXE | USBDEV_ENDPTCTRL_TXE, LPC43_USBDEV_ENDPTCTRL2);
lpc43_clrbits (USBDEV_ENDPTCTRL_RXE | USBDEV_ENDPTCTRL_TXE, LPC43_USBDEV_ENDPTCTRL3);
@@ -2584,12 +2583,9 @@ void up_usbinitialize(void)
struct lpc43_usbdev_s *priv = &g_usbdev;
int i;
uint32_t regval;
irqstate_t flags;
usbtrace(TRACE_DEVINIT, 0);
/* Disable USB interrupts */
lpc43_putreg(0, LPC43_USBDEV_USBINTR);
flags = irqsave();
/* Initialize the device state structure */
@@ -2647,10 +2643,15 @@ void up_usbinitialize(void)
}
}
/* Enable PLL0 clock */
lpc43_pll0usbconfig();
lpc43_pll0usbenable();
/* Clock */
regval = getreg32(LPC43_BASE_USB0_CLK);
regval &= ~BASE_USB0_CLK_CLKSEL_MASK;
regval &= ~(BASE_USB0_CLK_CLKSEL_MASK | BASE_USB0_CLK_PD) ;
regval |= (BASE_USB0_CLKSEL_PLL0USB | BASE_USB0_CLK_AUTOBLOCK);
putreg32(regval, LPC43_BASE_USB0_CLK);
@@ -2660,20 +2661,11 @@ void up_usbinitialize(void)
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU1_M4_USB0_CFG);
/* Enable PLL0 clock */
//lpc43_putreg(RGU_CTRL0_USB0_RST, LPC43_RGU_CTRL0); /* Reset USB block */
lpc43_pll0usbconfig();
lpc43_pll0usbenable();
lpc43_pullup(&priv->usbdev, false); /* disconnect device */
/* Reset USB block */
regval = lpc43_getreg(LPC43_RGU_CTRL0);
regval |= RGU_CTRL0_USB0_RST;
lpc43_putreg(regval, LPC43_RGU_CTRL0);
/* Reset the controller */
lpc43_putreg (USBDEV_USBCMD_RST, LPC43_USBDEV_USBCMD);
lpc43_setbits (USBDEV_USBCMD_RST, LPC43_USBDEV_USBCMD); /* Reset the controller */
while (lpc43_getreg (LPC43_USBDEV_USBCMD) & USBDEV_USBCMD_RST)
;
@@ -2683,33 +2675,25 @@ void up_usbinitialize(void)
regval &= ~CREG0_USB0PHY;
putreg32(regval, LPC43_CREG0);
/* Attach USB controller interrupt handler */
if (irq_attach(LPC43M4_IRQ_USB0, lpc43_usbinterrupt) != 0)
{
usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_IRQREGISTRATION),
(uint16_t)LPC43M4_IRQ_USB0);
goto errout;
}
lpc43_putreg(0, LPC43_USBDEV_USBINTR); /* Disable USB interrupts */
/* Program the controller to be the USB device controller */
lpc43_putreg (USBDEV_USBMODE_SDIS | USBDEV_USBMODE_SLOM | USBDEV_USBMODE_CM_DEVICE,
LPC43_USBDEV_USBMODE);
/* Disconnect device */
/* Attach USB controller interrupt handler */
lpc43_pullup(&priv->usbdev, false);
irq_attach(LPC43M4_IRQ_USB0, lpc43_usbinterrupt);
up_enable_irq(LPC43M4_IRQ_USB0);
irqrestore(flags);
/* Reset/Re-initialize the USB hardware */
lpc43_usbreset(priv);
return;
errout:
up_usbuninitialize();
}
/****************************************************************************
@@ -2742,7 +2726,7 @@ void up_usbuninitialize(void)
/* Reset the controller */
lpc43_putreg (USBDEV_USBCMD_RST, LPC43_USBDEV_USBCMD);
lpc43_setbits (USBDEV_USBCMD_RST, LPC43_USBDEV_USBCMD);
while (lpc43_getreg (LPC43_USBDEV_USBCMD) & USBDEV_USBCMD_RST)
;
@@ -2850,3 +2834,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
g_usbdev.driver = NULL;
return OK;
}