mirror of
https://github.com/apache/nuttx.git
synced 2026-05-22 05:42:05 +08:00
BCM2708: Add framework for a Mini-UART driver (incomplete)
This commit is contained in:
Gregory Nutt
@@ -77,3 +77,7 @@ CHIP_CSRCS += bcm_tickless.c bcm_gpio.c bcm_aux.c bcm_lowputc.c bcm_serial.c
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ifeq ($(CONFIG_BCM2708_GPIO_IRQ),y)
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CHIP_CSRCS += bcm_gpioint.c
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endif
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ifeq ($(CONFIG_BCM2708_MINI_UART),y)
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CHIP_CSRCS += bcm_miniuart.c
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endif
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@@ -80,6 +80,12 @@ static const struct uart_config_s g_console_config =
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.parity = BCM_CONSOLE_PARITY, /* 0=none, 1=odd, 2=even */
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.bits = BCM_CONSOLE_BITS, /* Number of bits (5-9) */
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.stopbits2 = BCM_CONSOLE_2STOP, /* true: Configure with 2 stop bits instead of 1 */
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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.iflow = false; /* true: Input flow control enabled */
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#endif
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#ifdef CONFIG_SERIAL_OFLOWCONTROL
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.oflow = false; /* true: Output flow control enabled. */
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#endif
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};
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#endif
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@@ -54,7 +54,6 @@
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* Public Types
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****************************************************************************/
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#ifdef BCM_HAVE_UART
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/* This structure describes the configuration of an UART */
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struct uart_config_s
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@@ -63,8 +62,13 @@ struct uart_config_s
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (5-9) */
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bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
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};
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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bool iflow; /* true: Input flow control enabled */
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#endif
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#ifdef CONFIG_SERIAL_OFLOWCONTROL
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bool oflow; /* true: Output flow control enabled. */
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#endif
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};
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/****************************************************************************
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* Public Function Prototypes
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File diff suppressed because it is too large
Load Diff
@@ -33,15 +33,16 @@
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_BCM_CHIP_BCM_AUX_H
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#define __ARCH_ARM_SRC_BCM_CHIP_BCM_AUX_H
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#ifndef __ARCH_ARM_SRC_BCM2708_CHIP_BCM2708_AUX_H
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#define __ARCH_ARM_SRC_BCM2708_CHIP_BCM2708_AUX_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/bcm2708_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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@@ -103,80 +104,83 @@
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/* UART Register Bit Definitions ****************************************************/
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#define BCM_AUX_IRQ_MU (1 << 0) /* Mini UART IRQ pending */
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#define BCM_AUX_IRQ_SPI1 (1 << 1) /* SPI 1 IRQ pending */
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#define BCM_AUX_IRQ_SPI2 (1 << 2) /* SPI 2 IRQ pending */
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#define BCM_AUX_IRQ_MU (1 << 0) /* Mini UART IRQ pending */
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#define BCM_AUX_IRQ_SPI1 (1 << 1) /* SPI 1 IRQ pending */
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#define BCM_AUX_IRQ_SPI2 (1 << 2) /* SPI 2 IRQ pending */
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#define BCM_AUX_ENB_MU (1 << 0) /* Mini UART Enable */
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#define BCM_AUX_ENB_SPI1 (1 << 1) /* SPI 1 Enable */
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#define BCM_AUX_ENB_SPI2 (1 << 2) /* SPI 2 Enable */
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#define BCM_AUX_ENB_MU (1 << 0) /* Mini UART Enable */
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#define BCM_AUX_ENB_SPI1 (1 << 1) /* SPI 1 Enable */
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#define BCM_AUX_ENB_SPI2 (1 << 2) /* SPI 2 Enable */
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#define BCM_AUX_MU_IO_SHIFT 0 /* LSB 8-bit of baudrate or TXD/RXD */
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#define BCM_AUX_MU_IO_BAUDRATE (0xff << BCM_AUX_MU_IO_SHIFT) /* If DLAB = 1 */
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#define BCM_AUX_MU_IO_TXD (0xff << BCM_AUX_MU_IO_SHIFT) /* If DLAB = 0 */
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#define BCM_AUX_MU_IO_RXD (0xff << BCM_AUX_MU_IO_SHIFT) /* If DLAB = 0 */
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#define BCM_AUX_MU_IO_SHIFT 0 /* LSB 8-bit of baudrate or TXD/RXD */
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#define BCM_AUX_MU_IO_BAUDRATE (0xff << BCM_AUX_MU_IO_SHIFT) /* If DLAB = 1 */
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#define BCM_AUX_MU_IO_TXD (0 << BCM_AUX_MU_IO_SHIFT) /* If DLAB = 0 */
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#define BCM_AUX_MU_IO_RXD (1 << BCM_AUX_MU_IO_SHIFT) /* If DLAB = 0 */
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#define BCM_AUX_MU_IER_SHIFT 0 /* MSB 8-bit of baudrate or IRQTXE/IRQRXE */
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#define BCM_AUX_MU_IER_BAUDRATE (0xff << BCM_AUX_MU_IIR_SHIFT) /* If DLAB = 1 */
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#define BCM_AUX_MU_IER_TXD (1 << 0) /* Enable Transmit Interruption */
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#define BCM_AUX_MU_IER_RXD (1 << 1) /* Enable Receive Interruption */
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#define BCM_AUX_MU_IER_SHIFT 0 /* MSB 8-bit of baudrate or IRQTXE/IRQRXE */
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#define BCM_AUX_MU_IER_BAUDRATE (0xff << BCM_AUX_MU_IER_SHIFT) /* If DLAB = 1 */
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#define BCM_AUX_MU_IER_TXD (1 << 0) /* Enable Transmit Interrupt */
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#define BCM_AUX_MU_IER_RXD (1 << 1) /* Enable Receive Interrupt */
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#define BCM_AUX_MU_IIR_PEND (1 << 0) /* This bit is clear whenever an IRQ is pending */
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#define BCM_AUX_MU_IIR_SHIFT 1 /* On read this register shows the interrupt ID bit */
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# define BCM_AUX_MU_IIR_NONE (0 << BCM_AUX_MU_IIR_SHIFT) /* No ints */
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# define BCM_AUX_MU_IIR_TXEMPTY (1 << BCM_AUX_MU_IIR_SHIFT) /* TX FIFO empty */
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# define BCM_AUX_MU_IIR_RXDATA (2 << BCM_AUX_MU_IIR_SHIFT) /* Data in TX FIFO */
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#define BCM_AUX_MU_IIR_PEND (1 << 0) /* This bit is clear whenever an IRQ is pending */
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#define BCM_AUX_MU_IIR_SHIFT 1 /* On read this register shows the interrupt ID bit */
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#define BCM_AUX_MU_IIR_MASK (3 << BCM_AUX_MU_IIR_SHIFT)
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# define BCM_AUX_MU_IIR_NONE (0 << BCM_AUX_MU_IIR_SHIFT) /* No interrupts */
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# define BCM_AUX_MU_IIR_TXEMPTY (1 << BCM_AUX_MU_IIR_SHIFT) /* TX FIFO empty (read) */
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# define BCM_AUX_MU_IIR_RXDATA (2 << BCM_AUX_MU_IIR_SHIFT) /* Data in RX FIFO (read) */
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# define BCM_AUX_MU_IIR_TXCLEAR (1 << BCM_AUX_MU_IIR_SHIFT) /* Clear RX FIFO (write) */
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# define BCM_AUX_MU_IIR_RXCLEAR (2 << BCM_AUX_MU_IIR_SHIFT) /* Clear TX FIFO (write) */
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#define BCM_AUX_MU_LCR_DATA8BIT (1 << 0) /* 1 = UART 8-bit 0 = UART 7-bit */
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#define BCM_AUX_MU_LCR_BREAK (1 << 6) /* Set UART TX line to low, breaks if at least 12 bits times */
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#define BCM_AUX_MU_LCR_DLAB (1 << 7) /* If set access Baudrate register */
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#define BCM_AUX_MU_LCR_DATA8BIT (1 << 0) /* 1 = UART 8-bit 0 = UART 7-bit */
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#define BCM_AUX_MU_LCR_BREAK (1 << 6) /* Set UART TX line to low, breaks if at least 12 bits times */
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#define BCM_AUX_MU_LCR_DLAB (1 << 7) /* If set access Baudrate register */
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#define BCM_AUX_MU_MCR_RTS (1 << 1) /* if set RTS line is low */
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#define BCM_AUX_MU_MCR_RTS (1 << 1) /* if set RTS line is low */
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#define BCM_AUX_MU_LSR_DTREADY (1 << 0) /* This bit is set if FIFO has data */
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#define BCM_AUX_MU_LSR_RXOVR (1 << 1) /* Receiver Overrun */
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#define BCM_AUX_MU_LSR_TXEMPTY (1 << 5) /* TX FIFO can accept at least 1 byte */
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#define BCM_AUX_MU_LSR_TXIDLE (1 << 6) /* TX FIFO empty and transmitter idle */
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#define BCM_AUX_MU_LSR_DTREADY (1 << 0) /* This bit is set if FIFO has data */
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#define BCM_AUX_MU_LSR_RXOVR (1 << 1) /* Receiver Overrun */
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#define BCM_AUX_MU_LSR_TXEMPTY (1 << 5) /* TX FIFO can accept at least 1 byte */
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#define BCM_AUX_MU_LSR_TXIDLE (1 << 6) /* TX FIFO empty and transmitter idle */
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#define BCM_AUX_MU_MSR_CTS (1 << 5) /* Holds the inverse of UART CTS status */
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#define BCM_AUX_MU_MSR_CTS (1 << 5) /* Holds the inverse of UART CTS status */
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#define BCM_AUX_MU_CNTL_RXEN (1 << 0) /* Receiver Enable */
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#define BCM_AUX_MU_CNTL_TXEN (1 << 1) /* Transmitter Enable */
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#define BCM_AUX_MU_CNTL_RXAUTOFLOW (1 << 2) /* Enable RXD Auto-flow using RTS */
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#define BCM_AUX_MU_CNTL_TXAUTOFLOW (1 << 3) /* Enable TXD Auto-flow using CTS */
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#define BCM_AUX_MU_CNTL_RTSLEVEL_SHIFT 4 /* RX FIFO level to deassert RTS */
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#define BCM_AUX_MU_CNTL_RXEN (1 << 0) /* Receiver Enable */
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#define BCM_AUX_MU_CNTL_TXEN (1 << 1) /* Transmitter Enable */
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#define BCM_AUX_MU_CNTL_RXAUTOFLOW (1 << 2) /* Enable RXD Auto-flow using RTS */
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#define BCM_AUX_MU_CNTL_TXAUTOFLOW (1 << 3) /* Enable TXD Auto-flow using CTS */
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#define BCM_AUX_MU_CNTL_RTSLEVEL_SHIFT 4 /* RX FIFO level to deassert RTS */
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#define BCM_AUX_MU_CNTL_RTSLEVEL_MASK (3 << BCM_AUX_MU_CNTL_RTSLEVEL_SHIFT)
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# define BCM_AUX_MU_CNTL_RTSLEVEL_3 (0 << BCM_AUX_MU_CNTL_RTSLEVEL_SHIFT)
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# define BCM_AUX_MU_CNTL_RTSLEVEL_2 (1 << BCM_AUX_MU_CNTL_RTSLEVEL_SHIFT)
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# define BCM_AUX_MU_CNTL_RTSLEVEL_1 (2 << BCM_AUX_MU_CNTL_RTSLEVEL_SHIFT)
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# define BCM_AUX_MU_CNTL_RTSLEVEL_4 (3 << BCM_AUX_MU_CNTL_RTSLEVEL_SHIFT)
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#define BCM_AUX_MU_CNTL_RTS_ASSERT (1 << 6) /* Invert RTS auto-flow polarity */
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#define BCM_AUX_MU_CNTL_CTS_ASSERT (1 << 7) /* Invert CTS auto-flow polarity */
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#define BCM_AUX_MU_CNTL_RTS_ASSERT (1 << 6) /* Invert RTS auto-flow polarity */
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#define BCM_AUX_MU_CNTL_CTS_ASSERT (1 << 7) /* Invert CTS auto-flow polarity */
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#define BCM_AUX_MU_STAT_SYM_AVAIL (1 << 0) /* There is at least one symbol in the RX FIFO */
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#define BCM_AUX_MU_STAT_SPC_AVAIL (1 << 1) /* There is at least one free position in the TX FIFO */
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#define BCM_AUX_MU_STAT_RX_IDLE (1 << 2) /* The RX is Idle */
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#define BCM_AUX_MU_STAT_TX_IDLE (1 << 3) /* The TX is Idle */
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#define BCM_AUX_MU_STAT_RX_OVR (1 << 4) /* Receiver overrun */
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#define BCM_AUX_MU_STAT_TX_FULL (1 << 5) /* This is the inverse of bit 1 */
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#define BCM_AUX_MU_STAT_RTS_STAT (1 << 6) /* Status of RTS line */
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#define BCM_AUX_MU_STAT_CTS_STAT (1 << 7) /* Status of CTS line */
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#define BCM_AUX_MU_STAT_TX_EMPTY (1 << 8) /* TX FIFO is Empty */
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#define BCM_AUX_MU_STAT_TX_DONE (1 << 9) /* TX is Idle and FIFO is Empty */
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#define BCM_AUX_MU_STAT_RX_LEVEL_SHIFT 16 /* Bits 19-16: how many symbols in RX FIFO */
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#define BCM_AUX_MU_STAT_SYM_AVAIL (1 << 0) /* There is at least one symbol in the RX FIFO */
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#define BCM_AUX_MU_STAT_SPC_AVAIL (1 << 1) /* There is at least one free position in the TX FIFO */
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#define BCM_AUX_MU_STAT_RX_IDLE (1 << 2) /* The RX is Idle */
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#define BCM_AUX_MU_STAT_TX_IDLE (1 << 3) /* The TX is Idle */
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#define BCM_AUX_MU_STAT_RX_OVR (1 << 4) /* Receiver overrun */
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#define BCM_AUX_MU_STAT_TX_FULL (1 << 5) /* This is the inverse of bit 1 */
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#define BCM_AUX_MU_STAT_RTS_STAT (1 << 6) /* Status of RTS line */
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#define BCM_AUX_MU_STAT_CTS_STAT (1 << 7) /* Status of CTS line */
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#define BCM_AUX_MU_STAT_TX_EMPTY (1 << 8) /* TX FIFO is Empty */
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#define BCM_AUX_MU_STAT_TX_DONE (1 << 9) /* TX is Idle and FIFO is Empty */
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#define BCM_AUX_MU_STAT_RX_LEVEL_SHIFT 16 /* Bits 19-16: how many symbols in RX FIFO */
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#define BCM_AUX_MU_STAT_RX_LEVEL_MASK (0xf << BCM_AUX_MU_STAT_RX_LEVEL_SHIFT)
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#define BCM_AUX_MU_STAT_TX_LEVEL_SHIFT 24 /* Bits 27-24: how many symbols in TX FIFO */
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#define BCM_AUX_MU_STAT_TX_LEVEL_SHIFT 24 /* Bits 27-24: how many symbols in TX FIFO */
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#define BCM_AUX_MU_STAT_TX_LEVEL_MASK (0xf << BCM_AUX_MU_STAT_TX_LEVEL_SHIFT)
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#define BCM_AUX_SPI_CNTL0_SFT_LEN_SHIFT 0 /* Specifies the number of bits to shift */
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#define BCM_AUX_SPI_CNTL0_SFT_LEN_SHIFT 0 /* Specifies the number of bits to shift */
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#define BCM_AUX_SPI_CNTL0_SFT_LEN_MASK (0x3f << BCM_AUX_SPI_CNTL0_SFT_LEN_SHIFT)
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#define BCM_AUX_SPI_CNTL0_MSB_FIRST (1 << 6) /* If 1 the data is shifted out starting with the MS bit */
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#define BCM_AUX_SPI_CNTL0_INV_SPICLK (1 << 7) /* If 1 the 'idle' clock line state is high */
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#define BCM_AUX_SPI_CNTL0_OUT_RISING (1 << 8) /* if 1 data is clocked out on the rising edge of the SPI clock */
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#define BCM_AUX_SPI_CNTL0_CLR_FIFO (1 << 9) /* Clear RX and TX FIFOs */
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#define BCM_AUX_SPI_CNTL0_MSB_FIRST (1 << 6) /* If 1 the data is shifted out starting with the MS bit */
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#define BCM_AUX_SPI_CNTL0_INV_SPICLK (1 << 7) /* If 1 the 'idle' clock line state is high */
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#define BCM_AUX_SPI_CNTL0_OUT_RISING (1 << 8) /* if 1 data is clocked out on the rising edge of the SPI clock */
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#define BCM_AUX_SPI_CNTL0_CLR_FIFO (1 << 9) /* Clear RX and TX FIFOs */
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#define BCM_AUX_SPI_CNTL0_IN_RISING (1 << 10) /* If 1 data is clocked in on the rising edge of the SPI clock */
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#define BCM_AUX_SPI_CNTL0_ENABLE (1 << 11) /* Enables the SPI interface. */
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#define BCM_AUX_SPI_CNTL0_DOHT_SHIFT 12 /* Bit 13-12: DOUT Hold Time */
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#define BCM_AUX_SPI_CNTL0_DOHT_SHIFT 12 /* Bit 13-12: DOUT Hold Time */
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#define BCM_AUX_SPI_CNTL0_DOHT_MASK (3 << BCM_AUX_SPI_CNTL0_DOHT_SHIFT)
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# define BCM_AUX_SPI_CNTL0_DOHT_NONE (0 << BCM_AUX_SPI_CNTL0_DOHT_SHIFT)
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# define BCM_AUX_SPI_CNTL0_DOHT_1CLK (1 << BCM_AUX_SPI_CNTL0_DOHT_SHIFT)
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@@ -185,27 +189,27 @@
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#define BCM_AUX_SPI_CNTL0_VAR_WIDTH (1 << 14) /* Variable Width based on TX FIFO */
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#define BCM_AUX_SPI_CNTL0_VAR_CS (1 << 15) /* CS pattern and data from TX FIFO */
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#define BCM_AUX_SPI_CNTL0_PIM (1 << 16) /* Post Input Mode */
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#define BCM_AUX_SPI_CNTL0_CS_SHIFT 17 /* The pattern output on the CS pins when active */
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#define BCM_AUX_SPI_CNTL0_CS_SHIFT 17 /* The pattern output on the CS pins when active */
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#define BCM_AUX_SPI_CNTL0_CS_MASK (7 << BCM_AUX_SPI_CNTL0_CS_SHIFT)
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#define BCM_AUX_SPI_CNTL0_SPEED_SHIFT 20
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#define BCM_AUX_SPI_CNTL0_SPEED_MASK (0xfff << BCM_AUX_SPI_CNTL0_SPEED_SHIFT)
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#define BCM_AUX_SPI_CNTL1_KEEP_IN (1 << 0) /* Keep input, shift register is not cleared */
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#define BCM_AUX_SPI_CNTL1_MSB_FIRST (1 << 1) /* Shift data from MSB */
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#define BCM_AUX_SPI_CNTL1_DONE_IRQ (1 << 6) /* If 1 the interrupt line is high when the interface is idle */
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#define BCM_AUX_SPI_CNTL1_TXEMPTY_IRQ (1 << 7) /* Enable IRQ Line when FIFO is Empty */
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#define BCM_AUX_SPI_CNTL1_CSHT_SHIFT 8 /* Bits 10-8: Additional CS High Time */
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#define BCM_AUX_SPI_CNTL1_KEEP_IN (1 << 0) /* Keep input, shift register is not cleared */
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#define BCM_AUX_SPI_CNTL1_MSB_FIRST (1 << 1) /* Shift data from MSB */
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#define BCM_AUX_SPI_CNTL1_DONE_IRQ (1 << 6) /* If 1 the interrupt line is high when the interface is idle */
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#define BCM_AUX_SPI_CNTL1_TXEMPTY_IRQ (1 << 7) /* Enable IRQ Line when FIFO is Empty */
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#define BCM_AUX_SPI_CNTL1_CSHT_SHIFT 8 /* Bits 10-8: Additional CS High Time */
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#define BCM_AUX_SPI_CNTL1_CSHT_MASK (7 << BCM_AUX_SPI_CNTL1_CSHT_SHIFT)
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#define BCM_AUX_SPI_STAT_BITCNT_SHIFT 0 /* Bits 5-0: The number of bits still to be processed */
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#define BCM_AUX_SPI_STAT_BITCNT_SHIFT 0 /* Bits 5-0: The number of bits still to be processed */
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#define BCM_AUX_SPI_STAT_BITCNT_MASK (0x3f << BCM_AUX_SPI_STAT_BITCNT_SHIFT)
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#define BCM_AUX_SPI_STAT_BUSY (1 << 6) /* The module is busy transferring data */
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#define BCM_AUX_SPI_STAT_RXEMPTY (1 << 7) /* RX FIFO is empty */
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#define BCM_AUX_SPI_STAT_TXEMPTY (1 << 8) /* TX FIFO is empty */
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#define BCM_AUX_SPI_STAT_TXFULL (1 << 9) /* TX FIFO is full */
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#define BCM_AUX_SPI_STAT_RXLEVEL_SHIFT 12 /* Data units in the RX FIFO */
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#define BCM_AUX_SPI_STAT_BUSY (1 << 6) /* The module is busy transferring data */
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#define BCM_AUX_SPI_STAT_RXEMPTY (1 << 7) /* RX FIFO is empty */
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#define BCM_AUX_SPI_STAT_TXEMPTY (1 << 8) /* TX FIFO is empty */
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#define BCM_AUX_SPI_STAT_TXFULL (1 << 9) /* TX FIFO is full */
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#define BCM_AUX_SPI_STAT_RXLEVEL_SHIFT 12 /* Data units in the RX FIFO */
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#define BCM_AUX_SPI_STAT_RXLEVEL_MASK (0xfff << BCM_AUX_SPI_STAT_RXLEVEL_SHIFT)
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#define BCM_AUX_SPI_STAT_TXLEVEL_SHIFT 24 /* Data units in the FX FIFO */
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#define BCM_AUX_SPI_STAT_TXLEVEL_SHIFT 24 /* Data units in the FX FIFO */
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#define BCM_AUX_SPI_STAT_TXLEVEL_MASK (0xff << BCM_AUX_SPI_STAT_TXLEVEL_SHIFT)
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#endif /* __ARCH_ARM_SRC_BCM_CHIP_BCM_AUX_H */
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#endif /* __ARCH_ARM_SRC_BCM2708_CHIP_BCM2708_AUX_H */
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