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stm32h7 sdmmc: do not enable power saving configuration bit (in SD 4-bit mode) because

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the SDIO clock is not enabled when the bus goes to the idle state, that, in turn, breaks
IRQ delivering mechanism over DAT[1]/IRQ SDIO line to the host.
This commit is contained in:
Alexander Lunev
2021-11-03 22:50:14 -05:00
committed by Xiang Xiao
parent 02e2b33c1c
commit 60de445ab3
1 changed files with 15 additions and 4 deletions
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arch/arm/src/stm32h7/stm32_sdmmc.c
+15 -4
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@@ -212,10 +212,21 @@
STM32_SDMMC_CLKCR_EDGE | \
STM32_SDMMC_CLKCR_PWRSAV | \
STM32_SDMMC_CLKCR_WIDBUS_D1)
#define STM32_SDMMC_CLCKR_SDWIDEXFR (STM32_SDMMC_SDXFR_CLKDIV | \
STM32_SDMMC_CLKCR_EDGE | \
STM32_SDMMC_CLKCR_PWRSAV | \
STM32_SDMMC_CLKCR_WIDBUS_D4)
#ifdef HAVE_SDMMC_SDIO_MODE
/* Do not enable power saving configuration bit (in SD 4-bit mode) because
* the SDIO clock is not enabled when the bus goes to the idle state.
* This condition breaks interrupts delivering mechanism over DAT[1]/IRQ
* SDIO line to the host.
*/
# define STM32_SDMMC_CLCKR_SDWIDEXFR (STM32_SDMMC_SDXFR_CLKDIV | \
STM32_SDMMC_CLKCR_EDGE | \
STM32_SDMMC_CLKCR_WIDBUS_D4)
#else
# define STM32_SDMMC_CLCKR_SDWIDEXFR (STM32_SDMMC_SDXFR_CLKDIV | \
STM32_SDMMC_CLKCR_EDGE | \
STM32_SDMMC_CLKCR_PWRSAV | \
STM32_SDMMC_CLKCR_WIDBUS_D4)
#endif
/* Timing */