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synced 2026-06-08 10:32:47 +08:00
Separate memory mapping tables for SAMA5D2, 3, and 4
This commit is contained in:
Gregory Nutt
@@ -132,8 +132,8 @@ CHIP_ASRCS =
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# SAMA5-specific C source files
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CHIP_CSRCS = sam_allocateheap.c sam_boot.c sam_clockconfig.c sam_irq.c
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CHIP_CSRCS += sam_lowputc.c sam_memories.c sam_pck.c sam_pio.c sam_pmc.c
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CHIP_CSRCS += sam_sckc.c sam_serial.c
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CHIP_CSRCS += sam_lowputc.c sam_memories.c sam_memorymap.c sam_pck.c
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CHIP_CSRCS += sam_pio.c sam_pmc.c sam_sckc.c sam_serial.c
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# Configuration dependent C and assembly language files
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+23
-286
@@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/sama5/sam_boot.c
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*
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* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
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* Copyright (C) 2013-2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -59,7 +59,9 @@
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#include "chip/sam_wdt.h"
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#include "chip/sam_aximx.h"
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#include "sam_clockconfig.h"
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#include "sam_memorymap.h"
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#include "sam_lowputc.h"
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#include "sam_serial.h"
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#include "sam_lcd.h"
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@@ -67,52 +69,13 @@
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* The vectors are, by default, positioned at the beginning of the text
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* section. Under what conditions do we have to remap the these vectors?
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*
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* 1) If we are using high vectors (CONFIG_ARCH_LOWVECTORS=n). In this case,
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* the vectors will lie at virtual address 0xffff:000 and we will need
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* to a) copy the vectors to another location, and b) map the vectors
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* to that address, and
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*
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* For the case of CONFIG_ARCH_LOWVECTORS=y, defined. The SAMA5 boot-up
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* logic will map the beginning of the boot memory to address 0x0000:0000
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* using both the MMU and the AXI matrix REMAP register. No vector copy
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* is required because the vectors are position at the beginning of the
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* boot memory at link time and no additional MMU mapping required.
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*
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* 2) We are not using a ROM page table. We cannot set any custom mappings in
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* the case and the build must conform to the ROM page table properties
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*/
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#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_ARCH_ROMPGTABLE)
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# error High vector remap cannot be performed if we are using a ROM page table
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#endif
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/* If SDRAM needs to be configured, then it will be configured twice: It
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* will first be configured to a temporary state to support low-level
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* initialization. After the SDRAM has been fully initialized, SRAM be used
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* to set the SDRM in its final, fully cache-able state.
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*/
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#undef NEED_SDRAM_CONFIGURATION
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#if defined(CONFIG_SAMA5_DDRCS) && !defined(CONFIG_SAMA5_BOOT_SDRAM)
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# define NEED_SDRAM_CONFIGURATION 1
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#endif
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#undef NEED_SDRAM_MAPPING
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#undef NEED_SDRAM_REMAPPING
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#if defined(NEED_SDRAM_CONFIGURATION) && !defined(CONFIG_ARCH_ROMPGTABLE)
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# define NEED_SDRAM_MAPPING 1
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# define NEED_SDRAM_REMAPPING 1
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/****************************************************************************
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* Public Variables
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* Public Data
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****************************************************************************/
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/* Symbols defined via the linker script */
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@@ -121,247 +84,9 @@ extern uint32_t _vector_start; /* Beginning of vector block */
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extern uint32_t _vector_end; /* End+1 of vector block */
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/****************************************************************************
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* Private Variables
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* Private Data
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****************************************************************************/
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/* This table describes how to map a set of 1Mb pages to space the physical
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* address space of the SAMA5.
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*/
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#ifndef CONFIG_ARCH_ROMPGTABLE
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static const struct section_mapping_s section_mapping[] =
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{
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/* SAMA5 Internal Memories */
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/* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the
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* beginning of the .text region must appear at address at the address
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* specified in the VBAR. There are three ways to accomplish this:
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*
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* 1. By explicitly mapping the beginning of .text region with a page
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* table entry so that the virtual address zero maps to the beginning
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* of the .text region. VBAR == 0x0000:0000.
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*
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* 2. A second way is to map the use the AXI MATRIX remap register to
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* map physical address zero to the beginning of the text region,
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* either internal SRAM or EBI CS 0. Then we can set an identity
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* mapping to map the boot region at 0x0000:0000 to virtual address
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* 0x0000:00000. VBAR == 0x0000:0000.
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*
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* This method is used when booting from ISRAM or NOR FLASH. In
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& that case, vectors must lie at the beginning of NOFR FLASH.
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*
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* 3. Set the Cortex-A5 VBAR register so that the vector table address
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* is moved to a location other than 0x0000:0000.
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*
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* This is the method used when booting from SDRAM.
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*
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* - When executing from NOR FLASH, the first level bootloader is supposed
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* to provide the AXI MATRIX mapping for us at boot time base on the state
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* of the BMS pin. However, I have found that in the test environments
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* that I use, I cannot always be assured of that physical address mapping.
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*
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* So we do both here. If we are executing from NOR FLASH, then we provide
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* the MMU to map the physical address of FLASH to address 0x0000:0000;
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*
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* - If we are executing out of ISRAM, then the SAMA5 primary bootloader
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* probably copied us into ISRAM and set the AXI REMAP bit for us.
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*
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* - If we are executing from external SDRAM, then a secondary bootloader must
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* have loaded us into SDRAM. In this case, simply set the VBAR register
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* to the address of the vector table (not necessary at the beginning
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* or SDRAM).
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*/
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#if defined(CONFIG_ARCH_LOWVECTORS) && !defined(CONFIG_SAMA5_BOOT_ISRAM) && \
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!defined(CONFIG_SAMA5_BOOT_SDRAM)
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{ CONFIG_FLASH_START, 0x00000000,
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MMU_ROMFLAGS, 1
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},
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#else
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{ SAM_BOOTMEM_PSECTION, SAM_BOOTMEM_VSECTION,
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SAM_BOOTMEM_MMUFLAGS, SAM_BOOTMEM_NSECTIONS
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},
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#endif
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{ SAM_ROM_PSECTION, SAM_ROM_VSECTION,
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SAM_ROM_MMUFLAGS, SAM_ROM_NSECTIONS
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},
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{ SAM_NFCSRAM_PSECTION, SAM_NFCSRAM_VSECTION,
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SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS
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},
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#ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */
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{ SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION,
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SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS
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},
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#endif
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#ifdef SAM_VDEC_PSECTION
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/* If the memory map supports a video decoder (VDEC), then map it */
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{ SAM_VDEC_PSECTION, SAM_VDEC_VSECTION,
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SAM_VDEC_MMUFLAGS, SAM_VDEC_NSECTIONS
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},
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#endif
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{ SAM_SMD_PSECTION, SAM_SMD_VSECTION,
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SAM_SMD_MMUFLAGS, SAM_SMD_NSECTIONS
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},
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{ SAM_UDPHSRAM_PSECTION, SAM_UDPHSRAM_VSECTION,
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SAM_UDPHSRAM_MMUFLAGS, SAM_UDPHSRAM_NSECTIONS
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},
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{ SAM_UHPOHCI_PSECTION, SAM_UHPOHCI_VSECTION,
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SAM_UHPOHCI_MMUFLAGS, SAM_UHPOHCI_NSECTIONS
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},
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{ SAM_UHPEHCI_PSECTION, SAM_UHPEHCI_VSECTION,
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SAM_UHPEHCI_MMUFLAGS, SAM_UHPEHCI_NSECTIONS
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},
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{ SAM_AXIMX_PSECTION, SAM_AXIMX_VSECTION,
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SAM_AXIMX_MMUFLAGS, SAM_AXIMX_NSECTIONS
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},
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{ SAM_DAP_PSECTION, SAM_DAP_VSECTION,
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SAM_DAP_MMUFLAGS, SAM_DAP_NSECTIONS
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},
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#ifdef SAM_L2CC_PSECTION
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/* If the memory map supports an L2 cache controller (L2CC), then map it */
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{ SAM_L2CC_PSECTION, SAM_L2CC_VSECTION,
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SAM_L2CC_MMUFLAGS, SAM_L2CC_NSECTIONS
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},
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#endif
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/* SAMA5 CS0 External Memories */
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#ifdef CONFIG_SAMA5_EBICS0
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{ SAM_EBICS0_PSECTION, SAM_EBICS0_VSECTION,
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SAM_EBICS0_MMUFLAGS, SAM_EBICS0_NSECTIONS
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},
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#endif
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/* SAMA5 External SDRAM Memory. The SDRAM is not usable until it has been
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* initialized. If we are running out of SDRAM now, we can assume that some
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* second level boot loader has properly configured SRAM for us. In that
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* case, we set the MMU flags for the final, fully cache-able state.
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*
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* Also, in this case, the mapping for the SDRAM was done in arm_head.S and
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* need not be repeated here.
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*
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* If we are running from ISRAM or NOR flash, then we will need to configure
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* the SDRAM ourselves. In this case, we set the MMU flags to the strongly
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* ordered, non-cacheable state. We need this direct access to SDRAM in
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* order to configure it. Once SDRAM has been initialized, it will be re-
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* configured in its final state.
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*/
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#ifdef NEED_SDRAM_MAPPING
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{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
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MMU_STRONGLY_ORDERED, SAM_DDRCS_NSECTIONS
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},
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#endif
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/* SAMA5 CS1-3 External Memories */
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#ifdef CONFIG_SAMA5_EBICS1
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{ SAM_EBICS1_PSECTION, SAM_EBICS1_VSECTION,
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SAM_EBICS1_MMUFLAGS, SAM_EBICS1_NSECTIONS
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},
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#endif
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#ifdef CONFIG_SAMA5_EBICS2
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{ SAM_EBICS2_PSECTION, SAM_EBICS2_VSECTION,
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SAM_EBICS2_MMUFLAGS, SAM_EBICS2_NSECTIONS
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},
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#endif
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#ifdef CONFIG_SAMA5_EBICS3
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{ SAM_EBICS3_PSECTION, SAM_EBICS3_VSECTION,
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SAM_EBICS3_MMUFLAGS, SAM_EBICS3_NSECTIONS
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},
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#endif
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#ifdef CONFIG_SAMA5_HAVE_NAND
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{ SAM_NFCCR_PSECTION, SAM_NFCCR_VSECTION,
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SAM_NFCCR_MMUFLAGS, SAM_NFCCR_NSECTIONS
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},
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#endif
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/* SAMA5 Internal Peripherals
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*
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* Naming of peripheral sections differs between the SAMA5D3 and SAMA5D4.
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* There is nothing called SYSC in the SAMA5D4 memory map. The third
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* peripheral section is un-named in the SAMA5D4 memory map, but I have
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* chosen the name PERIPHC for this usage.
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*/
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{ SAM_PERIPHA_PSECTION, SAM_PERIPHA_VSECTION,
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SAM_PERIPHA_MMUFLAGS, SAM_PERIPHA_NSECTIONS
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},
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{ SAM_PERIPHB_PSECTION, SAM_PERIPHB_VSECTION,
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SAM_PERIPHB_MMUFLAGS, SAM_PERIPHB_NSECTIONS
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},
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#ifdef SAM_PERIPHC_PSECTION
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{ SAM_PERIPHC_PSECTION, SAM_PERIPHC_VSECTION,
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SAM_PERIPHC_MMUFLAGS, SAM_PERIPHC_NSECTIONS
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},
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#endif
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#ifdef SAM_SYSC_PSECTION
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{ SAM_SYSC_PSECTION, SAM_SYSC_VSECTION,
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SAM_SYSC_MMUFLAGS, SAM_SYSC_NSECTIONS
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},
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#endif
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/* LCDC Framebuffer. This entry reprograms a part of one of the above
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* regions, making it non-cacheable and non-buffereable.
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*
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* If SDRAM will be reconfigured, then we will defer setup of the framebuffer
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* until after the SDRAM remapping (since the framebuffer problem resides) in
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* SDRAM.
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*/
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#if defined(CONFIG_SAMA5_LCDC) && !defined(NEED_SDRAM_REMAPPING)
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{ CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE,
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MMU_IOFLAGS, SAMA5_LCDC_FBNSECTIONS
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},
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#endif
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};
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#define NMAPPINGS \
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(sizeof(section_mapping) / sizeof(struct section_mapping_s))
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#endif
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/* SAMA5 External SDRAM Memory. Final configuration. The SDRAM was
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* configured in a temporary state to support low-level ininitialization.
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* After the SDRAM has been fully initialized, this structure is used to
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* set the SDRM in its final, fully cache-able state.
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*/
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#ifdef NEED_SDRAM_REMAPPING
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static const struct section_mapping_s operational_mapping[] =
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{
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/* This entry reprograms the SDRAM entry, making it cacheable and
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* bufferable.
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*/
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{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
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SAM_DDRCS_MMUFLAGS, SAM_DDRCS_NSECTIONS
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},
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/* LCDC Framebuffer. This entry reprograms a part of one of the above
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* regions, making it non-cacheable and non-buffereable.
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*/
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#ifdef CONFIG_SAMA5_LCDC
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{ CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE,
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MMU_IOFLAGS, SAMA5_LCDC_FBNSECTIONS
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},
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#endif
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};
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#define NREMAPPINGS \
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(sizeof(operational_mapping) / sizeof(struct section_mapping_s))
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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@@ -370,7 +95,7 @@ static const struct section_mapping_s operational_mapping[] =
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* Name: sam_setupmappings
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*
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* Description
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* Map all of the initial memory regions defined in section_mapping[]
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* Map all of the initial memory regions defined in g_section_mapping[]
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*
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****************************************************************************/
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@@ -381,9 +106,9 @@ static inline void sam_setupmappings(void)
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/* Set up each group of section mappings */
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for (i = 0; i < NMAPPINGS; i++)
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for (i = 0; i < g_num_mappings; i++)
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{
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mmu_l1_map_region(§ion_mapping[i]);
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mmu_l1_map_region(&g_section_mapping[i]);
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}
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}
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#endif
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@@ -392,7 +117,7 @@ static inline void sam_setupmappings(void)
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* Name: sam_remap
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*
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* Description
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* Map all of the final memory regions defined in operation_mapping[]
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* Map all of the final memory regions defined in g_operational_mapping[]
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*
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****************************************************************************/
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@@ -403,9 +128,9 @@ static inline void sam_remap(void)
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/* Re-map each group of section */
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for (i = 0; i < NREMAPPINGS; i++)
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for (i = 0; i < g_num_opmappings; i++)
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{
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mmu_l1_map_region(&operational_mapping[i]);
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mmu_l1_map_region(&g_operational_mapping[i]);
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}
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}
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#endif
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@@ -688,6 +413,18 @@ void up_boot(void)
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uint32_t *dest;
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAMA5D2) && !defined(CONFIG_ARCH_L2CACHE)
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/* The SAMA5D2 features a second 128-Kbyte SRAM that can be allocated
|
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* either to the L2 cache controller or used as an internal SRAM. After
|
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* reset, this block is connected to the L2 cache controller. The
|
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* SRAM_SEL bit, located in the SFR_L2CC_HRAMC register, is used to
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* reassign this memory as system SRAM, making the two 128-Kbyte
|
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* RAMs contiguous.
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*/
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# warning Missing Logic
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#endif
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#ifndef CONFIG_ARCH_ROMPGTABLE
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/* __start provided the basic MMU mappings for SRAM. Now provide mappings
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* for all IO regions (Including the vector region).
|
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@@ -0,0 +1,55 @@
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/************************************************************************************
|
||||
* arch/arm/src/sama5/sam_memorymap.c
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
/* chip.h holds the characteristics of the configured chip */
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <arch/sama5/chip.h>
|
||||
|
||||
/* Include the correct logic for the configured chip */
|
||||
|
||||
#if defined(ATSAMA5D2)
|
||||
# include "sama5d2x_memorymap.c"
|
||||
#elif defined(ATSAMA5D3)
|
||||
# include "sama5d3x_memorymap.c"
|
||||
#elif defined(ATSAMA5D4)
|
||||
# include "sama5d4x_memorymap.c"
|
||||
#else
|
||||
# error Unrecognized SAMA5 family
|
||||
#endif
|
||||
@@ -0,0 +1,116 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/sama5/sam_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_SAMA5_SAM_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <arch/sama5/chip.h>
|
||||
|
||||
#include "mmu.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* The vectors are, by default, positioned at the beginning of the text
|
||||
* section. Under what conditions do we have to remap the these vectors?
|
||||
*
|
||||
* 1) If we are using high vectors (CONFIG_ARCH_LOWVECTORS=n). In this case,
|
||||
* the vectors will lie at virtual address 0xffff:000 and we will need
|
||||
* to a) copy the vectors to another location, and b) map the vectors
|
||||
* to that address, and
|
||||
*
|
||||
* For the case of CONFIG_ARCH_LOWVECTORS=y, defined. The SAMA5 boot-up
|
||||
* logic will map the beginning of the boot memory to address 0x0000:0000
|
||||
* using both the MMU and the AXI matrix REMAP register. No vector copy
|
||||
* is required because the vectors are position at the beginning of the
|
||||
* boot memory at link time and no additional MMU mapping required.
|
||||
*
|
||||
* 2) We are not using a ROM page table. We cannot set any custom mappings in
|
||||
* the case and the build must conform to the ROM page table properties
|
||||
*/
|
||||
|
||||
#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_ARCH_ROMPGTABLE)
|
||||
# error High vector remap cannot be performed if we are using a ROM page table
|
||||
#endif
|
||||
|
||||
/* If SDRAM needs to be configured, then it will be configured twice: It
|
||||
* will first be configured to a temporary state to support low-level
|
||||
* initialization. After the SDRAM has been fully initialized, SRAM be used
|
||||
* to set the SDRM in its final, fully cache-able state.
|
||||
*/
|
||||
|
||||
#undef NEED_SDRAM_CONFIGURATION
|
||||
#if defined(CONFIG_SAMA5_DDRCS) && !defined(CONFIG_SAMA5_BOOT_SDRAM)
|
||||
# define NEED_SDRAM_CONFIGURATION 1
|
||||
#endif
|
||||
|
||||
#undef NEED_SDRAM_MAPPING
|
||||
#undef NEED_SDRAM_REMAPPING
|
||||
#if defined(NEED_SDRAM_CONFIGURATION) && !defined(CONFIG_ARCH_ROMPGTABLE)
|
||||
# define NEED_SDRAM_MAPPING 1
|
||||
# define NEED_SDRAM_REMAPPING 1
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/* This table describes how to map a set of 1Mb pages to space the physical
|
||||
* address space of the SAMA5.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_ARCH_ROMPGTABLE
|
||||
extern const struct section_mapping_s g_section_mapping[];
|
||||
extern const size_t g_num_mappings;
|
||||
#endif
|
||||
|
||||
/* SAMA5 External SDRAM Memory. Final configuration. The SDRAM was
|
||||
* configured in a temporary state to support low-level ininitialization.
|
||||
* After the SDRAM has been fully initialized, this structure is used to
|
||||
* set the SDRM in its final, fully cache-able state.
|
||||
*/
|
||||
|
||||
#ifdef NEED_SDRAM_REMAPPING
|
||||
extern const struct section_mapping_s g_operational_mapping[];
|
||||
extern const size_t g_num_opmappings;
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_MEMORYMAP_H */
|
||||
@@ -45,7 +45,7 @@
|
||||
#include <nuttx/config.h>
|
||||
#include <arch/sama5/chip.h>
|
||||
|
||||
/* Include the correctly logic for the configured chip */
|
||||
/* Include the correct logic for the configured chip */
|
||||
|
||||
#if defined(ATSAMA5D2)
|
||||
# include "sama5d2x_periphclks.h"
|
||||
|
||||
@@ -0,0 +1,316 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/sama5/sama5d2x_memorymap.c
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "mmu.h"
|
||||
|
||||
#include "chip/sam_memorymap.h"
|
||||
#include "sam_lcd.h"
|
||||
#include "sam_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/* This table describes how to map a set of 1Mb pages to space the physical
|
||||
* address space of the SAMA5.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_ARCH_ROMPGTABLE
|
||||
const struct section_mapping_s g_section_mapping[] =
|
||||
{
|
||||
/* SAMA5 Internal Memories */
|
||||
|
||||
/* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the
|
||||
* beginning of the .text region must appear at address at the address
|
||||
* specified in the VBAR. There are three ways to accomplish this:
|
||||
*
|
||||
* 1. By explicitly mapping the beginning of .text region with a page
|
||||
* table entry so that the virtual address zero maps to the beginning
|
||||
* of the .text region. VBAR == 0x0000:0000.
|
||||
*
|
||||
* 2. A second way is to map the use the AXI MATRIX remap register to
|
||||
* map physical address zero to the beginning of the text region,
|
||||
* either internal SRAM or EBI CS 0. Then we can set an identity
|
||||
* mapping to map the boot region at 0x0000:0000 to virtual address
|
||||
* 0x0000:00000. VBAR == 0x0000:0000.
|
||||
*
|
||||
* This method is used when booting from ISRAM or NOR FLASH. In
|
||||
& that case, vectors must lie at the beginning of NOFR FLASH.
|
||||
*
|
||||
* 3. Set the Cortex-A5 VBAR register so that the vector table address
|
||||
* is moved to a location other than 0x0000:0000.
|
||||
*
|
||||
* This is the method used when booting from SDRAM.
|
||||
*
|
||||
* The system always boots from the ROM memory at address 0x0. After
|
||||
* reset, and until the Remap command is performed, the SRAM is accessible
|
||||
* at address 0x0020 0000. When the AXI Bus Matrix is remapped, the SRAM is
|
||||
* also available at address 0x0.
|
||||
*
|
||||
* If we are executing out of ISRAM, then the SAMA5 primary bootloader
|
||||
* probably copied us into ISRAM and set the AXI REMAP0 bit for us.
|
||||
*
|
||||
* If we are executing from external SDRAM, then a secondary bootloader must
|
||||
* have loaded us into SDRAM. In this case, simply set the VBAR register
|
||||
* to the address of the vector table (not necessary at the beginning
|
||||
* or SDRAM).
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARCH_LOWVECTORS
|
||||
{ SAM_SRAMREMAP_PSECTION, SAM_SRAMREMAP_vSECTION,
|
||||
SAM_SRAMREMAP_MMUFLAGS, SAM_SRAMREMAP_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
{ SAM_NFCSRAM_PSECTION, SAM_NFCSRAM_VSECTION,
|
||||
SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS
|
||||
},
|
||||
|
||||
#ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */
|
||||
{ SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION,
|
||||
SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
{ SAM_UDPHSRAM_PSECTION, SAM_UDPHSRAM_VSECTION,
|
||||
SAM_UDPHSRAM_MMUFLAGS, SAM_UDPHSRAM_NSECTIONS
|
||||
},
|
||||
{ SAM_UHPOHCI_PSECTION, SAM_UHPOHCI_VSECTION,
|
||||
SAM_UHPOHCI_MMUFLAGS, SAM_UHPOHCI_NSECTIONS
|
||||
},
|
||||
{ SAM_UHPEHCI_PSECTION, SAM_UHPEHCI_VSECTION,
|
||||
SAM_UHPEHCI_MMUFLAGS, SAM_UHPEHCI_NSECTIONS
|
||||
},
|
||||
{ SAM_AXIMX_PSECTION, SAM_AXIMX_VSECTION,
|
||||
SAM_AXIMX_MMUFLAGS, SAM_AXIMX_NSECTIONS
|
||||
},
|
||||
{ SAM_DAP_PSECTION, SAM_DAP_VSECTION,
|
||||
SAM_DAP_MMUFLAGS, SAM_DAP_NSECTIONS
|
||||
},
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAMA5D2) && !defined(CONFIG_ARCH_L2CACHE)
|
||||
/* The SAMA5D2 features a second 128-Kbyte SRAM that can be allocated
|
||||
* either to the L2 cache controller or used as an internal SRAM. After
|
||||
* reset, this block is connected to the L2 cache controller. The
|
||||
* SRAM_SEL bit, located in the SFR_L2CC_HRAMC register, is used to
|
||||
* reassign this memory as system SRAM, making the two 128-Kbyte
|
||||
* RAMs contiguous.
|
||||
*/
|
||||
|
||||
{ SAM_L2CC_PSECTION, SAM_L2CC_VSECTION,
|
||||
SAM_L2CC_MMUFLAGS, SAM_L2CC_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
/* SAMA5 CS0 External Memories */
|
||||
|
||||
#ifdef CONFIG_SAMA5_EBICS0
|
||||
{ SAM_EBICS0_PSECTION, SAM_EBICS0_VSECTION,
|
||||
SAM_EBICS0_MMUFLAGS, SAM_EBICS0_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
/* SAMA5 External SDRAM Memory. The SDRAM is not usable until it has been
|
||||
* initialized. If we are running out of SDRAM now, we can assume that some
|
||||
* second level boot loader has properly configured SRAM for us. In that
|
||||
* case, we set the MMU flags for the final, fully cache-able state.
|
||||
*
|
||||
* Also, in this case, the mapping for the SDRAM was done in arm_head.S and
|
||||
* need not be repeated here.
|
||||
*
|
||||
* If we are running from ISRAM or NOR flash, then we will need to configure
|
||||
* the SDRAM ourselves. In this case, we set the MMU flags to the strongly
|
||||
* ordered, non-cacheable state. We need this direct access to SDRAM in
|
||||
* order to configure it. Once SDRAM has been initialized, it will be re-
|
||||
* configured in its final state.
|
||||
*/
|
||||
|
||||
#ifdef NEED_SDRAM_MAPPING
|
||||
{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
|
||||
MMU_STRONGLY_ORDERED, SAM_DDRCS_NSECTIONS
|
||||
},
|
||||
{ SAM_DDRAESCS_PSECTION, SAM_DDRAESCS_VSECTION,
|
||||
MMU_STRONGLY_ORDERED, SAM_DDRAESCS_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
/* SAMA5 CS1-3 External Memories */
|
||||
|
||||
#ifdef CONFIG_SAMA5_EBICS1
|
||||
{ SAM_EBICS1_PSECTION, SAM_EBICS1_VSECTION,
|
||||
SAM_EBICS1_MMUFLAGS, SAM_EBICS1_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_EBICS2
|
||||
{ SAM_EBICS2_PSECTION, SAM_EBICS2_VSECTION,
|
||||
SAM_EBICS2_MMUFLAGS, SAM_EBICS2_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_EBICS3
|
||||
{ SAM_EBICS3_PSECTION, SAM_EBICS3_VSECTION,
|
||||
SAM_EBICS3_MMUFLAGS, SAM_EBICS3_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_QSPI0AES
|
||||
{ SAM_QSPI0AES_PSECTION, SAM_QSPI0AES_VSECTION,
|
||||
SAM_QSPI0AES_MMUFLAGS, SAM_QSPI0AES_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_QSPI1AES
|
||||
{ SAM_QSPI1AES_PSECTION, SAM_QSPI1AES_VSECTION,
|
||||
SAM_QSPI1AES_MMUFLAGS, SAM_QSPI1AES_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_SDMMC0
|
||||
{ SAM_SDMMC0_PSECTION, SAM_SDMMC0_VSECTION,
|
||||
SAM_SDMMC0_MMUFLAGS, SAM_SDMMC0_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_SDMMC1
|
||||
{ SAM_SDMMC1_PSECTION, SAM_SDMMC1_VSECTION,
|
||||
SAM_SDMMC1_MMUFLAGS, SAM_SDMMC1_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_HAVE_NAND
|
||||
{ SAM_NFCCR_PSECTION, SAM_NFCCR_VSECTION,
|
||||
SAM_NFCCR_MMUFLAGS, SAM_NFCCR_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_QSPI0
|
||||
{ SAM_QSPI0_PSECTION, SAM_QSPI0_VSECTION,
|
||||
SAM_QSPI0_MMUFLAGS, SAM_QSPI0_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_QSPI1
|
||||
{ SAM_QSPI1_PSECTION, SAM_QSPI1_VSECTION,
|
||||
SAM_QSPI1_MMUFLAGS, SAM_QSPI1_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
/* SAMA5 Internal Peripherals
|
||||
*
|
||||
* Naming of peripheral sections differs between the SAMA5D3 and SAMA5D4.
|
||||
* There is nothing called SYSC in the SAMA5D4 memory map. The third
|
||||
* peripheral section is un-named in the SAMA5D4 memory map, but I have
|
||||
* chosen the name PERIPHC for this usage.
|
||||
*/
|
||||
|
||||
{ SAM_PERIPHA_PSECTION, SAM_PERIPHA_VSECTION,
|
||||
SAM_PERIPHA_MMUFLAGS, SAM_PERIPHA_NSECTIONS
|
||||
},
|
||||
{ SAM_PERIPHB_PSECTION, SAM_PERIPHB_VSECTION,
|
||||
SAM_PERIPHB_MMUFLAGS, SAM_PERIPHB_NSECTIONS
|
||||
},
|
||||
{ SAM_PERIPHC_PSECTION, SAM_PERIPHC_VSECTION,
|
||||
SAM_PERIPHC_MMUFLAGS, SAM_PERIPHC_NSECTIONS
|
||||
},
|
||||
|
||||
/* LCDC Framebuffer. This entry reprograms a part of one of the above
|
||||
* regions, making it non-cacheable and non-buffereable.
|
||||
*
|
||||
* If SDRAM will be reconfigured, then we will defer setup of the framebuffer
|
||||
* until after the SDRAM remapping (since the framebuffer problem resides) in
|
||||
* SDRAM.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_SAMA5_LCDC) && !defined(NEED_SDRAM_REMAPPING)
|
||||
{ CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE,
|
||||
MMU_IOFLAGS, SAMA5_LCDC_FBNSECTIONS
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
/* The number of entries in the mapping table */
|
||||
|
||||
#define NMAPPINGS \
|
||||
(sizeof(g_section_mapping) / sizeof(struct section_mapping_s))
|
||||
|
||||
const size_t g_num_mappings = NMAPPINGS;
|
||||
|
||||
#endif /* CONFIG_ARCH_ROMPGTABLE */
|
||||
|
||||
/* SAMA5 External SDRAM Memory. Final configuration. The SDRAM was
|
||||
* configured in a temporary state to support low-level ininitialization.
|
||||
* After the SDRAM has been fully initialized, this structure is used to
|
||||
* set the SDRM in its final, fully cache-able state.
|
||||
*/
|
||||
|
||||
#ifdef NEED_SDRAM_REMAPPING
|
||||
const struct section_mapping_s g_operational_mapping[] =
|
||||
{
|
||||
/* This entry reprograms the SDRAM entry, making it cacheable and
|
||||
* bufferable.
|
||||
*/
|
||||
|
||||
{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
|
||||
SAM_DDRCS_MMUFLAGS, SAM_DDRCS_NSECTIONS
|
||||
},
|
||||
{ SAM_DDRAESCS_PSECTION, SAM_DDRAESCS_VSECTION,
|
||||
SAM_DDRAESCS_MMUFLAGS, SAM_DDRAESCS_NSECTIONS
|
||||
},
|
||||
|
||||
/* LCDC Framebuffer. This entry reprograms a part of one of the above
|
||||
* regions, making it non-cacheable and non-buffereable.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SAMA5_LCDC
|
||||
{ CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE,
|
||||
MMU_IOFLAGS, SAMA5_LCDC_FBNSECTIONS
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
/* The number of entries in the operational mapping table */
|
||||
|
||||
#define NREMAPPINGS \
|
||||
(sizeof(g_operational_mapping) / sizeof(struct section_mapping_s))
|
||||
|
||||
const size_t g_num_opmappings = NREMAPPINGS;
|
||||
|
||||
#endif /* NEED_SDRAM_REMAPPING */
|
||||
@@ -0,0 +1,282 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/sama5/sama5d3x_memorymap.c
|
||||
*
|
||||
* Copyright (C) 2013-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "mmu.h"
|
||||
|
||||
#include "chip/sam_memorymap.h"
|
||||
#include "sam_lcd.h"
|
||||
#include "sam_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/* This table describes how to map a set of 1Mb pages to space the physical
|
||||
* address space of the SAMA5.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_ARCH_ROMPGTABLE
|
||||
const struct section_mapping_s g_section_mapping[] =
|
||||
{
|
||||
/* SAMA5 Internal Memories */
|
||||
|
||||
/* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the
|
||||
* beginning of the .text region must appear at address at the address
|
||||
* specified in the VBAR. There are three ways to accomplish this:
|
||||
*
|
||||
* 1. By explicitly mapping the beginning of .text region with a page
|
||||
* table entry so that the virtual address zero maps to the beginning
|
||||
* of the .text region. VBAR == 0x0000:0000.
|
||||
*
|
||||
* 2. A second way is to map the use the AXI MATRIX remap register to
|
||||
* map physical address zero to the beginning of the text region,
|
||||
* either internal SRAM or EBI CS 0. Then we can set an identity
|
||||
* mapping to map the boot region at 0x0000:0000 to virtual address
|
||||
* 0x0000:00000. VBAR == 0x0000:0000.
|
||||
*
|
||||
* This method is used when booting from ISRAM or NOR FLASH. In
|
||||
& that case, vectors must lie at the beginning of NOFR FLASH.
|
||||
*
|
||||
* 3. Set the Cortex-A5 VBAR register so that the vector table address
|
||||
* is moved to a location other than 0x0000:0000.
|
||||
*
|
||||
* This is the method used when booting from SDRAM.
|
||||
*
|
||||
* - When executing from NOR FLASH, the first level bootloader is supposed
|
||||
* to provide the AXI MATRIX mapping for us at boot time base on the state
|
||||
* of the BMS pin. However, I have found that in the test environments
|
||||
* that I use, I cannot always be assured of that physical address mapping.
|
||||
*
|
||||
* So we do both here. If we are executing from NOR FLASH, then we provide
|
||||
* the MMU to map the physical address of FLASH to address 0x0000:0000;
|
||||
*
|
||||
* - If we are executing out of ISRAM, then the SAMA5 primary bootloader
|
||||
* probably copied us into ISRAM and set the AXI REMAP bit for us.
|
||||
*
|
||||
* - If we are executing from external SDRAM, then a secondary bootloader must
|
||||
* have loaded us into SDRAM. In this case, simply set the VBAR register
|
||||
* to the address of the vector table (not necessary at the beginning
|
||||
* or SDRAM).
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_LOWVECTORS) && !defined(CONFIG_SAMA5_BOOT_ISRAM) && \
|
||||
!defined(CONFIG_SAMA5_BOOT_SDRAM)
|
||||
{ CONFIG_FLASH_START, 0x00000000,
|
||||
MMU_ROMFLAGS, 1
|
||||
},
|
||||
#else
|
||||
{ SAM_BOOTMEM_PSECTION, SAM_BOOTMEM_VSECTION,
|
||||
SAM_BOOTMEM_MMUFLAGS, SAM_BOOTMEM_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
{ SAM_ROM_PSECTION, SAM_ROM_VSECTION,
|
||||
SAM_ROM_MMUFLAGS, SAM_ROM_NSECTIONS
|
||||
},
|
||||
{ SAM_NFCSRAM_PSECTION, SAM_NFCSRAM_VSECTION,
|
||||
SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS
|
||||
},
|
||||
|
||||
#ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */
|
||||
{ SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION,
|
||||
SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
{ SAM_SMD_PSECTION, SAM_SMD_VSECTION,
|
||||
SAM_SMD_MMUFLAGS, SAM_SMD_NSECTIONS
|
||||
},
|
||||
{ SAM_UDPHSRAM_PSECTION, SAM_UDPHSRAM_VSECTION,
|
||||
SAM_UDPHSRAM_MMUFLAGS, SAM_UDPHSRAM_NSECTIONS
|
||||
},
|
||||
{ SAM_UHPOHCI_PSECTION, SAM_UHPOHCI_VSECTION,
|
||||
SAM_UHPOHCI_MMUFLAGS, SAM_UHPOHCI_NSECTIONS
|
||||
},
|
||||
{ SAM_UHPEHCI_PSECTION, SAM_UHPEHCI_VSECTION,
|
||||
SAM_UHPEHCI_MMUFLAGS, SAM_UHPEHCI_NSECTIONS
|
||||
},
|
||||
{ SAM_AXIMX_PSECTION, SAM_AXIMX_VSECTION,
|
||||
SAM_AXIMX_MMUFLAGS, SAM_AXIMX_NSECTIONS
|
||||
},
|
||||
{ SAM_DAP_PSECTION, SAM_DAP_VSECTION,
|
||||
SAM_DAP_MMUFLAGS, SAM_DAP_NSECTIONS
|
||||
},
|
||||
|
||||
/* SAMA5 CS0 External Memories */
|
||||
|
||||
#ifdef CONFIG_SAMA5_EBICS0
|
||||
{ SAM_EBICS0_PSECTION, SAM_EBICS0_VSECTION,
|
||||
SAM_EBICS0_MMUFLAGS, SAM_EBICS0_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
/* SAMA5 External SDRAM Memory. The SDRAM is not usable until it has been
|
||||
* initialized. If we are running out of SDRAM now, we can assume that some
|
||||
* second level boot loader has properly configured SRAM for us. In that
|
||||
* case, we set the MMU flags for the final, fully cache-able state.
|
||||
*
|
||||
* Also, in this case, the mapping for the SDRAM was done in arm_head.S and
|
||||
* need not be repeated here.
|
||||
*
|
||||
* If we are running from ISRAM or NOR flash, then we will need to configure
|
||||
* the SDRAM ourselves. In this case, we set the MMU flags to the strongly
|
||||
* ordered, non-cacheable state. We need this direct access to SDRAM in
|
||||
* order to configure it. Once SDRAM has been initialized, it will be re-
|
||||
* configured in its final state.
|
||||
*/
|
||||
|
||||
#ifdef NEED_SDRAM_MAPPING
|
||||
{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
|
||||
MMU_STRONGLY_ORDERED, SAM_DDRCS_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
/* SAMA5 CS1-3 External Memories */
|
||||
|
||||
#ifdef CONFIG_SAMA5_EBICS1
|
||||
{ SAM_EBICS1_PSECTION, SAM_EBICS1_VSECTION,
|
||||
SAM_EBICS1_MMUFLAGS, SAM_EBICS1_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_EBICS2
|
||||
{ SAM_EBICS2_PSECTION, SAM_EBICS2_VSECTION,
|
||||
SAM_EBICS2_MMUFLAGS, SAM_EBICS2_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_EBICS3
|
||||
{ SAM_EBICS3_PSECTION, SAM_EBICS3_VSECTION,
|
||||
SAM_EBICS3_MMUFLAGS, SAM_EBICS3_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_HAVE_NAND
|
||||
{ SAM_NFCCR_PSECTION, SAM_NFCCR_VSECTION,
|
||||
SAM_NFCCR_MMUFLAGS, SAM_NFCCR_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
/* SAMA5 Internal Peripherals
|
||||
*
|
||||
* Naming of peripheral sections differs between the SAMA5D3 and SAMA5D4.
|
||||
* There is nothing called SYSC in the SAMA5D4 memory map. The third
|
||||
* peripheral section is un-named in the SAMA5D4 memory map, but I have
|
||||
* chosen the name PERIPHC for this usage.
|
||||
*/
|
||||
|
||||
{ SAM_PERIPHA_PSECTION, SAM_PERIPHA_VSECTION,
|
||||
SAM_PERIPHA_MMUFLAGS, SAM_PERIPHA_NSECTIONS
|
||||
},
|
||||
|
||||
{ SAM_PERIPHB_PSECTION, SAM_PERIPHB_VSECTION,
|
||||
SAM_PERIPHB_MMUFLAGS, SAM_PERIPHB_NSECTIONS
|
||||
},
|
||||
|
||||
{ SAM_SYSC_PSECTION, SAM_SYSC_VSECTION,
|
||||
SAM_SYSC_MMUFLAGS, SAM_SYSC_NSECTIONS
|
||||
},
|
||||
|
||||
/* LCDC Framebuffer. This entry reprograms a part of one of the above
|
||||
* regions, making it non-cacheable and non-buffereable.
|
||||
*
|
||||
* If SDRAM will be reconfigured, then we will defer setup of the framebuffer
|
||||
* until after the SDRAM remapping (since the framebuffer problem resides) in
|
||||
* SDRAM.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_SAMA5_LCDC) && !defined(NEED_SDRAM_REMAPPING)
|
||||
{ CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE,
|
||||
MMU_IOFLAGS, SAMA5_LCDC_FBNSECTIONS
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
/* The number of entries in the mapping table */
|
||||
|
||||
#define NMAPPINGS \
|
||||
(sizeof(g_section_mapping) / sizeof(struct section_mapping_s))
|
||||
|
||||
const size_t g_num_mappings = NMAPPINGS;
|
||||
|
||||
#endif /* CONFIG_ARCH_ROMPGTABLE */
|
||||
|
||||
/* SAMA5 External SDRAM Memory. Final configuration. The SDRAM was
|
||||
* configured in a temporary state to support low-level ininitialization.
|
||||
* After the SDRAM has been fully initialized, this structure is used to
|
||||
* set the SDRM in its final, fully cache-able state.
|
||||
*/
|
||||
|
||||
#ifdef NEED_SDRAM_REMAPPING
|
||||
const struct section_mapping_s g_operational_mapping[] =
|
||||
{
|
||||
/* This entry reprograms the SDRAM entry, making it cacheable and
|
||||
* bufferable.
|
||||
*/
|
||||
|
||||
{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
|
||||
SAM_DDRCS_MMUFLAGS, SAM_DDRCS_NSECTIONS
|
||||
},
|
||||
|
||||
/* LCDC Framebuffer. This entry reprograms a part of one of the above
|
||||
* regions, making it non-cacheable and non-buffereable.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SAMA5_LCDC
|
||||
{ CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE,
|
||||
MMU_IOFLAGS, SAMA5_LCDC_FBNSECTIONS
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
/* The number of entries in the operational mapping table */
|
||||
|
||||
#define NREMAPPINGS \
|
||||
(sizeof(g_operational_mapping) / sizeof(struct section_mapping_s))
|
||||
|
||||
const size_t g_num_opmappings = NREMAPPINGS;
|
||||
|
||||
#endif /* NEED_SDRAM_REMAPPING */
|
||||
@@ -0,0 +1,286 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/sama5/sama5d4x_memorymap.c
|
||||
*
|
||||
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "mmu.h"
|
||||
|
||||
#include "chip/sam_memorymap.h"
|
||||
#include "sam_lcd.h"
|
||||
#include "sam_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/* This table describes how to map a set of 1Mb pages to space the physical
|
||||
* address space of the SAMA5.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_ARCH_ROMPGTABLE
|
||||
const struct section_mapping_s g_section_mapping[] =
|
||||
{
|
||||
/* SAMA5 Internal Memories */
|
||||
|
||||
/* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the
|
||||
* beginning of the .text region must appear at address at the address
|
||||
* specified in the VBAR. There are three ways to accomplish this:
|
||||
*
|
||||
* 1. By explicitly mapping the beginning of .text region with a page
|
||||
* table entry so that the virtual address zero maps to the beginning
|
||||
* of the .text region. VBAR == 0x0000:0000.
|
||||
*
|
||||
* 2. A second way is to map the use the AXI MATRIX remap register to
|
||||
* map physical address zero to the beginning of the text region,
|
||||
* either internal SRAM or EBI CS 0. Then we can set an identity
|
||||
* mapping to map the boot region at 0x0000:0000 to virtual address
|
||||
* 0x0000:00000. VBAR == 0x0000:0000.
|
||||
*
|
||||
* This method is used when booting from ISRAM or NOR FLASH. In
|
||||
& that case, vectors must lie at the beginning of NOFR FLASH.
|
||||
*
|
||||
* 3. Set the Cortex-A5 VBAR register so that the vector table address
|
||||
* is moved to a location other than 0x0000:0000.
|
||||
*
|
||||
* This is the method used when booting from SDRAM.
|
||||
*
|
||||
* - When executing from NOR FLASH, the first level bootloader is supposed
|
||||
* to provide the AXI MATRIX mapping for us at boot time base on the state
|
||||
* of the BMS pin. However, I have found that in the test environments
|
||||
* that I use, I cannot always be assured of that physical address mapping.
|
||||
*
|
||||
* So we do both here. If we are executing from NOR FLASH, then we provide
|
||||
* the MMU to map the physical address of FLASH to address 0x0000:0000;
|
||||
*
|
||||
* - If we are executing out of ISRAM, then the SAMA5 primary bootloader
|
||||
* probably copied us into ISRAM and set the AXI REMAP bit for us.
|
||||
*
|
||||
* - If we are executing from external SDRAM, then a secondary bootloader must
|
||||
* have loaded us into SDRAM. In this case, simply set the VBAR register
|
||||
* to the address of the vector table (not necessary at the beginning
|
||||
* or SDRAM).
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_LOWVECTORS) && !defined(CONFIG_SAMA5_BOOT_ISRAM) && \
|
||||
!defined(CONFIG_SAMA5_BOOT_SDRAM)
|
||||
{ CONFIG_FLASH_START, 0x00000000,
|
||||
MMU_ROMFLAGS, 1
|
||||
},
|
||||
#else
|
||||
{ SAM_BOOTMEM_PSECTION, SAM_BOOTMEM_VSECTION,
|
||||
SAM_BOOTMEM_MMUFLAGS, SAM_BOOTMEM_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
{ SAM_ROM_PSECTION, SAM_ROM_VSECTION,
|
||||
SAM_ROM_MMUFLAGS, SAM_ROM_NSECTIONS
|
||||
},
|
||||
{ SAM_NFCSRAM_PSECTION, SAM_NFCSRAM_VSECTION,
|
||||
SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS
|
||||
},
|
||||
|
||||
#ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */
|
||||
{ SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION,
|
||||
SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
{ SAM_VDEC_PSECTION, SAM_VDEC_VSECTION,
|
||||
SAM_VDEC_MMUFLAGS, SAM_VDEC_NSECTIONS
|
||||
},
|
||||
{ SAM_SMD_PSECTION, SAM_SMD_VSECTION,
|
||||
SAM_SMD_MMUFLAGS, SAM_SMD_NSECTIONS
|
||||
},
|
||||
{ SAM_UDPHSRAM_PSECTION, SAM_UDPHSRAM_VSECTION,
|
||||
SAM_UDPHSRAM_MMUFLAGS, SAM_UDPHSRAM_NSECTIONS
|
||||
},
|
||||
{ SAM_UHPOHCI_PSECTION, SAM_UHPOHCI_VSECTION,
|
||||
SAM_UHPOHCI_MMUFLAGS, SAM_UHPOHCI_NSECTIONS
|
||||
},
|
||||
{ SAM_UHPEHCI_PSECTION, SAM_UHPEHCI_VSECTION,
|
||||
SAM_UHPEHCI_MMUFLAGS, SAM_UHPEHCI_NSECTIONS
|
||||
},
|
||||
{ SAM_AXIMX_PSECTION, SAM_AXIMX_VSECTION,
|
||||
SAM_AXIMX_MMUFLAGS, SAM_AXIMX_NSECTIONS
|
||||
},
|
||||
{ SAM_DAP_PSECTION, SAM_DAP_VSECTION,
|
||||
SAM_DAP_MMUFLAGS, SAM_DAP_NSECTIONS
|
||||
},
|
||||
{ SAM_L2CC_PSECTION, SAM_L2CC_VSECTION,
|
||||
SAM_L2CC_MMUFLAGS, SAM_L2CC_NSECTIONS
|
||||
},
|
||||
|
||||
/* SAMA5 CS0 External Memories */
|
||||
|
||||
#ifdef CONFIG_SAMA5_EBICS0
|
||||
{ SAM_EBICS0_PSECTION, SAM_EBICS0_VSECTION,
|
||||
SAM_EBICS0_MMUFLAGS, SAM_EBICS0_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
/* SAMA5 External SDRAM Memory. The SDRAM is not usable until it has been
|
||||
* initialized. If we are running out of SDRAM now, we can assume that some
|
||||
* second level boot loader has properly configured SRAM for us. In that
|
||||
* case, we set the MMU flags for the final, fully cache-able state.
|
||||
*
|
||||
* Also, in this case, the mapping for the SDRAM was done in arm_head.S and
|
||||
* need not be repeated here.
|
||||
*
|
||||
* If we are running from ISRAM or NOR flash, then we will need to configure
|
||||
* the SDRAM ourselves. In this case, we set the MMU flags to the strongly
|
||||
* ordered, non-cacheable state. We need this direct access to SDRAM in
|
||||
* order to configure it. Once SDRAM has been initialized, it will be re-
|
||||
* configured in its final state.
|
||||
*/
|
||||
|
||||
#ifdef NEED_SDRAM_MAPPING
|
||||
{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
|
||||
MMU_STRONGLY_ORDERED, SAM_DDRCS_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
/* SAMA5 CS1-3 External Memories */
|
||||
|
||||
#ifdef CONFIG_SAMA5_EBICS1
|
||||
{ SAM_EBICS1_PSECTION, SAM_EBICS1_VSECTION,
|
||||
SAM_EBICS1_MMUFLAGS, SAM_EBICS1_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_EBICS2
|
||||
{ SAM_EBICS2_PSECTION, SAM_EBICS2_VSECTION,
|
||||
SAM_EBICS2_MMUFLAGS, SAM_EBICS2_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_EBICS3
|
||||
{ SAM_EBICS3_PSECTION, SAM_EBICS3_VSECTION,
|
||||
SAM_EBICS3_MMUFLAGS, SAM_EBICS3_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_HAVE_NAND
|
||||
{ SAM_NFCCR_PSECTION, SAM_NFCCR_VSECTION,
|
||||
SAM_NFCCR_MMUFLAGS, SAM_NFCCR_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
/* SAMA5 Internal Peripherals
|
||||
*
|
||||
* Naming of peripheral sections differs between the SAMA5D3 and SAMA5D4.
|
||||
* There is nothing called SYSC in the SAMA5D4 memory map. The third
|
||||
* peripheral section is un-named in the SAMA5D4 memory map, but I have
|
||||
* chosen the name PERIPHC for this usage.
|
||||
*/
|
||||
|
||||
{ SAM_PERIPHA_PSECTION, SAM_PERIPHA_VSECTION,
|
||||
SAM_PERIPHA_MMUFLAGS, SAM_PERIPHA_NSECTIONS
|
||||
},
|
||||
{ SAM_PERIPHB_PSECTION, SAM_PERIPHB_VSECTION,
|
||||
SAM_PERIPHB_MMUFLAGS, SAM_PERIPHB_NSECTIONS
|
||||
},
|
||||
{ SAM_PERIPHC_PSECTION, SAM_PERIPHC_VSECTION,
|
||||
SAM_PERIPHC_MMUFLAGS, SAM_PERIPHC_NSECTIONS
|
||||
},
|
||||
|
||||
/* LCDC Framebuffer. This entry reprograms a part of one of the above
|
||||
* regions, making it non-cacheable and non-buffereable.
|
||||
*
|
||||
* If SDRAM will be reconfigured, then we will defer setup of the framebuffer
|
||||
* until after the SDRAM remapping (since the framebuffer problem resides) in
|
||||
* SDRAM.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_SAMA5_LCDC) && !defined(NEED_SDRAM_REMAPPING)
|
||||
{ CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE,
|
||||
MMU_IOFLAGS, SAMA5_LCDC_FBNSECTIONS
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
/* The number of entries in the mapping table */
|
||||
|
||||
#define NMAPPINGS \
|
||||
(sizeof(g_section_mapping) / sizeof(struct section_mapping_s))
|
||||
|
||||
const size_t g_num_mappings = NMAPPINGS;
|
||||
|
||||
#endif /* CONFIG_ARCH_ROMPGTABLE */
|
||||
|
||||
/* SAMA5 External SDRAM Memory. Final configuration. The SDRAM was
|
||||
* configured in a temporary state to support low-level ininitialization.
|
||||
* After the SDRAM has been fully initialized, this structure is used to
|
||||
* set the SDRM in its final, fully cache-able state.
|
||||
*/
|
||||
|
||||
#ifdef NEED_SDRAM_REMAPPING
|
||||
const struct section_mapping_s g_operational_mapping[] =
|
||||
{
|
||||
/* This entry reprograms the SDRAM entry, making it cacheable and
|
||||
* bufferable.
|
||||
*/
|
||||
|
||||
{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
|
||||
SAM_DDRCS_MMUFLAGS, SAM_DDRCS_NSECTIONS
|
||||
},
|
||||
|
||||
/* LCDC Framebuffer. This entry reprograms a part of one of the above
|
||||
* regions, making it non-cacheable and non-buffereable.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SAMA5_LCDC
|
||||
{ CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE,
|
||||
MMU_IOFLAGS, SAMA5_LCDC_FBNSECTIONS
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
/* The number of entries in the operational mapping table */
|
||||
|
||||
#define NREMAPPINGS \
|
||||
(sizeof(g_operational_mapping) / sizeof(struct section_mapping_s))
|
||||
|
||||
const size_t g_num_opmappings = NREMAPPINGS;
|
||||
|
||||
#endif /* NEED_SDRAM_REMAPPING */
|
||||
Reference in New Issue
Block a user