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Merge remote-tracking branch 'origin/master'

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This commit is contained in:
Lok Tep
2015-11-09 23:47:33 +01:00
parent b654a6f467 3b4c71ef8d
commit 5eff3a202b
202 changed files with 7678 additions and 2460 deletions
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arch/arm/Kconfig
+2 -1
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@@ -426,7 +426,8 @@ config ARMV7M_MPU
config ARMV7M_MPU_NREGIONS
int "Number of MPU regions"
default 8
default 16 if ARCH_CORTEXM7
default 8 if !ARCH_CORTEXM7
depends on ARMV7M_MPU
---help---
This is the number of protection regions supported by the MPU.
arch/arm/include/lpc43xx/chip.h
+54 -29
View File
@@ -46,7 +46,7 @@
* Pre-processor Definitions
************************************************************************************/
/* Per the data sheet: LPC4350/30/20/10 Rev. 3.2 4 June 2012 */
/* Per the data sheet: LPC4350/30/20/10 Rev. 3.2 — 4 June 2012 */
/* Get customizations for each supported chip.
*
* SRAM Resources
@@ -74,37 +74,37 @@
* manager. This gives some symmetry to all of the members of the family.
*/
/* Per the user manual: UM10503, Rev. 1.2 � 8 June 2012 */
/* Per the user manual: UM10503, Rev. 1.2 — 8 June 2012 */
/* Get customizations for each supported chip.
*
* SRAM Resources
* --------------------- -------- ------- ------- ------- ------- -------
* Local SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357
* --------------------- -------- ------- ------- ------- ------- -------
* BANK 0 (0x1000 0000) 96Kb 96Kb 128Kb 128Kb 32Kb 32Kb
* BANK 1 (0x1008 0000) 40Kb 40Kb 72Kb 72Kb 40Kb 40Kb
* --------------------- -------- ------- ------- ------- ------- -------
* SUBTOTAL 136Kb 136Kb 200Kb 200Kb 72Kb 72Kb
* --------------------- -------- ------- ------- ------- ------- -------
* AHB SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357
* --------------------- -------- ------- ------- ------- ------- -------
* BANK 0 (0x2000 0000) 16Kb 48Kb 48Kb 48Kb 48Kb 48Kb
* BANK 1 (0x2000 8000) NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1
* BANK 2 (0x2000 c000) 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb
* --------------------- -------- ------- ------- ------- ------- -------
* SUBTOTAL 32Kb 64Kb 64Kb 64Kb 64Kb 64Kb
* --------------------- -------- ------- ------- ------- ------- -------
* TOTAL 168Kb 200Kb 264Kb 264Kb 136Kb 136Kb
* --------------------- -------- ------- ------- ------- ------- -------
* --------------------- -------- ------- ------- ------- ------- ------- -------
* Local SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 LPC4337
* --------------------- -------- ------- ------- ------- ------- ------- -------
* BANK 0 (0x1000 0000) 96Kb 96Kb 128Kb 128Kb 32Kb 32Kb 32Kb
* BANK 1 (0x1008 0000) 40Kb 40Kb 72Kb 72Kb 40Kb 40Kb 40Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
* SUBTOTAL 136Kb 136Kb 200Kb 200Kb 72Kb 72Kb 72Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
* AHB SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 LPC4337
* --------------------- -------- ------- ------- ------- ------- ------- -------
* BANK 0 (0x2000 0000) 16Kb 48Kb 48Kb 48Kb 48Kb 48Kb 48Kb
* BANK 1 (0x2000 8000) NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1
* BANK 2 (0x2000 c000) 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
* SUBTOTAL 32Kb 64Kb 64Kb 64Kb 64Kb 64Kb 64Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
* TOTAL 168Kb 200Kb 264Kb 264Kb 136Kb 136Kb 136Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
*
* --------------------- -------- ------- ------- ------- ------- -------
* FLASH LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357
* --------------------- -------- ------- ------- ------- ------- -------
* BANK A (0x1a00 0000) 256Kb 512Kb
* BANK B (0x1b00 8000) 256Kb 512Kb
* --------------------- -------- ------- ------- ------- ------- -------
* TOTAL None None None None 512Kb 1024Kb
* --------------------- -------- ------- ------- ------- ------- -------
* --------------------- -------- ------- ------- ------- ------- ------- -------
* FLASH LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 LPC4337
* --------------------- -------- ------- ------- ------- ------- ------- -------
* BANK A (0x1a00 0000) 256Kb 512Kb 512Kb
* BANK B (0x1b00 8000) 256Kb 512Kb 512Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
* TOTAL None None None None 512Kb 1024Kb 1024Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
*
* NOTE 1: The 64Kb of AHB of SRAM on the LPC4350/30/20 span all AHB SRAM
* banks but are treated as two banks of 48 an 16Kb by the NuttX memory
@@ -321,6 +321,32 @@
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4337JBD144)
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (512*1025)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
# define LPC43_NLCD (0) /* Has LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# define LPC43_USB1_ULPI (0) /* Have USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (1) /* One PWM interface */
# define LPC43_QEI (0) /* One Quadrature Encoder interface */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
@@ -606,7 +632,6 @@
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels (per ADC)*/
# define LPC43_NADC12 (1) /* ONne 12-bit ADC controllers (ADCHS)*/
>>>>>>> remotes/nuttx/arch/master
#else
# error "Unsupported LPC43xx chip"
#endif
arch/arm/include/stm32/chip.h
+38
View File
@@ -2307,6 +2307,44 @@
# define STM32_NRNG 0 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F429N) /* TFBGA216 1024/2048KiB flash 256KiB SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define STM32_NDMA 2 /* DMA1-2 */
# define STM32_NSPI 4 /* SPI1-4 */
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 168 /* GPIOA-K */
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#else
# error "Unsupported STM32 chip"
#endif
arch/arm/src/arm/up_assert.c
+3 -3
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@@ -316,9 +316,9 @@ static void _up_assert(int errorcode)
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
@@ -343,7 +343,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",
arch/arm/src/arm/up_doirq.c
+2 -2
View File
@@ -74,7 +74,7 @@
void up_doirq(int irq, uint32_t *regs)
{
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@@ -130,5 +130,5 @@ void up_doirq(int irq, uint32_t *regs)
current_regs = NULL;
#endif
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
}
arch/arm/src/arm/up_nommuhead.S
+1 -1
View File
@@ -125,7 +125,7 @@ __start:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
bl board_led_initialize
bl board_autoled_initialize
#endif
#ifdef CONFIG_STACK_COLORATION
arch/arm/src/arm/up_sigdeliver.c
+2 -2
View File
@@ -93,7 +93,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@@ -132,7 +132,7 @@ void up_sigdeliver(void)
/* Then restore the correct state for this thread of execution. */
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}
arch/arm/src/armv6-m/up_assert.c
+3 -3
View File
@@ -371,9 +371,9 @@ static void _up_assert(int errorcode)
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
@@ -398,7 +398,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",
arch/arm/src/armv6-m/up_doirq.c
+2 -2
View File
@@ -72,7 +72,7 @@
uint32_t *up_doirq(int irq, uint32_t *regs)
{
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@@ -116,6 +116,6 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
current_regs = savestate;
#endif
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
return regs;
}
arch/arm/src/armv6-m/up_sigdeliver.c
+2 -2
View File
@@ -98,7 +98,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@@ -143,7 +143,7 @@ void up_sigdeliver(void)
* execution.
*/
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}
arch/arm/src/armv7-a/arm_assert.c
+3 -3
View File
@@ -371,9 +371,9 @@ static void _up_assert(int errorcode)
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
@@ -397,7 +397,7 @@ void up_assert(const uint8_t *filename, int lineno)
#ifdef CONFIG_PRINT_TASKNAME
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",
arch/arm/src/armv7-a/arm_doirq.c
+2 -2
View File
@@ -74,7 +74,7 @@
uint32_t *arm_doirq(int irq, uint32_t *regs)
{
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@@ -128,6 +128,6 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
current_regs = NULL;
#endif
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
return regs;
}
arch/arm/src/armv7-a/arm_sigdeliver.c
+2 -2
View File
@@ -93,7 +93,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@@ -132,7 +132,7 @@ void up_sigdeliver(void)
/* Then restore the correct state for this thread of execution. */
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}
arch/arm/src/armv7-m/cache.h
+2
View File
@@ -76,9 +76,11 @@
#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory")
#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory")
#define ARM_DSB() arm_dsb(15)
#define ARM_ISB() arm_isb(15)
#define ARM_DMB() arm_dmb(15)
/****************************************************************************
* Inline Functions
arch/arm/src/armv7-m/mpu.h
+54 -12
View File
@@ -248,14 +248,56 @@ static inline void mpu_control(bool enable, bool hfnmiena, bool privdefena)
}
/****************************************************************************
* Name: mpu_userflash
* Name: mpu_priv_stronglyordered
*
* Description:
* Configure a region for privileged, strongly ordered memory
*
****************************************************************************/
#if defined(CONFIG_ARMV7M_HAVE_ICACHE) || defined(CONFIG_ARMV7M_DCACHE)
static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
uint8_t l2size;
uint8_t subregions;
/* Select the region */
putreg32(region, MPU_RNR);
/* Select the region base address */
putreg32((base & MPU_RBAR_ADDR_MASK) | region | MPU_RBAR_VALID, MPU_RBAR);
/* Select the region size and the sub-region map */
l2size = mpu_log2regionceil(size);
subregions = mpu_subregion(base, size, l2size);
/* The configure the region */
regval = MPU_RASR_ENABLE | /* Enable region */
MPU_RASR_SIZE_LOG2((uint32_t)l2size) | /* Region size */
((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions */
/* Not Cacheable */
/* Not Bufferable */
MPU_RASR_S | /* Shareable */
MPU_RASR_AP_RWNO; /* P:RW U:None */
putreg32(regval, MPU_RASR);
}
#endif
/****************************************************************************
* Name: mpu_user_flash
*
* Description:
* Configure a region for user program flash
*
****************************************************************************/
static inline void mpu_userflash(uintptr_t base, size_t size)
static inline void mpu_user_flash(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
@@ -286,14 +328,14 @@ static inline void mpu_userflash(uintptr_t base, size_t size)
}
/****************************************************************************
* Name: mpu_privflash
* Name: mpu_priv_flash
*
* Description:
* Configure a region for privileged program flash
*
****************************************************************************/
static inline void mpu_privflash(uintptr_t base, size_t size)
static inline void mpu_priv_flash(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
@@ -324,14 +366,14 @@ static inline void mpu_privflash(uintptr_t base, size_t size)
}
/****************************************************************************
* Name: mpu_userintsram
* Name: mpu_user_intsram
*
* Description:
* Configure a region as user internal SRAM
*
****************************************************************************/
static inline void mpu_userintsram(uintptr_t base, size_t size)
static inline void mpu_user_intsram(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
@@ -363,14 +405,14 @@ static inline void mpu_userintsram(uintptr_t base, size_t size)
}
/****************************************************************************
* Name: mpu_privintsram
* Name: mpu_priv_intsram
*
* Description:
* Configure a region as privileged internal SRAM
*
****************************************************************************/
static inline void mpu_privintsram(uintptr_t base, size_t size)
static inline void mpu_priv_intsram(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
@@ -402,14 +444,14 @@ static inline void mpu_privintsram(uintptr_t base, size_t size)
}
/****************************************************************************
* Name: mpu_userextsram
* Name: mpu_user_extsram
*
* Description:
* Configure a region as user external SRAM
*
****************************************************************************/
static inline void mpu_userextsram(uintptr_t base, size_t size)
static inline void mpu_user_extsram(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
@@ -442,14 +484,14 @@ static inline void mpu_userextsram(uintptr_t base, size_t size)
}
/****************************************************************************
* Name: mpu_privextsram
* Name: mpu_priv_extsram
*
* Description:
* Configure a region as privileged external SRAM
*
****************************************************************************/
static inline void mpu_privextsram(uintptr_t base, size_t size)
static inline void mpu_priv_extsram(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
arch/arm/src/armv7-m/up_assert.c
+3 -3
View File
@@ -380,9 +380,9 @@ static void _up_assert(int errorcode)
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
@@ -407,7 +407,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",
arch/arm/src/armv7-m/up_doirq.c
+2 -2
View File
@@ -72,7 +72,7 @@
uint32_t *up_doirq(int irq, uint32_t *regs)
{
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@@ -116,6 +116,6 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
current_regs = savestate;
#endif
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
return regs;
}
arch/arm/src/armv7-m/up_lazyexception.S
+1 -1
View File
@@ -1,5 +1,5 @@
/************************************************************************************************
* arch/arm/src/armv7-m/sam_vectors.S
* arch/arm/src/armv7-m/up_lazyexcption.S
*
* Copyright (C) 2009-2010, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/armv7-m/up_sigdeliver.c
+2 -2
View File
@@ -93,7 +93,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@@ -146,7 +146,7 @@ void up_sigdeliver(void)
* execution.
*/
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}
arch/arm/src/armv7-m/up_stackcheck.c
+1
View File
@@ -1,4 +1,5 @@
/****************************************************************************
* arch/arm/src/armv7-m/up_stackcheck.c
*
* Copyright (c) 2013, 2014 PX4 Development Team. All rights reserved.
*
arch/arm/src/common/up_allocateheap.c
+2 -2
View File
@@ -142,14 +142,14 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
#else
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif
arch/arm/src/common/up_createstack.c
+1 -1
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@@ -227,7 +227,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
up_stack_color(tcb->stack_alloc_ptr, tcb->adj_stack_size);
#endif
board_led_on(LED_STACKCREATED);
board_autoled_on(LED_STACKCREATED);
return OK;
}
arch/arm/src/common/up_initialize.c
+1 -1
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@@ -275,5 +275,5 @@ void up_initialize(void)
/* Initialize the L2 cache if present and selected */
up_l2ccinitialize();
board_led_on(LED_IRQSENABLED);
board_autoled_on(LED_IRQSENABLED);
}
arch/arm/src/dm320/dm320_allocateheap.c
+1 -1
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@@ -85,7 +85,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = (DM320_SDRAM_VADDR + CONFIG_RAM_SIZE) - g_idle_topstack;
}
arch/arm/src/dm320/dm320_boot.c
+2 -1
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@@ -225,8 +225,9 @@ void up_boot(void)
/* Set up the board-specific LEDs */
#ifdef CONFIG_ARCH_LEDS
board_led_initialize();
board_autoled_initialize();
#endif
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT
arch/arm/src/efm32/efm32_idle.c
+2 -2
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@@ -61,8 +61,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
arch/arm/src/efm32/efm32_pwm.c
+1 -1
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@@ -808,7 +808,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
/* Disable interrupts momentary to stop any ongoing timer processing and
* to prevent any concurrent access to the reset register.
*/
*/
flags = irqsave();
arch/arm/src/efm32/efm32_usbhost.c
+1 -1
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@@ -3949,7 +3949,7 @@ static int efm32_enumerate(FAR struct usbhost_connection_s *conn,
/* If this is a connection on the root hub, then we need to go to
* little more effort to get the device speed. If it is a connection
* on an external hub, then we already have that information.
*/
*/
#ifdef CONFIG_USBHOST_HUB
if (ROOTHUB(hport))
arch/arm/src/imx/imx_allocateheap.c
+1 -1
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@@ -85,7 +85,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = (IMX_SDRAM_VSECTION + CONFIG_RAM_SIZE) - g_idle_topstack;
}
arch/arm/src/imx/imx_boot.c
+2 -1
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@@ -216,8 +216,9 @@ void up_boot(void)
/* Set up the board-specific LEDs */
#ifdef CONFIG_ARCH_LEDS
board_led_initialize();
board_autoled_initialize();
#endif
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT
arch/arm/src/imx/imx_irq.c
+1 -1
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@@ -87,7 +87,7 @@ void up_irqinitialize(void)
/* Set masking of normal interrupts by priority. Writing all ones
* (or -1) to the NIMASK register sets the normal interrupt mask to
* -1 and does not disable any normal interrupt priority levels.
*/
*/
#ifndef CONFIG_SUPPRESS_INTERRUPTS
putreg32(-1, IMX_AITC_NIMASK); /* -1: No priority levels masked */
arch/arm/src/kinetis/kinetis_allocateheap.c
+2 -2
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@@ -131,7 +131,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
@@ -142,7 +142,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif
arch/arm/src/kinetis/kinetis_idle.c
+2 -2
View File
@@ -54,8 +54,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
arch/arm/src/kinetis/kinetis_mpuinit.c
+4 -4
View File
@@ -95,10 +95,10 @@ void kinetis_mpuinitialize(void)
/* Configure user flash and SRAM space */
mpu_userflash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_userintsram(datastart, dataend - datastart);
mpu_user_intsram(datastart, dataend - datastart);
/* Then enable the MPU */
@@ -117,7 +117,7 @@ void kinetis_mpuinitialize(void)
void kinetis_mpu_uheap(uintptr_t start, size_t size)
{
mpu_userintsram(start, size);
mpu_user_intsram(start, size);
}
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARMV7M_MPU */
arch/arm/src/kl/kl_idle.c
+2 -2
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@@ -58,8 +58,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
arch/arm/src/lpc11xx/lpc11_idle.c
+2 -2
View File
@@ -53,8 +53,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
arch/arm/src/lpc17xx/lpc17_allocateheap.c
+2 -2
View File
@@ -249,7 +249,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
@@ -260,7 +260,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif
arch/arm/src/lpc17xx/lpc17_idle.c
+2 -2
View File
@@ -55,8 +55,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
arch/arm/src/lpc17xx/lpc17_mpuinit.c
+4 -4
View File
@@ -95,10 +95,10 @@ void lpc17_mpuinitialize(void)
/* Configure user flash and SRAM space */
mpu_userflash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_userintsram(datastart, dataend - datastart);
mpu_user_intsram(datastart, dataend - datastart);
/* Then enable the MPU */
@@ -117,7 +117,7 @@ void lpc17_mpuinitialize(void)
void lpc17_mpu_uheap(uintptr_t start, size_t size)
{
mpu_userintsram(start, size);
mpu_user_intsram(start, size);
}
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARMV7M_MPU */
arch/arm/src/lpc214x/lpc214x_head.S
+1 -1
View File
@@ -592,7 +592,7 @@ __start:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
bl board_led_initialize
bl board_autoled_initialize
#endif
/* Then jump to OS entry */
arch/arm/src/lpc2378/lpc23xx_head.S
+1 -1
View File
@@ -193,7 +193,7 @@ __start:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
bl board_led_initialize
bl board_autoled_initialize
#endif
/* Then jump to OS entry */
arch/arm/src/lpc31xx/lpc31_allocateheap.c
+1 -1
View File
@@ -180,7 +180,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = LPC31_HEAP_VEND - g_idle_topstack;
}
arch/arm/src/lpc43xx/Kconfig
+8
View File
@@ -34,6 +34,9 @@ config ARCH_CHIP_LPC4330FET180
config ARCH_CHIP_LPC4330FET256
bool "LPC4330FET256"
config ARCH_CHIP_LPC4337JBD144
bool "LPC4337JBD144"
config ARCH_CHIP_LPC4350FBD208
bool "LPC4350FBD208"
@@ -81,6 +84,11 @@ config ARCH_FAMILY_LPC4330
default y if ARCH_CHIP_LPC4330FBD144 || ARCH_CHIP_LPC4330FET100 || ARCH_CHIP_LPC4330FET180 || ARCH_CHIP_LPC4330FET256
select ARCH_HAVE_TICKLESS
config ARCH_FAMILY_LPC4337
bool
default y if ARCH_CHIP_LPC4337JBD144
select ARCH_HAVE_TICKLESS
config ARCH_FAMILY_LPC4350
bool
default y if ARCH_CHIP_LPC4350FBD208 || ARCH_CHIP_LPC4350FET180 || ARCH_CHIP_LPC4350FET256
arch/arm/src/lpc43xx/chip.h
+4
View File
@@ -97,6 +97,10 @@
# define ARMV7M_PERIPHERAL_INTERRUPTS 53
# include "chip/lpc4310203050_memorymap.h"
# include "chip/lpc4310203050_pinconfig.h"
#elif defined(CONFIG_ARCH_CHIP_LPC4337JBD144)
# define ARMV7M_PERIPHERAL_INTERRUPTS 53
# include "chip/lpc435357_memorymap.h"
# include "chip/lpc4357fet256_pinconfig.h"
#elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208)
# define ARMV7M_PERIPHERAL_INTERRUPTS 53
# include "chip/lpc4310203050_memorymap.h"
arch/arm/src/lpc43xx/chip/lpc43_timer.h
+68 -68
View File
@@ -68,77 +68,77 @@
/* Register addresses ***************************************************************/
#define LPC43_TMR0_IR (LPC43_TMR0_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR0_TCR (LPC43_TMR0_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR0_TC (LPC43_TMR0_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR0_PR (LPC43_TMR0_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR0_PC (LPC43_TMR0_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR0_MCR (LPC43_TMR0_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR0_MR0 (LPC43_TMR0_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR0_MR1 (LPC43_TMR0_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR0_MR2 (LPC43_TMR0_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR0_MR3 (LPC43_TMR0_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR0_CCR (LPC43_TMR0_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR0_CR0 (LPC43_TMR0_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR0_CR1 (LPC43_TMR0_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR0_CR2 (LPC43_TMR0_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR0_CR3 (LPC43_TMR0_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR0_EMR (LPC43_TMR0_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR0_CTCR (LPC43_TMR0_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR0_IR (LPC43_TIMER0_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR0_TCR (LPC43_TIMER0_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR0_TC (LPC43_TIMER0_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR0_PR (LPC43_TIMER0_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR0_PC (LPC43_TIMER0_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR0_MCR (LPC43_TIMER0_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR0_MR0 (LPC43_TIMER0_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR0_MR1 (LPC43_TIMER0_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR0_MR2 (LPC43_TIMER0_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR0_MR3 (LPC43_TIMER0_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR0_CCR (LPC43_TIMER0_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR0_CR0 (LPC43_TIMER0_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR0_CR1 (LPC43_TIMER0_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR0_CR2 (LPC43_TIMER0_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR0_CR3 (LPC43_TIMER0_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR0_EMR (LPC43_TIMER0_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR0_CTCR (LPC43_TIMER0_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR1_IR (LPC43_TMR1_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR1_TCR (LPC43_TMR1_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR1_TC (LPC43_TMR1_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR1_PR (LPC43_TMR1_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR1_PC (LPC43_TMR1_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR1_MCR (LPC43_TMR1_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR1_MR0 (LPC43_TMR1_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR1_MR1 (LPC43_TMR1_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR1_MR2 (LPC43_TMR1_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR1_MR3 (LPC43_TMR1_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR1_CCR (LPC43_TMR1_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR1_CR0 (LPC43_TMR1_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR1_CR1 (LPC43_TMR1_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR1_CR2 (LPC43_TMR1_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR1_CR3 (LPC43_TMR1_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR1_EMR (LPC43_TMR1_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR1_CTCR (LPC43_TMR1_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR1_IR (LPC43_TIMER1_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR1_TCR (LPC43_TIMER1_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR1_TC (LPC43_TIMER1_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR1_PR (LPC43_TIMER1_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR1_PC (LPC43_TIMER1_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR1_MCR (LPC43_TIMER1_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR1_MR0 (LPC43_TIMER1_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR1_MR1 (LPC43_TIMER1_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR1_MR2 (LPC43_TIMER1_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR1_MR3 (LPC43_TIMER1_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR1_CCR (LPC43_TIMER1_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR1_CR0 (LPC43_TIMER1_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR1_CR1 (LPC43_TIMER1_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR1_CR2 (LPC43_TIMER1_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR1_CR3 (LPC43_TIMER1_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR1_EMR (LPC43_TIMER1_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR1_CTCR (LPC43_TIMER1_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR2_IR (LPC43_TMR2_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR2_TCR (LPC43_TMR2_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR2_TC (LPC43_TMR2_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR2_PR (LPC43_TMR2_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR2_PC (LPC43_TMR2_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR2_MCR (LPC43_TMR2_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR2_MR0 (LPC43_TMR2_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR2_MR1 (LPC43_TMR2_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR2_MR2 (LPC43_TMR2_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR2_MR3 (LPC43_TMR2_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR2_CCR (LPC43_TMR2_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR2_CR0 (LPC43_TMR2_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR2_CR1 (LPC43_TMR2_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR2_CR2 (LPC43_TMR2_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR2_CR3 (LPC43_TMR2_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR2_EMR (LPC43_TMR2_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR2_CTCR (LPC43_TMR2_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR2_IR (LPC43_TIMER2_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR2_TCR (LPC43_TIMER2_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR2_TC (LPC43_TIMER2_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR2_PR (LPC43_TIMER2_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR2_PC (LPC43_TIMER2_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR2_MCR (LPC43_TIMER2_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR2_MR0 (LPC43_TIMER2_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR2_MR1 (LPC43_TIMER2_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR2_MR2 (LPC43_TIMER2_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR2_MR3 (LPC43_TIMER2_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR2_CCR (LPC43_TIMER2_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR2_CR0 (LPC43_TIMER2_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR2_CR1 (LPC43_TIMER2_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR2_CR2 (LPC43_TIMER2_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR2_CR3 (LPC43_TIMER2_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR2_EMR (LPC43_TIMER2_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR2_CTCR (LPC43_TIMER2_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR3_IR (LPC43_TMR3_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR3_TCR (LPC43_TMR3_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR3_TC (LPC43_TMR3_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR3_PR (LPC43_TMR3_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR3_PC (LPC43_TMR3_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR3_MCR (LPC43_TMR3_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR3_MR0 (LPC43_TMR3_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR3_MR1 (LPC43_TMR3_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR3_MR2 (LPC43_TMR3_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR3_MR3 (LPC43_TMR3_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR3_CCR (LPC43_TMR3_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR3_CR0 (LPC43_TMR3_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR3_CR1 (LPC43_TMR3_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR3_CR2 (LPC43_TMR3_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR3_CR3 (LPC43_TMR3_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR3_EMR (LPC43_TMR3_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR3_CTCR (LPC43_TMR3_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR3_IR (LPC43_TIMER3_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR3_TCR (LPC43_TIMER3_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR3_TC (LPC43_TIMER3_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR3_PR (LPC43_TIMER3_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR3_PC (LPC43_TIMER3_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR3_MCR (LPC43_TIMER3_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR3_MR0 (LPC43_TIMER3_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR3_MR1 (LPC43_TIMER3_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR3_MR2 (LPC43_TIMER3_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR3_MR3 (LPC43_TIMER3_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR3_CCR (LPC43_TIMER3_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR3_CR0 (LPC43_TIMER3_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR3_CR1 (LPC43_TIMER3_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR3_CR2 (LPC43_TIMER3_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR3_CR3 (LPC43_TIMER3_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR3_EMR (LPC43_TIMER3_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR3_CTCR (LPC43_TIMER3_BASE+LPC43_TMR_CTCR_OFFSET)
/* Register bit definitions *********************************************************/
/* Registers holding 32-bit numeric values (no bit field definitions):
arch/arm/src/lpc43xx/lpc43_allocateheap.c
+1 -1
View File
@@ -248,7 +248,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
/* Start with the first SRAM region */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
}
arch/arm/src/lpc43xx/lpc43_idle.c
+2 -2
View File
@@ -57,8 +57,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
arch/arm/src/lpc43xx/lpc43_mpuinit.c
+4 -4
View File
@@ -95,10 +95,10 @@ void lpc43_mpuinitialize(void)
/* Configure user flash and SRAM space */
mpu_userflash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_userintsram(datastart, dataend - datastart);
mpu_user_intsram(datastart, dataend - datastart);
/* Then enable the MPU */
@@ -117,7 +117,7 @@ void lpc43_mpuinitialize(void)
void lpc43_mpu_uheap(uintptr_t start, size_t size)
{
mpu_userintsram(start, size);
mpu_user_intsram(start, size);
}
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARMV7M_MPU */
arch/arm/src/lpc43xx/lpc43_usb0dev.c
+1 -1
View File
@@ -2847,4 +2847,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
g_usbdev.driver = NULL;
return OK;
}
>>>>>>> remotes/nuttx/arch/master
arch/arm/src/nuc1xx/nuc_idle.c
+2 -2
View File
@@ -58,8 +58,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

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