SAMA5: Add DMA controller register definitions

2026-05-21 04:52:02 +08:00 · 2013-08-03 12:13:42 -06:00
parent 6422792f57
commit 5cdc3db214
3 changed files with 793 additions and 1 deletions
@@ -5274,3 +5274,5 @@
 	  interrupts (2013-8-3).
 	* arch/*/src/*/*_irq.c:  Standardize configuration variables used
 	  to enable interrupt controller debug output (2013-8-3).
+	* arch/arm/src/sama5/chip/sam_dmac.h: Add register definitions for the
+	  SAMA5 DMA controller (2013-8-3).
@@ -58,7 +58,7 @@
 #define SAM_DMAC_SREQ_OFFSET           0x08 /* DMAC Software Single Request Register */
 #define SAM_DMAC_CREQ_OFFSET           0x0c /* DMAC Software Chunk Transfer Request Register */
 #define SAM_DMAC_LAST_OFFSET           0x10 /* DMAC Software Last Transfer Flag Register */
-                                            /* 0x014-0x18: Reserved */
+                                            /* 0x014: Reserved */
 #define SAM_DMAC_EBCIER_OFFSET         0x18 /* DMAC Error Enable */
 #define SAM_DMAC_EBCIDR_OFFSET         0x1C /* DMAC Error Disable */
 #define SAM_DMAC_EBCIMR_OFFSET         0x20 /* DMAC Error Mask */