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https://github.com/apache/nuttx.git
synced 2026-06-07 09:18:00 +08:00
Xtensa: A little more interrupt handling logic
This commit is contained in:
Gregory Nutt
@@ -35,18 +35,6 @@ config XTENSA_NCOPROCESSORS
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int "Number of co-processors"
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default 1
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config XTENSA_INT_NLEVELS
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int "Number of interrupt levels"
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default 5
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config XTENSA_EXCM_LEVEL
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int "Level masked by PS.EXCM"
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default 3
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config XTENSA_HAVE_LOOPS
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bool "Zero overhead loops"
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default n
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config XTENSA_HAVE_INTERRUPTS
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bool
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default n
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File diff suppressed because it is too large
Load Diff
+24
-24
@@ -48,6 +48,7 @@
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#include <nuttx/irq.h>
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#include <arch/types.h>
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#include <arch/chip/core-isa.h>
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/* Include architecture-specific IRQ definitions */
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@@ -72,32 +73,31 @@
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/* IRQ Stack Frame Format. Each value is a uint32_t register index */
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#define REG_EXIT (0) /* Exit point for dispatch */
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#define REG_PC (1) /* Return PC */
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#define REG_PS (2) /* Return PS */
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#define REG_A0 (3)
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#define REG_A1 (4) /* Stack pointer before interrupt */
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#define REG_A2 (5)
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#define REG_A3 (6)
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#define REG_A4 (7)
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#define REG_A5 (8)
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#define REG_A6 (9)
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#define REG_A7 (10)
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#define REG_A8 (11)
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#define REG_A9 (12)
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#define REG_A10 (13)
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#define REG_A11 (14)
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#define REG_A12 (15)
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#define REG_A13 (16)
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#define REG_A14 (17)
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#define REG_A15 (18)
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#define REG_SAR (19)
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#define REG_EXCCAUSE (20)
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#define REG_EXCVADDR (21)
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#define REG_PC (0) /* Return PC */
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#define REG_PS (1) /* Return PS */
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#define REG_A0 (2)
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#define REG_A1 (3) /* Stack pointer before interrupt */
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#define REG_A2 (4)
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#define REG_A3 (5)
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#define REG_A4 (6)
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#define REG_A5 (7)
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#define REG_A6 (8)
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#define REG_A7 (9)
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#define REG_A8 (10)
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#define REG_A9 (11)
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#define REG_A10 (12)
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#define REG_A11 (13)
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#define REG_A12 (14)
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#define REG_A13 (15)
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#define REG_A14 (16)
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#define REG_A15 (17)
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#define REG_SAR (18)
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#define REG_EXCCAUSE (19)
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#define REG_EXCVADDR (20)
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#define _REG_LOOPS_START (22)
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#define _REG_LOOPS_START (21)
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#ifdef CONFIG_XTENSA_HAVE_LOOPS
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#ifdef XTENSA_HAVE_LOOPS
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# define REG_LBEG (_REG_LOOPS_START + 0)
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# define REG_LEND (_REG_LOOPS_START + 1)
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# define REG_LCOUNT (_REG_LOOPS_START + 2)
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@@ -31,6 +31,8 @@
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*
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****************************************************************************/
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.file "xtensa_context.S"
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/* XTENSA CONTEXT SAVE AND RESTORE ROUTINES
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*
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* Low-level Call0 functions for handling generic context save and restore
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@@ -57,14 +59,15 @@
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/chip/core-isa.h>
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#include <arch/irq.h>
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#ifdef CONFIG_XTENSA_USE_OVLY
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# include <xtensa/overlay_os_asm.h>
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#endif
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#warning REVIST XCHAL_EXTRA_SA_SIZE is not yet provided
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#define XCHAL_EXTRA_SA_SIZE 0 /* REMOVE ME */
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#warning REVIST XTENSA_EXTRA_SA_SIZE is not yet provided
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#define XTENSA_EXTRA_SA_SIZE 0 /* REMOVE ME */
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/****************************************************************************
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* Public Functions
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@@ -155,7 +158,7 @@ _xtensa_context_save:
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rsr a3, SAR
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s32i a3, sp, (4 * REG_SAR)
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#ifdef CONFIG_XTENSA_HAVE_LOOPS
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#ifdef XTENSA_HAVE_LOOPS
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rsr a3, LBEG
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s32i a3, sp, (4 * REG_LBEG)
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rsr a3, LEND
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@@ -172,7 +175,7 @@ _xtensa_context_save:
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s32i a3, sp, (4 * REG_VPRI)
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#endif
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#if XCHAL_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI)
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#if XTENSA_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI)
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mov a9, a0 /* Preserve ret addr */
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#endif
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@@ -180,7 +183,7 @@ _xtensa_context_save:
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/* To spill the reg windows, temp. need pre-interrupt stack ptr and
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* a4-15. Need to save a9,12,13 temporarily (in frame temps) and
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* recover originals. Interrupts need to be disabled below
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* CONFIG_XTENSA_EXCM_LEVEL and window overflow and underflow exceptions
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* XTENSA_EXCM_LEVEL and window overflow and underflow exceptions
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* disabled (assured by PS.EXCM == 1).
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*/
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@@ -210,7 +213,7 @@ _xtensa_context_save:
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l32i a9, sp, (4 * REG_TMP2)
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#endif
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#if XCHAL_EXTRA_SA_SIZE > 0
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#if XTENSA_EXTRA_SA_SIZE > 0
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/* NOTE: Normally the xthal_save_extra_nw macro only affects address
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* registers a2-a5. It is theoretically possible for Xtensa processor
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* designers to write TIE that causes more address registers to be
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@@ -221,14 +224,14 @@ _xtensa_context_save:
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*/
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addi a2, sp, (4 * REG_EXTRA) /* Where to save it */
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#if XCHAL_EXTRA_SA_ALIGN > 16
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movi a3, -XCHAL_EXTRA_SA_ALIGN
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#if XTENSA_EXTRA_SA_ALIGN > 16
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movi a3, -XTENSA_EXTRA_SA_ALIGN
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and a2, a2, a3 /* Align dynamically >16 bytes */
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#endif
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call0 xthal_save_extra_nw /* Destroys a0,2,3,4,5 */
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#endif
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#if XCHAL_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI)
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#if XTENSA_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI)
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mov a0, a9 /* Retrieve ret addr */
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#endif
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@@ -288,7 +291,7 @@ _xtensa_full_context_restore:
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_xtensa_context_restore:
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#if XCHAL_EXTRA_SA_SIZE > 0
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#if XTENSA_EXTRA_SA_SIZE > 0
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/* NOTE: Normally the xthal_restore_extra_nw macro only affects address
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* registers a2-a5. It is theoretically possible for Xtensa processor
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* designers to write TIE that causes more address registers to be
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@@ -301,15 +304,15 @@ _xtensa_context_restore:
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mov a13, a0 /* Preserve ret addr */
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addi a2, sp, (4 * REG_EXTRA) /* Where to find it */
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#if XCHAL_EXTRA_SA_ALIGN > 16
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movi a3, -XCHAL_EXTRA_SA_ALIGN
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#if XTENSA_EXTRA_SA_ALIGN > 16
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movi a3, -XTENSA_EXTRA_SA_ALIGN
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and a2, a2, a3 /* Align dynamically >16 bytes */
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#endif
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call0 xthal_restore_extra_nw /* Destroys a0,2,3,4,5 */
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mov a0, a13 /* Retrieve ret addr */
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#endif
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#ifdef CONFIG_XTENSA_HAVE_LOOPS
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#ifdef XTENSA_HAVE_LOOPS
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l32i a2, sp, (4 * REG_LBEG)
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l32i a3, sp, (4 * REG_LEND)
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wsr a2, LBEG
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@@ -31,367 +31,15 @@
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*
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****************************************************************************/
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/* XTENSA CONTEXT SAVE AND RESTORE ROUTINES
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*
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* Low-level Call0 functions for handling generic context save and restore of
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* registers not specifically addressed by the interrupt vectors and handlers.
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* Those registers (not handled by these functions) are PC, PS, A0, A1 (SP).
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* Except for the calls to RTOS functions, this code is generic to Xtensa.
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*
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* Note that in Call0 ABI, interrupt handlers are expected to preserve the callee-
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* save regs (A12-A15), which is always the case if the handlers are coded in C.
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* However A12, A13 are made available as scratch registers for interrupt dispatch
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* code, so are presumed saved anyway, and are always restored even in Call0 ABI.
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* Only A14, A15 are truly handled as callee-save regs.
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*
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* Because Xtensa is a configurable architecture, this port supports all user
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* generated configurations (except restrictions stated in the release notes).
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* This is accomplished by conditional compilation using macros and functions
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* defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
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* Only the processor state included in your configuration is saved and restored,
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* including any processor state added by user configuration options or TIE.
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*/
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.file "xtensa_coproc.S"
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "xtensa_context.h"
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#ifdef CONFIG_XTENSA_USE_OVLY
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# include <xtensa/overlay_os_asm.h>
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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.text
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/****************************************************************************
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* Name: _xt_coproc_init
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*
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* Description:
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* Initializes global co-processor management data, setting all co-
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* processors to "unowned". Leaves CPENABLE as it found it (does NOT clear
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* it).
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*
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* Called during initialization of the RTOS, before any threads run.
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*
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* This may be called from normal Xtensa single-threaded application code
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* which might use co-processors. The Xtensa run-time initialization enables
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* all co-processors. They must remain enabled here, else a co-processor
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* exception might occur outside of a thread, which the exception handler
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* doesn't expect.
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*
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* Entry Conditions:
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* - Xtensa single-threaded run-time environment is in effect.
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* No thread is yet running.
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*
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* Exit conditions:
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* - None.
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*
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* Obeys ABI conventions per prototype:
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* void _xt_coproc_init(void)
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*
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****************************************************************************/
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#if CONFIG_XTENSA_NCOPROCESSORS > 0
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.global _xt_coproc_init
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.type _xt_coproc_init,@function
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.align 4
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.literal_position
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.align 4
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_xt_coproc_init:
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ENTRY0
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/* Initialize thread co-processor ownerships to 0 (unowned). */
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movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */
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addi a3, a2, (XCHAL_CP_MAX*portNUM_PROCESSORS) << 2 /* a3 = top+1 of owner array */
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movi a4, 0 /* a4 = 0 (unowned) */
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1: s32i a4, a2, 0
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addi a2, a2, 4
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bltu a2, a3, 1b
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RET0
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#endif
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/****************************************************************************
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* Name: _xt_coproc_release
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*
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* Description:
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* Releases any and all co-processors owned by a given thread. The thread
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* is identified by it's co-processor state save area defined in
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* xtensa_context.h.
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*
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* Must be called before a thread's co-proc save area is deleted to avoid
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* memory corruption when the exception handler tries to save the state.
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* May be called when a thread terminates or completes but does not delete
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* the co-proc save area, to avoid the exception handler having to save
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* the thread's co-proc state before another thread can use it
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* (optimization).
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*
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* Entry Conditions:
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* - A2 = Pointer to base of co-processor state save area.
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*
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* Exit conditions:
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* - None.
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*
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* Obeys ABI conventions per prototype:
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* void _xt_coproc_release(void * coproc_sa_base)
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*
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****************************************************************************/
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#if CONFIG_XTENSA_NCOPROCESSORS > 0
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.global _xt_coproc_release
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.type _xt_coproc_release,@function
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.align 4
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.literal_position
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.align 4
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_xt_coproc_release:
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ENTRY0 /* a2 = base of save area */
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getcoreid a5
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movi a3, XCHAL_CP_MAX << 2
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mull a5, a5, a3
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movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */
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add a3, a3, a5
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addi a4, a3, XCHAL_CP_MAX << 2 /* a4 = top+1 of owner array */
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movi a5, 0 /* a5 = 0 (unowned) */
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rsil a6, CONFIG_XTENSA_EXCM_LEVEL /* Lock interrupts */
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1: l32i a7, a3, 0 /* a7 = owner at a3 */
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bne a2, a7, 2f /* if (coproc_sa_base == owner) */
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s32i a5, a3, 0 /* owner = unowned */
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2: addi a3, a3, 1 << 2 /* a3 = next entry in owner array */
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bltu a3, a4, 1b /* Repeat until end of array */
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3: wsr a6, PS /* Restore interrupts */
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RET0
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#endif
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/****************************************************************************
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* Name: _xt_coproc_savecs
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*
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* Description:
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* If there is a current thread and it has a coprocessor state save area,
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* then save all callee-saved state into this area. This function is called
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* from the solicited context switch handler. It calls a system-specific
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* function to get the coprocessor save area base address.
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*
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* Entry conditions:
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* - The thread being switched out is still the current thread.
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* - CPENABLE state reflects which coprocessors are active.
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* - Registers have been saved/spilled already.
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*
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* Exit conditions:
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* - All necessary CP callee-saved state has been saved.
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* - Registers a2-a7, a13-a15 have been trashed.
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*
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* Must be called from assembly code only, using CALL0.
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*
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****************************************************************************/
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#if CONFIG_XTENSA_NCOPROCESSORS > 0
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.extern _xt_coproc_sa_offset /* external reference */
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.global _xt_coproc_savecs
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.type _xt_coproc_savecs,@function
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.align 4
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.literal_position
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.align 4
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_xt_coproc_savecs:
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/* At entry, CPENABLE should be showing which CPs are enabled. */
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rsr a2, CPENABLE /* a2 = which CPs are enabled */
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beqz a2, .Ldone /* quick exit if none */
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mov a14, a0 /* save return address */
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call0 XT_RTOS_CP_STATE /* get address of CP save area */
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mov a0, a14 /* restore return address */
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beqz a15, .Ldone /* if none then nothing to do */
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s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */
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movi a13, _xt_coproc_sa_offset /* array of CP save offsets */
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l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */
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#if XCHAL_CP0_SA_SIZE
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bbci.l a2, 0, 2f /* CP 0 not enabled */
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l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */
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add a3, a14, a15 /* a3 = save area for CP 0 */
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xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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#if XCHAL_CP1_SA_SIZE
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bbci.l a2, 1, 2f /* CP 1 not enabled */
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l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */
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add a3, a14, a15 /* a3 = save area for CP 1 */
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xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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#if XCHAL_CP2_SA_SIZE
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bbci.l a2, 2, 2f
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l32i a14, a13, 8
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add a3, a14, a15
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xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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#if XCHAL_CP3_SA_SIZE
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bbci.l a2, 3, 2f
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l32i a14, a13, 12
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add a3, a14, a15
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xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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#if XCHAL_CP4_SA_SIZE
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bbci.l a2, 4, 2f
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l32i a14, a13, 16
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add a3, a14, a15
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xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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#if XCHAL_CP5_SA_SIZE
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bbci.l a2, 5, 2f
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l32i a14, a13, 20
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add a3, a14, a15
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||||
xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||
2:
|
||||
#endif
|
||||
|
||||
#if XCHAL_CP6_SA_SIZE
|
||||
bbci.l a2, 6, 2f
|
||||
l32i a14, a13, 24
|
||||
add a3, a14, a15
|
||||
xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||
2:
|
||||
#endif
|
||||
|
||||
#if XCHAL_CP7_SA_SIZE
|
||||
bbci.l a2, 7, 2f
|
||||
l32i a14, a13, 28
|
||||
add a3, a14, a15
|
||||
xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||
2:
|
||||
#endif
|
||||
|
||||
.Ldone:
|
||||
ret
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: _xt_coproc_restorecs
|
||||
*
|
||||
* Description:
|
||||
* Restore any callee-saved coprocessor state for the incoming thread.
|
||||
* This function is called from coprocessor exception handling, when
|
||||
* giving ownership to a thread that solicited a context switch earlier.
|
||||
* It calls a system-specific function to get the coprocessor save area
|
||||
* base address.
|
||||
*
|
||||
* Entry conditions:
|
||||
* - The incoming thread is set as the current thread.
|
||||
* - CPENABLE is set up correctly for all required coprocessors.
|
||||
* - a2 = mask of coprocessors to be restored.
|
||||
*
|
||||
* Exit conditions:
|
||||
* - All necessary CP callee-saved state has been restored.
|
||||
* - CPENABLE - unchanged.
|
||||
* - Registers a2-a7, a13-a15 have been trashed.
|
||||
*
|
||||
* Must be called from assembly code only, using CALL0.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if CONFIG_XTENSA_NCOPROCESSORS > 0
|
||||
.global _xt_coproc_restorecs
|
||||
.type _xt_coproc_restorecs,@function
|
||||
.align 4
|
||||
.literal_position
|
||||
.align 4
|
||||
_xt_coproc_restorecs:
|
||||
|
||||
mov a14, a0 /* Save return address */
|
||||
call0 XT_RTOS_CP_STATE /* Get address of CP save area */
|
||||
mov a0, a14 /* Restore return address */
|
||||
beqz a15, .Ldone2 /* If none then nothing to do */
|
||||
l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */
|
||||
xor a3, a3, a2 /* Clear the ones being restored */
|
||||
s32i a3, a15, XT_CP_CS_ST /* Update saved CP mask */
|
||||
movi a13, _xt_coproc_sa_offset /* Array of CP save offsets */
|
||||
l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */
|
||||
|
||||
#if XCHAL_CP0_SA_SIZE
|
||||
bbci.l a2, 0, 2f /* CP 0 not enabled */
|
||||
l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */
|
||||
add a3, a14, a15 /* a3 = save area for CP 0 */
|
||||
xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||
2:
|
||||
#endif
|
||||
|
||||
#if XCHAL_CP1_SA_SIZE
|
||||
bbci.l a2, 1, 2f /* CP 1 not enabled */
|
||||
l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */
|
||||
add a3, a14, a15 /* a3 = save area for CP 1 */
|
||||
xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||
2:
|
||||
#endif
|
||||
|
||||
#if XCHAL_CP2_SA_SIZE
|
||||
bbci.l a2, 2, 2f
|
||||
l32i a14, a13, 8
|
||||
add a3, a14, a15
|
||||
xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||
2:
|
||||
#endif
|
||||
|
||||
#if XCHAL_CP3_SA_SIZE
|
||||
bbci.l a2, 3, 2f
|
||||
l32i a14, a13, 12
|
||||
add a3, a14, a15
|
||||
xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||
2:
|
||||
#endif
|
||||
|
||||
#if XCHAL_CP4_SA_SIZE
|
||||
bbci.l a2, 4, 2f
|
||||
l32i a14, a13, 16
|
||||
add a3, a14, a15
|
||||
xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||
2:
|
||||
#endif
|
||||
|
||||
#if XCHAL_CP5_SA_SIZE
|
||||
bbci.l a2, 5, 2f
|
||||
l32i a14, a13, 20
|
||||
add a3, a14, a15
|
||||
xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||
2:
|
||||
#endif
|
||||
|
||||
#if XCHAL_CP6_SA_SIZE
|
||||
bbci.l a2, 6, 2f
|
||||
l32i a14, a13, 24
|
||||
add a3, a14, a15
|
||||
xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||
2:
|
||||
#endif
|
||||
|
||||
#if XCHAL_CP7_SA_SIZE
|
||||
bbci.l a2, 7, 2f
|
||||
l32i a14, a13, 28
|
||||
add a3, a14, a15
|
||||
xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||
2:
|
||||
#endif
|
||||
|
||||
.Ldone2:
|
||||
ret
|
||||
|
||||
#endif
|
||||
|
||||
@@ -46,7 +46,9 @@
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <arch/chip/core-isa.h>
|
||||
|
||||
#include "sched/sched.h"
|
||||
#include "xtensa.h"
|
||||
@@ -125,7 +127,7 @@ static inline void xtensa_registerdump(void)
|
||||
(unsigned long)g_current_regs[REG_EXIT],
|
||||
(unsigned long)g_current_regs[REG_EXCCAUSE],
|
||||
(unsigned long)g_current_regs[REG_EXCVADDR]);
|
||||
#ifdef CONFIG_XTENSA_HAVE_LOOPS
|
||||
#ifdef XTENSA_HAVE_LOOPS
|
||||
_alert(" LBEG: %08lx LEND: %08lx LCNT: %08lx\n",
|
||||
(unsigned long)g_current_regs[REG_LBEG],
|
||||
(unsigned long)g_current_regs[REG_LEND],
|
||||
|
||||
@@ -45,15 +45,11 @@
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/irq.h>
|
||||
#include <arch/chip/core-isa.h>
|
||||
|
||||
#include "xtensa.h"
|
||||
#include "xtensa_corebits.h"
|
||||
|
||||
/* Temporary for clean compile */
|
||||
|
||||
#warning REVISIT _xt_user_exit
|
||||
void _xt_user_exit(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
@@ -89,7 +85,6 @@ void up_initial_state(struct tcb_s *tcb)
|
||||
xcp->regs[REG_PC] = (uint32_t)tcb->start; /* Task entrypoint */
|
||||
xcp->regs[REG_A0] = 0; /* To terminate GDB backtrace */
|
||||
xcp->regs[REG_A1] = (uint32_t)tcb->adj_stack_ptr; /* Physical top of stack frame */
|
||||
xcp->regs[REG_EXIT] = (uint32_t)_xt_user_exit; /* User exception exit dispatcher */
|
||||
|
||||
/* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user
|
||||
* mode.
|
||||
@@ -122,7 +117,7 @@ void up_initial_state(struct tcb_s *tcb)
|
||||
ptr = (uint32_t *)(((uint32_t)tcb->adj_stack_ptr - XT_CP_SIZE) & ~0xf);
|
||||
ptr[0] = 0;
|
||||
ptr[1] = 0;
|
||||
ptr[2] = (((uint32_t)ptr) + 12 + XCHAL_TOTAL_SA_ALIGN - 1) & -XCHAL_TOTAL_SA_ALIGN;
|
||||
ptr[2] = (((uint32_t)ptr) + 12 + XTENSA_TOTAL_SA_ALIGN - 1) & -XTENSA_TOTAL_SA_ALIGN;
|
||||
#endif
|
||||
#endif /* REVISIT */
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -58,7 +58,7 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if CONFIG_XTENSA_EXCM_LEVEL >= 2
|
||||
#if XTENSA_EXCM_LEVEL >= 2
|
||||
.begin literal_prefix .xtensa_level2_vector
|
||||
.section .xtensa_level2_vector.text, "ax"
|
||||
.global _xtensa_level2_vector
|
||||
@@ -77,7 +77,7 @@ _xtensa_level2_vector:
|
||||
.size _xtensa_level2_vector, . - _xtensa_level2_vector
|
||||
#endif
|
||||
|
||||
#if CONFIG_XTENSA_EXCM_LEVEL >= 3
|
||||
#if XTENSA_EXCM_LEVEL >= 3
|
||||
.begin literal_prefix .xtensa_level3_vector
|
||||
.section .xtensa_level3_vector.text, "ax"
|
||||
.global _xtensa_level3_vector
|
||||
@@ -96,7 +96,7 @@ _xtensa_level3_vector:
|
||||
.size _xtensa_level3_vector, . - _xtensa_level3_vector
|
||||
#endif
|
||||
|
||||
#if CONFIG_XTENSA_EXCM_LEVEL >= 4
|
||||
#if XTENSA_EXCM_LEVEL >= 4
|
||||
.begin literal_prefix .xtensa_level4_vector
|
||||
.section .xtensa_level4_vector.text, "ax"
|
||||
.global _xtensa_level4_vector
|
||||
@@ -115,7 +115,7 @@ _xtensa_level4_vector:
|
||||
.size _xtensa_level5_vector, . - _xtensa_level5_vector
|
||||
#endif
|
||||
|
||||
#if CONFIG_XTENSA_EXCM_LEVEL >= 5
|
||||
#if XTENSA_EXCM_LEVEL >= 5
|
||||
.begin literal_prefix .xtensa_level5_vector
|
||||
.section .xtensa_level5_vector.text, "ax"
|
||||
.global _xtensa_level5_vector
|
||||
@@ -134,7 +134,7 @@ _xtensa_level5_vector:
|
||||
.size _xtensa_level5_vector, . - _xtensa_level5_vector
|
||||
#endif
|
||||
|
||||
#if CONFIG_XTENSA_EXCM_LEVEL >= 6
|
||||
#if XTENSA_EXCM_LEVEL >= 6
|
||||
.begin literal_prefix .xtensa_level6_vector
|
||||
.section .xtensa_level6_vector.text, "ax"
|
||||
.global _xtensa_level6_vector
|
||||
|
||||
@@ -0,0 +1,147 @@
|
||||
/****************************************************************************
|
||||
* arch/xtensa/src/common/xtensa_irq.S
|
||||
*
|
||||
* Adapted from use in NuttX by:
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Derives from logic originally provided by Cadence Design Systems Inc.
|
||||
* Copyright (c) 2003-2015 Cadence Design Systems, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_TIMER_H
|
||||
#define __ARCH_XTENSA_SRC_COMMON_XTENSA_TIMER_H
|
||||
|
||||
#ifdef __ASSEMBLER__
|
||||
#include <xtensa/coreasm.h>
|
||||
#endif
|
||||
|
||||
#include <xtensa/corebits.h>
|
||||
#include <xtensa/config/system.h>
|
||||
|
||||
/* Select timer to use for periodic tick, and determine its interrupt number
|
||||
* and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
|
||||
* in which case its validity is checked (it must exist in this core and must
|
||||
* not be on a high priority interrupt - an error will be reported in invalid).
|
||||
* Otherwise select the first low or medium priority interrupt timer available.
|
||||
*/
|
||||
|
||||
#if XTENSA_NUM_TIMERS == 0
|
||||
|
||||
# error "This Xtensa configuration is unsupported, it has no timers."
|
||||
|
||||
#else
|
||||
|
||||
#ifndef XT_TIMER_INDEX
|
||||
# if XTENSA_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
|
||||
# if XTENSA_INT_LEVEL(XTENSA_TIMER3_INTERRUPT) <= XTENSA_EXCM_LEVEL
|
||||
# undef XT_TIMER_INDEX
|
||||
# define XT_TIMER_INDEX 3
|
||||
# endif
|
||||
# endif
|
||||
# if XTENSA_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
|
||||
# if XTENSA_INT_LEVEL(XTENSA_TIMER2_INTERRUPT) <= XTENSA_EXCM_LEVEL
|
||||
# undef XT_TIMER_INDEX
|
||||
# define XT_TIMER_INDEX 2
|
||||
# endif
|
||||
# endif
|
||||
# if XTENSA_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
|
||||
# if XTENSA_INT_LEVEL(XTENSA_TIMER1_INTERRUPT) <= XTENSA_EXCM_LEVEL
|
||||
# undef XT_TIMER_INDEX
|
||||
# define XT_TIMER_INDEX 1
|
||||
# endif
|
||||
# endif
|
||||
# if XTENSA_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
|
||||
# if XTENSA_INT_LEVEL(XTENSA_TIMER0_INTERRUPT) <= XTENSA_EXCM_LEVEL
|
||||
# undef XT_TIMER_INDEX
|
||||
# define XT_TIMER_INDEX 0
|
||||
# endif
|
||||
# endif
|
||||
#endif
|
||||
#ifndef XT_TIMER_INDEX
|
||||
# error "There is no suitable timer in this Xtensa configuration."
|
||||
#endif
|
||||
|
||||
#define XT_CCOMPARE (CCOMPARE + XT_TIMER_INDEX)
|
||||
#define XT_TIMER_INTNUM XTENSA_TIMER_INTERRUPT(XT_TIMER_INDEX)
|
||||
#define XT_TIMER_INTPRI XTENSA_INT_LEVEL(XT_TIMER_INTNUM)
|
||||
#define XT_TIMER_INTEN (1 << XT_TIMER_INTNUM)
|
||||
|
||||
#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
|
||||
# error "The timer selected by XT_TIMER_INDEX does not exist in this core."
|
||||
#elif XT_TIMER_INTPRI > XTENSA_EXCM_LEVEL
|
||||
# error "The timer interrupt cannot be high priority (use medium or low)."
|
||||
#endif
|
||||
|
||||
#endif /* XTENSA_NUM_TIMERS */
|
||||
|
||||
/* Set processor clock frequency, used to determine clock divisor for timer
|
||||
* tick. User should BE SURE TO ADJUST THIS for the Xtensa platform being
|
||||
* used. If using a supported board via the board-independent API defined in
|
||||
* xtbsp.h, this may be left undefined and frequency and tick divisor will
|
||||
* be computed and cached during run-time initialization.
|
||||
*
|
||||
* NOTE ON SIMULATOR:
|
||||
* Under the Xtensa instruction set simulator, the frequency can only be
|
||||
* estimated because it depends on the speed of the host and the version of
|
||||
* the simulator. Also because it runs much slower than hardware, it is not
|
||||
* possible to achieve real-time performance for most applications under the
|
||||
* simulator. A frequency too low does not allow enough time between timer
|
||||
* interrupts, starving threads. To obtain a more convenient but non-real-
|
||||
* time tick duration on the simulator, compile with xt-xcc option
|
||||
* "-DXT_SIMULATOR". Adjust this frequency to taste (it's not real-time
|
||||
* anyway!).
|
||||
*/
|
||||
|
||||
#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
|
||||
# define XT_CLOCK_FREQ
|
||||
#endif
|
||||
|
||||
#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
|
||||
# error "XT_CLOCK_FREQ must be defined for the target platform."
|
||||
#endif
|
||||
|
||||
/* Default number of timer "ticks" per second (default 100 for 10ms tick).
|
||||
* RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
|
||||
* User may redefine this to an optimal value for the application, either by
|
||||
* editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
|
||||
* "-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number.
|
||||
*/
|
||||
|
||||
#ifndef XT_TICK_PER_SEC
|
||||
# define XT_TICK_PER_SEC (1000000 / CONFIG_USEC_PER_TICK)
|
||||
#endif
|
||||
|
||||
/* Derivation of clock divisor for timer tick and interrupt (one per tick). */
|
||||
|
||||
#ifdef XT_CLOCK_FREQ
|
||||
# define XT_TICK_DIVISOR (XT_CLOCK_FREQ / XT_TICK_PER_SEC)
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
extern unsigned _xt_tick_divisor;
|
||||
void _xt_tick_divisor_init(void);
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_TIMER_H */
|
||||
Reference in New Issue
Block a user