mirror of
https://github.com/apache/nuttx.git
synced 2026-09-21 21:47:28 +08:00
xtensa/esp32s2: Add RTC support
This commit is contained in:
Eren Terzioglu
committed by
Alan Carvalho de Assis
Alan Carvalho de Assis
parent
31abcb0e9a
commit
5b19d8b2cb
@@ -297,6 +297,22 @@ After successfully built and flashed, run on the boards' terminal::
|
||||
|
||||
nxlooper> loopback 2 8 44100
|
||||
|
||||
rtc
|
||||
---
|
||||
|
||||
This configuration demonstrates the use of the RTC driver through alarms.
|
||||
You can set an alarm, check its progress and receive a notification after it expires::
|
||||
|
||||
nsh> alarm 10
|
||||
alarm_daemon started
|
||||
alarm_daemon: Running
|
||||
Opening /dev/rtc0
|
||||
Alarm 0 set in 10 seconds
|
||||
nsh> alarm -r
|
||||
Opening /dev/rtc0
|
||||
Alarm 0 is active with 10 seconds to expiration
|
||||
nsh> alarm_daemon: alarm 0 received
|
||||
|
||||
twai
|
||||
----
|
||||
|
||||
|
||||
@@ -335,6 +335,22 @@ To test it, just run ``rand`` to get 32 randomly generated bytes::
|
||||
0000 98 b9 66 a2 a2 c0 a2 ae 09 70 93 d1 b5 91 86 c8 ..f......p......
|
||||
0010 8f 0e 0b 04 29 64 21 72 01 92 7c a2 27 60 6f 90 ....)d!r..|.'`o.
|
||||
|
||||
rtc
|
||||
---
|
||||
|
||||
This configuration demonstrates the use of the RTC driver through alarms.
|
||||
You can set an alarm, check its progress and receive a notification after it expires::
|
||||
|
||||
nsh> alarm 10
|
||||
alarm_daemon started
|
||||
alarm_daemon: Running
|
||||
Opening /dev/rtc0
|
||||
Alarm 0 set in 10 seconds
|
||||
nsh> alarm -r
|
||||
Opening /dev/rtc0
|
||||
Alarm 0 is active with 10 seconds to expiration
|
||||
nsh> alarm_daemon: alarm 0 received
|
||||
|
||||
timer
|
||||
-----
|
||||
|
||||
|
||||
@@ -420,6 +420,10 @@ config ESP32S2_RWDT
|
||||
to have the RTC module reset, please, use the Timers' Module WDTs.
|
||||
They will only reset Main System.
|
||||
|
||||
config ESP32S2_RTC
|
||||
bool "Real Time Clock (RTC)"
|
||||
default y
|
||||
|
||||
config ESP32S2_UART0
|
||||
bool "UART 0"
|
||||
default n
|
||||
@@ -1020,6 +1024,49 @@ config ESP32S2_SPIRAM_IGNORE_NOTFOUND
|
||||
|
||||
endmenu # SPI RAM Configuration
|
||||
|
||||
menu "RTC Configuration"
|
||||
depends on ESP32S2_RTC
|
||||
|
||||
choice ESP32S2_RTC_CLK_SRC
|
||||
prompt "RTC clock source"
|
||||
default ESP32S2_RTC_CLK_INT_RC
|
||||
---help---
|
||||
Choose which clock is used as RTC clock source.
|
||||
|
||||
- "Internal 90KHz oscillator" option provides lowest deep sleep current
|
||||
consumption, and does not require extra external components. However
|
||||
frequency stability with respect to temperature is poor, so time may
|
||||
drift in deep/light sleep modes.
|
||||
- "External 32KHz crystal" provides better frequency stability, at the
|
||||
expense of slightly higher (1uA) deep sleep current consumption.
|
||||
- "External 32KHz oscillator" allows using 32KHz clock generated by an
|
||||
external circuit. In this case, external clock signal must be connected
|
||||
to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal,
|
||||
and <1V in case of square wave signal. Common mode voltage should be
|
||||
0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude.
|
||||
Additionally, 1nF capacitor must be connected between 32K_XP pin and
|
||||
ground. 32K_XP pin can not be used as a GPIO in this case.
|
||||
- "Internal 8.5MHz oscillator divided by 256" option results in higher
|
||||
deep sleep current (by 5uA) but has better frequency stability than
|
||||
the internal 90KHz oscillator. It does not require external components.
|
||||
|
||||
config ESP32S2_RTC_CLK_INT_RC
|
||||
bool "Internal 90KHz RC oscillator"
|
||||
|
||||
config ESP32S2_RTC_CLK_EXT_XTAL
|
||||
bool "External 32KHz crystal"
|
||||
select ESP_SYSTEM_RTC_EXT_XTAL
|
||||
|
||||
config ESP32S2_RTC_CLK_EXT_OSC
|
||||
bool "External 32KHz oscillator at 32K_XN pin"
|
||||
select ESP_SYSTEM_RTC_EXT_XTAL
|
||||
|
||||
config ESP32S2_RTC_CLK_INT_8MD256
|
||||
bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)"
|
||||
|
||||
endchoice
|
||||
endmenu # "RTC Configuration"
|
||||
|
||||
menu "Real-Time Timer Configuration"
|
||||
depends on ESP32S2_RT_TIMER
|
||||
|
||||
|
||||
@@ -137,6 +137,12 @@ CHIP_CSRCS += esp32s2_spiram.c
|
||||
CHIP_CSRCS += esp32s2_psram.c
|
||||
endif
|
||||
|
||||
CHIP_CSRCS += esp32s2_rtc.c
|
||||
|
||||
ifeq ($(CONFIG_RTC_DRIVER),y)
|
||||
CHIP_CSRCS += esp32s2_rtc_lowerhalf.c
|
||||
endif
|
||||
|
||||
#############################################################################
|
||||
# Espressif HAL for 3rd Party Platforms
|
||||
#############################################################################
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,56 @@
|
||||
/****************************************************************************
|
||||
* arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_LOWERHALF_H
|
||||
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_LOWERHALF_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifdef CONFIG_RTC_DRIVER
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: esp32s2_rtc_driverinit
|
||||
*
|
||||
* Description:
|
||||
* Bind the configuration timer to a timer lower half instance and register
|
||||
* the timer drivers at 'devpath'
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success; A negated errno value is returned
|
||||
* to indicate the nature of any failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int esp32s2_rtc_driverinit(void);
|
||||
|
||||
#endif /* CONFIG_RTC_DRIVER */
|
||||
|
||||
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_LOWERHALF_H */
|
||||
@@ -42,6 +42,7 @@
|
||||
#include "esp32s2_start.h"
|
||||
#include "esp32s2_lowputc.h"
|
||||
#include "esp32s2_wdt.h"
|
||||
#include "esp32s2_rtc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@@ -338,6 +339,11 @@ static void noreturn_function IRAM_ATTR __esp32s2_start(void)
|
||||
|
||||
esp32s2_wdt_early_deinit();
|
||||
|
||||
/* Initialize RTC parameters */
|
||||
|
||||
esp32s2_rtc_init();
|
||||
esp32s2_rtc_clk_set();
|
||||
|
||||
/* Set CPU frequency configured in board.h */
|
||||
|
||||
esp32s2_clockconfig();
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -58,10 +58,17 @@
|
||||
|
||||
#define RTC_CNTL_SWD_WKEY_VALUE 0x8f1d312a
|
||||
|
||||
#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG
|
||||
#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG
|
||||
|
||||
#define DPORT_CPUPERIOD_SEL_80 0
|
||||
#define DPORT_CPUPERIOD_SEL_160 1
|
||||
#define DPORT_CPUPERIOD_SEL_240 2
|
||||
|
||||
#define DPORT_SOC_CLK_SEL_XTAL 0
|
||||
#define DPORT_SOC_CLK_SEL_PLL 1
|
||||
#define DPORT_SOC_CLK_SEL_8M 2
|
||||
|
||||
#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
|
||||
|
||||
/* RTC_CNTL_OPTIONS0_REG register
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,192 @@
|
||||
/****************************************************************************
|
||||
* arch/xtensa/src/esp32s2/hardware/regi2c_bbpll.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_BBPLL_H
|
||||
#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_BBPLL_H
|
||||
|
||||
/**
|
||||
* @file regi2c_bbpll.h
|
||||
* @brief Register definitions for digital PLL (BBPLL)
|
||||
*
|
||||
* This file lists register fields of BBPLL, located on an internal
|
||||
* configuration bus. These definitions are used via macros defined
|
||||
* in regi2c_ctrl.h, by rtc_clk_cpu_freq_set function in rtc_clk.c.
|
||||
*/
|
||||
|
||||
#define I2C_BBPLL 0x66
|
||||
#define I2C_BBPLL_HOSTID 1
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_DELAY 0
|
||||
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
|
||||
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_CK_DIV 0
|
||||
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
|
||||
#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_EXT_CAP 1
|
||||
#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3
|
||||
#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_ENX_CAP 1
|
||||
#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4
|
||||
#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_RSTB 1
|
||||
#define I2C_BBPLL_IR_CAL_RSTB_MSB 5
|
||||
#define I2C_BBPLL_IR_CAL_RSTB_LSB 5
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_START 1
|
||||
#define I2C_BBPLL_IR_CAL_START_MSB 6
|
||||
#define I2C_BBPLL_IR_CAL_START_LSB 6
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_UNSTOP 1
|
||||
#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7
|
||||
#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_REF_DIV 2
|
||||
#define I2C_BBPLL_OC_REF_DIV_MSB 3
|
||||
#define I2C_BBPLL_OC_REF_DIV_LSB 0
|
||||
|
||||
#define I2C_BBPLL_OC_DCHGP 2
|
||||
#define I2C_BBPLL_OC_DCHGP_MSB 6
|
||||
#define I2C_BBPLL_OC_DCHGP_LSB 4
|
||||
|
||||
#define I2C_BBPLL_OC_ENB_FCAL 2
|
||||
#define I2C_BBPLL_OC_ENB_FCAL_MSB 7
|
||||
#define I2C_BBPLL_OC_ENB_FCAL_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_DIV_7_0 3
|
||||
#define I2C_BBPLL_OC_DIV_7_0_MSB 7
|
||||
#define I2C_BBPLL_OC_DIV_7_0_LSB 0
|
||||
|
||||
#define I2C_BBPLL_RSTB_DIV_ADC 4
|
||||
#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0
|
||||
#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0
|
||||
|
||||
#define I2C_BBPLL_MODE_HF 4
|
||||
#define I2C_BBPLL_MODE_HF_MSB 1
|
||||
#define I2C_BBPLL_MODE_HF_LSB 1
|
||||
|
||||
#define I2C_BBPLL_DIV_ADC 4
|
||||
#define I2C_BBPLL_DIV_ADC_MSB 3
|
||||
#define I2C_BBPLL_DIV_ADC_LSB 2
|
||||
|
||||
#define I2C_BBPLL_DIV_DAC 4
|
||||
#define I2C_BBPLL_DIV_DAC_MSB 4
|
||||
#define I2C_BBPLL_DIV_DAC_LSB 4
|
||||
|
||||
#define I2C_BBPLL_DIV_CPU 4
|
||||
#define I2C_BBPLL_DIV_CPU_MSB 5
|
||||
#define I2C_BBPLL_DIV_CPU_LSB 5
|
||||
|
||||
#define I2C_BBPLL_OC_ENB_VCON 4
|
||||
#define I2C_BBPLL_OC_ENB_VCON_MSB 6
|
||||
#define I2C_BBPLL_OC_ENB_VCON_LSB 6
|
||||
|
||||
#define I2C_BBPLL_OC_TSCHGP 4
|
||||
#define I2C_BBPLL_OC_TSCHGP_MSB 7
|
||||
#define I2C_BBPLL_OC_TSCHGP_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_DR1 5
|
||||
#define I2C_BBPLL_OC_DR1_MSB 2
|
||||
#define I2C_BBPLL_OC_DR1_LSB 0
|
||||
|
||||
#define I2C_BBPLL_OC_DR3 5
|
||||
#define I2C_BBPLL_OC_DR3_MSB 6
|
||||
#define I2C_BBPLL_OC_DR3_LSB 4
|
||||
|
||||
#define I2C_BBPLL_EN_USB 5
|
||||
#define I2C_BBPLL_EN_USB_MSB 7
|
||||
#define I2C_BBPLL_EN_USB_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_DCUR 6
|
||||
#define I2C_BBPLL_OC_DCUR_MSB 2
|
||||
#define I2C_BBPLL_OC_DCUR_LSB 0
|
||||
|
||||
#define I2C_BBPLL_INC_CUR 6
|
||||
#define I2C_BBPLL_INC_CUR_MSB 3
|
||||
#define I2C_BBPLL_INC_CUR_LSB 3
|
||||
|
||||
#define I2C_BBPLL_OC_DHREF_SEL 6
|
||||
#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
|
||||
#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
|
||||
|
||||
#define I2C_BBPLL_OC_DLREF_SEL 6
|
||||
#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
|
||||
#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_CAP 8
|
||||
#define I2C_BBPLL_OR_CAL_CAP_MSB 3
|
||||
#define I2C_BBPLL_OR_CAL_CAP_LSB 0
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_UDF 8
|
||||
#define I2C_BBPLL_OR_CAL_UDF_MSB 4
|
||||
#define I2C_BBPLL_OR_CAL_UDF_LSB 4
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_OVF 8
|
||||
#define I2C_BBPLL_OR_CAL_OVF_MSB 5
|
||||
#define I2C_BBPLL_OR_CAL_OVF_LSB 5
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_END 8
|
||||
#define I2C_BBPLL_OR_CAL_END_MSB 6
|
||||
#define I2C_BBPLL_OR_CAL_END_LSB 6
|
||||
|
||||
#define I2C_BBPLL_OR_LOCK 8
|
||||
#define I2C_BBPLL_OR_LOCK_MSB 7
|
||||
#define I2C_BBPLL_OR_LOCK_LSB 7
|
||||
|
||||
#define I2C_BBPLL_BBADC_DELAY1 9
|
||||
#define I2C_BBPLL_BBADC_DELAY1_MSB 1
|
||||
#define I2C_BBPLL_BBADC_DELAY1_LSB 0
|
||||
|
||||
#define I2C_BBPLL_BBADC_DELAY2 9
|
||||
#define I2C_BBPLL_BBADC_DELAY2_MSB 3
|
||||
#define I2C_BBPLL_BBADC_DELAY2_LSB 2
|
||||
|
||||
#define I2C_BBPLL_BBADC_DVDD 9
|
||||
#define I2C_BBPLL_BBADC_DVDD_MSB 5
|
||||
#define I2C_BBPLL_BBADC_DVDD_LSB 4
|
||||
|
||||
#define I2C_BBPLL_BBADC_DREF 9
|
||||
#define I2C_BBPLL_BBADC_DREF_MSB 7
|
||||
#define I2C_BBPLL_BBADC_DREF_LSB 6
|
||||
|
||||
#define I2C_BBPLL_BBADC_DCUR 10
|
||||
#define I2C_BBPLL_BBADC_DCUR_MSB 1
|
||||
#define I2C_BBPLL_BBADC_DCUR_LSB 0
|
||||
|
||||
#define I2C_BBPLL_BBADC_INPUT_SHORT 10
|
||||
#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2
|
||||
#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2
|
||||
|
||||
#define I2C_BBPLL_ENT_PLL 10
|
||||
#define I2C_BBPLL_ENT_PLL_MSB 3
|
||||
#define I2C_BBPLL_ENT_PLL_LSB 3
|
||||
|
||||
#define I2C_BBPLL_DTEST 10
|
||||
#define I2C_BBPLL_DTEST_MSB 5
|
||||
#define I2C_BBPLL_DTEST_LSB 4
|
||||
|
||||
#define I2C_BBPLL_ENT_ADC 10
|
||||
#define I2C_BBPLL_ENT_ADC_MSB 7
|
||||
#define I2C_BBPLL_ENT_ADC_LSB 6
|
||||
|
||||
#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_BBPLL_H */
|
||||
@@ -0,0 +1,54 @@
|
||||
/****************************************************************************
|
||||
* arch/xtensa/src/esp32s2/hardware/regi2c_ctrl.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_CTRL_H
|
||||
#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_CTRL_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "esp32s2_soc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Convenience macros for the above functions, these use register
|
||||
* definitions from regi2c_bbpll.h/regi2c_dig_reg.h/regi2c_lp_bias.h/
|
||||
* regi2c_bias.h header files.
|
||||
*/
|
||||
|
||||
#define REGI2C_WRITE_MASK(block, reg_add, indata) \
|
||||
rom_i2c_writereg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, \
|
||||
reg_add##_LSB, indata)
|
||||
|
||||
#define REGI2C_READ_MASK(block, reg_add) \
|
||||
rom_i2c_readreg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, \
|
||||
reg_add##_LSB)
|
||||
|
||||
#define REGI2C_WRITE(block, reg_add, indata) \
|
||||
rom_i2c_writereg(block, block##_HOSTID, reg_add, indata)
|
||||
|
||||
#define REGI2C_READ(block, reg_add) \
|
||||
rom_i2c_readreg(block, block##_HOSTID, reg_add)
|
||||
|
||||
#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_CTRL_H */
|
||||
@@ -0,0 +1,56 @@
|
||||
/****************************************************************************
|
||||
* arch/xtensa/src/esp32s2/hardware/regi2c_lp_bias.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_LP_BIAS_H
|
||||
#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_LP_BIAS_H
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register definitions for analog to calibrate o_code for getting a more
|
||||
* precise voltage. This file lists register fields of low power dbais,
|
||||
* located on an internal configuration bus.
|
||||
*/
|
||||
|
||||
#define I2C_ULP 0x61
|
||||
#define I2C_ULP_HOSTID 1
|
||||
|
||||
#define I2C_ULP_IR_RESETB 0
|
||||
#define I2C_ULP_IR_RESETB_MSB 0
|
||||
#define I2C_ULP_IR_RESETB_LSB 0
|
||||
|
||||
#define I2C_ULP_O_DONE_FLAG 3
|
||||
#define I2C_ULP_O_DONE_FLAG_MSB 0
|
||||
#define I2C_ULP_O_DONE_FLAG_LSB 0
|
||||
|
||||
#define I2C_ULP_BG_O_DONE_FLAG 3
|
||||
#define I2C_ULP_BG_O_DONE_FLAG_MSB 3
|
||||
#define I2C_ULP_BG_O_DONE_FLAG_LSB 3
|
||||
|
||||
#define I2C_ULP_IR_FORCE_CODE 5
|
||||
#define I2C_ULP_IR_FORCE_CODE_MSB 6
|
||||
#define I2C_ULP_IR_FORCE_CODE_LSB 6
|
||||
|
||||
#define I2C_ULP_EXT_CODE 6
|
||||
#define I2C_ULP_EXT_CODE_MSB 7
|
||||
#define I2C_ULP_EXT_CODE_LSB 0
|
||||
|
||||
#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_LP_BIAS_H */
|
||||
@@ -0,0 +1,51 @@
|
||||
#
|
||||
# This file is autogenerated: PLEASE DO NOT EDIT IT.
|
||||
#
|
||||
# You can use "make menuconfig" to make any modifications to the installed .config file.
|
||||
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
|
||||
# modifications.
|
||||
#
|
||||
# CONFIG_ARCH_LEDS is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
|
||||
CONFIG_ARCH="xtensa"
|
||||
CONFIG_ARCH_BOARD="esp32s2-kaluga-1"
|
||||
CONFIG_ARCH_BOARD_COMMON=y
|
||||
CONFIG_ARCH_BOARD_ESP32S2_KALUGA_1=y
|
||||
CONFIG_ARCH_CHIP="esp32s2"
|
||||
CONFIG_ARCH_CHIP_ESP32S2=y
|
||||
CONFIG_ARCH_CHIP_ESP32S2WROVER=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARCH_XTENSA=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=16717
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_ESP32S2_RT_TIMER=y
|
||||
CONFIG_ESP32S2_UART0=y
|
||||
CONFIG_EXAMPLES_ALARM=y
|
||||
CONFIG_FS_PROCFS=y
|
||||
CONFIG_HAVE_CXX=y
|
||||
CONFIG_HAVE_CXXINITIALIZE=y
|
||||
CONFIG_IDLETHREAD_STACKSIZE=3072
|
||||
CONFIG_INIT_ENTRYPOINT="nsh_main"
|
||||
CONFIG_INTELHEX_BINARY=y
|
||||
CONFIG_MM_REGIONS=3
|
||||
CONFIG_NSH_ARCHINIT=y
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_FILEIOSIZE=512
|
||||
CONFIG_NSH_LINELEN=64
|
||||
CONFIG_NSH_READLINE=y
|
||||
CONFIG_PREALLOC_TIMERS=4
|
||||
CONFIG_RAM_SIZE=114688
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_RTC=y
|
||||
CONFIG_RTC_ALARM=y
|
||||
CONFIG_RTC_DRIVER=y
|
||||
CONFIG_RTC_NALARMS=2
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_START_DAY=6
|
||||
CONFIG_START_MONTH=12
|
||||
CONFIG_START_YEAR=2011
|
||||
CONFIG_SYSLOG_BUFFER=y
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_UART0_SERIAL_CONSOLE=y
|
||||
@@ -84,6 +84,10 @@
|
||||
# include "esp32s2_board_spislavedev.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTC_DRIVER
|
||||
# include "esp32s2_rtc_lowerhalf.h"
|
||||
#endif
|
||||
|
||||
#include "esp32s2-kaluga-1.h"
|
||||
|
||||
/****************************************************************************
|
||||
@@ -312,6 +316,17 @@ int esp32s2_bringup(void)
|
||||
|
||||
#endif /* CONFIG_ESP32S2_I2S */
|
||||
|
||||
#ifdef CONFIG_RTC_DRIVER
|
||||
/* Instantiate the ESP32 RTC driver */
|
||||
|
||||
ret = esp32s2_rtc_driverinit();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR,
|
||||
"ERROR: Failed to Instantiate the RTC driver: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* If we got here then perhaps not all initialization was successful, but
|
||||
* at least enough succeeded to bring-up NSH with perhaps reduced
|
||||
* capabilities.
|
||||
|
||||
@@ -0,0 +1,51 @@
|
||||
#
|
||||
# This file is autogenerated: PLEASE DO NOT EDIT IT.
|
||||
#
|
||||
# You can use "make menuconfig" to make any modifications to the installed .config file.
|
||||
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
|
||||
# modifications.
|
||||
#
|
||||
# CONFIG_ARCH_LEDS is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
|
||||
CONFIG_ARCH="xtensa"
|
||||
CONFIG_ARCH_BOARD="esp32s2-saola-1"
|
||||
CONFIG_ARCH_BOARD_COMMON=y
|
||||
CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y
|
||||
CONFIG_ARCH_CHIP="esp32s2"
|
||||
CONFIG_ARCH_CHIP_ESP32S2=y
|
||||
CONFIG_ARCH_CHIP_ESP32S2WROVER=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARCH_XTENSA=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=16717
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_ESP32S2_RT_TIMER=y
|
||||
CONFIG_ESP32S2_UART0=y
|
||||
CONFIG_EXAMPLES_ALARM=y
|
||||
CONFIG_FS_PROCFS=y
|
||||
CONFIG_HAVE_CXX=y
|
||||
CONFIG_HAVE_CXXINITIALIZE=y
|
||||
CONFIG_IDLETHREAD_STACKSIZE=3072
|
||||
CONFIG_INIT_ENTRYPOINT="nsh_main"
|
||||
CONFIG_INTELHEX_BINARY=y
|
||||
CONFIG_MM_REGIONS=3
|
||||
CONFIG_NSH_ARCHINIT=y
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_FILEIOSIZE=512
|
||||
CONFIG_NSH_LINELEN=64
|
||||
CONFIG_NSH_READLINE=y
|
||||
CONFIG_PREALLOC_TIMERS=4
|
||||
CONFIG_RAM_SIZE=114688
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_RTC=y
|
||||
CONFIG_RTC_ALARM=y
|
||||
CONFIG_RTC_DRIVER=y
|
||||
CONFIG_RTC_NALARMS=2
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_START_DAY=6
|
||||
CONFIG_START_MONTH=12
|
||||
CONFIG_START_YEAR=2011
|
||||
CONFIG_SYSLOG_BUFFER=y
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_UART0_SERIAL_CONSOLE=y
|
||||
@@ -84,6 +84,10 @@
|
||||
# include "esp32s2_board_spislavedev.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTC_DRIVER
|
||||
# include "esp32s2_rtc_lowerhalf.h"
|
||||
#endif
|
||||
|
||||
#include "esp32s2-saola-1.h"
|
||||
|
||||
/****************************************************************************
|
||||
@@ -358,6 +362,17 @@ int esp32s2_bringup(void)
|
||||
|
||||
#endif /* CONFIG_ESP32S2_I2S */
|
||||
|
||||
#ifdef CONFIG_RTC_DRIVER
|
||||
/* Instantiate the ESP32 RTC driver */
|
||||
|
||||
ret = esp32s2_rtc_driverinit();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR,
|
||||
"ERROR: Failed to Instantiate the RTC driver: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* If we got here then perhaps not all initialization was successful, but
|
||||
* at least enough succeeded to bring-up NSH with perhaps reduced
|
||||
* capabilities.
|
||||
|
||||
Reference in New Issue
Block a user