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arch/tricore: Adjust the related structures of arch and chip.

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support tc4evb board, so need adjust some Kconfig

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
This commit is contained in:
zhangyu117
2025-11-24 11:05:45 +08:00
committed by Alin Jerpelea
parent c98eccf08d
commit 5b18435f96
8 changed files with 94 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/tricore/src/Makefile
+1 -1
View File
@@ -23,7 +23,7 @@
include $(TOPDIR)/Make.defs
include chip/Make.defs
ifeq ($(CONFIG_ARCH_TC3XX),y)
ifeq ($(CONFIG_ARCH_CHIP_TC3XX),y)
ARCH_SUBDIR = tc3xx
include $(ARCH_SUBDIR)/Make.defs
endif
arch/tricore/src/cmake/ToolchainGnuc.cmake
+1 -1
View File
@@ -27,7 +27,7 @@ set(CMAKE_SYSTEM_VERSION 1)
set(ARCH_SUBDIR)
if(CONFIG_ARCH_TC3XX) # TC3XX
if(CONFIG_ARCH_CHIP_TC3XX) # TC3XX
set(ARCH_SUBDIR tc3xx)
else()
set(ARCH_SUBDIR tc3xx)
arch/tricore/src/cmake/ToolchainTasking.cmake
+1 -1
View File
@@ -27,7 +27,7 @@ set(CMAKE_SYSTEM_VERSION 1)
set(ARCH_SUBDIR)
if(CONFIG_ARCH_TC3XX) # TC3XX
if(CONFIG_ARCH_CHIP_TC3XX) # TC3XX
set(ARCH_SUBDIR tc3xx)
else()
set(ARCH_SUBDIR tc3xx)
arch/tricore/src/common/tricore_irq.c
+3 -3
View File
@@ -99,7 +99,7 @@ static void tricore_gpsrinitialize(void)
for (i = 0; i < 6; i++)
{
#ifdef CONFIG_ARCH_TC3XX
#ifdef CONFIG_ARCH_CHIP_TC3XX
IfxSrc_init(src, IfxSrc_Tos_cpu0 + up_cpu_index(),
IRQ_TO_NDX(TRICORE_SRC2IRQ(src)));
#else
@@ -113,7 +113,7 @@ static void tricore_gpsrinitialize(void)
/* Cpucs gpsr init */
#ifndef CONFIG_ARCH_TC3XX
#ifndef CONFIG_ARCH_CHIP_TC3XX
src = &SRC_GPSR6_SR0 + up_cpu_index();
IfxSrc_init(src, IfxSrc_Tos_cpu0 + up_cpu_index(),
IRQ_TO_NDX(TRICORE_SRC2IRQ(src)),
@@ -188,7 +188,7 @@ void up_enable_irq(int irq)
{
volatile Ifx_SRC_SRCR *src = &SRC_CPU_CPU0_SB + irq;
#ifdef CONFIG_ARCH_TC3XX
#ifdef CONFIG_ARCH_CHIP_TC3XX
IfxSrc_init(src, IfxSrc_Tos_cpu0, IRQ_TO_NDX(irq));
#else
IfxSrc_init(src, IfxSrc_Tos_cpu0, IRQ_TO_NDX(irq), IfxSrc_VmId_none);
arch/tricore/src/common/tricore_main.c
+2 -2
View File
@@ -68,10 +68,10 @@ void core0_main(void)
* to ensure the normal startup of the system.
*/
#if defined(CONFIG_ARCH_CHIP_AURIX_TC3XX)
#if defined(CONFIG_ARCH_CHIP_TC3XX)
IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword());
IfxScuWdt_disableSafetyWatchdog(IfxScuWdt_getSafetyWatchdogPassword());
#elif defined(CONFIG_ARCH_CHIP_AURIX_TC4XX)
#elif defined(CONFIG_ARCH_CHIP_TC4XX)
IfxWtu_disableCpuWatchdog(IfxWtu_getCpuWatchdogPassword());
IfxWtu_disableSystemWatchdog(IfxWtu_getSystemWatchdogPassword());
#endif
arch/tricore/src/common/tricore_mpu.c
+20
View File
@@ -66,12 +66,14 @@ static Ifx_CPU_DPRE get_dpre_value(unsigned int set)
case 5:
dpre_value.U = __mfcr(CPU_DPRE_5);
break;
#ifndef CONFIG_ARCH_CHIP_TC3XX
case 6:
dpre_value.U = __mfcr(CPU_DPRE_6);
break;
case 7:
dpre_value.U = __mfcr(CPU_DPRE_7);
break;
#endif
default:
dpre_value.U = 0;
break;
@@ -102,12 +104,14 @@ static void set_dpre_value(unsigned int set, Ifx_CPU_DPRE dpre_value)
case 5:
__mtcr(CPU_DPRE_5, dpre_value.U);
break;
#ifndef CONFIG_ARCH_CHIP_TC3XX
case 6:
__mtcr(CPU_DPRE_6, dpre_value.U);
break;
case 7:
__mtcr(CPU_DPRE_7, dpre_value.U);
break;
#endif
default:
break;
}
@@ -139,12 +143,14 @@ static Ifx_CPU_DPWE get_dpwe_value(unsigned int set)
case 5:
dpwe_value.U = __mfcr(CPU_DPWE_5);
break;
#ifndef CONFIG_ARCH_CHIP_TC3XX
case 6:
dpwe_value.U = __mfcr(CPU_DPWE_6);
break;
case 7:
dpwe_value.U = __mfcr(CPU_DPWE_7);
break;
#endif
default:
dpwe_value.U = 0;
break;
@@ -176,11 +182,13 @@ static void set_dpwe_value(unsigned int set, Ifx_CPU_DPWE dpwe_value)
__mtcr(CPU_DPWE_5, dpwe_value.U);
break;
case 6:
#ifndef CONFIG_ARCH_CHIP_TC3XX
__mtcr(CPU_DPWE_6, dpwe_value.U);
break;
case 7:
__mtcr(CPU_DPWE_7, dpwe_value.U);
break;
#endif
default:
break;
}
@@ -212,12 +220,14 @@ static Ifx_CPU_CPXE get_cpxe_value(unsigned int set)
case 5:
cpxe_value.U = __mfcr(CPU_CPXE_5);
break;
#ifndef CONFIG_ARCH_CHIP_TC3XX
case 6:
cpxe_value.U = __mfcr(CPU_CPXE_6);
break;
case 7:
cpxe_value.U = __mfcr(CPU_CPXE_7);
break;
#endif
default:
cpxe_value.U = 0;
break;
@@ -248,12 +258,14 @@ static void set_cpxe_value(unsigned int set, Ifx_CPU_CPXE cpxe_value)
case 5:
__mtcr(CPU_CPXE_5, cpxe_value.U);
break;
#ifndef CONFIG_ARCH_CHIP_TC3XX
case 6:
__mtcr(CPU_CPXE_6, cpxe_value.U);
break;
case 7:
__mtcr(CPU_CPXE_7, cpxe_value.U);
break;
#endif
default:
break;
}
@@ -339,6 +351,7 @@ static int get_dpr_addrass_value(unsigned int region,
dpr_l->U = __mfcr(CPU_DPR17_L);
dpr_u->U = __mfcr(CPU_DPR17_U);
break;
#ifndef CONFIG_ARCH_CHIP_TC3XX
case 18:
dpr_l->U = __mfcr(CPU_DPR18_L);
dpr_u->U = __mfcr(CPU_DPR18_U);
@@ -363,6 +376,7 @@ static int get_dpr_addrass_value(unsigned int region,
dpr_l->U = __mfcr(CPU_DPR23_L);
dpr_u->U = __mfcr(CPU_DPR23_U);
break;
#endif
default:
return -EINVAL;
}
@@ -448,6 +462,7 @@ static void set_dpr_address_value(unsigned int region,
__mtcr(CPU_DPR17_L, dpr_l.U);
__mtcr(CPU_DPR17_U, dpr_u.U);
break;
#ifndef CONFIG_ARCH_CHIP_TC3XX
case 18:
__mtcr(CPU_DPR18_L, dpr_l.U);
__mtcr(CPU_DPR18_U, dpr_u.U);
@@ -472,6 +487,7 @@ static void set_dpr_address_value(unsigned int region,
__mtcr(CPU_DPR23_L, dpr_l.U);
__mtcr(CPU_DPR23_U, dpr_u.U);
break;
#endif
default:
break;
}
@@ -525,6 +541,7 @@ static int get_cpr_address_region(unsigned int region,
cpr_l->U = __mfcr(CPU_CPR9_L);
cpr_u->U = __mfcr(CPU_CPR9_U);
break;
#ifndef CONFIG_ARCH_CHIP_TC3XX
case 10:
cpr_l->U = __mfcr(CPU_CPR10_L);
cpr_u->U = __mfcr(CPU_CPR10_U);
@@ -549,6 +566,7 @@ static int get_cpr_address_region(unsigned int region,
cpr_l->U = __mfcr(CPU_CPR15_L);
cpr_u->U = __mfcr(CPU_CPR15_U);
break;
#endif
default:
return -EINVAL;
}
@@ -602,6 +620,7 @@ static void set_cpr_address_value(unsigned int region,
__mtcr(CPU_CPR9_L, cpr_l.U);
__mtcr(CPU_CPR9_U, cpr_u.U);
break;
#ifndef CONFIG_ARCH_CHIP_TC3XX
case 10:
__mtcr(CPU_CPR10_L, cpr_l.U);
__mtcr(CPU_CPR10_U, cpr_u.U);
@@ -626,6 +645,7 @@ static void set_cpr_address_value(unsigned int region,
__mtcr(CPU_CPR15_L, cpr_l.U);
__mtcr(CPU_CPR15_U, cpr_u.U);
break;
#endif
}
UP_ISB();