arch/tricore: Adjust the related structures of arch and chip.

support tc4evb board, so need adjust some Kconfig

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>

arch/tricore/Kconfig

@@ -22,30 +22,76 @@ config TRICORE_TOOLCHAIN_GNU
 
 endchoice # Tricore Toolchain Selection
 
-config ARCH_TC3XX
+config ARCH_TC1V6
 	bool
-	select ARCH_HAVE_TESTSET
+	select ARCH_HAVE_MPU
 	select ARCH_HAVE_IRQTRIGGER
-	select ARCH_MINIMAL_VECTORTABLE
-	select ARCH_MINIMAL_VECTORTABLE_DYNAMIC
+	select ARCH_HAVE_PERF_EVENTS
+	select ARCH_HAVE_POWEROFF
+	select ARCH_HAVE_PERF_EVENTS_USER_ACCESS
+	select ARCH_HAVE_SETJMP
+	select ARCH_HAVE_RESET
+	select ARCH_HAVE_TESTSET
+	default n
+
+config ARCH_TC1V8
+	bool
+	select ARCH_DCACHE
+	select ARCH_ICACHE
+	select ARCH_HAVE_MPU
+	select ARCH_HAVE_IRQTRIGGER
+	select ARCH_HAVE_PERF_EVENTS
+	select ARCH_HAVE_PERF_EVENTS_USER_ACCESS
+	select ARCH_HAVE_POWEROFF
+	select ARCH_HAVE_SETJMP
+	select ARCH_HAVE_RESET
+	select ARCH_HAVE_TESTSET
 	default n
 
 config ARCH_FAMILY
 	string
-	default "tc3xx"		if ARCH_TC3XX
+	default "tc1v6"		if ARCH_TC1V6
+	default "tc1v8"		if ARCH_TC1V8
 
-config ARCH_CHIP
-	string
-	default "tc397"		if ARCH_CHIP_TC397
-
-config ARCH_CHIP_TC397
-	bool "AURIX Family TC397"
-	select ARCH_TC3XX
+config ARCH_CHIP_TC3XX
+	bool "infineon aurix tc3xx"
+	select ARCH_TC1V6
+	select ARCH_HAVE_ADDRENV
+	select ARCH_HAVE_I2CRESET
+	select ARCH_MINIMAL_VECTORTABLE
+	select ARCH_MINIMAL_VECTORTABLE_DYNAMIC
 	select ALARM_ARCH
 	select ONESHOT
 	select ONESHOT_COUNT
 	---help---
-		AURIX TC39x family: TC397
+		Infineon aurix tc3xx (six cores)
+
+config ARCH_CHIP_TC4XX
+	bool "infineon aurix tc4xx"
+	select ARCH_TC1V8
+	select ARCH_HAVE_ADDRENV
+	select ARCH_HAVE_I2CRESET
+	select ARCH_MINIMAL_VECTORTABLE
+	select ARCH_MINIMAL_VECTORTABLE_DYNAMIC
+	select ALARM_ARCH
+	select ONESHOT
+	select ONESHOT_COUNT
+	select HAVE_SECURITY_CORE
+	---help---
+		Infineon aurix tc4xx (six cores and one security core)
+
+config ARCH_CHIP_TC397
+	bool "AURIX CHIP TC397"
+	select ARCH_CHIP_TC3XX
+
+config ARCH_CHIP_TC4DA
+	bool "AURIX CHIP TC4DA"
+	select ARCH_CHIP_TC4XX
+
+config ARCH_CHIP
+	string
+	default "tc397"		if ARCH_CHIP_TC397
+	default "tc4da"		if ARCH_CHIP_TC4DA
 
 config ARCH_DCACHE_ADDR
 	hex "AURIX Dcache base address"
@@ -72,11 +118,15 @@ config ARCH_MPU_CODE_NREGIONS
 	---help---
 		The code regions count
 
+config HAVE_SECURITY_CORE
+	bool
+	--help--
+		In addition to the 6 cores, tc4xx also has one more security core.
 
-if ARCH_TC3XX
+if ARCH_CHIP_TC3XX
 source "arch/tricore/src/tc3xx/Kconfig"
 endif
-if ARCH_TC397
+if ARCH_CHIP_TC397
 source "arch/tricore/src/tc397/Kconfig"
 endif
 endif # ARCH_TRICORE

arch/tricore/src/Makefile

@@ -23,7 +23,7 @@
 include $(TOPDIR)/Make.defs
 include chip/Make.defs
 
-ifeq ($(CONFIG_ARCH_TC3XX),y)
+ifeq ($(CONFIG_ARCH_CHIP_TC3XX),y)
 ARCH_SUBDIR = tc3xx
 include $(ARCH_SUBDIR)/Make.defs
 endif

arch/tricore/src/cmake/ToolchainGnuc.cmake

@@ -27,7 +27,7 @@ set(CMAKE_SYSTEM_VERSION 1)
 
 set(ARCH_SUBDIR)
 
-if(CONFIG_ARCH_TC3XX) # TC3XX
+if(CONFIG_ARCH_CHIP_TC3XX) # TC3XX
   set(ARCH_SUBDIR tc3xx)
 else()
   set(ARCH_SUBDIR tc3xx)

arch/tricore/src/cmake/ToolchainTasking.cmake

@@ -27,7 +27,7 @@ set(CMAKE_SYSTEM_VERSION 1)
 
 set(ARCH_SUBDIR)
 
-if(CONFIG_ARCH_TC3XX) # TC3XX
+if(CONFIG_ARCH_CHIP_TC3XX) # TC3XX
   set(ARCH_SUBDIR tc3xx)
 else()
   set(ARCH_SUBDIR tc3xx)

arch/tricore/src/common/tricore_irq.c

@@ -99,7 +99,7 @@ static void tricore_gpsrinitialize(void)
 
   for (i = 0; i < 6; i++)
     {
-#ifdef CONFIG_ARCH_TC3XX
+#ifdef CONFIG_ARCH_CHIP_TC3XX
       IfxSrc_init(src, IfxSrc_Tos_cpu0 + up_cpu_index(),
                   IRQ_TO_NDX(TRICORE_SRC2IRQ(src)));
 #else
@@ -113,7 +113,7 @@ static void tricore_gpsrinitialize(void)
 
   /* Cpucs gpsr init */
 
-#ifndef CONFIG_ARCH_TC3XX
+#ifndef CONFIG_ARCH_CHIP_TC3XX
   src = &SRC_GPSR6_SR0 + up_cpu_index();
   IfxSrc_init(src, IfxSrc_Tos_cpu0 + up_cpu_index(),
               IRQ_TO_NDX(TRICORE_SRC2IRQ(src)),
@@ -188,7 +188,7 @@ void up_enable_irq(int irq)
 {
   volatile Ifx_SRC_SRCR *src = &SRC_CPU_CPU0_SB + irq;
 
-#ifdef CONFIG_ARCH_TC3XX
+#ifdef CONFIG_ARCH_CHIP_TC3XX
   IfxSrc_init(src, IfxSrc_Tos_cpu0, IRQ_TO_NDX(irq));
 #else
   IfxSrc_init(src, IfxSrc_Tos_cpu0, IRQ_TO_NDX(irq), IfxSrc_VmId_none);

arch/tricore/src/common/tricore_main.c

@@ -68,10 +68,10 @@ void core0_main(void)
    * to ensure the normal startup of the system.
    */
 
-#if defined(CONFIG_ARCH_CHIP_AURIX_TC3XX)
+#if defined(CONFIG_ARCH_CHIP_TC3XX)
   IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword());
   IfxScuWdt_disableSafetyWatchdog(IfxScuWdt_getSafetyWatchdogPassword());
-#elif defined(CONFIG_ARCH_CHIP_AURIX_TC4XX)
+#elif defined(CONFIG_ARCH_CHIP_TC4XX)
   IfxWtu_disableCpuWatchdog(IfxWtu_getCpuWatchdogPassword());
   IfxWtu_disableSystemWatchdog(IfxWtu_getSystemWatchdogPassword());
 #endif

arch/tricore/src/common/tricore_mpu.c

@@ -66,12 +66,14 @@ static Ifx_CPU_DPRE get_dpre_value(unsigned int set)
       case 5:
         dpre_value.U = __mfcr(CPU_DPRE_5);
         break;
+#ifndef CONFIG_ARCH_CHIP_TC3XX
       case 6:
         dpre_value.U = __mfcr(CPU_DPRE_6);
         break;
       case 7:
         dpre_value.U = __mfcr(CPU_DPRE_7);
         break;
+#endif
       default:
         dpre_value.U = 0;
         break;
@@ -102,12 +104,14 @@ static void set_dpre_value(unsigned int set, Ifx_CPU_DPRE dpre_value)
       case 5:
         __mtcr(CPU_DPRE_5, dpre_value.U);
         break;
+#ifndef CONFIG_ARCH_CHIP_TC3XX
       case 6:
         __mtcr(CPU_DPRE_6, dpre_value.U);
         break;
       case 7:
         __mtcr(CPU_DPRE_7, dpre_value.U);
         break;
+#endif
       default:
         break;
     }
@@ -139,12 +143,14 @@ static Ifx_CPU_DPWE get_dpwe_value(unsigned int set)
       case 5:
         dpwe_value.U = __mfcr(CPU_DPWE_5);
         break;
+#ifndef CONFIG_ARCH_CHIP_TC3XX
       case 6:
         dpwe_value.U = __mfcr(CPU_DPWE_6);
         break;
       case 7:
         dpwe_value.U = __mfcr(CPU_DPWE_7);
         break;
+#endif
       default:
         dpwe_value.U = 0;
         break;
@@ -176,11 +182,13 @@ static void set_dpwe_value(unsigned int set, Ifx_CPU_DPWE dpwe_value)
         __mtcr(CPU_DPWE_5, dpwe_value.U);
         break;
       case 6:
+#ifndef CONFIG_ARCH_CHIP_TC3XX
         __mtcr(CPU_DPWE_6, dpwe_value.U);
         break;
       case 7:
         __mtcr(CPU_DPWE_7, dpwe_value.U);
         break;
+#endif
       default:
         break;
     }
@@ -212,12 +220,14 @@ static Ifx_CPU_CPXE get_cpxe_value(unsigned int set)
       case 5:
         cpxe_value.U = __mfcr(CPU_CPXE_5);
         break;
+#ifndef CONFIG_ARCH_CHIP_TC3XX
       case 6:
         cpxe_value.U = __mfcr(CPU_CPXE_6);
         break;
       case 7:
         cpxe_value.U = __mfcr(CPU_CPXE_7);
         break;
+#endif
       default:
         cpxe_value.U = 0;
         break;
@@ -248,12 +258,14 @@ static void set_cpxe_value(unsigned int set, Ifx_CPU_CPXE cpxe_value)
       case 5:
         __mtcr(CPU_CPXE_5, cpxe_value.U);
         break;
+#ifndef CONFIG_ARCH_CHIP_TC3XX
       case 6:
         __mtcr(CPU_CPXE_6, cpxe_value.U);
         break;
       case 7:
         __mtcr(CPU_CPXE_7, cpxe_value.U);
         break;
+#endif
       default:
         break;
     }
@@ -339,6 +351,7 @@ static int get_dpr_addrass_value(unsigned int region,
         dpr_l->U = __mfcr(CPU_DPR17_L);
         dpr_u->U = __mfcr(CPU_DPR17_U);
         break;
+#ifndef CONFIG_ARCH_CHIP_TC3XX
       case 18:
         dpr_l->U = __mfcr(CPU_DPR18_L);
         dpr_u->U = __mfcr(CPU_DPR18_U);
@@ -363,6 +376,7 @@ static int get_dpr_addrass_value(unsigned int region,
         dpr_l->U = __mfcr(CPU_DPR23_L);
         dpr_u->U = __mfcr(CPU_DPR23_U);
         break;
+#endif
       default:
         return -EINVAL;
     }
@@ -448,6 +462,7 @@ static void set_dpr_address_value(unsigned int region,
         __mtcr(CPU_DPR17_L, dpr_l.U);
         __mtcr(CPU_DPR17_U, dpr_u.U);
         break;
+#ifndef CONFIG_ARCH_CHIP_TC3XX
       case 18:
         __mtcr(CPU_DPR18_L, dpr_l.U);
         __mtcr(CPU_DPR18_U, dpr_u.U);
@@ -472,6 +487,7 @@ static void set_dpr_address_value(unsigned int region,
         __mtcr(CPU_DPR23_L, dpr_l.U);
         __mtcr(CPU_DPR23_U, dpr_u.U);
         break;
+#endif
       default:
         break;
     }
@@ -525,6 +541,7 @@ static int get_cpr_address_region(unsigned int region,
         cpr_l->U = __mfcr(CPU_CPR9_L);
         cpr_u->U = __mfcr(CPU_CPR9_U);
         break;
+#ifndef CONFIG_ARCH_CHIP_TC3XX
       case 10:
         cpr_l->U = __mfcr(CPU_CPR10_L);
         cpr_u->U = __mfcr(CPU_CPR10_U);
@@ -549,6 +566,7 @@ static int get_cpr_address_region(unsigned int region,
         cpr_l->U = __mfcr(CPU_CPR15_L);
         cpr_u->U = __mfcr(CPU_CPR15_U);
         break;
+#endif
       default:
         return -EINVAL;
     }
@@ -602,6 +620,7 @@ static void set_cpr_address_value(unsigned int region,
         __mtcr(CPU_CPR9_L, cpr_l.U);
         __mtcr(CPU_CPR9_U, cpr_u.U);
         break;
+#ifndef CONFIG_ARCH_CHIP_TC3XX
       case 10:
         __mtcr(CPU_CPR10_L, cpr_l.U);
         __mtcr(CPU_CPR10_U, cpr_u.U);
@@ -626,6 +645,7 @@ static void set_cpr_address_value(unsigned int region,
         __mtcr(CPU_CPR15_L, cpr_l.U);
         __mtcr(CPU_CPR15_U, cpr_u.U);
         break;
+#endif
     }
 
   UP_ISB();

boards/tricore/tc397/a2g-tc397-5v-tft/configs/nsh/defconfig

@@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="a2g-tc397-5v-tft"
 CONFIG_ARCH_BOARD_A2G_TC397_5V_TFT=y
 CONFIG_ARCH_CHIP="tc397"
 CONFIG_ARCH_CHIP_TC397=y
+CONFIG_ARCH_CHIP_TC3XX=y
 CONFIG_ARCH_INTERRUPTSTACK=2048
 CONFIG_ARCH_NUSER_INTERRUPTS=48
 CONFIG_ARCH_STACKDUMP=y