mirror of
https://github.com/apache/nuttx.git
synced 2026-05-21 21:34:07 +08:00
Merged nuttx/nuttx/master into master
This commit is contained in:
Masayuki Ishikawa
@@ -8,7 +8,7 @@
|
||||
<tr align="center" bgcolor="#e4e4e4">
|
||||
<td>
|
||||
<h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
|
||||
<p>Last Updated: February 19, 2017</p>
|
||||
<p>Last Updated: March 21, 2017</p>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
@@ -297,6 +297,8 @@ nuttx/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/us7032evb1/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- viewtool-stm32f107/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/viewtool-stm32f107/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- xmc4500-relax/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/xmc4500-relax/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- xtrs/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/xtrs/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- z16f2800100zcog/
|
||||
|
||||
@@ -1681,6 +1681,8 @@ nuttx/
|
||||
| | `- README.txt
|
||||
| |- viewtool-stm32f107/
|
||||
| | `- README.txt
|
||||
| |- xmc5400-relax/
|
||||
| | `- README.txt
|
||||
| |- xtrs/
|
||||
| | `- README.txt
|
||||
| |- z16f2800100zcog/
|
||||
|
||||
@@ -51,23 +51,23 @@
|
||||
#if defined(CONFIG_ARCH_CHIP_XMC4500)
|
||||
# define XMC4_NUSIC 3 /* Three USIC modules: USCI0-2 */
|
||||
# undef XMC4_SCU_GATING /* No clock gating registers */
|
||||
# define XMC4_NECATN 0 /* No EtherCAT support */
|
||||
# define XMC4_NECAT 0 /* No EtherCAT support */
|
||||
#elif defined(CONFIG_ARCH_CHIP_XMC4700)
|
||||
# define XMC4_NUSIC 3 /* Three USIC modules: USCI0-2 */
|
||||
# define XMC4_SCU_GATING 1 /* Has clock gating registers */
|
||||
# define XMC4_NECATN 0 /* No EtherCAT support */
|
||||
# define XMC4_NECAT 0 /* No EtherCAT support */
|
||||
#elif defined(CONFIG_ARCH_CHIP_XMC4700)
|
||||
# define XMC4_NUSIC 3 /* Three USIC modules: USCI0-2 */
|
||||
# define XMC4_SCU_GATING 1 /* Has clock gating registers */
|
||||
# define XMC4_NECATN 1 /* One EtherCAT module */
|
||||
# define XMC4_NECAT 1 /* One EtherCAT module */
|
||||
#else
|
||||
# error "Unsupported XMC4xxx chip"
|
||||
#endif
|
||||
|
||||
/* NVIC priority levels *************************************************************/
|
||||
/* Each priority field holds a priority value, 0-15. The lower the value, the greater
|
||||
* the priority of the corresponding interrupt. The XMC4500 implements only
|
||||
* bits[7:2] of this field, bits[1:0] read as zero and ignore writes.
|
||||
/* Each priority field holds a priority value. The lower the value, the greater the
|
||||
* priority of the corresponding interrupt. The XMC4500 implements only bits[7:2]
|
||||
* of this field, bits[1:0] read as zero and ignore writes.
|
||||
*/
|
||||
|
||||
#define NVIC_SYSH_PRIORITY_MIN 0xfc /* All bits[7:2] set is minimum priority */
|
||||
|
||||
@@ -184,7 +184,7 @@
|
||||
#define XMC4_IRQ_SDMMC_SR0 (XMC4_IRQ_FIRST+106) /* 106: SDMMC, SR0 */
|
||||
#define XMC4_IRQ_USB0_SR0 (XMC4_IRQ_FIRST+107) /* 107: USB, SR0 */
|
||||
#define XMC4_IRQ_ETH0_SR0 (XMC4_IRQ_FIRST+108) /* 108: Ethernet, module 0, SR0 */
|
||||
#define XMC4_IRQ_RESVD109 (XMC4_IRQ_FIRST+109) /* 109: Reserved */
|
||||
#define XMC4_IRQ_ECAT0_SR0 (XMC4_IRQ_FIRST+109) /* 109: EtherCAT, module 0, SR0 */
|
||||
#define XMC4_IRQ_GPCMA1_SR0 (XMC4_IRQ_FIRST+110) /* 110: GPDMA1, SR0 */
|
||||
#define XMC4_IRQ_RESVD111 (XMC4_IRQ_FIRST+111) /* 111: Reserved */
|
||||
|
||||
|
||||
@@ -6190,6 +6190,16 @@ config STM32_I2C_DUTY16_9
|
||||
default n
|
||||
depends on STM32_I2C
|
||||
|
||||
config STM32_I2C_DMA
|
||||
bool "I2C DMA Support"
|
||||
default n
|
||||
depends on STM32_I2C && STM32_STM32F40XX && STM32_DMA1
|
||||
---help---
|
||||
This option enables the DMA for I2C transfers.
|
||||
Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value for the
|
||||
I2C dma streams, else the default priority level is set to medium.
|
||||
Note: This option is compatible with CONFIG_I2C_POLLED.
|
||||
|
||||
endmenu
|
||||
|
||||
menu "SDIO Configuration"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -221,7 +221,7 @@
|
||||
#define XMC4_USB0_EP4_BASE 0x50040980
|
||||
#define XMC4_USB0_EP5_BASE 0x500409a0
|
||||
#define XMC4_USB0_EP6_BASE 0x500409c0
|
||||
#define XMC4_USB0_EP6_BASE 0x50100000 /* ECAT0 */
|
||||
#define XMC4_ECAT0_BASE 0x50100000 /* ECAT0 */
|
||||
|
||||
#define XMC4_PMU0_BASE 0x58000000 /* PMU0 registers */
|
||||
#define XMC4_FLASH0_BASE 0x58001000
|
||||
|
||||
@@ -71,7 +71,7 @@
|
||||
#define XMC4_PORT_OUT_OFFSET 0x0000 /* Port Output Register */
|
||||
#define XMC4_PORT_OMR_OFFSET 0x0004 /* Port Output Modification Register */
|
||||
|
||||
#define XMC4_PORT_IOCR_OFFSET(n) (0x0010 + ((n) & 3))
|
||||
#define XMC4_PORT_IOCR_OFFSET(n) (0x0010 + ((n) & ~3))
|
||||
#define XMC4_PORT_IOCR0_OFFSET 0x0010 /* Port Input/Output Control Register 0 */
|
||||
#define XMC4_PORT_IOCR4_OFFSET 0x0014 /* Port Input/Output Control Register 4 */
|
||||
#define XMC4_PORT_IOCR8_OFFSET 0x0018 /* Port Input/Output Control Register 8 */
|
||||
@@ -79,7 +79,7 @@
|
||||
|
||||
#define XMC4_PORT_IN_OFFSET 0x0024 /* Port Input Register */
|
||||
|
||||
#define XMC4_PORT_PDR_OFFSET(n) (0x0010 + (((n) >> 1) & 3))
|
||||
#define XMC4_PORT_PDR_OFFSET(n) (0x0040 + (((n) >> 1) & ~3))
|
||||
#define XMC4_PORT_PDR0_OFFSET 0x0040 /* Port Pad Driver Mode 0 Register */
|
||||
#define XMC4_PORT_PDR1_OFFSET 0x0044 /* Port Pad Driver Mode 1 Register */
|
||||
|
||||
@@ -399,19 +399,19 @@
|
||||
#define PORT_PDR0_PD2_SHIFT (8) /* Bit 8-10: Pad Driver Mode for Port n Pin 2 */
|
||||
#define PORT_PDR0_PD2_MASK (7 << PORT_PDR0_PD2_SHIFT)
|
||||
# define PORT_PDR0_PD2(n) ((uint32_t)(n) << PORT_PDR0_PD2_SHIFT)
|
||||
#define PORT_PDR0_PD3_SHIFT (12) /* Bit 12-14: Pad Driver Mode for Port 0 Pin 3 */
|
||||
#define PORT_PDR0_PD3_SHIFT (12) /* Bit 12-14: Pad Driver Mode for Port n Pin 3 */
|
||||
#define PORT_PDR0_PD3_MASK (7 << PORT_PDR0_PD3_SHIFT)
|
||||
# define PORT_PDR0_PD3(n) ((uint32_t)(n) << PORT_PDR0_PD3_SHIFT)
|
||||
#define PORT_PDR0_PD4_SHIFT (16) /* Bit 16-18: Pad Driver Mode for Port 0 Pin 4 */
|
||||
#define PORT_PDR0_PD4_SHIFT (16) /* Bit 16-18: Pad Driver Mode for Port n Pin 4 */
|
||||
#define PORT_PDR0_PD4_MASK (7 << PORT_PDR0_PD4_SHIFT)
|
||||
# define PORT_PDR0_PD4(n) ((uint32_t)(n) << PORT_PDR0_PD4_SHIFT)
|
||||
#define PORT_PDR0_PD5_SHIFT (20) /* Bit 20-22: Pad Driver Mode for Port 0 Pin 5 */
|
||||
#define PORT_PDR0_PD5_SHIFT (20) /* Bit 20-22: Pad Driver Mode for Port n Pin 5 */
|
||||
#define PORT_PDR0_PD5_MASK (7 << PORT_PDR0_PD5_SHIFT)
|
||||
# define PORT_PDR0_PD5(n) ((uint32_t)(n) << PORT_PDR0_PD5_SHIFT)
|
||||
#define PORT_PDR0_PD6_SHIFT (24) /* Bit 24-26: Pad Driver Mode for Port 0 Pin 6 */
|
||||
#define PORT_PDR0_PD6_SHIFT (24) /* Bit 24-26: Pad Driver Mode for Port n Pin 6 */
|
||||
#define PORT_PDR0_PD6_MASK (7 << PORT_PDR0_PD6_SHIFT)
|
||||
# define PORT_PDR0_PD6(n) ((uint32_t)(n) << PORT_PDR0_PD6_SHIFT)
|
||||
#define PORT_PDR0_PD7_SHIFT (28) /* Bit 28-30: Pad Driver Mode for Port 0 Pin 7 */
|
||||
#define PORT_PDR0_PD7_SHIFT (28) /* Bit 28-30: Pad Driver Mode for Port n Pin 7 */
|
||||
#define PORT_PDR0_PD7_MASK (7 << PORT_PDR0_PD7_SHIFT)
|
||||
# define PORT_PDR0_PD7(n) ((uint32_t)(n) << PORT_PDR0_PD7_SHIFT)
|
||||
|
||||
@@ -429,19 +429,19 @@
|
||||
#define PORT_PDR1_PD10_SHIFT (8) /* Bit 8-10: Pad Driver Mode for Port n Pin 10 */
|
||||
#define PORT_PDR1_PD10_MASK (7 << PORT_PDR1_PD10_SHIFT)
|
||||
# define PORT_PDR1_PD10(n) ((uint32_t)(n) << PORT_PDR1_PD10_SHIFT)
|
||||
#define PORT_PDR1_PD11_SHIFT (12) /* Bit 12-14: Pad Driver Mode for Port 0 Pin 11 */
|
||||
#define PORT_PDR1_PD11_SHIFT (12) /* Bit 12-14: Pad Driver Mode for Port n Pin 11 */
|
||||
#define PORT_PDR1_PD11_MASK (7 << PORT_PDR1_PD11_SHIFT)
|
||||
# define PORT_PDR1_PD11(n) ((uint32_t)(n) << PORT_PDR1_PD11_SHIFT)
|
||||
#define PORT_PDR1_PD12_SHIFT (16) /* Bit 16-18: Pad Driver Mode for Port 0 Pin 12 */
|
||||
#define PORT_PDR1_PD12_SHIFT (16) /* Bit 16-18: Pad Driver Mode for Port n Pin 12 */
|
||||
#define PORT_PDR1_PD12_MASK (7 << PORT_PDR1_PD12_SHIFT)
|
||||
# define PORT_PDR1_PD12(n) ((uint32_t)(n) << PORT_PDR1_PD12_SHIFT)
|
||||
#define PORT_PDR1_PD13_SHIFT (20) /* Bit 20-22: Pad Driver Mode for Port 0 Pin 13 */
|
||||
#define PORT_PDR1_PD13_SHIFT (20) /* Bit 20-22: Pad Driver Mode for Port n Pin 13 */
|
||||
#define PORT_PDR1_PD13_MASK (7 << PORT_PDR1_PD13_SHIFT)
|
||||
# define PORT_PDR1_PD13(n) ((uint32_t)(n) << PORT_PDR1_PD13_SHIFT)
|
||||
#define PORT_PDR1_PD14_SHIFT (24) /* Bit 24-26: Pad Driver Mode for Port 0 Pin 14 */
|
||||
#define PORT_PDR1_PD14_SHIFT (24) /* Bit 24-26: Pad Driver Mode for Port n Pin 14 */
|
||||
#define PORT_PDR1_PD14_MASK (7 << PORT_PDR1_PD14_SHIFT)
|
||||
# define PORT_PDR1_PD14(n) ((uint32_t)(n) << PORT_PDR1_PD14_SHIFT)
|
||||
#define PORT_PDR1_PD15_SHIFT (28) /* Bit 28-30: Pad Driver Mode for Port 0 Pin 15 */
|
||||
#define PORT_PDR1_PD15_SHIFT (28) /* Bit 28-30: Pad Driver Mode for Port n Pin 15 */
|
||||
#define PORT_PDR1_PD15_MASK (7 << PORT_PDR1_PD15_SHIFT)
|
||||
# define PORT_PDR1_PD15(n) ((uint32_t)(n) << PORT_PDR1_PD15_SHIFT)
|
||||
|
||||
|
||||
@@ -889,7 +889,7 @@
|
||||
|
||||
#define SCU_PBCLKCR_PBDIV (1 << 0) /* Bit 0: PB Clock Divider Enable */
|
||||
# define SCU_PBCLKCR_PBDIV_FCPU (0) /* 0=fCPU */
|
||||
# define SCU_PBCLKCR_PBDIV_DIV2 ((1 << 0) /* 1=fCPU/2 */
|
||||
# define SCU_PBCLKCR_PBDIV_DIV2 (1 << 0) /* 1=fCPU/2 */
|
||||
|
||||
/* USB Clock Control */
|
||||
|
||||
|
||||
@@ -563,7 +563,7 @@
|
||||
# define USIC_SCTR_TRM_ACTIVE (3 << USIC_SCTR_TRM_SHIFT) /* Active without regard to signal level */
|
||||
#define USIC_SCTR_FLE_SHIFT (16) /* Bits 16-21: Frame Length */
|
||||
#define USIC_SCTR_FLE_MASK (0x3f << USIC_SCTR_FLE_SHIFT)
|
||||
# define USIC_SCTR_FLE(n) ((uint32_t)(n) << USIC_SCTR_FLE_SHIFT)
|
||||
# define USIC_SCTR_FLE(n) ((uint32_t)((n)-1) << USIC_SCTR_FLE_SHIFT)
|
||||
#define USIC_SCTR_WLE_SHIFT (24) /* Bits 24-27: Word Length */
|
||||
#define USIC_SCTR_WLE_MASK (15 << USIC_SCTR_WLE_SHIFT)
|
||||
# define USIC_SCTR_WLE(n) ((uint32_t)((n)-1) << USIC_SCTR_WLE_SHIFT)
|
||||
|
||||
@@ -105,13 +105,18 @@
|
||||
#define CLKSET_VALUE (0x00000000)
|
||||
#define SYSCLKCR_VALUE (0x00010001)
|
||||
#define CPUCLKCR_VALUE (0x00000000)
|
||||
#define PBCLKCR_VALUE (0x00000000)
|
||||
#define CCUCLKCR_VALUE (0x00000000)
|
||||
#define WDTCLKCR_VALUE (0x00000000)
|
||||
#define EBUCLKCR_VALUE (0x00000003)
|
||||
#define USBCLKCR_VALUE (0x00010000)
|
||||
#define EXTCLKCR_VALUE (0x01200003)
|
||||
|
||||
#if BOARD_PBDIV == 1
|
||||
# define PBCLKCR_VALUE SCU_PBCLKCR_PBDIV_FCPU
|
||||
#else /* BOARD_PBDIV == 2 */
|
||||
# define PBCLKCR_VALUE SCU_PBCLKCR_PBDIV_DIV2
|
||||
#endif
|
||||
|
||||
#if ((USBCLKCR_VALUE & SCU_USBCLKCR_USBSEL) == SCU_USBCLKCR_USBSEL_USBPLL)
|
||||
# define USB_DIV 3
|
||||
#else
|
||||
@@ -182,9 +187,9 @@ void xmc4_clock_configure(void)
|
||||
regval = getreg32(XMC4_SCU_PWRSTAT);
|
||||
if ((regval & SCU_PWR_HIBEN) == 0)
|
||||
{
|
||||
regval = getreg32(XMC4_SCU_PWRSET);
|
||||
regval |= SCU_PWR_HIBEN;
|
||||
putreg32(regval, XMC4_SCU_PWRSTAT);
|
||||
/* Enable the HIB domain */
|
||||
|
||||
putreg32(SCU_PWR_HIBEN, XMC4_SCU_PWRSET);
|
||||
|
||||
/* Wait until HIB domain is enabled */
|
||||
|
||||
@@ -193,7 +198,7 @@ void xmc4_clock_configure(void)
|
||||
}
|
||||
}
|
||||
|
||||
/* Remove the reset only if HIB domain were in a state of reset */
|
||||
/* Remove the reset only if HIB domain was in a state of reset */
|
||||
|
||||
regval = getreg32(XMC4_SCU_RSTSTAT);
|
||||
if ((regval & SCU_RSTSTAT_HIBRS) != 0)
|
||||
@@ -387,7 +392,7 @@ void xmc4_clock_configure(void)
|
||||
/* Before scaling to final frequency we need to setup the clock dividers */
|
||||
|
||||
putreg32(SYSCLKCR_VALUE, XMC4_SCU_SYSCLKCR);
|
||||
putreg32(PBCLKCR_VALUE, XMC4_SCU_PBCLKCR);
|
||||
putreg32(PBCLKCR_VALUE, XMC4_SCU_PBCLKCR);
|
||||
putreg32(CPUCLKCR_VALUE, XMC4_SCU_CPUCLKCR);
|
||||
putreg32(CCUCLKCR_VALUE, XMC4_SCU_CCUCLKCR);
|
||||
putreg32(WDTCLKCR_VALUE, XMC4_SCU_WDTCLKCR);
|
||||
|
||||
@@ -161,6 +161,7 @@ uint32_t xmc4_get_coreclock(void)
|
||||
uint32_t xmc4_get_periphclock(void)
|
||||
{
|
||||
uint32_t periphclock;
|
||||
uint32_t regval;
|
||||
|
||||
/* Get the CPU clock frequency. Unless it is divided down, this also the
|
||||
* peripheral clock frequency.
|
||||
@@ -170,12 +171,12 @@ uint32_t xmc4_get_periphclock(void)
|
||||
|
||||
/* Get the peripheral clock divider */
|
||||
|
||||
periphclock = getreg32(XMC4_SCU_PBCLKCR);
|
||||
if ((periphclock & SCU_PBCLKCR_PBDIV) != 0)
|
||||
regval = getreg32(XMC4_SCU_PBCLKCR);
|
||||
if ((regval & SCU_PBCLKCR_PBDIV) != 0)
|
||||
{
|
||||
/* The peripheral clock is fCPU/2 */
|
||||
|
||||
periphclock <<= 1;
|
||||
periphclock >>= 1;
|
||||
}
|
||||
|
||||
return periphclock;
|
||||
|
||||
@@ -234,7 +234,7 @@ static inline void xmc4_gpio_hwsel(uintptr_t portbase, unsigned int pin,
|
||||
****************************************************************************/
|
||||
|
||||
static inline void xmc4_gpio_pdisc(uintptr_t portbase, unsigned int pin,
|
||||
bool value)
|
||||
bool enable)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t mask;
|
||||
@@ -243,16 +243,21 @@ static inline void xmc4_gpio_pdisc(uintptr_t portbase, unsigned int pin,
|
||||
|
||||
regval = xmc4_gpio_getreg(portbase, XMC4_PORT_PDISC_OFFSET);
|
||||
|
||||
/* Set/clear the enable/disable (or analg) value for this field */
|
||||
/* Set or clear the pin field in the PDISC register.
|
||||
*
|
||||
* Disable = set
|
||||
* Analog = set
|
||||
* Enable = clear
|
||||
*/
|
||||
|
||||
mask = PORT_PIN(pin);
|
||||
if (value)
|
||||
if (enable)
|
||||
{
|
||||
regval |= mask;
|
||||
regval &= ~mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval &= ~mask;
|
||||
regval |= mask;
|
||||
}
|
||||
|
||||
xmc4_gpio_putreg(portbase, XMC4_PORT_PDISC_OFFSET, regval);
|
||||
@@ -267,7 +272,7 @@ static inline void xmc4_gpio_pdisc(uintptr_t portbase, unsigned int pin,
|
||||
****************************************************************************/
|
||||
|
||||
static inline void xmc4_gpio_pps(uintptr_t portbase, unsigned int pin,
|
||||
bool value)
|
||||
bool powersave)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t mask;
|
||||
@@ -276,10 +281,10 @@ static inline void xmc4_gpio_pps(uintptr_t portbase, unsigned int pin,
|
||||
|
||||
regval = xmc4_gpio_getreg(portbase, XMC4_PORT_PPS_OFFSET);
|
||||
|
||||
/* Set/clear the enable/disable (or analg) value for this field */
|
||||
/* Set/clear the enable/disable power save value for this field */
|
||||
|
||||
mask = PORT_PIN(pin);
|
||||
if (value)
|
||||
if (powersave)
|
||||
{
|
||||
regval |= mask;
|
||||
}
|
||||
@@ -307,7 +312,7 @@ static void xmc4_gpio_pdr(uintptr_t portbase, unsigned int pin,
|
||||
unsigned int offset;
|
||||
unsigned int shift;
|
||||
|
||||
/* Read the PDRregister */
|
||||
/* Read the PDR register */
|
||||
|
||||
offset = XMC4_PORT_PDR_OFFSET(pin);
|
||||
regval = xmc4_gpio_getreg(portbase, offset);
|
||||
@@ -412,18 +417,18 @@ int xmc4_gpio_config(gpioconfig_t pinconfig)
|
||||
value = xmc4_gpio_pinctrl(pinconfig);
|
||||
xmc4_gpio_hwsel(portbase, pin, value);
|
||||
|
||||
/* Select drive strength */
|
||||
/* Select drive strength (PDR) */
|
||||
|
||||
value = xmc4_gpio_padtype(pinconfig);
|
||||
xmc4_gpio_pdr(portbase, pin, value);
|
||||
|
||||
/* Enable/enable pad or Analog only (PDISC) */
|
||||
|
||||
xmc4_gpio_pdisc(portbase, pin, ((pinconfig & GPIO_PAD_DISABLE) != 0));
|
||||
xmc4_gpio_pdisc(portbase, pin, ((pinconfig & GPIO_PAD_DISABLE) == 0));
|
||||
|
||||
/* Make sure pin is not in power save mode (PDR) */
|
||||
/* Make sure pin is not in power save mode (PPS) */
|
||||
|
||||
xmc4_gpio_pdisc(portbase, pin, false);
|
||||
xmc4_gpio_pps(portbase, pin, false);
|
||||
|
||||
leave_critical_section(flags);
|
||||
return OK;
|
||||
|
||||
@@ -79,8 +79,8 @@
|
||||
# define GPIO_OUTPUT_ALT4 (IOCR_OUTPUT_ALT4 << GPIO_PINTYPE_SHIFT)
|
||||
|
||||
# define _GPIO_OUTPUT_BIT (16 << GPIO_PINTYPE_SHIFT)
|
||||
# define GPIO_ISINPUT(p) (((p) & _GPIO_OUTPUT_BIT) != 0)
|
||||
# define GPIO_ISOUTPUT(p) (((p) & _GPIO_OUTPUT_BIT) == 0)
|
||||
# define GPIO_ISINPUT(p) (((p) & _GPIO_OUTPUT_BIT) == 0)
|
||||
# define GPIO_ISOUTPUT(p) (((p) & _GPIO_OUTPUT_BIT) != 0)
|
||||
|
||||
/* Pin type modifier:
|
||||
*
|
||||
@@ -160,7 +160,7 @@
|
||||
*/
|
||||
|
||||
#define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */
|
||||
#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT)
|
||||
@@ -180,7 +180,7 @@
|
||||
*/
|
||||
|
||||
#define GPIO_PIN_SHIFT (0) /* Bits 0-3: GPIO pin: 0-15 */
|
||||
#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
|
||||
|
||||
@@ -275,7 +275,7 @@ int xmc4_uart_configure(enum usic_channel_e channel,
|
||||
* the config structure.
|
||||
*/
|
||||
|
||||
ret = xmc4_uisc_baudrate(channel, config->baud, UART_OVERSAMPLING);
|
||||
ret = xmc4_usic_baudrate(channel, config->baud, UART_OVERSAMPLING);
|
||||
|
||||
/* Configure frame format.
|
||||
*
|
||||
|
||||
@@ -121,12 +121,12 @@ int xmc4_enable_usic(enum usic_e usic)
|
||||
|
||||
putreg32(SCU_CGAT0_USIC0, XMC4_SCU_CGATCLR0);
|
||||
|
||||
/* De-assert peripheral reset USIC0 */
|
||||
/* Set bit in PRCLR0 to de-assert USIC0 peripheral reset */
|
||||
|
||||
putreg32(SCU_PR0_USIC0RS, XMC4_SCU_PRCLR0);
|
||||
}
|
||||
#else
|
||||
/* De-assert peripheral reset USIC0 */
|
||||
/* Set bit in PRCLR0 to de-assert USIC0 peripheral reset */
|
||||
|
||||
putreg32(SCU_PR0_USIC0RS, XMC4_SCU_PRCLR0);
|
||||
#endif
|
||||
@@ -143,12 +143,12 @@ int xmc4_enable_usic(enum usic_e usic)
|
||||
|
||||
putreg32(SCU_CGAT1_USIC1, XMC4_SCU_CGATCLR1);
|
||||
|
||||
/* De-assert peripheral reset USIC1 */
|
||||
/* Set bit in PRCLR1 to de-assert USIC1 peripheral reset */
|
||||
|
||||
putreg32(SCU_PR1_USIC1RS, XMC4_SCU_PRCLR1);
|
||||
}
|
||||
#else
|
||||
/* De-assert peripheral reset USIC1 */
|
||||
/* Set bit in PRCLR1 to de-assert USIC1 peripheral reset */
|
||||
|
||||
putreg32(SCU_PR1_USIC1RS, XMC4_SCU_PRCLR1);
|
||||
#endif
|
||||
@@ -165,12 +165,12 @@ int xmc4_enable_usic(enum usic_e usic)
|
||||
|
||||
putreg32(SCU_CGAT1_USIC2, XMC4_SCU_CGATCLR1);
|
||||
|
||||
/* De-assert peripheral reset USIC2 */
|
||||
/* Set bit in PRCLR1 to de-assert USIC2 peripheral reset */
|
||||
|
||||
putreg32(SCU_PR1_USIC2RS, XMC4_SCU_PRCLR1);
|
||||
}
|
||||
#else
|
||||
/* De-assert peripheral reset USIC2 */
|
||||
/* Set bit in PRCLR1 to de-assert USIC2 peripheral reset */
|
||||
|
||||
putreg32(SCU_PR1_USIC2RS, XMC4_SCU_PRCLR1);
|
||||
#endif
|
||||
@@ -203,7 +203,7 @@ int xmc4_disable_usic(enum usic_e usic)
|
||||
switch (usic)
|
||||
{
|
||||
case USIC0:
|
||||
/* Assert peripheral reset USIC0 */
|
||||
/* Set bit in PRSET0 to assert USIC0 peripheral reset */
|
||||
|
||||
putreg32(SCU_PR0_USIC0RS, XMC4_SCU_PRSET0);
|
||||
|
||||
@@ -216,7 +216,7 @@ int xmc4_disable_usic(enum usic_e usic)
|
||||
|
||||
#if XMC4_NUSIC > 1
|
||||
case USIC1:
|
||||
/* Assert peripheral reset USIC0 */
|
||||
/* Set bit in PRSET1 to assert USIC1 peripheral reset */
|
||||
|
||||
putreg32(SCU_PR1_USIC1RS, XMC4_SCU_PRSET1);
|
||||
|
||||
@@ -229,7 +229,7 @@ int xmc4_disable_usic(enum usic_e usic)
|
||||
|
||||
#if XMC4_NUSIC > 2
|
||||
case USIC2:
|
||||
/* Assert peripheral reset USIC0 */
|
||||
/* Set bit in PRSET1 to assert USIC2 peripheral reset */
|
||||
|
||||
putreg32(SCU_PR1_USIC2RS, XMC4_SCU_PRSET1);
|
||||
|
||||
@@ -385,7 +385,7 @@ int xmc4_disable_usic_channel(enum usic_channel_e channel)
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: xmc4_uisc_baudrate
|
||||
* Name: xmc4_usic_baudrate
|
||||
*
|
||||
* Description:
|
||||
* Set the USIC baudrate for the USIC channel
|
||||
@@ -396,7 +396,7 @@ int xmc4_disable_usic_channel(enum usic_channel_e channel)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int xmc4_uisc_baudrate(enum usic_channel_e channel, uint32_t baud,
|
||||
int xmc4_usic_baudrate(enum usic_channel_e channel, uint32_t baud,
|
||||
uint32_t oversampling)
|
||||
{
|
||||
uintptr_t base;
|
||||
@@ -448,14 +448,14 @@ int xmc4_uisc_baudrate(enum usic_channel_e channel, uint32_t baud,
|
||||
|
||||
/* Select and setup the fractional divider */
|
||||
|
||||
regval = USIC_FDR_DM_FRACTIONAL | (clkdiv_min << USIC_FDR_STEP_SHIFT);
|
||||
regval = USIC_FDR_DM_FRACTIONAL | USIC_FDR_STEP(clkdiv_min);
|
||||
putreg32(regval, base + XMC4_USIC_FDR_OFFSET);
|
||||
|
||||
/* Setup and enable the baud rate generator */
|
||||
|
||||
regval = getreg32(base + XMC4_USIC_BRG_OFFSET);
|
||||
regval &= ~(USIC_BRG_DCTQ_MASK | USIC_BRG_PDIV_MASK | USIC_BRG_PCTQ_MASK | USIC_BRG_PPPEN);
|
||||
regval |= (USIC_BRG_DCTQ(oversampling - 1) | USIC_BRG_PDIV(pdiv_int_min - 1));
|
||||
regval |= (USIC_BRG_DCTQ(oversampling - 1) | USIC_BRG_PDIV(pdiv_int_min - 1));
|
||||
putreg32(regval, base + XMC4_USIC_BRG_OFFSET);
|
||||
|
||||
ret = OK;
|
||||
|
||||
@@ -177,7 +177,7 @@ int xmc4_enable_usic_channel(enum usic_channel_e channel);
|
||||
int xmc4_disable_usic_channel(enum usic_channel_e channel);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: xmc4_uisc_baudrate
|
||||
* Name: xmc4_usic_baudrate
|
||||
*
|
||||
* Description:
|
||||
* Set the USIC baudrate for the USIC channel
|
||||
@@ -188,7 +188,7 @@ int xmc4_disable_usic_channel(enum usic_channel_e channel);
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int xmc4_uisc_baudrate(enum usic_channel_e channel, uint32_t baud,
|
||||
int xmc4_usic_baudrate(enum usic_channel_e channel, uint32_t baud,
|
||||
uint32_t oversampling);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_XMC4_XMC4_USIC_H */
|
||||
|
||||
@@ -0,0 +1,168 @@
|
||||
README for the XMC4500 Relax
|
||||
============================
|
||||
|
||||
The directory provides board support for the Infinion XMC4500 Relax v1
|
||||
boards. There are to variants of this board: There is a Lite version
|
||||
that has fewer features, for example, no 32.768KHz crystal.
|
||||
|
||||
The current configurations support only the Lite version of the board.
|
||||
|
||||
Status
|
||||
======
|
||||
|
||||
2017-03-21: The XMC4500 Relax boots into NSH, provides the NSH prompt,
|
||||
and the LEDs are working. But there is a problem with the USIC baud
|
||||
(probably); I get garbage on the serial console. This probably means
|
||||
that either the peripheral clocking is wrong or the baud configuration
|
||||
is wrong.
|
||||
|
||||
Serial Console
|
||||
==============
|
||||
|
||||
Be default, UART0 (aka, USIC0, channel 0) is used as the serial console.
|
||||
The RX and TX pins is available:
|
||||
|
||||
RX - P1.4, Connector X2, pin 17
|
||||
TX - P1.5, Connector X2, pin 16
|
||||
GND - Available on pins 1-4 of either connector X1 or X2
|
||||
VDD3.3 - Available on pins 37-38 of either connector X1 or X2
|
||||
VDD5 - Available on pins 39-40 of either connector X1 or X2
|
||||
|
||||
A TTL to RS-232 convertor or a USB TTL-to-USB serial adaptor is required.
|
||||
The notion of what is TX and what is RX depends on your point of view.
|
||||
With the TTL to RS-232 converter, I connect pin 17 to the pin labeled
|
||||
TX on the converter and pin 16 to the RX pin on the converter.
|
||||
|
||||
LEDs
|
||||
====
|
||||
|
||||
The XMC4500 Relax Lite v1 board has two LEDs:
|
||||
|
||||
LED1 P1.1 High output illuminates
|
||||
LED2 P1.0 High output illuminates
|
||||
|
||||
If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in
|
||||
any way. The definitions provided in the board.h header file can be used
|
||||
to access individual LEDs.
|
||||
|
||||
These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
|
||||
defined. In that case, the usage by the board port is defined in
|
||||
include/board.h and src/sam_autoleds.c. The LEDs are used to encode
|
||||
OS-related events as follows:
|
||||
|
||||
SYMBOL Meaning LED state
|
||||
LED1 LED2
|
||||
------------------ ------------------------ ------ ------
|
||||
LED_STARTED NuttX has been started OFF OFF
|
||||
LED_HEAPALLOCATE Heap has been allocated OFF OFF
|
||||
LED_IRQSENABLED Interrupts enabled OFF OFF
|
||||
LED_STACKCREATED Idle stack created ON OFF
|
||||
LED_INIRQ In an interrupt No change
|
||||
LED_SIGNAL In a signal handler No change
|
||||
LED_ASSERTION An assertion failed No change
|
||||
LED_PANIC The system has crashed N/C Blinking
|
||||
LED_IDLE MCU is is sleep mode Not used
|
||||
|
||||
Thus if LED1 is statically on, NuttX has successfully booted and is,
|
||||
apparently, running normally. If LED2 is flashing at approximately
|
||||
2Hz, then a fatal error has been detected and the system has halted.
|
||||
|
||||
Buttons
|
||||
=======
|
||||
|
||||
The XMC4500 Relax Lite v1 board has two buttons:
|
||||
|
||||
BUTTON1 P1.14 Low input sensed when button pressed
|
||||
BUTTON2 P1.15 Low input sensed when button pressed
|
||||
|
||||
Configurations
|
||||
==============
|
||||
|
||||
Information Common to All Configurations
|
||||
----------------------------------------
|
||||
Each XMC4500 Relax configuration is maintained in a sub-directory and
|
||||
can be selected as follow:
|
||||
|
||||
cd tools
|
||||
./configure.sh xmc5400-relax/<subdir>
|
||||
cd -
|
||||
. ./setenv.sh
|
||||
|
||||
Before sourcing the setenv.sh file above, you should examine it and
|
||||
perform edits as necessary so that TOOLCHAIN_BIN is the correct path
|
||||
to the directory than holds your toolchain binaries.
|
||||
|
||||
And then build NuttX by simply typing the following. At the conclusion of
|
||||
the make, the nuttx binary will reside in an ELF file called, simply, nuttx.
|
||||
|
||||
make oldconfig
|
||||
make
|
||||
|
||||
The <subdir> that is provided above as an argument to the tools/configure.sh
|
||||
must be is one of the following.
|
||||
|
||||
NOTES:
|
||||
|
||||
1. These configurations use the mconf-based configuration tool. To
|
||||
change any of these configurations using that tool, you should:
|
||||
|
||||
a. Build and install the kconfig-mconf tool. See nuttx/README.txt
|
||||
see additional README.txt files in the NuttX tools repository.
|
||||
|
||||
b. Execute 'make menuconfig' in nuttx/ in order to start the
|
||||
reconfiguration process.
|
||||
|
||||
2. Unless stated otherwise, all configurations generate console
|
||||
output on UART0 (aka USIC0, channel 0) as described above under
|
||||
"Serial Console". The relevant configuration settings are listed
|
||||
below:
|
||||
|
||||
CONFIG_XMC4_USIC0=y
|
||||
CONFIG_XMC4_USIC0_CHAN0_ISUART=y
|
||||
CONFIG_XMC4_USIC0_CHAN1_NONE=y
|
||||
|
||||
CONFIG_UART0_SERIALDRIVER=y
|
||||
CONFIG_UART0_SERIAL_CONSOLE=y
|
||||
|
||||
CONFIG_UART0_RXBUFSIZE=256
|
||||
CONFIG_UART0_TXBUFSIZE=256
|
||||
CONFIG_UART0_BAUD=115200
|
||||
CONFIG_UART0_BITS=8
|
||||
CONFIG_UART0_PARITY=0
|
||||
CONFIG_UART0_2STOP=0
|
||||
|
||||
|
||||
3. All of these configurations are set up to build under Windows using the
|
||||
"GNU Tools for ARM Embedded Processors" that is maintained by ARM
|
||||
(unless stated otherwise in the description of the configuration).
|
||||
|
||||
https://launchpad.net/gcc-arm-embedded
|
||||
|
||||
That toolchain selection can easily be reconfigured using
|
||||
'make menuconfig'. Here are the relevant current settings:
|
||||
|
||||
Build Setup:
|
||||
CONFIG_HOST_WINDOWS=y : Window environment
|
||||
CONFIG_WINDOWS_CYGWIN=y : Cywin under Windows
|
||||
|
||||
System Type -> Toolchain:
|
||||
CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain
|
||||
|
||||
Configuration sub-directories
|
||||
-----------------------------
|
||||
|
||||
nsh:
|
||||
|
||||
Configures the NuttShell (nsh) located at examples/nsh. This
|
||||
configuration is focused on low level, command-line driver testing. It
|
||||
has no network.
|
||||
|
||||
NOTES:
|
||||
|
||||
1. NSH built-in applications are supported.
|
||||
|
||||
Binary Formats:
|
||||
CONFIG_BUILTIN=y : Enable support for built-in programs
|
||||
|
||||
Application Configuration:
|
||||
CONFIG_NSH_BUILTIN_APPS=y : Enable starting apps from NSH command line
|
||||
@@ -53,16 +53,21 @@
|
||||
|
||||
/* Clocking *************************************************************************/
|
||||
/* Default clock initialization
|
||||
* fPLL = 288MHz => fSYS = 288MHz => fCPU = 144MHz
|
||||
* => fPB = 144MHz
|
||||
* => fCCU = 144MHz
|
||||
* => fETH = 72MHz
|
||||
* => fUSB = 48MHz
|
||||
* => fEBU = 72MHz
|
||||
*
|
||||
* fXTAL = 12Mhz
|
||||
* -> fPLL = (fXTAL / (2 * 1) * 48) = 288MHz
|
||||
* -> fSYS = (fPLL / 1) = 288MHz
|
||||
* -> fCPU = (fSYS / 2) = 144MHz
|
||||
* -> fPERIPH = (fCPU / 1) = 144MHz
|
||||
* -> fCCU = (fSYS / 2) = 144MHz
|
||||
* -> fETH = 72MHz (REVISIT)
|
||||
* -> fUSB = 48MHz (REVISIT)
|
||||
* -> fEBU = 72MHz (REVISIT)
|
||||
*
|
||||
* fUSBPLL Disabled, only enabled if SCU_CLK_USBCLKCR_USBSEL_USBPLL is selected
|
||||
*
|
||||
* fOFI = 24MHz => fWDT = 24MHz
|
||||
* fOFI = 24MHz
|
||||
* -> fWDT = 24MHz (REVISIT)
|
||||
*/
|
||||
|
||||
#undef BOARD_FOFI_CALIBRATION /* Enable factory calibration */
|
||||
@@ -79,7 +84,7 @@
|
||||
/* Select the external crystal as the PLL clock source */
|
||||
|
||||
#define BOARD_PLL_CLOCKSRC_XTAL 1 /* PLL Clock source == extnernal crystal */
|
||||
#undef BOARD_PLL_CLOCKSRC_OFI /* PLL Clock source != internal fast oscillator */
|
||||
#undef BOARD_PLL_CLOCKSRC_OFI /* PLL Clock source != internal fast oscillator */
|
||||
|
||||
/* PLL Configuration:
|
||||
*
|
||||
@@ -95,16 +100,21 @@
|
||||
#define BOARD_PLL_K2DIV 1
|
||||
#define BOARD_PLL_FREQUENCY 288000000
|
||||
|
||||
/* System frequency is divided down from PLL output */
|
||||
/* System frequency, fSYS, is divided down from PLL output */
|
||||
|
||||
#define BOARD_SYSDIV 1 /* PLL Output divider to get fSYS */
|
||||
#define BOARD_SYS_FREQUENCY 288000000
|
||||
|
||||
/* CPU frequency may be divided down from system frequency */
|
||||
/* CPU frequency, fCPU, may be divided down from system frequency */
|
||||
|
||||
#define BOARD_CPUDIV_ENABLE 1 /* Enable PLL dive by 2 for fCPU */
|
||||
#define BOARD_CPU_FREQUENCY 144000000
|
||||
|
||||
/* The peripheral clock, fPERIPH, derives from fCPU with no division */
|
||||
|
||||
#define BOARD_PBDIV 1 /* No division */
|
||||
#define BOARD_PERIPH_FREQUENCY 144000000
|
||||
|
||||
/* Standby clock source selection
|
||||
*
|
||||
* BOARD_STDBY_CLOCKSRC_OSI - Internal 32.768KHz slow oscillator
|
||||
@@ -112,7 +122,7 @@
|
||||
*/
|
||||
|
||||
#define BOARD_STDBY_CLOCKSRC_OSI 1
|
||||
#undef BOARD_STDBY_CLOCKSRC_OSCULP
|
||||
#undef BOARD_STDBY_CLOCKSRC_OSCULP
|
||||
#define BOARD_STDBY_FREQUENCY 32768
|
||||
|
||||
/* USB PLL settings.
|
||||
@@ -171,12 +181,9 @@
|
||||
#define LED_PANIC 3 /* The system has crashed N/C Blinking */
|
||||
#undef LED_IDLE /* MCU is is sleep mode Not used */
|
||||
|
||||
/* Thus if LED0 is statically on, NuttX has successfully booted and is,
|
||||
* apparently, running normally. If LED1 is flashing at approximately
|
||||
/* Thus if LED1 is statically on, NuttX has successfully booted and is,
|
||||
* apparently, running normally. If LED2 is flashing at approximately
|
||||
* 2Hz, then a fatal error has been detected and the system has halted.
|
||||
*
|
||||
* NOTE: That LED0 is not used after completion of booting and may
|
||||
* be used by other board-specific logic.
|
||||
*/
|
||||
|
||||
/* Button definitions ***************************************************************/
|
||||
|
||||
@@ -43,19 +43,19 @@
|
||||
* include/board.h and src/sam_autoleds.c. The LEDs are used to encode
|
||||
* OS-related events as follows:
|
||||
*
|
||||
* SYMBOL Meaning LED state
|
||||
* LED2 LED1
|
||||
* --------------------- -------------------------- ------ ------ */
|
||||
|
||||
#define LED_STARTED 0 /* NuttX has been started OFF OFF */
|
||||
#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF OFF */
|
||||
#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF */
|
||||
#define LED_STACKCREATED 1 /* Idle stack created ON OFF */
|
||||
#define LED_INIRQ 2 /* In an interrupt No change */
|
||||
#define LED_SIGNAL 2 /* In a signal handler No change */
|
||||
#define LED_ASSERTION 2 /* An assertion failed No change */
|
||||
#define LED_PANIC 3 /* The system has crashed N/C Blinking */
|
||||
#undef LED_IDLE /* MCU is is sleep mode Not used */
|
||||
* SYMBOL Meaning LED state
|
||||
* LED1 LED2
|
||||
* ------------------ ------------------------ ------ ------
|
||||
* LED_STARTED NuttX has been started OFF OFF
|
||||
* LED_HEAPALLOCATE Heap has been allocated OFF OFF
|
||||
* LED_IRQSENABLED Interrupts enabled OFF OFF
|
||||
* LED_STACKCREATED Idle stack created ON OFF
|
||||
* LED_INIRQ In an interrupt No change
|
||||
* LED_SIGNAL In a signal handler No change
|
||||
* LED_ASSERTION An assertion failed No change
|
||||
* LED_PANIC The system has crashed N/C Blinking
|
||||
* LED_IDLE MCU is is sleep mode Not used
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
|
||||
+35
-17
@@ -3,7 +3,7 @@
|
||||
*
|
||||
* Audio device driver for Wolfson Microelectronics WM8904 Audio codec.
|
||||
*
|
||||
* Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2014, 2016-2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* References:
|
||||
@@ -73,6 +73,14 @@
|
||||
|
||||
#include "wm8904.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Maximum number of retries */
|
||||
|
||||
#define MAX_RETRIES 3
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
@@ -251,7 +259,7 @@ uint16_t wm8904_readreg(FAR struct wm8904_dev_s *priv, uint8_t regaddr)
|
||||
|
||||
/* Try up to three times to read the register */
|
||||
|
||||
for (retries = 1; retries <= 3; retries++)
|
||||
for (retries = 1; retries <= MAX_RETRIES; retries++)
|
||||
{
|
||||
struct i2c_msg_s msg[2];
|
||||
uint8_t data[2];
|
||||
@@ -281,15 +289,20 @@ uint16_t wm8904_readreg(FAR struct wm8904_dev_s *priv, uint8_t regaddr)
|
||||
if (ret < 0)
|
||||
{
|
||||
#ifdef CONFIG_I2C_RESET
|
||||
/* Perhaps the I2C bus is locked up? Try to shake the bus free */
|
||||
/* Perhaps the I2C bus is locked up? Try to shake the bus free.
|
||||
* Don't bother with the reset if this was the last attempt.
|
||||
*/
|
||||
|
||||
audwarn("WARNING: I2C_TRANSFER failed: %d ... Resetting\n", ret);
|
||||
|
||||
ret = I2C_RESET(priv->i2c);
|
||||
if (ret < 0)
|
||||
if (retries < MAX_RETRIES)
|
||||
{
|
||||
auderr("ERROR: I2C_RESET failed: %d\n", ret);
|
||||
break;
|
||||
audwarn("WARNING: I2C_TRANSFER failed: %d ... Resetting\n", ret);
|
||||
|
||||
ret = I2C_RESET(priv->i2c);
|
||||
if (ret < 0)
|
||||
{
|
||||
auderr("ERROR: I2C_RESET failed: %d\n", ret);
|
||||
break;
|
||||
}
|
||||
}
|
||||
#else
|
||||
auderr("ERROR: I2C_TRANSFER failed: %d\n", ret);
|
||||
@@ -338,7 +351,7 @@ static void wm8904_writereg(FAR struct wm8904_dev_s *priv, uint8_t regaddr,
|
||||
|
||||
/* Try up to three times to read the register */
|
||||
|
||||
for (retries = 1; retries <= 3; retries++)
|
||||
for (retries = 1; retries <= MAX_RETRIES; retries++)
|
||||
{
|
||||
uint8_t data[3];
|
||||
int ret;
|
||||
@@ -357,15 +370,20 @@ static void wm8904_writereg(FAR struct wm8904_dev_s *priv, uint8_t regaddr,
|
||||
if (ret < 0)
|
||||
{
|
||||
#ifdef CONFIG_I2C_RESET
|
||||
/* Perhaps the I2C bus is locked up? Try to shake the bus free */
|
||||
/* Perhaps the I2C bus is locked up? Try to shake the bus free.
|
||||
* Don't bother with the reset if this was the last attempt.
|
||||
*/
|
||||
|
||||
audwarn("WARNING: i2c_write failed: %d ... Resetting\n", ret);
|
||||
|
||||
ret = I2C_RESET(priv->i2c);
|
||||
if (ret < 0)
|
||||
if (retries < MAX_RETRIES)
|
||||
{
|
||||
auderr("ERROR: I2C_RESET failed: %d\n", ret);
|
||||
break;
|
||||
audwarn("WARNING: i2c_write failed: %d ... Resetting\n", ret);
|
||||
|
||||
ret = I2C_RESET(priv->i2c);
|
||||
if (ret < 0)
|
||||
{
|
||||
auderr("ERROR: I2C_RESET failed: %d\n", ret);
|
||||
break;
|
||||
}
|
||||
}
|
||||
#else
|
||||
auderr("ERROR: I2C_TRANSFER failed: %d\n", ret);
|
||||
|
||||
+30
-16
@@ -1,7 +1,7 @@
|
||||
/****************************************************************************
|
||||
* drivers/input/mxt.c
|
||||
*
|
||||
* Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2014, 2016-2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -88,6 +88,10 @@
|
||||
|
||||
#define INVALID_POSITION 0x1000
|
||||
|
||||
/* Maximum number of retries */
|
||||
|
||||
#define MAX_RETRIES 3
|
||||
|
||||
/* Get a 16-bit value in little endian order (not necessarily aligned). The
|
||||
* source data is in little endian order. The host byte order does not
|
||||
* matter in this case.
|
||||
@@ -311,7 +315,7 @@ static int mxt_getreg(FAR struct mxt_dev_s *priv, uint16_t regaddr,
|
||||
|
||||
/* Try up to three times to read the register */
|
||||
|
||||
for (retries = 1; retries <= 3; retries++)
|
||||
for (retries = 1; retries <= MAX_RETRIES; retries++)
|
||||
{
|
||||
iinfo("retries=%d regaddr=%04x buflen=%d\n", retries, regaddr, buflen);
|
||||
|
||||
@@ -342,15 +346,20 @@ static int mxt_getreg(FAR struct mxt_dev_s *priv, uint16_t regaddr,
|
||||
if (ret < 0)
|
||||
{
|
||||
#ifdef CONFIG_I2C_RESET
|
||||
/* Perhaps the I2C bus is locked up? Try to shake the bus free */
|
||||
/* Perhaps the I2C bus is locked up? Try to shake the bus free.
|
||||
* Don't bother with the reset if this was the last attempt.
|
||||
*/
|
||||
|
||||
iwarn("WARNING: I2C_TRANSFER failed: %d ... Resetting\n", ret);
|
||||
|
||||
ret = I2C_RESET(priv->i2c);
|
||||
if (ret < 0)
|
||||
if (retries < MAX_RETRIES)
|
||||
{
|
||||
ierr("ERROR: I2C_RESET failed: %d\n", ret);
|
||||
break;
|
||||
iwarn("WARNING: I2C_TRANSFER failed: %d ... Resetting\n", ret);
|
||||
|
||||
ret = I2C_RESET(priv->i2c);
|
||||
if (ret < 0)
|
||||
{
|
||||
ierr("ERROR: I2C_RESET failed: %d\n", ret);
|
||||
break;
|
||||
}
|
||||
}
|
||||
#else
|
||||
ierr("ERROR: I2C_TRANSFER failed: %d\n", ret);
|
||||
@@ -385,7 +394,7 @@ static int mxt_putreg(FAR struct mxt_dev_s *priv, uint16_t regaddr,
|
||||
|
||||
/* Try up to three times to read the register */
|
||||
|
||||
for (retries = 1; retries <= 3; retries++)
|
||||
for (retries = 1; retries <= MAX_RETRIES; retries++)
|
||||
{
|
||||
iinfo("retries=%d regaddr=%04x buflen=%d\n", retries, regaddr, buflen);
|
||||
|
||||
@@ -416,14 +425,19 @@ static int mxt_putreg(FAR struct mxt_dev_s *priv, uint16_t regaddr,
|
||||
if (ret < 0)
|
||||
{
|
||||
#ifdef CONFIG_I2C_RESET
|
||||
/* Perhaps the I2C bus is locked up? Try to shake the bus free */
|
||||
/* Perhaps the I2C bus is locked up? Try to shake the bus free.
|
||||
* Don't bother with the reset if this was the last attempt.
|
||||
*/
|
||||
|
||||
iwarn("WARNING: I2C_TRANSFER failed: %d ... Resetting\n", ret);
|
||||
|
||||
ret = I2C_RESET(priv->i2c);
|
||||
if (ret < 0)
|
||||
if (retries < MAX_RETRIES)
|
||||
{
|
||||
ierr("ERROR: I2C_RESET failed: %d\n", ret);
|
||||
iwarn("WARNING: I2C_TRANSFER failed: %d ... Resetting\n", ret);
|
||||
|
||||
ret = I2C_RESET(priv->i2c);
|
||||
if (ret < 0)
|
||||
{
|
||||
ierr("ERROR: I2C_RESET failed: %d\n", ret);
|
||||
}
|
||||
}
|
||||
#else
|
||||
ierr("ERROR: I2C_TRANSFER failed: %d\n", ret);
|
||||
|
||||
@@ -48,6 +48,7 @@ config LCD_NOGETRUN
|
||||
|
||||
config LCD_MAXCONTRAST
|
||||
int "LCD maximum contrast"
|
||||
default 31 if AQM_1248A
|
||||
default 63 if NOKIA6100_S1D15G10 || LCD_SHARP_MEMLCD
|
||||
default 127 if NOKIA6100_PCF8833
|
||||
default 255 if LCD_P14201 || LCD_LCD1602
|
||||
@@ -596,6 +597,9 @@ config NHD_C12864KGZ
|
||||
config ERC_12864_3
|
||||
bool "like ERC12864-3"
|
||||
|
||||
config AQM_1248A
|
||||
bool "like AQM1248A"
|
||||
|
||||
endchoice
|
||||
|
||||
config ST7565_NINTERFACES
|
||||
@@ -613,6 +617,7 @@ config ST7565_XRES
|
||||
|
||||
config ST7565_YRES
|
||||
int "ST7565 Y Resolution"
|
||||
default 48 if AQM_1248A
|
||||
default 64
|
||||
---help---
|
||||
Specifies the Y resolution of the LCD.
|
||||
@@ -625,6 +630,7 @@ config ST7565_MIRROR_X
|
||||
|
||||
config ST7565_MIRROR_Y
|
||||
bool "ST7565 apply mirror on Y"
|
||||
default y if AQM_1248A
|
||||
default n
|
||||
---help---
|
||||
Mirror Y on LCD.
|
||||
|
||||
@@ -1030,6 +1030,27 @@ FAR struct lcd_dev_s *st7565_initialize(FAR struct st7565_lcd_s *lcd,
|
||||
(void)st7565_send_one_data(priv, ST7565_SETEVREG(0x24));
|
||||
(void)st7565_send_one_data(priv, ST7565_SETSTARTLINE);
|
||||
|
||||
#elif defined(CONFIG_AQM_1248A)
|
||||
|
||||
(void)st7565_send_one_data(priv, ST7565_DISPOFF);
|
||||
(void)st7565_send_one_data(priv, ST7565_ADCNORMAL);
|
||||
(void)st7565_send_one_data(priv, ST7565_SETCOMREVERSE);
|
||||
(void)st7565_send_one_data(priv, ST7565_BIAS_1_7);
|
||||
|
||||
(void)st7565_send_one_data(priv, ST7565_POWERCTRL_B);
|
||||
up_mdelay(2);
|
||||
(void)st7565_send_one_data(priv, ST7565_POWERCTRL_BR);
|
||||
up_mdelay(2);
|
||||
(void)st7565_send_one_data(priv, ST7565_POWERCTRL_INT);
|
||||
|
||||
(void)st7565_send_one_data(priv, ST7565_REG_RES_4_5);
|
||||
(void)st7565_send_one_data(priv, ST7565_SETEVMODE);
|
||||
(void)st7565_send_one_data(priv, ST7565_SETEVREG(0x1c));
|
||||
(void)st7565_send_one_data(priv, ST7565_DISPRAM);
|
||||
(void)st7565_send_one_data(priv, ST7565_SETSTARTLINE);
|
||||
(void)st7565_send_one_data(priv, ST7565_DISPNORMAL);
|
||||
(void)st7565_send_one_data(priv, ST7565_DISPON);
|
||||
|
||||
#else
|
||||
# error "No initialization sequence selected"
|
||||
#endif
|
||||
|
||||
@@ -100,6 +100,8 @@
|
||||
#define ST7565_POWERCTRL_VR 0x2b /* 0x2b: Only the voltage regulator circuit and the
|
||||
* voltage follower circuit are used
|
||||
*/
|
||||
#define ST7565_POWERCTRL_B 0x2c /* 0x2c: Booster=ON */
|
||||
#define ST7565_POWERCTRL_BR 0x2e /* 0x2e: Booster=ON V/R=ON */
|
||||
#define ST7565_POWERCTRL_INT 0x2f /* 0x2f: Only the internal power supply is used */
|
||||
|
||||
/* Regulation Resistior ratio V0 = (1+Rb/Ra)*Vev */
|
||||
|
||||
@@ -78,7 +78,7 @@ ssize_t psock_udp_send(FAR struct socket *psock, FAR const void *buf,
|
||||
socklen_t tolen;
|
||||
|
||||
DEBUGASSERT(psock != NULL && psock->s_crefs > 0);
|
||||
DEBUGASSERT(psock->s_type != SOCK_DGRAM);
|
||||
DEBUGASSERT(psock->s_type == SOCK_DGRAM);
|
||||
|
||||
conn = (FAR struct udp_conn_s *)psock->s_conn;
|
||||
DEBUGASSERT(conn);
|
||||
|
||||
@@ -156,7 +156,7 @@ static FAR struct semholder_s *sem_findholder(sem_t *sem,
|
||||
int i;
|
||||
pholder = NULL;
|
||||
|
||||
/* We have two hard-allocated holder structuse in sem_t */
|
||||
/* We have two hard-allocated holder structures in sem_t */
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
{
|
||||
@@ -338,7 +338,7 @@ static int sem_boostholderprio(FAR struct semholder_s *pholder,
|
||||
if (!sched_verifytcb(htcb))
|
||||
{
|
||||
serr("ERROR: TCB 0x%08x is a stale handle, counts lost\n", htcb);
|
||||
DEBUGASSERT(!sched_verifytcb(htcb));
|
||||
DEBUGPANIC();
|
||||
sem_freeholder(sem, pholder);
|
||||
}
|
||||
|
||||
@@ -498,7 +498,7 @@ static int sem_restoreholderprio(FAR struct tcb_s *htcb,
|
||||
if (!sched_verifytcb(htcb))
|
||||
{
|
||||
serr("ERROR: TCB 0x%08x is a stale handle, counts lost\n", htcb);
|
||||
DEBUGASSERT(!sched_verifytcb(htcb));
|
||||
DEBUGPANIC();
|
||||
pholder = sem_findholder(sem, htcb);
|
||||
if (pholder != NULL)
|
||||
{
|
||||
@@ -787,7 +787,6 @@ static inline void sem_restorebaseprio_task(FAR struct tcb_s *stcb,
|
||||
FAR sem_t *sem)
|
||||
{
|
||||
FAR struct tcb_s *rtcb = this_task();
|
||||
FAR struct semholder_s *pholder;
|
||||
|
||||
/* Perform the following actions only if a new thread was given a count.
|
||||
* The thread that received the count should be the highest priority
|
||||
@@ -831,7 +830,6 @@ static inline void sem_restorebaseprio_task(FAR struct tcb_s *stcb,
|
||||
*/
|
||||
|
||||
sem_findandfreeholder(sem, rtcb);
|
||||
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -905,14 +903,15 @@ void sem_destroyholder(FAR sem_t *sem)
|
||||
if (sem->hhead != NULL)
|
||||
{
|
||||
serr("ERROR: Semaphore destroyed with holders\n");
|
||||
DEBUGASSERT(sem->hhead != NULL);
|
||||
DEBUGPANIC();
|
||||
(void)sem_foreachholder(sem, sem_recoverholders, NULL);
|
||||
}
|
||||
|
||||
#else
|
||||
if (sem->holder[0].htcb != NULL || sem->holder[0].htcb != NULL)
|
||||
if (sem->holder[0].htcb != NULL || sem->holder[1].htcb != NULL)
|
||||
{
|
||||
DEBUGASSERT(sem->holder[0].htcb != NULL || sem->holder[0].htcb != NULL);
|
||||
serr("ERROR: Semaphore destroyed with holder\n");
|
||||
DEBUGPANIC();
|
||||
}
|
||||
|
||||
sem->holder[0].htcb = NULL;
|
||||
|
||||
Reference in New Issue
Block a user