mirror of
https://github.com/apache/nuttx.git
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arch/arm64/src/imx9: Add a more capable uart driver
Add an uart driver supporting LPUART1-8, dma, flow control, tc etc. Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This commit is contained in:
Jukka Laitinen
committed by
Xiang Xiao
Xiang Xiao
parent
f4bbe276e1
commit
58f0ee6364
@@ -28,10 +28,89 @@ config IMX9_FLEXIO_PWM
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default n
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menu "i.MX9 Peripheral Selection"
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config IMX9_UART1
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bool "UART1"
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menu "LPUART"
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config IMX9_LPUART
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bool
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default n
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select UART1_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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config IMX9_LPUART1
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bool "LPUART1"
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default n
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select IMX9_LPUART
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select LPUART1_SERIALDRIVER
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config IMX9_LPUART2
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bool "LPUART2"
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default n
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select IMX9_LPUART
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select LPUART2_SERIALDRIVER
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config IMX9_LPUART3
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bool "LPUART3"
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default n
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select IMX9_LPUART
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select LPUART3_SERIALDRIVER
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config IMX9_LPUART4
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bool "LPUART4"
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default n
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select IMX9_LPUART
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select LPUART4_SERIALDRIVER
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config IMX9_LPUART5
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bool "LPUART5"
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default n
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select IMX9_LPUART
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select LPUART5_SERIALDRIVER
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config IMX9_LPUART6
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bool "LPUART6"
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default n
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select IMX9_LPUART
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select LPUART6_SERIALDRIVER
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config IMX9_LPUART7
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bool "LPUART7"
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default n
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select IMX9_LPUART
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select LPUART7_SERIALDRIVER
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config IMX9_LPUART8
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bool "LPUART8"
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default n
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select IMX9_LPUART
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select LPUART8_SERIALDRIVER
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menu "LPUART Configuration"
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depends on IMX9_LPUART
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config IMX9_LPUART_INVERT
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bool "Signal Invert Support"
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default n
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config IMX9_LPUART_SINGLEWIRE
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bool "Signal Wire Support"
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default n
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config IMX9_SERIAL_RXDMA_BUFFER_SIZE
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int "RX DMA buffer size"
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default 64
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depends on LPUART1_RXDMA || LPUART2_RXDMA || LPUART3_RXDMA || LPUART4_RXDMA || \
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LPUART5_RXDMA || LPUART6_RXDMA || LPUART7_RXDMA || LPUART8_RXDMA
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---help---
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The DMA buffer size when using RX DMA to emulate a FIFO.
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When streaming data, the generic serial layer will be called
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every time the FIFO receives half this number of bytes.
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Value given here will be rounded up to next multiple of 64 bytes.
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endmenu # LPUART Configuration
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endmenu # LPUART
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config IMX9_FLEXIO1_PWM
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depends on PWM
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@@ -25,10 +25,7 @@ include common/Make.defs
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CHIP_CSRCS = imx9_boot.c imx9_ccm.c imx9_clockconfig.c imx9_gpio.c imx9_iomuxc.c
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ifeq ($(CONFIG_ARCH_CHIP_IMX93),y)
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CHIP_CSRCS += imx9_lpuart.c
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ifeq ($(CONFIG_ARCH_EARLY_PRINT),y)
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CHIP_ASRCS = imx93_lowputc.S
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endif
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CHIP_CSRCS += imx9_lpuart.c imx9_lowputc.c
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endif
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ifeq ($(CONFIG_IMX9_GPIO_IRQ),y)
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@@ -25,134 +25,289 @@
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <hardware/imx9_memorymap.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* 32-bit register definition */
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/* LPUART Register Offsets **************************************************/
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#define UARTVERID 0x0000 /* Version ID Register */
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#define UARTPARAM 0x0004 /* Parameter Register */
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#define UARTGLOBAL 0x0008 /* LPUART Global Register */
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#define UARTPINCFG 0x000c /* LPUART Pin Configuration Register */
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#define UARTBAUD 0x0010 /* LPUART Baud Rate Register */
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#define UARTSTAT 0x0014 /* LPUART Status Register */
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#define UARTCTRL 0x0018 /* LPUART Control Register */
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#define UARTDATA 0x001c /* LPUART Data Register */
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#define UARTMATCH 0x0020 /* LPUART Match Address Register */
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#define UARTMODIR 0x0024 /* LPUART Modem IrDA Register */
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#define UARTFIFO 0x0028 /* LPUART FIFO Register */
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#define UARTWATER 0x002c /* LPUART Watermark Register */
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#define IMX9_LPUART_VERID_OFFSET (0x00) /* Version ID Register (VERID) */
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#define IMX9_LPUART_PARAM_OFFSET (0x04) /* Parameter Register (PARAM) */
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#define IMX9_LPUART_GLOBAL_OFFSET (0x08) /* LPUART Global Register (GLOBAL) */
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#define IMX9_LPUART_PINCFG_OFFSET (0x0c) /* LPUART Pin Configuration Register (PINCFG) */
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#define IMX9_LPUART_BAUD_OFFSET (0x10) /* LPUART Baud Rate Register (BAUD) */
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#define IMX9_LPUART_STAT_OFFSET (0x14) /* LPUART Status Register (STAT) */
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#define IMX9_LPUART_CTRL_OFFSET (0x18) /* LPUART Control Register (CTRL) */
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#define IMX9_LPUART_DATA_OFFSET (0x1c) /* LPUART Data Register (DATA) */
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#define IMX9_LPUART_MATCH_OFFSET (0x20) /* LPUART Match Address Register (MATCH) */
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#define IMX9_LPUART_MODIR_OFFSET (0x24) /* LPUART Modem IrDA Register (MODIR) */
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#define IMX9_LPUART_FIFO_OFFSET (0x28) /* LPUART FIFO Register (FIFO) */
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#define IMX9_LPUART_WATER_OFFSET (0x2c) /* LPUART Watermark Register (WATER) */
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#define IMX9_LPUART_DATARO_OFFSET (0x30) /* Data read-only Register (DATARO) */
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#define UARTBAUD_MAEN1 0x80000000
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#define UARTBAUD_MAEN2 0x40000000
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#define UARTBAUD_M10 0x20000000
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#define UARTBAUD_TDMAE 0x00800000
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#define UARTBAUD_RDMAE 0x00200000
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#define UARTBAUD_RIDMAE 0x00100000
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#define UARTBAUD_MATCFG 0x00400000
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#define UARTBAUD_BOTHEDGE 0x00020000
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#define UARTBAUD_RESYNCDIS 0x00010000
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#define UARTBAUD_LBKDIE 0x00008000
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#define UARTBAUD_RXEDGIE 0x00004000
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#define UARTBAUD_SBNS 0x00002000
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#define UARTBAUD_SBR 0x00000000
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#define UARTBAUD_SBR_MASK 0x1fff
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#define UARTBAUD_OSR_MASK 0x1f
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#define UARTBAUD_OSR_SHIFT 24
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/* Register bit definitions *************************************************/
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#define UARTSTAT_LBKDIF 0x80000000
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#define UARTSTAT_RXEDGIF 0x40000000
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#define UARTSTAT_MSBF 0x20000000
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#define UARTSTAT_RXINV 0x10000000
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#define UARTSTAT_RWUID 0x08000000
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#define UARTSTAT_BRK13 0x04000000
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#define UARTSTAT_LBKDE 0x02000000
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#define UARTSTAT_RAF 0x01000000
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#define UARTSTAT_TDRE 0x00800000
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#define UARTSTAT_TC 0x00400000
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#define UARTSTAT_RDRF 0x00200000
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#define UARTSTAT_IDLE 0x00100000
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#define UARTSTAT_OR 0x00080000
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#define UARTSTAT_NF 0x00040000
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#define UARTSTAT_FE 0x00020000
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#define UARTSTAT_PE 0x00010000
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#define UARTSTAT_MA1F 0x00008000
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#define UARTSTAT_M21F 0x00004000
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/* Version ID Register (VERID) */
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#define UARTCTRL_R8T9 0x80000000
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#define UARTCTRL_R9T8 0x40000000
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#define UARTCTRL_TXDIR 0x20000000
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#define UARTCTRL_TXINV 0x10000000
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#define UARTCTRL_ORIE 0x08000000
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#define UARTCTRL_NEIE 0x04000000
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#define UARTCTRL_FEIE 0x02000000
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#define UARTCTRL_PEIE 0x01000000
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#define UARTCTRL_TIE 0x00800000
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#define UARTCTRL_TCIE 0x00400000
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#define UARTCTRL_RIE 0x00200000
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#define UARTCTRL_ILIE 0x00100000
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#define UARTCTRL_TE 0x00080000
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#define UARTCTRL_RE 0x00040000
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#define UARTCTRL_RWU 0x00020000
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#define UARTCTRL_SBK 0x00010000
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#define UARTCTRL_MA1IE 0x00008000
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#define UARTCTRL_MA2IE 0x00004000
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#define UARTCTRL_IDLECFG_OFF 0x8
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#define UARTCTRL_LOOPS 0x00000080
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#define UARTCTRL_DOZEEN 0x00000040
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#define UARTCTRL_RSRC 0x00000020
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#define UARTCTRL_M 0x00000010
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#define UARTCTRL_WAKE 0x00000008
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#define UARTCTRL_ILT 0x00000004
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#define UARTCTRL_PE 0x00000002
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#define UARTCTRL_PT 0x00000001
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#define LPUART_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Feature Identification Number (FEATURE) */
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#define LPUART_VERID_FEATURE_MASK (0xffff << LPUART_VERID_FEATURE_SHIFT)
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# define LPUART_VERID_FEATURE_STD (1 << LPUART_VERID_FEATURE_SHIFT) /* Standard feature set */
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# define LPUART_VERID_FEATURE_MODEM (3 << LPUART_VERID_FEATURE_SHIFT) /* MODEM/IrDA support */
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#define UARTDATA_NOISY 0x00008000
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#define UARTDATA_PARITYE 0x00004000
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#define UARTDATA_FRETSC 0x00002000
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#define UARTDATA_RXEMPT 0x00001000
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#define UARTDATA_IDLINE 0x00000800
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#define UARTDATA_MASK 0x3ff
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#define LPUART_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number (MINOR) */
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#define LPUART_VERID_MINOR_MASK (0xff << LPUART_VERID_MINOR_SHIFT)
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#define LPUART_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number (MAJOR) */
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#define LPUART_VERID_MAJOR_MASK (0xff << LPUART_VERID_MAJOR_SHIFT)
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#define UARTMODIR_IREN 0x00020000
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#define UARTMODIR_RTSWATER_S 0x8
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#define UARTMODIR_TXCTSSRC 0x00000020
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#define UARTMODIR_TXCTSC 0x00000010
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#define UARTMODIR_RXRTSE 0x00000008
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#define UARTMODIR_TXRTSPOL 0x00000004
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#define UARTMODIR_TXRTSE 0x00000002
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#define UARTMODIR_TXCTSE 0x00000001
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/* Parameter Register (PARAM) */
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#define UARTFIFO_TXEMPT 0x00800000
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#define UARTFIFO_RXEMPT 0x00400000
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#define UARTFIFO_TXOF 0x00020000
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#define UARTFIFO_RXUF 0x00010000
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#define UARTFIFO_TXFLUSH 0x00008000
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#define UARTFIFO_RXFLUSH 0x00004000
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#define UARTFIFO_RXIDEN_MASK 0x7
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#define UARTFIFO_RXIDEN_OFF 10
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#define UARTFIFO_TXOFE 0x00000200
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#define UARTFIFO_RXUFE 0x00000100
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#define UARTFIFO_TXFE 0x00000080
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#define UARTFIFO_FIFOSIZE_MASK 0x7
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#define UARTFIFO_TXSIZE_OFF 4
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#define UARTFIFO_RXFE 0x00000008
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#define UARTFIFO_RXSIZE_OFF 0
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#define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0))
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#define LPUART_PARAM_TXFIFO_SHIFT (0) /* Bits 0-7: Transmit FIFO Size (TXFIFO) */
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#define LPUART_PARAM_TXFIFO_MASK (0xff << LPUART_PARAM_TXFIFO_SHIFT)
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#define LPUART_PARAM_RXFIFO_SHIFT (8) /* Bits 8-15: Receive FIFO Size (RXFIFO) */
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#define LPUART_PARAM_RXFIFO_MASK (0xff << LPUART_PARAM_RXFIFO_SHIFT)
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/* Bits 16-31: Reserved */
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#define UARTWATER_COUNT_MASK 0xff
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#define UARTWATER_TXCNT_OFF 8
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#define UARTWATER_RXCNT_OFF 24
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#define UARTWATER_WATER_MASK 0xff
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#define UARTWATER_TXWATER_OFF 0
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#define UARTWATER_RXWATER_OFF 16
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/* LPUART Global Register (GLOBAL) */
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#define UARTGLOBAL_RST 0x2
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/* Bit 0: Reserved */
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#define LPUART_GLOBAL_RST (1 << 1) /* Bit 1: Software Reset (RST) */
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/* Bits 2-31: Reserved */
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#define UARTFIFO_RXIDEN_RDRF 0x3
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#define UARTCTRL_IDLECFG 0x7
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/* LPUART Pin Configuration Register (PINCFG) */
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#define LPUART_PINCFG_TRGSEL_SHIFT (0) /* Bits 0-1: Trigger Select (TRGSEL) */
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#define LPUART_PINCFG_TRGSEL_MASK (0x03 << LPUART_PINCFG_TRGSEL_SHIFT)
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# define LPUART_PINCFG_TRGSEL_DISABLE (0 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger disabled */
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# define LPUART_PINCFG_TRGSEL_RXD (1 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of RXD pin */
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# define LPUART_PINCFG_TRGSEL_CTSB (2 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of CTS_B pin */
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# define LPUART_PINCFG_TRGSEL_TXDMOD (3 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used to modulate the TXD output */
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/* Bits 2-31: Reserved */
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/* LPUART Baud Rate Register (BAUD) */
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#define LPUART_BAUD_SBR_SHIFT (0) /* Bits 0-12: Baud Rate Modulo Divisor (SBR) */
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#define LPUART_BAUD_SBR_MASK (0x1fff << LPUART_BAUD_SBR_SHIFT)
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# define LPUART_BAUD_SBR(n) ((n) << LPUART_BAUD_SBR_SHIFT)
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#define LPUART_BAUD_SBNS (1 << 13) /* Bit 13: Stop Bit Number Select (SBNS) */
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#define LPUART_BAUD_RXEDGIE (1 << 14) /* Bit 14: RX Input Active Edge Interrupt Enable (RXEDGIE) */
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#define LPUART_BAUD_LBKDIE (1 << 15) /* Bit 15: LIN Break Detect Interrupt Enable (LBKDIE) */
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#define LPUART_BAUD_RESYNCDIS (1 << 16) /* Bit 16: Resynchronization Disable (RESYNCDIS) */
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#define LPUART_BAUD_BOTHEDGE (1 << 17) /* Bit 17: Both Edge Sampling (BOTHEDGE) */
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#define LPUART_BAUD_MATCFG_SHIFT (18) /* Bits 18-19: Match Configuration (MATCFG) */
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#define LPUART_BAUD_MATCFG_MASK (0x03 << LPUART_BAUD_MATCFG_SHIFT)
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# define LPUART_BAUD_MATCFG_ADDR (0 << LPUART_BAUD_MATCFG_SHIFT) /* Address Match Wakeup */
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# define LPUART_BAUD_MATCFG_IDLE (1 << LPUART_BAUD_MATCFG_SHIFT) /* Idle Match Wakeup */
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# define LPUART_BAUD_MATCFG_ONOFF (2 << LPUART_BAUD_MATCFG_SHIFT) /* Match On and Match Off */
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# define LPUART_BAUD_MATCFG_RWUENAB (3 << LPUART_BAUD_MATCFG_SHIFT) /* Enables RWU on Data Match and Match On/Off for transmitter CTS input */
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/* Bit 20: Reserved */
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#define LPUART_BAUD_RDMAE (1 << 21) /* Bit 21: Receiver Full DMA Enable (RDMAE) */
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/* Bit 22: Reserved */
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#define LPUART_BAUD_TDMAE (1 << 23) /* Bit 23: Transmitter DMA Enable (TDMAE) */
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#define LPUART_BAUD_OSR_SHIFT (24) /* Bits 24-29: Oversampling Ratio (OSR) */
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#define LPUART_BAUD_OSR_MASK (0x1f << LPUART_BAUD_OSR_SHIFT)
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# define LPUART_BAUD_OSR(n) (((n) - 1) << LPUART_BAUD_OSR_SHIFT) /* n=4..32 */
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#define LPUART_BAUD_M10 (1 << 29) /* Bit 29: 10-bit Mode Select (M10) */
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#define LPUART_BAUD_MAEN2 (1 << 30) /* Bit 30: Match Address Mode Enable 2 (MAEN2) */
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#define LPUART_BAUD_MAEN1 (1 << 31) /* Bit 31: Match Address Mode Enable 1 (MAEN1) */
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/* LPUART Status Register (STAT) */
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#define LPUART_STAT_LBKFE (1 << 0) /* Bit 0: LIN Break Flag Enable (LBKFE) */
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#define LPUART_STAT_AME (1 << 1) /* Bit 1: Address Mark Enable (AME) */
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/* Bits 2-13: Reserved */
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#define LPUART_STAT_MA2F (1 << 14) /* Bit 14: Match 2 Flag (MA2F) */
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#define LPUART_STAT_MA1F (1 << 15) /* Bit 15: Match 1 Flag (MA1F) */
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#define LPUART_STAT_PF (1 << 16) /* Bit 16: Parity Error Flag (PF) */
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#define LPUART_STAT_FE (1 << 17) /* Bit 17: Framing Error Flag (FE) */
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#define LPUART_STAT_NF (1 << 18) /* Bit 18: Noise Flag (NF) */
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#define LPUART_STAT_OR (1 << 19) /* Bit 19: Receiver Overrun Flag (OR) */
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#define LPUART_STAT_IDLE (1 << 20) /* Bit 20: Idle Line Flag (IDLE) */
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#define LPUART_STAT_RDRF (1 << 21) /* Bit 21: Receive Data Register Full Flag (RDRF) */
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#define LPUART_STAT_TC (1 << 22) /* Bit 22: Transmission Complete Flag (TC) */
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#define LPUART_STAT_TDRE (1 << 23) /* Bit 23: Transmit Data Register Empty Flag (TDRE) */
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#define LPUART_STAT_RAF (1 << 24) /* Bit 24: Receiver Active Flag (RAF) */
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#define LPUART_STAT_LBKDE (1 << 25) /* Bit 25: LIN Break Detection Enable (LBKDE) */
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#define LPUART_STAT_BRK13 (1 << 26) /* Bit 26: Break Character Generation Length (BRK13) */
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#define LPUART_STAT_RWUID (1 << 27) /* Bit 27: Receive Wake Up Idle Detect (RWUID) */
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#define LPUART_STAT_RXINV (1 << 28) /* Bit 28: Receive Data Inversion (RXINV) */
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#define LPUART_STAT_MSBF (1 << 29) /* Bit 29: MSB First (MSBF) */
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#define LPUART_STAT_RXEDGIF (1 << 30) /* Bit 30: RXD Pin Active Edge Interrupt Flag (RXEDGIF) */
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#define LPUART_STAT_LBKDIF (1 << 31) /* Bit 31: LIN Break Detect Interrupt Flag (LBKDIF) */
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/* LPUART Control Register (CTRL) */
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#define LPUART_CTRL_PT (1 << 0) /* Bit 0: Parity Type */
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# define LPUART_CTRL_PT_EVEN (0 << 0) /* Even parity */
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# define LPUART_CTRL_PT_ODD (1 << 0) /* Odd parity */
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#define LPUART_CTRL_PE (1 << 1) /* Bit 1: Parity Enable */
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#define LPUART_CTRL_ILT (1 << 2) /* Bit 2: Idle Line Type Select */
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#define LPUART_CTRL_WAKE (1 << 3) /* Bit 3: Receiver Wakeup Method Select */
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#define LPUART_CTRL_M (1 << 4) /* Bit 4: 9-Bit or 8-Bit Mode Select */
|
||||
#define LPUART_CTRL_RSRC (1 << 5) /* Bit 5: Receiver Source Select */
|
||||
#define LPUART_CTRL_DOZEEN (1 << 6) /* Bit 6: Doze Enable */
|
||||
#define LPUART_CTRL_LOOPS (1 << 7) /* Bit 7: Loop Mode Select */
|
||||
#define LPUART_CTRL_IDLECFG_SHIFT (8) /* Bits 8-10: Idle Configuration */
|
||||
#define LPUART_CTRL_IDLECFG_MASK (0x07 << LPUART_CTRL_IDLECFG_SHIFT)
|
||||
# define LPUART_CTRL_IDLECFG_1 (0 << LPUART_CTRL_IDLECFG_SHIFT) /* 1 idle character */
|
||||
# define LPUART_CTRL_IDLECFG_2 (1 << LPUART_CTRL_IDLECFG_SHIFT) /* 2 idle characters */
|
||||
# define LPUART_CTRL_IDLECFG_4 (2 << LPUART_CTRL_IDLECFG_SHIFT) /* 4 idle characters */
|
||||
# define LPUART_CTRL_IDLECFG_8 (3 << LPUART_CTRL_IDLECFG_SHIFT) /* 8 idle characters */
|
||||
# define LPUART_CTRL_IDLECFG_16 (4 << LPUART_CTRL_IDLECFG_SHIFT) /* 6 idle characters */
|
||||
# define LPUART_CTRL_IDLECFG_32 (5 << LPUART_CTRL_IDLECFG_SHIFT) /* 32 idle characters */
|
||||
# define LPUART_CTRL_IDLECFG_64 (6 << LPUART_CTRL_IDLECFG_SHIFT) /* 64 idle characters */
|
||||
# define LPUART_CTRL_IDLECFG_128 (7 << LPUART_CTRL_IDLECFG_SHIFT) /* 128 idle characters */
|
||||
|
||||
#define LPUART_CTRL_M7 (1 << 11) /* Bit 11: 7-Bit Mode Select (M7) */
|
||||
/* Bits 12-13: Reserved */
|
||||
#define LPUART_CTRL_MA2IE (1 << 14) /* Bit 14: Match 2 Interrupt Enable (MA2IE) */
|
||||
#define LPUART_CTRL_MA1IE (1 << 15) /* Bit 15: Match 1 Interrupt Enable (MA1IE) */
|
||||
#define LPUART_CTRL_SBK (1 << 16) /* Bit 16: Send Break (SBK) */
|
||||
#define LPUART_CTRL_RWU (1 << 17) /* Bit 17: Receiver Wakeup Control (RWU) */
|
||||
#define LPUART_CTRL_RE (1 << 18) /* Bit 18: Receiver Enable (RE) */
|
||||
#define LPUART_CTRL_TE (1 << 19) /* Bit 19: Transmitter Enable (TE) */
|
||||
#define LPUART_CTRL_ILIE (1 << 20) /* Bit 20: Idle Line Interrupt Enable (ILIE) */
|
||||
#define LPUART_CTRL_RIE (1 << 21) /* Bit 21: Receiver Interrupt Enable (RIE) */
|
||||
#define LPUART_CTRL_TCIE (1 << 22) /* Bit 22: Transmission Complete Interrupt Enable (TCIE) */
|
||||
#define LPUART_CTRL_TIE (1 << 23) /* Bit 23: Transmit Interrupt Enable (TIE) */
|
||||
#define LPUART_CTRL_PEIE (1 << 24) /* Bit 24: Parity Error Interrupt Enable (PEIE) */
|
||||
#define LPUART_CTRL_FEIE (1 << 25) /* Bit 25: Framing Error Interrupt Enable (FEIE) */
|
||||
#define LPUART_CTRL_NEIE (1 << 26) /* Bit 26: Noise Error Interrupt Enable (NEIE) */
|
||||
#define LPUART_CTRL_ORIE (1 << 27) /* Bit 27: Overrun Interrupt Enable (ORIE) */
|
||||
#define LPUART_CTRL_TXINV (1 << 28) /* Bit 28: Transmit Data Inversion (TXINV) */
|
||||
#define LPUART_CTRL_TXDIR (1 << 29) /* Bit 29: TXD Pin Direction in Single-Wire Mode (TXDIR) */
|
||||
#define LPUART_CTRL_R9T8 (1 << 30) /* Bit 30: Receive Bit 9 / Transmit Bit 8 (R9T8) */
|
||||
#define LPUART_CTRL_R8T9 (1 << 31) /* Bit 31: Receive Bit 8 / Transmit Bit 9 (R8T9) */
|
||||
|
||||
#define LPUART_ALL_INTS (LPUART_CTRL_ORIE | LPUART_CTRL_NEIE | LPUART_CTRL_FEIE | \
|
||||
LPUART_CTRL_PEIE | LPUART_CTRL_TIE | LPUART_CTRL_TCIE | \
|
||||
LPUART_CTRL_RIE | LPUART_CTRL_ILIE | LPUART_CTRL_MA1IE | \
|
||||
LPUART_CTRL_MA2IE)
|
||||
|
||||
/* LPUART Data Register (DATA) */
|
||||
|
||||
#define LPUART_DATA_SHIFT (0) /* Bits 0-9: Data bits 0-9 (DATA)*/
|
||||
#define LPUART_DATA_MASK (0x03ff << LPUART_DATA_SHIFT)
|
||||
#define LPUART_DATA_LINBRK (1 << 10) /* Bit 10: LIN Break (LINBRK) */
|
||||
#define LPUART_DATA_STATUS_SHIFT (11) /* Bits 11-15: Status */
|
||||
#define LPUART_DATA_IDLINE (1 << 11) /* Bit 11: Idle Line (IDLINE) */
|
||||
#define LPUART_DATA_RXEMPT (1 << 12) /* Bit 12: Receive Buffer Empty (RXEMPT) */
|
||||
#define LPUART_DATA_FRETSC (1 << 13) /* Bit 13: Frame Error / Transmit Special Character (FRETSC) */
|
||||
#define LPUART_DATA_PARITYE (1 << 14) /* Bit 14: Parity Error (PARITYE) */
|
||||
#define LPUART_DATA_NOISY (1 << 15) /* Bit 15: Noisy Data Received (NOISY) */
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/* LPUART Match Address Register (MATCH) */
|
||||
|
||||
#define LPUART_MATCH_MA1_SHIFT (0) /* Bits 0-9: Match Address 1 (MA1) */
|
||||
#define LPUART_MATCH_MA1_MASK (0x03ff << LPUART_MATCH_MA1_SHIFT)
|
||||
# define LPUART_MATCH_MA1(n) ((n) << LPUART_MATCH_MA1_SHIFT)
|
||||
/* Bits 10-15: Reserved */
|
||||
#define LPUART_MATCH_MA2_SHIFT (16) /* Bits 16-25: Match Address 2 (MA2) */
|
||||
#define LPUART_MATCH_MA2_MASK (0x03ff << LPUART_MATCH_MA2_SHIFT)
|
||||
# define LPUART_MATCH_MA2(n) ((n) << LPUART_MATCH_MA2_SHIFT)
|
||||
/* Bits 26-31: Reserved */
|
||||
|
||||
/* LPUART Modem IrDA Register (MODIR) */
|
||||
|
||||
#define LPUART_MODIR_TXCTSE (1 << 0) /* Bit 0: Transmitter clear-to-send enable (TXCTSE) */
|
||||
#define LPUART_MODIR_TXRTSE (1 << 1) /* Bit 1: Transmitter request-to-send enable (TXRTSE) */
|
||||
#define LPUART_MODIR_TXRTSPOL (1 << 2) /* Bit 2: Transmitter request-to-send polarity (TXRTSPOL) */
|
||||
#define LPUART_MODIR_RXRTSE (1 << 3) /* Bit 3: Receiver request-to-send enable (RXRTSE) */
|
||||
#define LPUART_MODIR_TXCTSC (1 << 4) /* Bit 4: Transmit CTS Configuration (TXCTSC) */
|
||||
# define LPUART_MODIR_TXCTSC_START (0 << 4) /* CTS sampled at start of character */
|
||||
# define LPUART_MODIR_TXCTSC_IDLE (1 << 4) /* CTS sampled when transmitter idle */
|
||||
#define LPUART_MODIR_TXCTSSRC (1 << 5) /* Bit 5: Transmit CTS Source (TXCTSSRC) */
|
||||
# define LPUART_MODIR_TXCTSSRC_CTSB (0 << 5) /* CTS input is CTS_B pin */
|
||||
# define LPUART_MODIR_TXCTSSRC_RXMAT (1 << 5) /* CTS input is receiver address match result */
|
||||
/* Bits 6-7: Reserved */
|
||||
#define LPUART_MODIR_RTSWATER_SHIFT (8) /* Bits 8-9: Receive RTS Configuration (RTSWATER) */
|
||||
#define LPUART_MODIR_RTSWATER_MASK (0x03 << LPUART_MODIR_RTSWATER_SHIFT)
|
||||
# define LPUART_MODIR_RTSWATER(n) ((n) << LPUART_MODIR_RTSWATER_SHIFT)
|
||||
/* Bits 10-15: Reserved */
|
||||
#define LPUART_MODIR_TNP_SHIFT (16) /* Bits 16-17: Transmitter narrow pulse (TNP) */
|
||||
#define LPUART_MODIR_TNP_MASK (0x03 << LPUART_MODIR_TNP_SHIFT)
|
||||
# define LPUART_MODIR_TNP(n) (((n) - 1) << LPUART_MODIR_TNP_SHIFT) /* n/OSR */
|
||||
|
||||
#define LPUART_MODIR_IREN (1 << 18) /* Bit 18: Infrared enable (IREN) */
|
||||
/* Bits 19-31: Reserved */
|
||||
|
||||
/* LPUART FIFO Register (FIFO) */
|
||||
|
||||
#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0) /* Bits 0-2: Receive FIFO Buffer Depth (RXFIFOSIZE) */
|
||||
#define LPUART_FIFO_RXFIFOSIZE_MASK (0x07 << LPUART_FIFO_RXFIFOSIZE_SHIFT)
|
||||
# define LPUART_FIFO_RXFIFOSIZE_1 (0 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 1 dataword */
|
||||
# define LPUART_FIFO_RXFIFOSIZE_4 (1 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 4 datawords */
|
||||
# define LPUART_FIFO_RXFIFOSIZE_8 (2 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 8 datawords */
|
||||
# define LPUART_FIFO_RXFIFOSIZE_16 (3 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 16 datawords */
|
||||
# define LPUART_FIFO_RXFIFOSIZE_32 (4 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 32 datawords */
|
||||
# define LPUART_FIFO_RXFIFOSIZE_64 (5 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 64 datawords */
|
||||
# define LPUART_FIFO_RXFIFOSIZE_128 (6 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 128 datawords */
|
||||
# define LPUART_FIFO_RXFIFOSIZE_256 (7 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 256 datawords */
|
||||
|
||||
#define LPUART_FIFO_RXFE (1 << 3) /* Bit 3: Receive FIFO Enable (RXFE) */
|
||||
#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4) /* Bits 4-6: Transmit FIFO Buffer Depth (TXFIFOSIZE) */
|
||||
#define LPUART_FIFO_TXFIFOSIZE_MASK (0x07 << LPUART_FIFO_TXFIFOSIZE_SHIFT)
|
||||
# define LPUART_FIFO_TXFIFOSIZE_1 (0 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 1 dataword */
|
||||
# define LPUART_FIFO_TXFIFOSIZE_4 (1 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 4 datawords */
|
||||
# define LPUART_FIFO_TXFIFOSIZE_8 (2 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 8 datawords */
|
||||
# define LPUART_FIFO_TXFIFOSIZE_16 (3 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 16 datawords */
|
||||
# define LPUART_FIFO_TXFIFOSIZE_32 (4 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 32 datawords */
|
||||
# define LPUART_FIFO_TXFIFOSIZE_64 (5 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 64 datawords */
|
||||
# define LPUART_FIFO_TXFIFOSIZE_128 (6 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 128 datawords */
|
||||
# define LPUART_FIFO_TXFIFOSIZE_256 (7 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 256 datawords */
|
||||
|
||||
#define LPUART_FIFO_TXFE (1 << 7) /* Bit 7: Transmit FIFO Enable (TXFE) */
|
||||
#define LPUART_FIFO_RXUFE (1 << 8) /* Bit 8: Receive FIFO Underflow Interrupt Enable (RXUFE) */
|
||||
#define LPUART_FIFO_TXOFE (1 << 9) /* Bit 9: Transmit FIFO Overflow Interrupt Enable (TXOFE) */
|
||||
#define LPUART_FIFO_RXIDEN_SHIFT (10) /* Bits 10-12: Receiver Idle Empty Enable (RXIDEN) */
|
||||
#define LPUART_FIFO_RXIDEN_MASK (0x07 << LPUART_FIFO_RXIDEN_SHIFT)
|
||||
# define LPUART_FIFO_RXIDEN_DISABLE (0 << LPUART_FIFO_RXIDEN_SHIFT) /* Disable RDRF assertion when receiver is idle */
|
||||
# define LPUART_FIFO_RXIDEN_1 (1 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 1 character */
|
||||
# define LPUART_FIFO_RXIDEN_2 (2 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 2 characters */
|
||||
# define LPUART_FIFO_RXIDEN_4 (3 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 4 characters */
|
||||
# define LPUART_FIFO_RXIDEN_8 (4 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 8 characters */
|
||||
# define LPUART_FIFO_RXIDEN_16 (5 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 16 characters */
|
||||
# define LPUART_FIFO_RXIDEN_32 (6 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 32 characters */
|
||||
# define LPUART_FIFO_RXIDEN_64 (7 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 64 characters */
|
||||
|
||||
/* Bit 13: Reserved */
|
||||
#define LPUART_FIFO_RXFLUSH (1 << 14) /* Bit 14: Receive FIFO Flush (RXFLUSH) */
|
||||
#define LPUART_FIFO_TXFLUSH (1 << 15) /* Bit 15: Transmit FIFO Flush (TXFLUSH) */
|
||||
#define LPUART_FIFO_RXUF (1 << 16) /* Bit 16: Receiver FIFO Underflow Flag (RXUF) */
|
||||
#define LPUART_FIFO_TXOF (1 << 17) /* Bit 17: Transmitter FIFO Overflow Flag (TXOF) */
|
||||
/* Bits 18-21: Reserved */
|
||||
#define LPUART_FIFO_RXEMPT (1 << 22) /* Bit 22: Receive Buffer/FIFO Empty (RXEMPT) */
|
||||
#define LPUART_FIFO_TXEMPT (1 << 23) /* Bit 23: Transmit Buffer/FIFO Empty (TXEMPT) */
|
||||
/* Bits 24-31: Reserved */
|
||||
|
||||
/* LPUART Watermark Register (WATER) */
|
||||
|
||||
#define LPUART_WATER_TXWATER_SHIFT (0) /* Bits 0-1: Transmit Watermark (TXWATER) */
|
||||
#define LPUART_WATER_TXWATER_MASK (0x03 << LPUART_WATER_TXWATER_SHIFT)
|
||||
# define LPUART_WATER_TXWATER(n) ((n) << LPUART_WATER_TXWATER_SHIFT)
|
||||
/* Bits 2-7: Reserved */
|
||||
#define LPUART_WATER_TXCOUNT_SHIFT (8) /* Bits 8-10: Transmit Counter (TXCOUNT) */
|
||||
#define LPUART_WATER_TXCOUNT_MASK (0x07 << LPUART_WATER_TXCOUNT_SHIFT)
|
||||
# define LPUART_WATER_TXCOUNT(n) ((n) << LPUART_WATER_TXCOUNT_SHIFT)
|
||||
/* Bits 11-15: Reserved */
|
||||
#define LPUART_WATER_RXWATER_SHIFT (16) /* Bits 16-17: Receive Watermark (RXWATER) */
|
||||
#define LPUART_WATER_RXWATER_MASK (0x03 << LPUART_WATER_RXWATER_SHIFT)
|
||||
# define LPUART_WATER_RXWATER(n) ((n) << LPUART_WATER_RXWATER_SHIFT)
|
||||
/* Bits 18-23: Reserved */
|
||||
#define LPUART_WATER_RXCOUNT_SHIFT (24) /* Bits 24-26: Receive Counter (RXCOUNT) */
|
||||
#define LPUART_WATER_RXCOUNT_MASK (0x07 << LPUART_WATER_RXCOUNT_SHIFT)
|
||||
# define LPUART_WATER_RXCOUNT(n) ((n) << LPUART_WATER_RXCOUNT_SHIFT)
|
||||
/* Bits 27-31: Reserved */
|
||||
|
||||
/* Data read-only Register (DATARO) */
|
||||
|
||||
#define LPUART_DATARO_DATA_SHIFT (0) /* Bits 0-15: Receive Data (DATA) */
|
||||
#define LPUART_DATARO_DATA_MASK (0xffff << LPUART_DATARO_DATA_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPUART_H */
|
||||
|
||||
@@ -39,6 +39,7 @@
|
||||
#include "arm64_mmu.h"
|
||||
#include "imx9_boot.h"
|
||||
#include "imx9_serial.h"
|
||||
#include "imx9_lowputc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
@@ -96,6 +97,12 @@ void arm64_chip_boot(void)
|
||||
|
||||
arm64_mmu_init(true);
|
||||
|
||||
/* Do UART early initialization & pin muxing */
|
||||
|
||||
#ifdef CONFIG_IMX9_LPUART
|
||||
imx9_lowsetup();
|
||||
#endif
|
||||
|
||||
/* Perform board-specific device initialization. This would include
|
||||
* configuration of board specific resources such as GPIOs, LEDs, etc.
|
||||
*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,5 +1,5 @@
|
||||
/****************************************************************************
|
||||
* arch/arm64/src/imx9/imx93_lowputs.S
|
||||
* arch/arm64/src/imx9/imx9_lowputc.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
@@ -16,70 +16,69 @@
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************
|
||||
*
|
||||
* DESCRIPTION
|
||||
* Wrapper for early printk
|
||||
*
|
||||
***************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_LOWPUTC_H
|
||||
#define __ARCH_ARM_SRC_IMX9_IMX9_LOWPUTC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/compiler.h>
|
||||
|
||||
#include "arm64_macro.inc"
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "hardware/imx9_lpuart.h"
|
||||
#include "hardware/imx93/imx93_memorymap.h"
|
||||
#include "arm64_internal.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Symbols
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
.file "imx93_lowputc.S"
|
||||
/* This structure describes the configuration of an UART */
|
||||
|
||||
struct uart_config_s
|
||||
{
|
||||
uint32_t baud; /* Configured baud */
|
||||
uint8_t parity; /* 0=none, 1=odd, 2=even */
|
||||
uint8_t bits; /* Number of bits (5-9) */
|
||||
bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
|
||||
bool userts; /* True: Assert RTS when there are data to be sent */
|
||||
bool invrts; /* True: Invert sense of RTS pin (true=active high) */
|
||||
bool usects; /* True: Condition transmission on CTS asserted */
|
||||
bool users485; /* True: Assert RTS while transmission progresses */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Assembly Macros
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
* Name: imx9_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* Called at the very beginning of _start. Performs low level
|
||||
* initialization including setup of the console UART. This UART done
|
||||
* early so that the serial console is available for debugging very early
|
||||
* in the boot sequence.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void imx9_lowsetup(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
* Name: imx9_lpuart_configure
|
||||
*
|
||||
* Description:
|
||||
* Configure a UART for non-interrupt driven operation
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* PL011 UART initialization */
|
||||
int imx9_lpuart_configure(uint32_t base,
|
||||
int uartnum,
|
||||
const struct uart_config_s *config);
|
||||
|
||||
GTEXT(arm64_earlyprintinit)
|
||||
SECTION_FUNC(text, arm64_earlyprintinit)
|
||||
/* TODO: Assumes u-boot has set us up, assumption is fine for now */
|
||||
ret
|
||||
|
||||
/* i.MX93 wait LPUART to be ready to transmit
|
||||
* rb: register which contains the UART base address
|
||||
* rc: scratch register
|
||||
*/
|
||||
.macro early_uart_ready rb, rc
|
||||
1:
|
||||
ldr \rc, [\rb, #UARTSTAT] /* <- Flag register */
|
||||
tst \rc, #UARTSTAT_TDRE /* Check FIFO EMPTY bit */
|
||||
beq 1b /* Wait for the UART to be ready */
|
||||
.endm
|
||||
|
||||
/* i.MX93 LPUART transmit character
|
||||
* rb: register which contains the UART base address
|
||||
* rt: register which contains the character to transmit */
|
||||
.macro early_uart_transmit rb, rt
|
||||
str \rt, [\rb, #UARTDATA] /* -> Data Register */
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Print a character on the UART - this function is called by C
|
||||
* w0: character to print
|
||||
*/
|
||||
GTEXT(arm64_lowputc)
|
||||
SECTION_FUNC(text, arm64_lowputc)
|
||||
ldr x15, =IMX9_LPUART1_BASE
|
||||
early_uart_ready x15, w2
|
||||
early_uart_transmit x15, w0
|
||||
ret
|
||||
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_LOWPUTC_H */
|
||||
+2566
-695
File diff suppressed because it is too large
Load Diff
@@ -27,12 +27,185 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "arm64_internal.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_IMX9_LPUART1) || defined(CONFIG_IMX9_LPUART2) || \
|
||||
defined(CONFIG_IMX9_LPUART3) || defined(CONFIG_IMX9_LPUART4) || \
|
||||
defined(CONFIG_IMX9_LPUART5) || defined(CONFIG_IMX9_LPUART6) || \
|
||||
defined(CONFIG_IMX9_LPUART7) || defined(CONFIG_IMX9_LPUART8)
|
||||
# define HAVE_UART 1
|
||||
#endif
|
||||
|
||||
/* Assume DMA is not used on the console UART */
|
||||
|
||||
#undef SERIAL_HAVE_CONSOLE_RXDMA
|
||||
#undef SERIAL_HAVE_CONSOLE_TXDMA
|
||||
|
||||
#if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA)
|
||||
# undef CONFIG_LPUART1_RXDMA
|
||||
# undef CONFIG_LPUART1_TXDMA
|
||||
# undef CONFIG_LPUART2_RXDMA
|
||||
# undef CONFIG_LPUART2_TXDMA
|
||||
# undef CONFIG_LPUART3_RXDMA
|
||||
# undef CONFIG_LPUART3_TXDMA
|
||||
# undef CONFIG_LPUART4_RXDMA
|
||||
# undef CONFIG_LPUART4_TXDMA
|
||||
# undef CONFIG_LPUART5_RXDMA
|
||||
# undef CONFIG_LPUART5_TXDMA
|
||||
# undef CONFIG_LPUART6_RXDMA
|
||||
# undef CONFIG_LPUART6_TXDMA
|
||||
# undef CONFIG_LPUART7_RXDMA
|
||||
# undef CONFIG_LPUART7_TXDMA
|
||||
# undef CONFIG_LPUART8_RXDMA
|
||||
# undef CONFIG_LPUART8_TXDMA
|
||||
#endif
|
||||
|
||||
/* Disable the DMA configuration on all unused LPUARTs */
|
||||
|
||||
#ifndef CONFIG_IMX9_LPUART1
|
||||
# undef CONFIG_LPUART1_RXDMA
|
||||
# undef CONFIG_LPUART1_TXDMA
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_IMX9_LPUART2
|
||||
# undef CONFIG_LPUART2_RXDMA
|
||||
# undef CONFIG_LPUART2_TXDMA
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_IMX9_LPUART3
|
||||
# undef CONFIG_LPUART3_RXDMA
|
||||
# undef CONFIG_LPUART3_TXDMA
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_IMX9_LPUART4
|
||||
# undef CONFIG_LPUART4_RXDMA
|
||||
# undef CONFIG_LPUART4_TXDMA
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_IMX9_LPUART5
|
||||
# undef CONFIG_LPUART5_RXDMA
|
||||
# undef CONFIG_LPUART5_TXDMA
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_IMX9_LPUART6
|
||||
# undef CONFIG_LPUART6_RXDMA
|
||||
# undef CONFIG_LPUART6_TXDMA
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_IMX9_LPUART8
|
||||
# undef CONFIG_LPUART7_RXDMA
|
||||
# undef CONFIG_LPUART7_TXDMA
|
||||
#endif
|
||||
|
||||
/* Is RX DMA available on any (enabled) LPUART? */
|
||||
|
||||
#undef SERIAL_HAVE_RXDMA
|
||||
#if defined(CONFIG_LPUART1_RXDMA) || defined(CONFIG_LPUART2_RXDMA) || \
|
||||
defined(CONFIG_LPUART3_RXDMA) || defined(CONFIG_LPUART4_RXDMA) || \
|
||||
defined(CONFIG_LPUART5_RXDMA) || defined(CONFIG_LPUART6_RXDMA) || \
|
||||
defined(CONFIG_LPUART7_RXDMA) || defined(CONFIG_LPUART8_RXDMA)
|
||||
# define SERIAL_HAVE_RXDMA 1
|
||||
#endif
|
||||
|
||||
/* Is TX DMA available on any (enabled) LPUART? */
|
||||
#undef SERIAL_HAVE_TXDMA
|
||||
#if defined(CONFIG_LPUART1_TXDMA) || defined(CONFIG_LPUART2_TXDMA) || \
|
||||
defined(CONFIG_LPUART3_TXDMA) || defined(CONFIG_LPUART4_TXDMA) || \
|
||||
defined(CONFIG_LPUART5_TXDMA) || defined(CONFIG_LPUART6_TXDMA) || \
|
||||
defined(CONFIG_LPUART7_TXDMA) || defined(CONFIG_LPUART8_TXDMA)
|
||||
# define SERIAL_HAVE_TXDMA 1
|
||||
#endif
|
||||
|
||||
/* Is RX DMA used on all (enabled) LPUARTs */
|
||||
|
||||
#define SERIAL_HAVE_ONLY_RXDMA 1
|
||||
#if defined(CONFIG_IMX9_LPUART1) && !defined(CONFIG_LPUART1_RXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_RXDMA
|
||||
#elif defined(CONFIG_IMX9_LPUART2) && !defined(CONFIG_LPUART2_RXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_RXDMA
|
||||
#elif defined(CONFIG_IMX9_LPUART3) && !defined(CONFIG_LPUART3_RXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_RXDMA
|
||||
#elif defined(CONFIG_IMX9_LPUART4) && !defined(CONFIG_LPUART4_RXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_RXDMA
|
||||
#elif defined(CONFIG_IMX9_LPUART5) && !defined(CONFIG_LPUART5_RXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_RXDMA
|
||||
#elif defined(CONFIG_IMX9_LPUART6) && !defined(CONFIG_LPUART6_RXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_RXDMA
|
||||
#elif defined(CONFIG_IMX9_LPUART7) && !defined(CONFIG_LPUART7_RXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_RXDMA
|
||||
#elif defined(CONFIG_IMX9_LPUART8) && !defined(CONFIG_LPUART8_RXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_RXDMA
|
||||
#endif
|
||||
|
||||
/* Is TX DMA used on all (enabled) LPUARTs */
|
||||
|
||||
#define SERIAL_HAVE_ONLY_TXDMA 1
|
||||
#if defined(CONFIG_IMX9_LPUART1) && !defined(CONFIG_LPUART1_TXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_TXDMA
|
||||
#elif defined(CONFIG_IMX9_LPUART2) && !defined(CONFIG_LPUART2_TXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_TXDMA
|
||||
#elif defined(CONFIG_IMX9_LPUART3) && !defined(CONFIG_LPUART3_TXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_TXDMA
|
||||
#elif defined(CONFIG_IMX9_LPUART4) && !defined(CONFIG_LPUART4_TXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_TXDMA
|
||||
#elif defined(CONFIG_IMX9_LPUART5) && !defined(CONFIG_LPUART5_TXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_TXDMA
|
||||
#elif defined(CONFIG_IMX9_LPUART6) && !defined(CONFIG_LPUART6_TXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_TXDMA
|
||||
#elif defined(CONFIG_IMX9_LPUART7) && !defined(CONFIG_LPUART7_TXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_TXDMA
|
||||
#elif defined(CONFIG_IMX9_LPUART8) && !defined(CONFIG_LPUART8_TXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_TXDMA
|
||||
#endif
|
||||
|
||||
#undef SERIAL_HAVE_ONLY_DMA
|
||||
#if defined(SERIAL_HAVE_ONLY_RXDMA) && defined(SERIAL_HAVE_ONLY_TXDMA)
|
||||
#define SERIAL_HAVE_ONLY_DMA
|
||||
#endif
|
||||
|
||||
/* Verify that DMA has been enabled and the DMA channel has been defined.
|
||||
*/
|
||||
|
||||
#if defined(SERIAL_HAVE_TXDMA) || defined(SERIAL_HAVE_RXDMA)
|
||||
# ifndef CONFIG_IMX9_EDMA
|
||||
# error IMXRT LPUART receive or transmit DMA requires CONFIG_IMX9_EDMA
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(SERIAL_HAVE_RXDMA)
|
||||
/* Currently RS-485 support cannot be enabled when RXDMA is in use due to
|
||||
* lack of testing.
|
||||
*/
|
||||
|
||||
# if (defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_RS485)) || \
|
||||
(defined(CONFIG_LPUART2_RXDMA) && defined(CONFIG_LPUART2_RS485)) || \
|
||||
(defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_RS485)) || \
|
||||
(defined(CONFIG_LPUART4_RXDMA) && defined(CONFIG_LPUART4_RS485)) || \
|
||||
(defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_RS485)) || \
|
||||
(defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_RS485)) || \
|
||||
(defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_RS485)) || \
|
||||
(defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_RS485))
|
||||
# error "RXDMA and RS-485 cannot be enabled at the same time for the same LPUART"
|
||||
# endif
|
||||
#endif /* SERIAL_HAVE_RXDMA */
|
||||
|
||||
/* Currently RS-485 support cannot be enabled when TXDMA is in use due to
|
||||
* lack of testing.
|
||||
*/
|
||||
|
||||
# if (defined(CONFIG_LPUART1_TXDMA) && defined(CONFIG_LPUART1_RS485)) || \
|
||||
(defined(CONFIG_LPUART2_TXDMA) && defined(CONFIG_LPUART2_RS485)) || \
|
||||
(defined(CONFIG_LPUART3_TXDMA) && defined(CONFIG_LPUART3_RS485)) || \
|
||||
(defined(CONFIG_LPUART4_TXDMA) && defined(CONFIG_LPUART4_RS485)) || \
|
||||
(defined(CONFIG_LPUART5_TXDMA) && defined(CONFIG_LPUART5_RS485)) || \
|
||||
(defined(CONFIG_LPUART6_TXDMA) && defined(CONFIG_LPUART6_RS485)) || \
|
||||
(defined(CONFIG_LPUART7_TXDMA) && defined(CONFIG_LPUART7_RS485)) || \
|
||||
(defined(CONFIG_LPUART8_TXDMA) && defined(CONFIG_LPUART8_RS485))
|
||||
# error "TXDMA and RS-485 cannot be enabled at the same time for the same LPUART"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
@@ -47,50 +220,23 @@
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx_earlyserialinit
|
||||
*
|
||||
* Description:
|
||||
* Performs the low level UART initialization early in debug so that the
|
||||
* serial console will be available during bootup. This must be called
|
||||
* before arm_serialinit.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
void imx9_earlyserialinit(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: uart_earlyserialinit
|
||||
*
|
||||
* Description:
|
||||
* Performs the low level UART initialization early in debug so that the
|
||||
* serial console will be available during bootup. This must be called
|
||||
* before arm_serialinit.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(USE_EARLYSERIALINIT) && defined(IMX9_HAVE_UART)
|
||||
void uart_earlyserialinit(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: uart_serialinit
|
||||
*
|
||||
* Description:
|
||||
* Register the UART serial console and serial ports. This assumes that
|
||||
* uart_earlyserialinit was called previously.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef IMX9_HAVE_UART
|
||||
void uart_serialinit(void);
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_IMX9_IMX_SERIAL_H */
|
||||
#endif /* __ARCH_ARM64_SRC_IMX9_IMX9_SERIAL_H */
|
||||
|
||||
@@ -36,12 +36,13 @@ CONFIG_IMX9_GPIO_IRQ=y
|
||||
CONFIG_IMX9_LPI2C1=y
|
||||
CONFIG_IMX9_LPI2C_DYNTIMEO=y
|
||||
CONFIG_IMX9_LPI2C_DYNTIMEO_STARTSTOP=10
|
||||
CONFIG_IMX9_LPUART1=y
|
||||
CONFIG_IMX9_TPM3_PWM=y
|
||||
CONFIG_IMX9_TPM3_PWM_CHMUX=0x00000003
|
||||
CONFIG_IMX9_UART1=y
|
||||
CONFIG_IMX9_USBDEV_USBC1=y
|
||||
CONFIG_INIT_ENTRYPOINT="nsh_main"
|
||||
CONFIG_INTELHEX_BINARY=y
|
||||
CONFIG_LPUART1_SERIAL_CONSOLE=y
|
||||
CONFIG_NSH_ARCHINIT=y
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_FILEIOSIZE=512
|
||||
@@ -71,4 +72,3 @@ CONFIG_SYSTEM_SYSTEM=y
|
||||
CONFIG_SYSTEM_TIME64=y
|
||||
CONFIG_TESTING_GETPRIME=y
|
||||
CONFIG_TESTING_OSTEST=y
|
||||
CONFIG_UART1_SERIAL_CONSOLE=y
|
||||
|
||||
@@ -33,6 +33,11 @@
|
||||
|
||||
#define IOMUX_LPI2C_DEFAULT (IOMUXC_PAD_OD_ENABLE | IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6)
|
||||
|
||||
/* UART pin muxings */
|
||||
|
||||
#define MUX_LPUART1_RX IOMUX_CFG(IOMUXC_PAD_UART1_RXD_LPUART1_RX, 0, IOMUXC_MUX_SION_ON)
|
||||
#define MUX_LPUART1_TX IOMUX_CFG(IOMUXC_PAD_UART1_TXD_LPUART1_TX, IOMUXC_PAD_FSEL_SLOW | IOMUXC_PAD_DSE_X4, 0)
|
||||
|
||||
/* FLEXIO to PWM pin muxings */
|
||||
|
||||
/* EVK signals
|
||||
@@ -47,6 +52,8 @@
|
||||
#define FLEXIO1_PWM2_MUX IOMUX_CFG(IOMUXC_PAD_GPIO_IO06_FLEXIO1_FLEXIO06, IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6, 0)
|
||||
#define FLEXIO1_PWM3_MUX IOMUX_CFG(IOMUXC_PAD_GPIO_IO07_FLEXIO1_FLEXIO07, IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6, 0)
|
||||
|
||||
/* LPI2Cs */
|
||||
|
||||
/* TPM3 ch3 to PWM pin GPIO_IO24 muxing */
|
||||
|
||||
#define TPM3_PWM3_MUX IOMUX_CFG(IOMUXC_PAD_GPIO_IO24_TPM3_CH3, IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6, 0)
|
||||
|
||||
Reference in New Issue
Block a user